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-- Company: www.mlab.cz |
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-- Company: www.mlab.cz |
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-- Based on code written by MIHO. |
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-- Based on code written by MIHO. |
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-- |
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-- |
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-- HW Design Name: S3AN01A |
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-- HW Design Name: S3AN01A |
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-- Project Name: Atomic Counter |
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-- Project Name: Atomic Counter |
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-- Target Devices: XC3S50AN-4 |
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-- Target Devices: XC3S50AN-4 |
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-- Tool versions: ISE 13.3 |
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-- Tool versions: ISE 13.3 |
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-- Description: Counter up to 640 MHz synchonised by GPS. |
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-- Description: Counter up to 640 MHz synchonised by GPS. |
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-- Output frequency is displayed on the 7seg. LED display. |
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-- Output frequency is displayed on the 7seg. LED display. |
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-- You can choice half or full frequency by DIPSW7. |
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-- You can choice half or full frequency by DIPSW7. |
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-- |
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-- |
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-- Dependencies: TTLPECL01A, GPS01A |
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-- Dependencies: TTLPECL01A, GPS01A |
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-- |
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-- |
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-- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $ |
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-- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $ |
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-- |
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-- |
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---------------------------------------------------------------------------------- |
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---------------------------------------------------------------------------------- |
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|
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|
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library IEEE; |
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library IEEE; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.numeric_std.ALL; |
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use IEEE.numeric_std.ALL; |
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|
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|
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library UNISIM; |
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library UNISIM; |
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use UNISIM.vcomponents.all; |
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use UNISIM.vcomponents.all; |
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|
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|
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entity AtomicCounter is |
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entity AtomicCounter is |
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generic ( |
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generic ( |
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-- Top Value for 100MHz Clock Counter |
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-- Top Value for 100MHz Clock Counter |
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MAXCOUNT: integer := 10_000; -- Maximum for the first counter |
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MAXCOUNT: integer := 10_000; -- Maximum for the first counter |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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); |
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); |
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port ( |
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port ( |
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-- Clock on PCB |
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-- Clock on PCB |
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CLK100MHz: in std_logic; |
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CLK100MHz: in std_logic; |
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|
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|
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-- Mode Signals (usualy not used) |
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-- Mode Signals (usualy not used) |
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M: in std_logic_vector(2 downto 0); |
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M: in std_logic_vector(2 downto 0); |
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VS: in std_logic_vector(2 downto 0); |
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VS: in std_logic_vector(2 downto 0); |
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|
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|
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-- Dipswitch Inputs |
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-- Dipswitch Inputs |
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DIPSW: in std_logic_vector(7 downto 0); |
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DIPSW: in std_logic_vector(7 downto 0); |
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|
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|
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-- Push Buttons |
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-- Push Buttons |
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PB: in std_logic_vector(3 downto 0); |
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PB: in std_logic_vector(3 downto 0); |
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|
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|
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-- LED Bar Outputs |
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-- LED Bar Outputs |
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LED: out std_logic_vector(7 downto 0); |
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LED: out std_logic_vector(7 downto 0); |
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|
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|
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-- LED Display (8 digit with 7 segments and ddecimal point) |
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-- LED Display (8 digit with 7 segments and ddecimal point) |
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LD_A_n: out std_logic; |
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LD_A_n: out std_logic; |
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LD_B_n: out std_logic; |
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LD_B_n: out std_logic; |
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LD_C_n: out std_logic; |
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LD_C_n: out std_logic; |
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LD_D_n: out std_logic; |
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LD_D_n: out std_logic; |
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LD_E_n: out std_logic; |
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LD_E_n: out std_logic; |
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LD_F_n: out std_logic; |
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LD_F_n: out std_logic; |
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LD_G_n: out std_logic; |
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LD_G_n: out std_logic; |
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LD_DP_n: out std_logic; |
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LD_DP_n: out std_logic; |
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LD_0_n: out std_logic; |
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LD_0_n: out std_logic; |
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LD_1_n: out std_logic; |
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LD_1_n: out std_logic; |
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LD_2_n: out std_logic; |
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LD_2_n: out std_logic; |
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LD_3_n: out std_logic; |
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LD_3_n: out std_logic; |
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LD_4_n: out std_logic; |
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LD_4_n: out std_logic; |
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LD_5_n: out std_logic; |
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LD_5_n: out std_logic; |
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LD_6_n: out std_logic; |
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LD_6_n: out std_logic; |
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LD_7_n: out std_logic; |
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LD_7_n: out std_logic; |
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|
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|
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-- VGA Video Out Port |
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-- VGA Video Out Port |
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VGA_R: out std_logic_vector(1 downto 0); |
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VGA_R: out std_logic_vector(1 downto 0); |
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VGA_G: out std_logic_vector(1 downto 0); |
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VGA_G: out std_logic_vector(1 downto 0); |
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VGA_B: out std_logic_vector(1 downto 0); |
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VGA_B: out std_logic_vector(1 downto 0); |
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VGA_VS: out std_logic; |
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VGA_VS: out std_logic; |
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VGA_HS: out std_logic; |
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VGA_HS: out std_logic; |
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|
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|
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-- Bank 1 Pins - Inputs for this Test |
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-- Bank 1 Pins - Inputs for this Test |
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B: inout std_logic_vector(24 downto 0); |
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B: inout std_logic_vector(24 downto 0); |
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|
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|
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-- PS/2 Bidirectional Port (open collector, J31 and J32) |
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-- PS/2 Bidirectional Port (open collector, J31 and J32) |
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PS2_CLK1: inout std_logic; |
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PS2_CLK1: inout std_logic; |
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PS2_DATA1: inout std_logic; |
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PS2_DATA1: inout std_logic; |
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PS2_CLK2: inout std_logic; |
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PS2_CLK2: inout std_logic; |
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PS2_DATA2: inout std_logic; |
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PS2_DATA2: inout std_logic; |
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|
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|
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-- Diferencial Signals on 4 pin header (J7) |
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-- Diferencial Signals on 4 pin header (J7) |
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DIF1P: inout std_logic; |
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DIF1P: inout std_logic; |
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DIF1N: inout std_logic; |
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DIF1N: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2N: inout std_logic; |
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DIF2N: inout std_logic; |
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|
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|
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|
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|
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-- I2C Signals (on connector J30) |
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-- I2C Signals (on connector J30) |
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I2C_SCL: inout std_logic; |
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I2C_SCL: inout std_logic; |
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I2C_SDA: inout std_logic; |
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I2C_SDA: inout std_logic; |
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|
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|
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-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
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-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
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SD1AP: inout std_logic; |
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SD1AP: inout std_logic; |
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SD1AN: inout std_logic; |
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SD1AN: inout std_logic; |
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SD1BP: inout std_logic; |
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SD1BP: inout std_logic; |
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SD1BN: inout std_logic; |
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SD1BN: inout std_logic; |
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SD2AP: inout std_logic; |
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SD2AP: inout std_logic; |
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SD2AN: inout std_logic; |
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SD2AN: inout std_logic; |
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SD2BP: inout std_logic; |
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SD2BP: inout std_logic; |
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SD2BN: inout std_logic; |
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SD2BN: inout std_logic; |
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|
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|
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-- Analog In Out |
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-- Analog In Out |
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ANA_OUTD: out std_logic; |
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ANA_OUTD: out std_logic; |
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ANA_REFD: out std_logic; |
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ANA_REFD: out std_logic; |
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ANA_IND: in std_logic; |
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ANA_IND: in std_logic; |
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|
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|
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-- SPI Memory Interface |
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-- SPI Memory Interface |
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SPI_CS_n: inout std_logic; |
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SPI_CS_n: inout std_logic; |
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SPI_DO: inout std_logic; |
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SPI_DO: inout std_logic; |
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SPI_DI: inout std_logic; |
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SPI_DI: inout std_logic; |
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SPI_CLK: inout std_logic; |
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SPI_CLK: inout std_logic; |
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SPI_WP_n: inout std_logic |
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SPI_WP_n: inout std_logic |
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); |
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); |
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end entity AtomicCounter; |
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end entity AtomicCounter; |
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|
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|
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|
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|
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architecture AtomicCounter_a of AtomicCounter is |
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architecture AtomicCounter_a of AtomicCounter is |
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|
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|
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function to_bcd ( bin : std_logic_vector(31 downto 0) ) return std_logic_vector is |
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function to_bcd ( bin : std_logic_vector(31 downto 0) ) return std_logic_vector is |
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variable i : integer:=0; |
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variable i : integer:=0; |
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variable mybcd : std_logic_vector(35 downto 0) := (others => '0'); |
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variable mybcd : std_logic_vector(35 downto 0) := (others => '0'); |
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variable bint : std_logic_vector(31 downto 0) := bin; |
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variable bint : std_logic_vector(31 downto 0) := bin; |
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begin |
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begin |
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for i in 0 to 31 loop -- repeating 16 times. |
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for i in 0 to 31 loop -- repeating 16 times. |
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mybcd(35 downto 1) := mybcd(34 downto 0); --shifting the bits. |
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mybcd(35 downto 1) := mybcd(34 downto 0); --shifting the bits. |
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mybcd(0) := bint(31); |
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mybcd(0) := bint(31); |
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bint(31 downto 1) := bint(30 downto 0); |
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bint(31 downto 1) := bint(30 downto 0); |
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bint(0) :='0'; |
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bint(0) :='0'; |
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|
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|
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|
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|
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if(i < 31 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 31 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 31 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 31 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 31 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 31 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 31 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 31 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3); |
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mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 31 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 31 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3); |
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mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 31 and mybcd(23 downto 20) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 31 and mybcd(23 downto 20) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(23 downto 20) := std_logic_vector(unsigned(mybcd(23 downto 20)) + 3); |
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mybcd(23 downto 20) := std_logic_vector(unsigned(mybcd(23 downto 20)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 31 and mybcd(27 downto 24) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 31 and mybcd(27 downto 24) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(27 downto 24) := std_logic_vector(unsigned(mybcd(27 downto 24)) + 3); |
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mybcd(27 downto 24) := std_logic_vector(unsigned(mybcd(27 downto 24)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 31 and mybcd(31 downto 28) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 31 and mybcd(31 downto 28) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(31 downto 28) := std_logic_vector(unsigned(mybcd(31 downto 28)) + 3); |
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mybcd(31 downto 28) := std_logic_vector(unsigned(mybcd(31 downto 28)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 31 and mybcd(35 downto 32) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 31 and mybcd(35 downto 32) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(35 downto 32) := std_logic_vector(unsigned(mybcd(35 downto 32)) + 3); |
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mybcd(35 downto 32) := std_logic_vector(unsigned(mybcd(35 downto 32)) + 3); |
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end if; |
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end if; |
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|
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|
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end loop; |
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end loop; |
170 |
|
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|
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return mybcd; |
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return mybcd; |
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end to_bcd; |
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end to_bcd; |
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|
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|
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|
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|
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-- Counters |
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-- Counters |
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-- ---------------- |
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-- ---------------- |
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|
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|
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signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary) |
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signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary) |
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|
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|
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|
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|
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-- LED Display |
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-- LED Display |
182 |
-- ----------- |
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-- ----------- |
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|
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|
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signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input |
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signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input |
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signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency |
185 |
signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
187 |
signal Enable: std_logic; |
187 |
signal Enable: std_logic; |
188 |
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
188 |
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
189 |
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
189 |
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
191 |
|
191 |
|
192 |
|
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|
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signal LO_CLOCK: std_logic; -- Frequency divided by 2 |
193 |
signal LO_CLOCK: std_logic; -- Frequency divided by 2 |
194 |
signal EXT_CLOCK: std_logic; -- Input Frequency |
194 |
signal EXT_CLOCK: std_logic; -- Input Frequency |
195 |
|
195 |
|
196 |
signal Decko: std_logic; -- D flip-flop |
196 |
signal Decko: std_logic; -- D flip-flop |
197 |
signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata |
197 |
signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata |
198 |
|
198 |
|
199 |
begin |
199 |
begin |
200 |
|
200 |
|
201 |
-- Input divider by 2 |
201 |
-- Input divider by 2 |
202 |
process (EXT_CLOCK) |
202 |
process (EXT_CLOCK) |
203 |
begin |
203 |
begin |
204 |
if rising_edge(EXT_CLOCK) then |
204 |
if rising_edge(EXT_CLOCK) then |
205 |
LO_CLOCK <= not LO_CLOCK; |
205 |
LO_CLOCK <= not LO_CLOCK; |
206 |
end if; |
206 |
end if; |
207 |
end process; |
207 |
end process; |
208 |
|
208 |
|
209 |
|
209 |
|
210 |
-- Counter |
210 |
-- Counter |
211 |
process (LO_CLOCK) |
211 |
process (LO_CLOCK) |
212 |
begin |
212 |
begin |
213 |
|
213 |
|
214 |
if rising_edge(LO_CLOCK) then |
214 |
if rising_edge(LO_CLOCK) then |
215 |
|
215 |
|
216 |
if (State = 3) or (State = 0) then |
216 |
if (State = 3) or (State = 0) then |
217 |
if DIPSW(7) = '0' then -- Half/Full frequency |
217 |
if DIPSW(7) = '0' then -- Half/Full frequency |
218 |
Counter <= Counter + 1; |
218 |
Counter <= Counter + 1; |
219 |
else |
219 |
else |
220 |
Counter <= Counter + 2; |
220 |
Counter <= Counter + 2; |
221 |
end if; |
221 |
end if; |
222 |
end if; |
222 |
end if; |
223 |
if (State = 1) then |
223 |
if (State = 1) then |
224 |
Freq(31 downto 0) <= std_logic_vector(Counter); |
224 |
Freq(31 downto 0) <= std_logic_vector(Counter); |
225 |
end if; |
225 |
end if; |
226 |
if (State = 2) then |
226 |
if (State = 2) then |
227 |
Counter <= (others => '0'); |
227 |
Counter <= (others => '0'); |
228 |
end if; |
228 |
end if; |
229 |
end if; |
229 |
end if; |
230 |
|
230 |
|
231 |
end process; |
231 |
end process; |
232 |
|
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|
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|
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|
234 |
-- Sampling 1PPS signal |
234 |
-- Sampling 1PPS signal |
235 |
process (LO_CLOCK) |
235 |
process (LO_CLOCK) |
236 |
begin |
236 |
begin |
237 |
if rising_edge(LO_CLOCK) then |
237 |
if rising_edge(LO_CLOCK) then |
238 |
Decko <= B(22); |
238 |
Decko <= B(22); |
239 |
end if; |
239 |
end if; |
240 |
end process; |
240 |
end process; |
241 |
|
241 |
|
242 |
-- Automata for controlling the Counter |
242 |
-- Automata for controlling the Counter |
243 |
process (LO_CLOCK) |
243 |
process (LO_CLOCK) |
244 |
begin |
244 |
begin |
245 |
if rising_edge(LO_CLOCK) then |
245 |
if rising_edge(LO_CLOCK) then |
246 |
if (Decko = '1') then |
246 |
if (Decko = '1') then |
247 |
if (State < 3) then |
247 |
if (State < 3) then |
248 |
State <= State + 1; |
248 |
State <= State + 1; |
249 |
end if; |
249 |
end if; |
250 |
else |
250 |
else |
251 |
State <= (others => '0'); |
251 |
State <= (others => '0'); |
252 |
end if; |
252 |
end if; |
253 |
end if; |
253 |
end if; |
254 |
end process; |
254 |
end process; |
255 |
|
255 |
|
256 |
-- Coding to BCD for LED Display |
256 |
-- Coding to BCD for LED Display |
257 |
|
257 |
|
258 |
process (Decko) |
258 |
process (Decko) |
259 |
begin |
259 |
begin |
260 |
if falling_edge(Decko) then |
260 |
if falling_edge(Decko) then |
261 |
Number(35 downto 0) <= to_bcd(Freq(31 downto 0)); |
261 |
Number(35 downto 0) <= to_bcd(Freq(31 downto 0)); |
262 |
end if; |
262 |
end if; |
263 |
end process; |
263 |
end process; |
264 |
|
264 |
|
265 |
-- Number(35 downto 0) <= NumberPom(35 downto 0); |
265 |
-- Number(35 downto 0) <= NumberPom(35 downto 0); |
266 |
|
266 |
|
267 |
LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar |
267 |
LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar |
268 |
LED(6 downto 4) <= (others => '0'); |
268 |
LED(6 downto 4) <= (others => '0'); |
269 |
LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar |
269 |
LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar |
270 |
|
270 |
|
271 |
-- LED Display (multiplexed) |
271 |
-- LED Display (multiplexed) |
272 |
-- ========================= |
272 |
-- ========================= |
273 |
|
273 |
|
274 |
-- Connect LED Display Output Ports (negative outputs) |
274 |
-- Connect LED Display Output Ports (negative outputs) |
275 |
LD_A_n <= not (Segments(0) and Enable); |
275 |
LD_A_n <= not (Segments(0) and Enable); |
276 |
LD_B_n <= not (Segments(1) and Enable); |
276 |
LD_B_n <= not (Segments(1) and Enable); |
277 |
LD_C_n <= not (Segments(2) and Enable); |
277 |
LD_C_n <= not (Segments(2) and Enable); |
278 |
LD_D_n <= not (Segments(3) and Enable); |
278 |
LD_D_n <= not (Segments(3) and Enable); |
279 |
LD_E_n <= not (Segments(4) and Enable); |
279 |
LD_E_n <= not (Segments(4) and Enable); |
280 |
LD_F_n <= not (Segments(5) and Enable); |
280 |
LD_F_n <= not (Segments(5) and Enable); |
281 |
LD_G_n <= not (Segments(6) and Enable); |
281 |
LD_G_n <= not (Segments(6) and Enable); |
282 |
LD_DP_n <= not (Segments(7) and Enable); |
282 |
LD_DP_n <= not (Segments(7) and Enable); |
283 |
|
283 |
|
284 |
LD_0_n <= not Digits(0); |
284 |
LD_0_n <= not Digits(0); |
285 |
LD_1_n <= not Digits(1); |
285 |
LD_1_n <= not Digits(1); |
286 |
LD_2_n <= not Digits(2); |
286 |
LD_2_n <= not Digits(2); |
287 |
LD_3_n <= not Digits(3); |
287 |
LD_3_n <= not Digits(3); |
288 |
LD_4_n <= not Digits(4); |
288 |
LD_4_n <= not Digits(4); |
289 |
LD_5_n <= not Digits(5); |
289 |
LD_5_n <= not Digits(5); |
290 |
LD_6_n <= not Digits(6); |
290 |
LD_6_n <= not Digits(6); |
291 |
LD_7_n <= not Digits(7); |
291 |
LD_7_n <= not Digits(7); |
292 |
|
292 |
|
293 |
-- Time Multiplex |
293 |
-- Time Multiplex |
294 |
process (CLK100MHz) |
294 |
process (CLK100MHz) |
295 |
begin |
295 |
begin |
296 |
if rising_edge(CLK100MHz) then |
296 |
if rising_edge(CLK100MHz) then |
297 |
if MuxCounter < MUXCOUNT-1 then |
297 |
if MuxCounter < MUXCOUNT-1 then |
298 |
MuxCounter <= MuxCounter + 1; |
298 |
MuxCounter <= MuxCounter + 1; |
299 |
else |
299 |
else |
300 |
MuxCounter <= (others => '0'); |
300 |
MuxCounter <= (others => '0'); |
301 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
301 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
302 |
Enable <= '0'; |
302 |
Enable <= '0'; |
303 |
end if; |
303 |
end if; |
304 |
if MuxCounter > (MUXCOUNT-4) then |
304 |
if MuxCounter > (MUXCOUNT-4) then |
305 |
Enable <= '1'; |
305 |
Enable <= '1'; |
306 |
end if; |
306 |
end if; |
307 |
end if; |
307 |
end if; |
308 |
end process; |
308 |
end process; |
309 |
|
309 |
|
310 |
-- HEX to 7 Segmet Decoder |
310 |
-- HEX to 7 Segmet Decoder |
311 |
-- -- A |
311 |
-- -- A |
312 |
-- | | F B |
312 |
-- | | F B |
313 |
-- -- G |
313 |
-- -- G |
314 |
-- | | E C |
314 |
-- | | E C |
315 |
-- -- D H |
315 |
-- -- D H |
316 |
-- ABCDEFGH |
316 |
-- ABCDEFGH |
317 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
317 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
318 |
"01100000" when Code="0001" else -- Digit 1 |
318 |
"01100000" when Code="0001" else -- Digit 1 |
319 |
"11011010" when Code="0010" else -- Digit 2 |
319 |
"11011010" when Code="0010" else -- Digit 2 |
320 |
"11110010" when Code="0011" else -- Digit 3 |
320 |
"11110010" when Code="0011" else -- Digit 3 |
321 |
"01100110" when Code="0100" else -- Digit 4 |
321 |
"01100110" when Code="0100" else -- Digit 4 |
322 |
"10110110" when Code="0101" else -- Digit 5 |
322 |
"10110110" when Code="0101" else -- Digit 5 |
323 |
"10111110" when Code="0110" else -- Digit 6 |
323 |
"10111110" when Code="0110" else -- Digit 6 |
324 |
"11100000" when Code="0111" else -- Digit 7 |
324 |
"11100000" when Code="0111" else -- Digit 7 |
325 |
"11111110" when Code="1000" else -- Digit 8 |
325 |
"11111110" when Code="1000" else -- Digit 8 |
326 |
"11110110" when Code="1001" else -- Digit 9 |
326 |
"11110110" when Code="1001" else -- Digit 9 |
327 |
"11101110" when Code="1010" else -- Digit A |
327 |
"11101110" when Code="1010" else -- Digit A |
328 |
"00111110" when Code="1011" else -- Digit b |
328 |
"00111110" when Code="1011" else -- Digit b |
329 |
"10011100" when Code="1100" else -- Digit C |
329 |
"10011100" when Code="1100" else -- Digit C |
330 |
"01111010" when Code="1101" else -- Digit d |
330 |
"01111010" when Code="1101" else -- Digit d |
331 |
"10011110" when Code="1110" else -- Digit E |
331 |
"10011110" when Code="1110" else -- Digit E |
332 |
"10001110" when Code="1111" else -- Digit F |
332 |
"10001110" when Code="1111" else -- Digit F |
333 |
"00000000"; |
333 |
"00000000"; |
334 |
|
334 |
|
335 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
335 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
336 |
Number( 7 downto 4) when Digits="00000010" else |
336 |
Number( 7 downto 4) when Digits="00000010" else |
337 |
Number(11 downto 8) when Digits="00000100" else |
337 |
Number(11 downto 8) when Digits="00000100" else |
338 |
Number(15 downto 12) when Digits="00001000" else |
338 |
Number(15 downto 12) when Digits="00001000" else |
339 |
Number(19 downto 16) when Digits="00010000" else |
339 |
Number(19 downto 16) when Digits="00010000" else |
340 |
Number(23 downto 20) when Digits="00100000" else |
340 |
Number(23 downto 20) when Digits="00100000" else |
341 |
Number(27 downto 24) when Digits="01000000" else |
341 |
Number(27 downto 24) when Digits="01000000" else |
342 |
Number(31 downto 28) when Digits="10000000" else |
342 |
Number(31 downto 28) when Digits="10000000" else |
343 |
"0000"; |
343 |
"0000"; |
344 |
|
344 |
|
345 |
|
345 |
|
346 |
|
346 |
|
347 |
-- Diferencial In/Outs |
347 |
-- Diferencial In/Outs |
348 |
-- ======================== |
348 |
-- ======================== |
349 |
DIFbuffer1 : IBUFGDS |
349 |
DIFbuffer1 : IBUFGDS |
350 |
generic map ( |
350 |
generic map ( |
351 |
DIFF_TERM => FALSE, -- Differential Termination |
351 |
DIFF_TERM => FALSE, -- Differential Termination |
352 |
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
352 |
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
353 |
-- "0"-"16" |
353 |
-- "0"-"16" |
354 |
IOSTANDARD => "LVPECL_33") |
354 |
IOSTANDARD => "LVPECL_33") |
355 |
port map ( |
355 |
port map ( |
356 |
I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
356 |
I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
357 |
IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
357 |
IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
358 |
O => EXT_CLOCK -- Buffer output - Counter INPUT |
358 |
O => EXT_CLOCK -- Buffer output - Counter INPUT |
359 |
); |
359 |
); |
360 |
|
360 |
|
361 |
OBUFDS_inst : OBUFDS |
361 |
OBUFDS_inst : OBUFDS |
362 |
generic map ( |
362 |
generic map ( |
363 |
IOSTANDARD => "LVDS_33") |
363 |
IOSTANDARD => "LVDS_33") |
364 |
port map ( |
364 |
port map ( |
365 |
O => SD2AP, -- Diff_p output (connect directly to top-level port) |
365 |
O => SD2AP, -- Diff_p output (connect directly to top-level port) |
366 |
OB => SD2AN, -- Diff_n output (connect directly to top-level port) |
366 |
OB => SD2AN, -- Diff_n output (connect directly to top-level port) |
367 |
I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS |
367 |
I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS |
368 |
); |
368 |
); |
369 |
|
369 |
|
370 |
-- Output Signal on SATA Connector |
370 |
-- Output Signal on SATA Connector |
371 |
-- SD1AP <= 'Z'; -- Counter INPUT |
371 |
-- SD1AP <= 'Z'; -- Counter INPUT |
372 |
-- SD1AN <= 'Z'; |
372 |
-- SD1AN <= 'Z'; |
373 |
SD1BP <= 'Z'; |
373 |
SD1BP <= 'Z'; |
374 |
SD1BN <= 'Z'; |
374 |
SD1BN <= 'Z'; |
375 |
|
375 |
|
376 |
-- Input Here via SATA Cable |
376 |
-- Input Here via SATA Cable |
377 |
-- SD2AP <= 'Z'; -- Counter OUTPUT |
377 |
-- SD2AP <= 'Z'; -- Counter OUTPUT |
378 |
-- SD2AN <= 'Z'; |
378 |
-- SD2AN <= 'Z'; |
379 |
SD2BP <= 'Z'; |
379 |
SD2BP <= 'Z'; |
380 |
SD2BN <= 'Z'; |
380 |
SD2BN <= 'Z'; |
381 |
|
381 |
|
382 |
|
382 |
|
383 |
-- Unused Signals |
383 |
-- Unused Signals |
384 |
-- ============== |
384 |
-- ============== |
385 |
|
385 |
|
386 |
-- Differential inputs onn header |
386 |
-- Differential inputs onn header |
387 |
DIF1N <= 'Z'; |
387 |
DIF1N <= 'Z'; |
388 |
DIF1P <= 'Z'; |
388 |
DIF1P <= 'Z'; |
389 |
DIF2N <= 'Z'; |
389 |
DIF2N <= 'Z'; |
390 |
DIF2P <= 'Z'; |
390 |
DIF2P <= 'Z'; |
391 |
|
391 |
|
392 |
-- I2C Signals (on connector J30) |
392 |
-- I2C Signals (on connector J30) |
393 |
I2C_SCL <= 'Z'; |
393 |
I2C_SCL <= 'Z'; |
394 |
I2C_SDA <= 'Z'; |
394 |
I2C_SDA <= 'Z'; |
395 |
|
395 |
|
396 |
-- SPI Memory Interface |
396 |
-- SPI Memory Interface |
397 |
SPI_CS_n <= 'Z'; |
397 |
SPI_CS_n <= 'Z'; |
398 |
SPI_DO <= 'Z'; |
398 |
SPI_DO <= 'Z'; |
399 |
SPI_DI <= 'Z'; |
399 |
SPI_DI <= 'Z'; |
400 |
SPI_CLK <= 'Z'; |
400 |
SPI_CLK <= 'Z'; |
401 |
SPI_WP_n <= 'Z'; |
401 |
SPI_WP_n <= 'Z'; |
402 |
|
402 |
|
403 |
-- A/D |
403 |
-- A/D |
404 |
ANA_OUTD <= 'Z'; |
404 |
ANA_OUTD <= 'Z'; |
405 |
ANA_REFD <= 'Z'; |
405 |
ANA_REFD <= 'Z'; |
406 |
|
406 |
|
407 |
-- VGA |
407 |
-- VGA |
408 |
VGA_R <= "ZZ"; |
408 |
VGA_R <= "ZZ"; |
409 |
VGA_G <= "ZZ"; |
409 |
VGA_G <= "ZZ"; |
410 |
VGA_B <= "ZZ"; |
410 |
VGA_B <= "ZZ"; |
411 |
VGA_VS <= 'Z'; |
411 |
VGA_VS <= 'Z'; |
412 |
VGA_HS <= 'Z'; |
412 |
VGA_HS <= 'Z'; |
413 |
|
413 |
|
414 |
-- PS2 |
414 |
-- PS2 |
415 |
PS2_DATA2 <= 'Z'; |
415 |
PS2_DATA2 <= 'Z'; |
416 |
PS2_CLK2 <='Z'; |
416 |
PS2_CLK2 <='Z'; |
417 |
|
417 |
|
418 |
end architecture AtomicCounter_a; |
418 |
end architecture AtomicCounter_a; |