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/** |
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/** |
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****************************************************************************** |
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****************************************************************************** |
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* @file stm32f10x.h |
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* @file stm32f10x.h |
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* @author MCD Application Team |
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* @author MCD Application Team |
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* @version V3.4.0 |
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* @version V3.4.0 |
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* @date 10/15/2010 |
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* @date 10/15/2010 |
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
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* This file contains all the peripheral register's definitions, bits |
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* This file contains all the peripheral register's definitions, bits |
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* definitions and memory mapping for STM32F10x Connectivity line, |
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* definitions and memory mapping for STM32F10x Connectivity line, |
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* High density, High density value line, Medium density, |
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* High density, High density value line, Medium density, |
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* Medium density Value line, Low density, Low density Value line |
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* Medium density Value line, Low density, Low density Value line |
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* and XL-density devices. |
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* and XL-density devices. |
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****************************************************************************** |
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****************************************************************************** |
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* |
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* |
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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* |
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* |
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> |
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****************************************************************************** |
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****************************************************************************** |
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*/ |
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*/ |
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|
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|
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/** @addtogroup CMSIS |
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/** @addtogroup CMSIS |
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* @{ |
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* @{ |
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*/ |
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*/ |
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|
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|
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/** @addtogroup stm32f10x |
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/** @addtogroup stm32f10x |
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* @{ |
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* @{ |
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*/ |
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*/ |
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|
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|
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#ifndef __STM32F10x_H |
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#ifndef __STM32F10x_H |
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#define __STM32F10x_H |
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#define __STM32F10x_H |
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|
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|
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#ifdef __cplusplus |
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#ifdef __cplusplus |
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extern "C" { |
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extern "C" { |
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#endif |
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#endif |
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|
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|
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/** @addtogroup Library_configuration_section |
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/** @addtogroup Library_configuration_section |
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* @{ |
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* @{ |
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*/ |
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*/ |
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|
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|
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/* Uncomment the line below according to the target STM32 device used in your |
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/* Uncomment the line below according to the target STM32 device used in your |
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application |
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application |
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*/ |
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*/ |
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|
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|
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#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) |
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#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) |
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/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ |
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/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ |
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/* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ |
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/* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ |
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/* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ |
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/* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ |
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/* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ |
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/* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ |
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/* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ |
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/* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ |
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/* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ |
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/* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ |
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/* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ |
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/* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ |
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/* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ |
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/* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ |
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#endif |
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#endif |
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/* Tip: To avoid modifying this file each time you need to switch between these |
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/* Tip: To avoid modifying this file each time you need to switch between these |
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devices, you can define the device in your toolchain compiler preprocessor. |
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devices, you can define the device in your toolchain compiler preprocessor. |
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|
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|
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- Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers |
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- Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers |
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where the Flash memory density ranges between 16 and 32 Kbytes. |
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where the Flash memory density ranges between 16 and 32 Kbytes. |
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- Low-density value line devices are STM32F100xx microcontrollers where the Flash |
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- Low-density value line devices are STM32F100xx microcontrollers where the Flash |
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memory density ranges between 16 and 32 Kbytes. |
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memory density ranges between 16 and 32 Kbytes. |
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- Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers |
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- Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers |
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where the Flash memory density ranges between 64 and 128 Kbytes. |
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where the Flash memory density ranges between 64 and 128 Kbytes. |
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- Medium-density value line devices are STM32F100xx microcontrollers where the |
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- Medium-density value line devices are STM32F100xx microcontrollers where the |
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Flash memory density ranges between 64 and 128 Kbytes. |
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Flash memory density ranges between 64 and 128 Kbytes. |
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- High-density devices are STM32F101xx and STM32F103xx microcontrollers where |
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- High-density devices are STM32F101xx and STM32F103xx microcontrollers where |
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the Flash memory density ranges between 256 and 512 Kbytes. |
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the Flash memory density ranges between 256 and 512 Kbytes. |
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- High-density value line devices are STM32F100xx microcontrollers where the |
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- High-density value line devices are STM32F100xx microcontrollers where the |
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Flash memory density ranges between 256 and 512 Kbytes. |
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Flash memory density ranges between 256 and 512 Kbytes. |
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- XL-density devices are STM32F101xx and STM32F103xx microcontrollers where |
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- XL-density devices are STM32F101xx and STM32F103xx microcontrollers where |
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the Flash memory density ranges between 512 and 1024 Kbytes. |
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the Flash memory density ranges between 512 and 1024 Kbytes. |
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- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. |
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- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. |
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*/ |
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*/ |
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|
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|
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#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) |
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#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) |
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#error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" |
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#error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" |
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#endif |
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#endif |
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|
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|
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#if !defined USE_STDPERIPH_DRIVER |
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#if !defined USE_STDPERIPH_DRIVER |
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/** |
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/** |
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* @brief Comment the line below if you will not use the peripherals drivers. |
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* @brief Comment the line below if you will not use the peripherals drivers. |
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In this case, these drivers will not be included and the application code will |
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In this case, these drivers will not be included and the application code will |
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be based on direct access to peripherals registers |
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be based on direct access to peripherals registers |
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*/ |
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*/ |
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/*#define USE_STDPERIPH_DRIVER*/ |
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/*#define USE_STDPERIPH_DRIVER*/ |
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#endif |
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#endif |
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|
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|
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/** |
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/** |
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* @brief In the following line adjust the value of External High Speed oscillator (HSE) |
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* @brief In the following line adjust the value of External High Speed oscillator (HSE) |
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used in your application |
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used in your application |
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|
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|
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Tip: To avoid modifying this file each time you need to use different HSE, you |
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Tip: To avoid modifying this file each time you need to use different HSE, you |
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can define the HSE value in your toolchain compiler preprocessor. |
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can define the HSE value in your toolchain compiler preprocessor. |
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*/ |
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*/ |
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#if !defined HSE_VALUE |
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#if !defined HSE_VALUE |
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#ifdef STM32F10X_CL |
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#ifdef STM32F10X_CL |
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ |
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ |
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#else |
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#else |
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#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ |
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#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ |
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#endif /* STM32F10X_CL */ |
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#endif /* STM32F10X_CL */ |
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#endif /* HSE_VALUE */ |
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#endif /* HSE_VALUE */ |
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|
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|
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|
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|
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/** |
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/** |
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup |
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup |
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Timeout value |
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Timeout value |
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*/ |
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*/ |
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ |
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ |
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|
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|
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#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ |
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#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ |
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|
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|
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/** |
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/** |
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* @brief STM32F10x Standard Peripheral Library version number |
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* @brief STM32F10x Standard Peripheral Library version number |
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*/ |
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*/ |
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#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ |
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#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ |
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#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ |
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#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ |
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#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ |
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#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ |
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#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ |
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#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ |
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| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ |
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| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ |
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| __STM32F10X_STDPERIPH_VERSION_SUB2) |
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| __STM32F10X_STDPERIPH_VERSION_SUB2) |
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|
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|
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/** |
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/** |
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* @} |
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* @} |
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*/ |
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*/ |
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|
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|
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/** @addtogroup Configuration_section_for_CMSIS |
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/** @addtogroup Configuration_section_for_CMSIS |
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* @{ |
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* @{ |
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*/ |
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*/ |
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|
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|
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/** |
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/** |
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* @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
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* @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
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*/ |
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*/ |
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#ifdef STM32F10X_XL |
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#ifdef STM32F10X_XL |
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#define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ |
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#define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ |
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#else |
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#else |
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#define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ |
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#define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ |
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#endif /* STM32F10X_XL */ |
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#endif /* STM32F10X_XL */ |
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#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ |
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#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ |
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
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|
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|
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/** |
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/** |
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* @brief STM32F10x Interrupt Number Definition, according to the selected device |
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* @brief STM32F10x Interrupt Number Definition, according to the selected device |
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* in @ref Library_configuration_section |
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* in @ref Library_configuration_section |
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*/ |
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*/ |
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typedef enum IRQn |
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typedef enum IRQn |
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{ |
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{ |
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/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
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/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
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|
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|
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/****** STM32 specific Interrupt Numbers *********************************************************/ |
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/****** STM32 specific Interrupt Numbers *********************************************************/ |
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WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
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WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
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PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
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PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
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TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
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TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
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RTC_IRQn = 3, /*!< RTC global Interrupt */ |
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RTC_IRQn = 3, /*!< RTC global Interrupt */ |
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FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
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FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
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RCC_IRQn = 5, /*!< RCC global Interrupt */ |
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RCC_IRQn = 5, /*!< RCC global Interrupt */ |
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EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
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EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
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EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
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EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
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EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
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EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
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EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
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EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
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EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
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EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
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DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
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DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
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DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
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DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
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DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
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DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
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DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
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DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
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DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
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DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
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DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
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DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
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DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
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DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
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|
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|
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#ifdef STM32F10X_LD |
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#ifdef STM32F10X_LD |
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ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
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ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
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USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
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USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
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USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
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USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
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CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
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CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
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TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
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TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
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TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
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TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
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TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
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TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
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TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
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TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
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USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
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USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
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USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
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USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
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USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
201 |
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
202 |
#endif /* STM32F10X_LD */ |
202 |
#endif /* STM32F10X_LD */ |
203 |
|
203 |
|
204 |
#ifdef STM32F10X_LD_VL |
204 |
#ifdef STM32F10X_LD_VL |
205 |
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
205 |
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
206 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
206 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
207 |
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
207 |
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
208 |
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
208 |
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
209 |
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
209 |
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
210 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
210 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
211 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
211 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
212 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
212 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
213 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
213 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
214 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
214 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
215 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
215 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
216 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
216 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
217 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
217 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
218 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
218 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
219 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
219 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
220 |
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
220 |
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
221 |
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
221 |
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
222 |
TIM7_IRQn = 55 /*!< TIM7 Interrupt */ |
222 |
TIM7_IRQn = 55 /*!< TIM7 Interrupt */ |
223 |
#endif /* STM32F10X_LD_VL */ |
223 |
#endif /* STM32F10X_LD_VL */ |
224 |
|
224 |
|
225 |
#ifdef STM32F10X_MD |
225 |
#ifdef STM32F10X_MD |
226 |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
226 |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
227 |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
227 |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
228 |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
228 |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
229 |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
229 |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
230 |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
230 |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
231 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
231 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
232 |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
232 |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
233 |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
233 |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
234 |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
234 |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
235 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
235 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
236 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
236 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
237 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
237 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
238 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
238 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
239 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
239 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
240 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
240 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
241 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
241 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
242 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
242 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
243 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
243 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
244 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
244 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
245 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
245 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
246 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
246 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
247 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
247 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
248 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
248 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
249 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
249 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
250 |
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
250 |
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
251 |
#endif /* STM32F10X_MD */ |
251 |
#endif /* STM32F10X_MD */ |
252 |
|
252 |
|
253 |
#ifdef STM32F10X_MD_VL |
253 |
#ifdef STM32F10X_MD_VL |
254 |
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
254 |
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
255 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
255 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
256 |
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
256 |
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
257 |
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
257 |
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
258 |
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
258 |
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
259 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
259 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
260 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
260 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
261 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
261 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
262 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
262 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
263 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
263 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
264 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
264 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
265 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
265 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
266 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
266 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
267 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
267 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
268 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
268 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
269 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
269 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
270 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
270 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
271 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
271 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
272 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
272 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
273 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
273 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
274 |
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
274 |
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
275 |
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
275 |
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
276 |
TIM7_IRQn = 55 /*!< TIM7 Interrupt */ |
276 |
TIM7_IRQn = 55 /*!< TIM7 Interrupt */ |
277 |
#endif /* STM32F10X_MD_VL */ |
277 |
#endif /* STM32F10X_MD_VL */ |
278 |
|
278 |
|
279 |
#ifdef STM32F10X_HD |
279 |
#ifdef STM32F10X_HD |
280 |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
280 |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
281 |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
281 |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
282 |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
282 |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
283 |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
283 |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
284 |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
284 |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
285 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
285 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
286 |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
286 |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
287 |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
287 |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
288 |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
288 |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
289 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
289 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
290 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
290 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
291 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
291 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
292 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
292 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
293 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
293 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
294 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
294 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
295 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
295 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
296 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
296 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
297 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
297 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
298 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
298 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
299 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
299 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
300 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
300 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
301 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
301 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
302 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
302 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
303 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
303 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
304 |
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
304 |
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
305 |
TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ |
305 |
TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ |
306 |
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ |
306 |
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ |
307 |
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ |
307 |
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ |
308 |
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
308 |
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
309 |
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
309 |
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
310 |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
310 |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
311 |
SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
311 |
SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
312 |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
312 |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
313 |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
313 |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
314 |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
314 |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
315 |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
315 |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
316 |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
316 |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
317 |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
317 |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
318 |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
318 |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
319 |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
319 |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
320 |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
320 |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
321 |
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
321 |
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
322 |
#endif /* STM32F10X_HD */ |
322 |
#endif /* STM32F10X_HD */ |
323 |
|
323 |
|
324 |
#ifdef STM32F10X_HD_VL |
324 |
#ifdef STM32F10X_HD_VL |
325 |
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
325 |
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
326 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
326 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
327 |
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
327 |
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
328 |
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
328 |
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
329 |
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
329 |
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
330 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
330 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
331 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
331 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
332 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
332 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
333 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
333 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
334 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
334 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
335 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
335 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
336 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
336 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
337 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
337 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
338 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
338 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
339 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
339 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
340 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
340 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
341 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
341 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
342 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
342 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
343 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
343 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
344 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
344 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
345 |
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
345 |
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
346 |
TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ |
346 |
TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ |
347 |
TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ |
347 |
TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ |
348 |
TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ |
348 |
TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ |
349 |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
349 |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
350 |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
350 |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
351 |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
351 |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
352 |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
352 |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
353 |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
353 |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
354 |
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
354 |
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
355 |
TIM7_IRQn = 55, /*!< TIM7 Interrupt */ |
355 |
TIM7_IRQn = 55, /*!< TIM7 Interrupt */ |
356 |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
356 |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
357 |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
357 |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
358 |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
358 |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
359 |
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
359 |
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
360 |
DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is |
360 |
DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is |
361 |
mapped at postion 60 only if the MISC_REMAP bit in |
361 |
mapped at postion 60 only if the MISC_REMAP bit in |
362 |
the AFIO_MAPR2 register is set) */ |
362 |
the AFIO_MAPR2 register is set) */ |
363 |
#endif /* STM32F10X_HD_VL */ |
363 |
#endif /* STM32F10X_HD_VL */ |
364 |
|
364 |
|
365 |
#ifdef STM32F10X_XL |
365 |
#ifdef STM32F10X_XL |
366 |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
366 |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
367 |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
367 |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
368 |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
368 |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
369 |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
369 |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
370 |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
370 |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
371 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
371 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
372 |
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ |
372 |
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ |
373 |
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ |
373 |
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ |
374 |
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
374 |
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
375 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
375 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
376 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
376 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
377 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
377 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
378 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
378 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
379 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
379 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
380 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
380 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
381 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
381 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
382 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
382 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
383 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
383 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
384 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
384 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
385 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
385 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
386 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
386 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
387 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
387 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
388 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
388 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
389 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
389 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
390 |
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
390 |
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
391 |
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ |
391 |
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ |
392 |
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ |
392 |
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ |
393 |
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ |
393 |
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ |
394 |
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
394 |
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
395 |
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
395 |
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
396 |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
396 |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
397 |
SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
397 |
SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
398 |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
398 |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
399 |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
399 |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
400 |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
400 |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
401 |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
401 |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
402 |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
402 |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
403 |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
403 |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
404 |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
404 |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
405 |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
405 |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
406 |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
406 |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
407 |
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
407 |
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
408 |
#endif /* STM32F10X_XL */ |
408 |
#endif /* STM32F10X_XL */ |
409 |
|
409 |
|
410 |
#ifdef STM32F10X_CL |
410 |
#ifdef STM32F10X_CL |
411 |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
411 |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
412 |
CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
412 |
CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
413 |
CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
413 |
CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
414 |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
414 |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
415 |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
415 |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
416 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
416 |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
417 |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
417 |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
418 |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
418 |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
419 |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
419 |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
420 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
420 |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
421 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
421 |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
422 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
422 |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
423 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
423 |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
424 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
424 |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
425 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
425 |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
426 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
426 |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
427 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
427 |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
428 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
428 |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
429 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
429 |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
430 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
430 |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
431 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
431 |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
432 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
432 |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
433 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
433 |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
434 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
434 |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
435 |
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ |
435 |
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ |
436 |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
436 |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
437 |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
437 |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
438 |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
438 |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
439 |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
439 |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
440 |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
440 |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
441 |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
441 |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
442 |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
442 |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
443 |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
443 |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
444 |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
444 |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
445 |
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
445 |
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
446 |
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
446 |
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
447 |
ETH_IRQn = 61, /*!< Ethernet global Interrupt */ |
447 |
ETH_IRQn = 61, /*!< Ethernet global Interrupt */ |
448 |
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ |
448 |
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ |
449 |
CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ |
449 |
CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ |
450 |
CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ |
450 |
CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ |
451 |
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ |
451 |
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ |
452 |
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ |
452 |
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ |
453 |
OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ |
453 |
OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ |
454 |
#endif /* STM32F10X_CL */ |
454 |
#endif /* STM32F10X_CL */ |
455 |
} IRQn_Type; |
455 |
} IRQn_Type; |
456 |
|
456 |
|
457 |
/** |
457 |
/** |
458 |
* @} |
458 |
* @} |
459 |
*/ |
459 |
*/ |
460 |
|
460 |
|
461 |
#include "core_cm3.h" |
461 |
#include "core_cm3.h" |
462 |
#include "system_stm32f10x.h" |
462 |
#include "system_stm32f10x.h" |
463 |
#include <stdint.h> |
463 |
#include <stdint.h> |
464 |
|
464 |
|
465 |
/** @addtogroup Exported_types |
465 |
/** @addtogroup Exported_types |
466 |
* @{ |
466 |
* @{ |
467 |
*/ |
467 |
*/ |
468 |
|
468 |
|
469 |
/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ |
469 |
/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ |
470 |
typedef int32_t s32; |
470 |
typedef int32_t s32; |
471 |
typedef int16_t s16; |
471 |
typedef int16_t s16; |
472 |
typedef int8_t s8; |
472 |
typedef int8_t s8; |
473 |
|
473 |
|
474 |
typedef const int32_t sc32; /*!< Read Only */ |
474 |
typedef const int32_t sc32; /*!< Read Only */ |
475 |
typedef const int16_t sc16; /*!< Read Only */ |
475 |
typedef const int16_t sc16; /*!< Read Only */ |
476 |
typedef const int8_t sc8; /*!< Read Only */ |
476 |
typedef const int8_t sc8; /*!< Read Only */ |
477 |
|
477 |
|
478 |
typedef __IO int32_t vs32; |
478 |
typedef __IO int32_t vs32; |
479 |
typedef __IO int16_t vs16; |
479 |
typedef __IO int16_t vs16; |
480 |
typedef __IO int8_t vs8; |
480 |
typedef __IO int8_t vs8; |
481 |
|
481 |
|
482 |
typedef __I int32_t vsc32; /*!< Read Only */ |
482 |
typedef __I int32_t vsc32; /*!< Read Only */ |
483 |
typedef __I int16_t vsc16; /*!< Read Only */ |
483 |
typedef __I int16_t vsc16; /*!< Read Only */ |
484 |
typedef __I int8_t vsc8; /*!< Read Only */ |
484 |
typedef __I int8_t vsc8; /*!< Read Only */ |
485 |
|
485 |
|
486 |
typedef uint32_t u32; |
486 |
typedef uint32_t u32; |
487 |
typedef uint16_t u16; |
487 |
typedef uint16_t u16; |
488 |
typedef uint8_t u8; |
488 |
typedef uint8_t u8; |
489 |
|
489 |
|
490 |
typedef const uint32_t uc32; /*!< Read Only */ |
490 |
typedef const uint32_t uc32; /*!< Read Only */ |
491 |
typedef const uint16_t uc16; /*!< Read Only */ |
491 |
typedef const uint16_t uc16; /*!< Read Only */ |
492 |
typedef const uint8_t uc8; /*!< Read Only */ |
492 |
typedef const uint8_t uc8; /*!< Read Only */ |
493 |
|
493 |
|
494 |
typedef __IO uint32_t vu32; |
494 |
typedef __IO uint32_t vu32; |
495 |
typedef __IO uint16_t vu16; |
495 |
typedef __IO uint16_t vu16; |
496 |
typedef __IO uint8_t vu8; |
496 |
typedef __IO uint8_t vu8; |
497 |
|
497 |
|
498 |
typedef __I uint32_t vuc32; /*!< Read Only */ |
498 |
typedef __I uint32_t vuc32; /*!< Read Only */ |
499 |
typedef __I uint16_t vuc16; /*!< Read Only */ |
499 |
typedef __I uint16_t vuc16; /*!< Read Only */ |
500 |
typedef __I uint8_t vuc8; /*!< Read Only */ |
500 |
typedef __I uint8_t vuc8; /*!< Read Only */ |
501 |
|
501 |
|
502 |
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; |
502 |
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; |
503 |
|
503 |
|
504 |
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; |
504 |
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; |
505 |
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
505 |
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
506 |
|
506 |
|
507 |
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; |
507 |
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; |
508 |
|
508 |
|
509 |
/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ |
509 |
/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ |
510 |
#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT |
510 |
#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT |
511 |
#define HSE_Value HSE_VALUE |
511 |
#define HSE_Value HSE_VALUE |
512 |
#define HSI_Value HSI_VALUE |
512 |
#define HSI_Value HSI_VALUE |
513 |
/** |
513 |
/** |
514 |
* @} |
514 |
* @} |
515 |
*/ |
515 |
*/ |
516 |
|
516 |
|
517 |
/** @addtogroup Peripheral_registers_structures |
517 |
/** @addtogroup Peripheral_registers_structures |
518 |
* @{ |
518 |
* @{ |
519 |
*/ |
519 |
*/ |
520 |
|
520 |
|
521 |
/** |
521 |
/** |
522 |
* @brief Analog to Digital Converter |
522 |
* @brief Analog to Digital Converter |
523 |
*/ |
523 |
*/ |
524 |
|
524 |
|
525 |
typedef struct |
525 |
typedef struct |
526 |
{ |
526 |
{ |
527 |
__IO uint32_t SR; |
527 |
__IO uint32_t SR; |
528 |
__IO uint32_t CR1; |
528 |
__IO uint32_t CR1; |
529 |
__IO uint32_t CR2; |
529 |
__IO uint32_t CR2; |
530 |
__IO uint32_t SMPR1; |
530 |
__IO uint32_t SMPR1; |
531 |
__IO uint32_t SMPR2; |
531 |
__IO uint32_t SMPR2; |
532 |
__IO uint32_t JOFR1; |
532 |
__IO uint32_t JOFR1; |
533 |
__IO uint32_t JOFR2; |
533 |
__IO uint32_t JOFR2; |
534 |
__IO uint32_t JOFR3; |
534 |
__IO uint32_t JOFR3; |
535 |
__IO uint32_t JOFR4; |
535 |
__IO uint32_t JOFR4; |
536 |
__IO uint32_t HTR; |
536 |
__IO uint32_t HTR; |
537 |
__IO uint32_t LTR; |
537 |
__IO uint32_t LTR; |
538 |
__IO uint32_t SQR1; |
538 |
__IO uint32_t SQR1; |
539 |
__IO uint32_t SQR2; |
539 |
__IO uint32_t SQR2; |
540 |
__IO uint32_t SQR3; |
540 |
__IO uint32_t SQR3; |
541 |
__IO uint32_t JSQR; |
541 |
__IO uint32_t JSQR; |
542 |
__IO uint32_t JDR1; |
542 |
__IO uint32_t JDR1; |
543 |
__IO uint32_t JDR2; |
543 |
__IO uint32_t JDR2; |
544 |
__IO uint32_t JDR3; |
544 |
__IO uint32_t JDR3; |
545 |
__IO uint32_t JDR4; |
545 |
__IO uint32_t JDR4; |
546 |
__IO uint32_t DR; |
546 |
__IO uint32_t DR; |
547 |
} ADC_TypeDef; |
547 |
} ADC_TypeDef; |
548 |
|
548 |
|
549 |
/** |
549 |
/** |
550 |
* @brief Backup Registers |
550 |
* @brief Backup Registers |
551 |
*/ |
551 |
*/ |
552 |
|
552 |
|
553 |
typedef struct |
553 |
typedef struct |
554 |
{ |
554 |
{ |
555 |
uint32_t RESERVED0; |
555 |
uint32_t RESERVED0; |
556 |
__IO uint16_t DR1; |
556 |
__IO uint16_t DR1; |
557 |
uint16_t RESERVED1; |
557 |
uint16_t RESERVED1; |
558 |
__IO uint16_t DR2; |
558 |
__IO uint16_t DR2; |
559 |
uint16_t RESERVED2; |
559 |
uint16_t RESERVED2; |
560 |
__IO uint16_t DR3; |
560 |
__IO uint16_t DR3; |
561 |
uint16_t RESERVED3; |
561 |
uint16_t RESERVED3; |
562 |
__IO uint16_t DR4; |
562 |
__IO uint16_t DR4; |
563 |
uint16_t RESERVED4; |
563 |
uint16_t RESERVED4; |
564 |
__IO uint16_t DR5; |
564 |
__IO uint16_t DR5; |
565 |
uint16_t RESERVED5; |
565 |
uint16_t RESERVED5; |
566 |
__IO uint16_t DR6; |
566 |
__IO uint16_t DR6; |
567 |
uint16_t RESERVED6; |
567 |
uint16_t RESERVED6; |
568 |
__IO uint16_t DR7; |
568 |
__IO uint16_t DR7; |
569 |
uint16_t RESERVED7; |
569 |
uint16_t RESERVED7; |
570 |
__IO uint16_t DR8; |
570 |
__IO uint16_t DR8; |
571 |
uint16_t RESERVED8; |
571 |
uint16_t RESERVED8; |
572 |
__IO uint16_t DR9; |
572 |
__IO uint16_t DR9; |
573 |
uint16_t RESERVED9; |
573 |
uint16_t RESERVED9; |
574 |
__IO uint16_t DR10; |
574 |
__IO uint16_t DR10; |
575 |
uint16_t RESERVED10; |
575 |
uint16_t RESERVED10; |
576 |
__IO uint16_t RTCCR; |
576 |
__IO uint16_t RTCCR; |
577 |
uint16_t RESERVED11; |
577 |
uint16_t RESERVED11; |
578 |
__IO uint16_t CR; |
578 |
__IO uint16_t CR; |
579 |
uint16_t RESERVED12; |
579 |
uint16_t RESERVED12; |
580 |
__IO uint16_t CSR; |
580 |
__IO uint16_t CSR; |
581 |
uint16_t RESERVED13[5]; |
581 |
uint16_t RESERVED13[5]; |
582 |
__IO uint16_t DR11; |
582 |
__IO uint16_t DR11; |
583 |
uint16_t RESERVED14; |
583 |
uint16_t RESERVED14; |
584 |
__IO uint16_t DR12; |
584 |
__IO uint16_t DR12; |
585 |
uint16_t RESERVED15; |
585 |
uint16_t RESERVED15; |
586 |
__IO uint16_t DR13; |
586 |
__IO uint16_t DR13; |
587 |
uint16_t RESERVED16; |
587 |
uint16_t RESERVED16; |
588 |
__IO uint16_t DR14; |
588 |
__IO uint16_t DR14; |
589 |
uint16_t RESERVED17; |
589 |
uint16_t RESERVED17; |
590 |
__IO uint16_t DR15; |
590 |
__IO uint16_t DR15; |
591 |
uint16_t RESERVED18; |
591 |
uint16_t RESERVED18; |
592 |
__IO uint16_t DR16; |
592 |
__IO uint16_t DR16; |
593 |
uint16_t RESERVED19; |
593 |
uint16_t RESERVED19; |
594 |
__IO uint16_t DR17; |
594 |
__IO uint16_t DR17; |
595 |
uint16_t RESERVED20; |
595 |
uint16_t RESERVED20; |
596 |
__IO uint16_t DR18; |
596 |
__IO uint16_t DR18; |
597 |
uint16_t RESERVED21; |
597 |
uint16_t RESERVED21; |
598 |
__IO uint16_t DR19; |
598 |
__IO uint16_t DR19; |
599 |
uint16_t RESERVED22; |
599 |
uint16_t RESERVED22; |
600 |
__IO uint16_t DR20; |
600 |
__IO uint16_t DR20; |
601 |
uint16_t RESERVED23; |
601 |
uint16_t RESERVED23; |
602 |
__IO uint16_t DR21; |
602 |
__IO uint16_t DR21; |
603 |
uint16_t RESERVED24; |
603 |
uint16_t RESERVED24; |
604 |
__IO uint16_t DR22; |
604 |
__IO uint16_t DR22; |
605 |
uint16_t RESERVED25; |
605 |
uint16_t RESERVED25; |
606 |
__IO uint16_t DR23; |
606 |
__IO uint16_t DR23; |
607 |
uint16_t RESERVED26; |
607 |
uint16_t RESERVED26; |
608 |
__IO uint16_t DR24; |
608 |
__IO uint16_t DR24; |
609 |
uint16_t RESERVED27; |
609 |
uint16_t RESERVED27; |
610 |
__IO uint16_t DR25; |
610 |
__IO uint16_t DR25; |
611 |
uint16_t RESERVED28; |
611 |
uint16_t RESERVED28; |
612 |
__IO uint16_t DR26; |
612 |
__IO uint16_t DR26; |
613 |
uint16_t RESERVED29; |
613 |
uint16_t RESERVED29; |
614 |
__IO uint16_t DR27; |
614 |
__IO uint16_t DR27; |
615 |
uint16_t RESERVED30; |
615 |
uint16_t RESERVED30; |
616 |
__IO uint16_t DR28; |
616 |
__IO uint16_t DR28; |
617 |
uint16_t RESERVED31; |
617 |
uint16_t RESERVED31; |
618 |
__IO uint16_t DR29; |
618 |
__IO uint16_t DR29; |
619 |
uint16_t RESERVED32; |
619 |
uint16_t RESERVED32; |
620 |
__IO uint16_t DR30; |
620 |
__IO uint16_t DR30; |
621 |
uint16_t RESERVED33; |
621 |
uint16_t RESERVED33; |
622 |
__IO uint16_t DR31; |
622 |
__IO uint16_t DR31; |
623 |
uint16_t RESERVED34; |
623 |
uint16_t RESERVED34; |
624 |
__IO uint16_t DR32; |
624 |
__IO uint16_t DR32; |
625 |
uint16_t RESERVED35; |
625 |
uint16_t RESERVED35; |
626 |
__IO uint16_t DR33; |
626 |
__IO uint16_t DR33; |
627 |
uint16_t RESERVED36; |
627 |
uint16_t RESERVED36; |
628 |
__IO uint16_t DR34; |
628 |
__IO uint16_t DR34; |
629 |
uint16_t RESERVED37; |
629 |
uint16_t RESERVED37; |
630 |
__IO uint16_t DR35; |
630 |
__IO uint16_t DR35; |
631 |
uint16_t RESERVED38; |
631 |
uint16_t RESERVED38; |
632 |
__IO uint16_t DR36; |
632 |
__IO uint16_t DR36; |
633 |
uint16_t RESERVED39; |
633 |
uint16_t RESERVED39; |
634 |
__IO uint16_t DR37; |
634 |
__IO uint16_t DR37; |
635 |
uint16_t RESERVED40; |
635 |
uint16_t RESERVED40; |
636 |
__IO uint16_t DR38; |
636 |
__IO uint16_t DR38; |
637 |
uint16_t RESERVED41; |
637 |
uint16_t RESERVED41; |
638 |
__IO uint16_t DR39; |
638 |
__IO uint16_t DR39; |
639 |
uint16_t RESERVED42; |
639 |
uint16_t RESERVED42; |
640 |
__IO uint16_t DR40; |
640 |
__IO uint16_t DR40; |
641 |
uint16_t RESERVED43; |
641 |
uint16_t RESERVED43; |
642 |
__IO uint16_t DR41; |
642 |
__IO uint16_t DR41; |
643 |
uint16_t RESERVED44; |
643 |
uint16_t RESERVED44; |
644 |
__IO uint16_t DR42; |
644 |
__IO uint16_t DR42; |
645 |
uint16_t RESERVED45; |
645 |
uint16_t RESERVED45; |
646 |
} BKP_TypeDef; |
646 |
} BKP_TypeDef; |
647 |
|
647 |
|
648 |
/** |
648 |
/** |
649 |
* @brief Controller Area Network TxMailBox |
649 |
* @brief Controller Area Network TxMailBox |
650 |
*/ |
650 |
*/ |
651 |
|
651 |
|
652 |
typedef struct |
652 |
typedef struct |
653 |
{ |
653 |
{ |
654 |
__IO uint32_t TIR; |
654 |
__IO uint32_t TIR; |
655 |
__IO uint32_t TDTR; |
655 |
__IO uint32_t TDTR; |
656 |
__IO uint32_t TDLR; |
656 |
__IO uint32_t TDLR; |
657 |
__IO uint32_t TDHR; |
657 |
__IO uint32_t TDHR; |
658 |
} CAN_TxMailBox_TypeDef; |
658 |
} CAN_TxMailBox_TypeDef; |
659 |
|
659 |
|
660 |
/** |
660 |
/** |
661 |
* @brief Controller Area Network FIFOMailBox |
661 |
* @brief Controller Area Network FIFOMailBox |
662 |
*/ |
662 |
*/ |
663 |
|
663 |
|
664 |
typedef struct |
664 |
typedef struct |
665 |
{ |
665 |
{ |
666 |
__IO uint32_t RIR; |
666 |
__IO uint32_t RIR; |
667 |
__IO uint32_t RDTR; |
667 |
__IO uint32_t RDTR; |
668 |
__IO uint32_t RDLR; |
668 |
__IO uint32_t RDLR; |
669 |
__IO uint32_t RDHR; |
669 |
__IO uint32_t RDHR; |
670 |
} CAN_FIFOMailBox_TypeDef; |
670 |
} CAN_FIFOMailBox_TypeDef; |
671 |
|
671 |
|
672 |
/** |
672 |
/** |
673 |
* @brief Controller Area Network FilterRegister |
673 |
* @brief Controller Area Network FilterRegister |
674 |
*/ |
674 |
*/ |
675 |
|
675 |
|
676 |
typedef struct |
676 |
typedef struct |
677 |
{ |
677 |
{ |
678 |
__IO uint32_t FR1; |
678 |
__IO uint32_t FR1; |
679 |
__IO uint32_t FR2; |
679 |
__IO uint32_t FR2; |
680 |
} CAN_FilterRegister_TypeDef; |
680 |
} CAN_FilterRegister_TypeDef; |
681 |
|
681 |
|
682 |
/** |
682 |
/** |
683 |
* @brief Controller Area Network |
683 |
* @brief Controller Area Network |
684 |
*/ |
684 |
*/ |
685 |
|
685 |
|
686 |
typedef struct |
686 |
typedef struct |
687 |
{ |
687 |
{ |
688 |
__IO uint32_t MCR; |
688 |
__IO uint32_t MCR; |
689 |
__IO uint32_t MSR; |
689 |
__IO uint32_t MSR; |
690 |
__IO uint32_t TSR; |
690 |
__IO uint32_t TSR; |
691 |
__IO uint32_t RF0R; |
691 |
__IO uint32_t RF0R; |
692 |
__IO uint32_t RF1R; |
692 |
__IO uint32_t RF1R; |
693 |
__IO uint32_t IER; |
693 |
__IO uint32_t IER; |
694 |
__IO uint32_t ESR; |
694 |
__IO uint32_t ESR; |
695 |
__IO uint32_t BTR; |
695 |
__IO uint32_t BTR; |
696 |
uint32_t RESERVED0[88]; |
696 |
uint32_t RESERVED0[88]; |
697 |
CAN_TxMailBox_TypeDef sTxMailBox[3]; |
697 |
CAN_TxMailBox_TypeDef sTxMailBox[3]; |
698 |
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; |
698 |
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; |
699 |
uint32_t RESERVED1[12]; |
699 |
uint32_t RESERVED1[12]; |
700 |
__IO uint32_t FMR; |
700 |
__IO uint32_t FMR; |
701 |
__IO uint32_t FM1R; |
701 |
__IO uint32_t FM1R; |
702 |
uint32_t RESERVED2; |
702 |
uint32_t RESERVED2; |
703 |
__IO uint32_t FS1R; |
703 |
__IO uint32_t FS1R; |
704 |
uint32_t RESERVED3; |
704 |
uint32_t RESERVED3; |
705 |
__IO uint32_t FFA1R; |
705 |
__IO uint32_t FFA1R; |
706 |
uint32_t RESERVED4; |
706 |
uint32_t RESERVED4; |
707 |
__IO uint32_t FA1R; |
707 |
__IO uint32_t FA1R; |
708 |
uint32_t RESERVED5[8]; |
708 |
uint32_t RESERVED5[8]; |
709 |
#ifndef STM32F10X_CL |
709 |
#ifndef STM32F10X_CL |
710 |
CAN_FilterRegister_TypeDef sFilterRegister[14]; |
710 |
CAN_FilterRegister_TypeDef sFilterRegister[14]; |
711 |
#else |
711 |
#else |
712 |
CAN_FilterRegister_TypeDef sFilterRegister[28]; |
712 |
CAN_FilterRegister_TypeDef sFilterRegister[28]; |
713 |
#endif /* STM32F10X_CL */ |
713 |
#endif /* STM32F10X_CL */ |
714 |
} CAN_TypeDef; |
714 |
} CAN_TypeDef; |
715 |
|
715 |
|
716 |
/** |
716 |
/** |
717 |
* @brief Consumer Electronics Control (CEC) |
717 |
* @brief Consumer Electronics Control (CEC) |
718 |
*/ |
718 |
*/ |
719 |
typedef struct |
719 |
typedef struct |
720 |
{ |
720 |
{ |
721 |
__IO uint32_t CFGR; |
721 |
__IO uint32_t CFGR; |
722 |
__IO uint32_t OAR; |
722 |
__IO uint32_t OAR; |
723 |
__IO uint32_t PRES; |
723 |
__IO uint32_t PRES; |
724 |
__IO uint32_t ESR; |
724 |
__IO uint32_t ESR; |
725 |
__IO uint32_t CSR; |
725 |
__IO uint32_t CSR; |
726 |
__IO uint32_t TXD; |
726 |
__IO uint32_t TXD; |
727 |
__IO uint32_t RXD; |
727 |
__IO uint32_t RXD; |
728 |
} CEC_TypeDef; |
728 |
} CEC_TypeDef; |
729 |
|
729 |
|
730 |
/** |
730 |
/** |
731 |
* @brief CRC calculation unit |
731 |
* @brief CRC calculation unit |
732 |
*/ |
732 |
*/ |
733 |
|
733 |
|
734 |
typedef struct |
734 |
typedef struct |
735 |
{ |
735 |
{ |
736 |
__IO uint32_t DR; |
736 |
__IO uint32_t DR; |
737 |
__IO uint8_t IDR; |
737 |
__IO uint8_t IDR; |
738 |
uint8_t RESERVED0; |
738 |
uint8_t RESERVED0; |
739 |
uint16_t RESERVED1; |
739 |
uint16_t RESERVED1; |
740 |
__IO uint32_t CR; |
740 |
__IO uint32_t CR; |
741 |
} CRC_TypeDef; |
741 |
} CRC_TypeDef; |
742 |
|
742 |
|
743 |
/** |
743 |
/** |
744 |
* @brief Digital to Analog Converter |
744 |
* @brief Digital to Analog Converter |
745 |
*/ |
745 |
*/ |
746 |
|
746 |
|
747 |
typedef struct |
747 |
typedef struct |
748 |
{ |
748 |
{ |
749 |
__IO uint32_t CR; |
749 |
__IO uint32_t CR; |
750 |
__IO uint32_t SWTRIGR; |
750 |
__IO uint32_t SWTRIGR; |
751 |
__IO uint32_t DHR12R1; |
751 |
__IO uint32_t DHR12R1; |
752 |
__IO uint32_t DHR12L1; |
752 |
__IO uint32_t DHR12L1; |
753 |
__IO uint32_t DHR8R1; |
753 |
__IO uint32_t DHR8R1; |
754 |
__IO uint32_t DHR12R2; |
754 |
__IO uint32_t DHR12R2; |
755 |
__IO uint32_t DHR12L2; |
755 |
__IO uint32_t DHR12L2; |
756 |
__IO uint32_t DHR8R2; |
756 |
__IO uint32_t DHR8R2; |
757 |
__IO uint32_t DHR12RD; |
757 |
__IO uint32_t DHR12RD; |
758 |
__IO uint32_t DHR12LD; |
758 |
__IO uint32_t DHR12LD; |
759 |
__IO uint32_t DHR8RD; |
759 |
__IO uint32_t DHR8RD; |
760 |
__IO uint32_t DOR1; |
760 |
__IO uint32_t DOR1; |
761 |
__IO uint32_t DOR2; |
761 |
__IO uint32_t DOR2; |
762 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
762 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
763 |
__IO uint32_t SR; |
763 |
__IO uint32_t SR; |
764 |
#endif |
764 |
#endif |
765 |
} DAC_TypeDef; |
765 |
} DAC_TypeDef; |
766 |
|
766 |
|
767 |
/** |
767 |
/** |
768 |
* @brief Debug MCU |
768 |
* @brief Debug MCU |
769 |
*/ |
769 |
*/ |
770 |
|
770 |
|
771 |
typedef struct |
771 |
typedef struct |
772 |
{ |
772 |
{ |
773 |
__IO uint32_t IDCODE; |
773 |
__IO uint32_t IDCODE; |
774 |
__IO uint32_t CR; |
774 |
__IO uint32_t CR; |
775 |
}DBGMCU_TypeDef; |
775 |
}DBGMCU_TypeDef; |
776 |
|
776 |
|
777 |
/** |
777 |
/** |
778 |
* @brief DMA Controller |
778 |
* @brief DMA Controller |
779 |
*/ |
779 |
*/ |
780 |
|
780 |
|
781 |
typedef struct |
781 |
typedef struct |
782 |
{ |
782 |
{ |
783 |
__IO uint32_t CCR; |
783 |
__IO uint32_t CCR; |
784 |
__IO uint32_t CNDTR; |
784 |
__IO uint32_t CNDTR; |
785 |
__IO uint32_t CPAR; |
785 |
__IO uint32_t CPAR; |
786 |
__IO uint32_t CMAR; |
786 |
__IO uint32_t CMAR; |
787 |
} DMA_Channel_TypeDef; |
787 |
} DMA_Channel_TypeDef; |
788 |
|
788 |
|
789 |
typedef struct |
789 |
typedef struct |
790 |
{ |
790 |
{ |
791 |
__IO uint32_t ISR; |
791 |
__IO uint32_t ISR; |
792 |
__IO uint32_t IFCR; |
792 |
__IO uint32_t IFCR; |
793 |
} DMA_TypeDef; |
793 |
} DMA_TypeDef; |
794 |
|
794 |
|
795 |
/** |
795 |
/** |
796 |
* @brief Ethernet MAC |
796 |
* @brief Ethernet MAC |
797 |
*/ |
797 |
*/ |
798 |
|
798 |
|
799 |
typedef struct |
799 |
typedef struct |
800 |
{ |
800 |
{ |
801 |
__IO uint32_t MACCR; |
801 |
__IO uint32_t MACCR; |
802 |
__IO uint32_t MACFFR; |
802 |
__IO uint32_t MACFFR; |
803 |
__IO uint32_t MACHTHR; |
803 |
__IO uint32_t MACHTHR; |
804 |
__IO uint32_t MACHTLR; |
804 |
__IO uint32_t MACHTLR; |
805 |
__IO uint32_t MACMIIAR; |
805 |
__IO uint32_t MACMIIAR; |
806 |
__IO uint32_t MACMIIDR; |
806 |
__IO uint32_t MACMIIDR; |
807 |
__IO uint32_t MACFCR; |
807 |
__IO uint32_t MACFCR; |
808 |
__IO uint32_t MACVLANTR; /* 8 */ |
808 |
__IO uint32_t MACVLANTR; /* 8 */ |
809 |
uint32_t RESERVED0[2]; |
809 |
uint32_t RESERVED0[2]; |
810 |
__IO uint32_t MACRWUFFR; /* 11 */ |
810 |
__IO uint32_t MACRWUFFR; /* 11 */ |
811 |
__IO uint32_t MACPMTCSR; |
811 |
__IO uint32_t MACPMTCSR; |
812 |
uint32_t RESERVED1[2]; |
812 |
uint32_t RESERVED1[2]; |
813 |
__IO uint32_t MACSR; /* 15 */ |
813 |
__IO uint32_t MACSR; /* 15 */ |
814 |
__IO uint32_t MACIMR; |
814 |
__IO uint32_t MACIMR; |
815 |
__IO uint32_t MACA0HR; |
815 |
__IO uint32_t MACA0HR; |
816 |
__IO uint32_t MACA0LR; |
816 |
__IO uint32_t MACA0LR; |
817 |
__IO uint32_t MACA1HR; |
817 |
__IO uint32_t MACA1HR; |
818 |
__IO uint32_t MACA1LR; |
818 |
__IO uint32_t MACA1LR; |
819 |
__IO uint32_t MACA2HR; |
819 |
__IO uint32_t MACA2HR; |
820 |
__IO uint32_t MACA2LR; |
820 |
__IO uint32_t MACA2LR; |
821 |
__IO uint32_t MACA3HR; |
821 |
__IO uint32_t MACA3HR; |
822 |
__IO uint32_t MACA3LR; /* 24 */ |
822 |
__IO uint32_t MACA3LR; /* 24 */ |
823 |
uint32_t RESERVED2[40]; |
823 |
uint32_t RESERVED2[40]; |
824 |
__IO uint32_t MMCCR; /* 65 */ |
824 |
__IO uint32_t MMCCR; /* 65 */ |
825 |
__IO uint32_t MMCRIR; |
825 |
__IO uint32_t MMCRIR; |
826 |
__IO uint32_t MMCTIR; |
826 |
__IO uint32_t MMCTIR; |
827 |
__IO uint32_t MMCRIMR; |
827 |
__IO uint32_t MMCRIMR; |
828 |
__IO uint32_t MMCTIMR; /* 69 */ |
828 |
__IO uint32_t MMCTIMR; /* 69 */ |
829 |
uint32_t RESERVED3[14]; |
829 |
uint32_t RESERVED3[14]; |
830 |
__IO uint32_t MMCTGFSCCR; /* 84 */ |
830 |
__IO uint32_t MMCTGFSCCR; /* 84 */ |
831 |
__IO uint32_t MMCTGFMSCCR; |
831 |
__IO uint32_t MMCTGFMSCCR; |
832 |
uint32_t RESERVED4[5]; |
832 |
uint32_t RESERVED4[5]; |
833 |
__IO uint32_t MMCTGFCR; |
833 |
__IO uint32_t MMCTGFCR; |
834 |
uint32_t RESERVED5[10]; |
834 |
uint32_t RESERVED5[10]; |
835 |
__IO uint32_t MMCRFCECR; |
835 |
__IO uint32_t MMCRFCECR; |
836 |
__IO uint32_t MMCRFAECR; |
836 |
__IO uint32_t MMCRFAECR; |
837 |
uint32_t RESERVED6[10]; |
837 |
uint32_t RESERVED6[10]; |
838 |
__IO uint32_t MMCRGUFCR; |
838 |
__IO uint32_t MMCRGUFCR; |
839 |
uint32_t RESERVED7[334]; |
839 |
uint32_t RESERVED7[334]; |
840 |
__IO uint32_t PTPTSCR; |
840 |
__IO uint32_t PTPTSCR; |
841 |
__IO uint32_t PTPSSIR; |
841 |
__IO uint32_t PTPSSIR; |
842 |
__IO uint32_t PTPTSHR; |
842 |
__IO uint32_t PTPTSHR; |
843 |
__IO uint32_t PTPTSLR; |
843 |
__IO uint32_t PTPTSLR; |
844 |
__IO uint32_t PTPTSHUR; |
844 |
__IO uint32_t PTPTSHUR; |
845 |
__IO uint32_t PTPTSLUR; |
845 |
__IO uint32_t PTPTSLUR; |
846 |
__IO uint32_t PTPTSAR; |
846 |
__IO uint32_t PTPTSAR; |
847 |
__IO uint32_t PTPTTHR; |
847 |
__IO uint32_t PTPTTHR; |
848 |
__IO uint32_t PTPTTLR; |
848 |
__IO uint32_t PTPTTLR; |
849 |
uint32_t RESERVED8[567]; |
849 |
uint32_t RESERVED8[567]; |
850 |
__IO uint32_t DMABMR; |
850 |
__IO uint32_t DMABMR; |
851 |
__IO uint32_t DMATPDR; |
851 |
__IO uint32_t DMATPDR; |
852 |
__IO uint32_t DMARPDR; |
852 |
__IO uint32_t DMARPDR; |
853 |
__IO uint32_t DMARDLAR; |
853 |
__IO uint32_t DMARDLAR; |
854 |
__IO uint32_t DMATDLAR; |
854 |
__IO uint32_t DMATDLAR; |
855 |
__IO uint32_t DMASR; |
855 |
__IO uint32_t DMASR; |
856 |
__IO uint32_t DMAOMR; |
856 |
__IO uint32_t DMAOMR; |
857 |
__IO uint32_t DMAIER; |
857 |
__IO uint32_t DMAIER; |
858 |
__IO uint32_t DMAMFBOCR; |
858 |
__IO uint32_t DMAMFBOCR; |
859 |
uint32_t RESERVED9[9]; |
859 |
uint32_t RESERVED9[9]; |
860 |
__IO uint32_t DMACHTDR; |
860 |
__IO uint32_t DMACHTDR; |
861 |
__IO uint32_t DMACHRDR; |
861 |
__IO uint32_t DMACHRDR; |
862 |
__IO uint32_t DMACHTBAR; |
862 |
__IO uint32_t DMACHTBAR; |
863 |
__IO uint32_t DMACHRBAR; |
863 |
__IO uint32_t DMACHRBAR; |
864 |
} ETH_TypeDef; |
864 |
} ETH_TypeDef; |
865 |
|
865 |
|
866 |
/** |
866 |
/** |
867 |
* @brief External Interrupt/Event Controller |
867 |
* @brief External Interrupt/Event Controller |
868 |
*/ |
868 |
*/ |
869 |
|
869 |
|
870 |
typedef struct |
870 |
typedef struct |
871 |
{ |
871 |
{ |
872 |
__IO uint32_t IMR; |
872 |
__IO uint32_t IMR; |
873 |
__IO uint32_t EMR; |
873 |
__IO uint32_t EMR; |
874 |
__IO uint32_t RTSR; |
874 |
__IO uint32_t RTSR; |
875 |
__IO uint32_t FTSR; |
875 |
__IO uint32_t FTSR; |
876 |
__IO uint32_t SWIER; |
876 |
__IO uint32_t SWIER; |
877 |
__IO uint32_t PR; |
877 |
__IO uint32_t PR; |
878 |
} EXTI_TypeDef; |
878 |
} EXTI_TypeDef; |
879 |
|
879 |
|
880 |
/** |
880 |
/** |
881 |
* @brief FLASH Registers |
881 |
* @brief FLASH Registers |
882 |
*/ |
882 |
*/ |
883 |
|
883 |
|
884 |
typedef struct |
884 |
typedef struct |
885 |
{ |
885 |
{ |
886 |
__IO uint32_t ACR; |
886 |
__IO uint32_t ACR; |
887 |
__IO uint32_t KEYR; |
887 |
__IO uint32_t KEYR; |
888 |
__IO uint32_t OPTKEYR; |
888 |
__IO uint32_t OPTKEYR; |
889 |
__IO uint32_t SR; |
889 |
__IO uint32_t SR; |
890 |
__IO uint32_t CR; |
890 |
__IO uint32_t CR; |
891 |
__IO uint32_t AR; |
891 |
__IO uint32_t AR; |
892 |
__IO uint32_t RESERVED; |
892 |
__IO uint32_t RESERVED; |
893 |
__IO uint32_t OBR; |
893 |
__IO uint32_t OBR; |
894 |
__IO uint32_t WRPR; |
894 |
__IO uint32_t WRPR; |
895 |
#ifdef STM32F10X_XL |
895 |
#ifdef STM32F10X_XL |
896 |
uint32_t RESERVED1[8]; |
896 |
uint32_t RESERVED1[8]; |
897 |
__IO uint32_t KEYR2; |
897 |
__IO uint32_t KEYR2; |
898 |
uint32_t RESERVED2; |
898 |
uint32_t RESERVED2; |
899 |
__IO uint32_t SR2; |
899 |
__IO uint32_t SR2; |
900 |
__IO uint32_t CR2; |
900 |
__IO uint32_t CR2; |
901 |
__IO uint32_t AR2; |
901 |
__IO uint32_t AR2; |
902 |
#endif /* STM32F10X_XL */ |
902 |
#endif /* STM32F10X_XL */ |
903 |
} FLASH_TypeDef; |
903 |
} FLASH_TypeDef; |
904 |
|
904 |
|
905 |
/** |
905 |
/** |
906 |
* @brief Option Bytes Registers |
906 |
* @brief Option Bytes Registers |
907 |
*/ |
907 |
*/ |
908 |
|
908 |
|
909 |
typedef struct |
909 |
typedef struct |
910 |
{ |
910 |
{ |
911 |
__IO uint16_t RDP; |
911 |
__IO uint16_t RDP; |
912 |
__IO uint16_t USER; |
912 |
__IO uint16_t USER; |
913 |
__IO uint16_t Data0; |
913 |
__IO uint16_t Data0; |
914 |
__IO uint16_t Data1; |
914 |
__IO uint16_t Data1; |
915 |
__IO uint16_t WRP0; |
915 |
__IO uint16_t WRP0; |
916 |
__IO uint16_t WRP1; |
916 |
__IO uint16_t WRP1; |
917 |
__IO uint16_t WRP2; |
917 |
__IO uint16_t WRP2; |
918 |
__IO uint16_t WRP3; |
918 |
__IO uint16_t WRP3; |
919 |
} OB_TypeDef; |
919 |
} OB_TypeDef; |
920 |
|
920 |
|
921 |
/** |
921 |
/** |
922 |
* @brief Flexible Static Memory Controller |
922 |
* @brief Flexible Static Memory Controller |
923 |
*/ |
923 |
*/ |
924 |
|
924 |
|
925 |
typedef struct |
925 |
typedef struct |
926 |
{ |
926 |
{ |
927 |
__IO uint32_t BTCR[8]; |
927 |
__IO uint32_t BTCR[8]; |
928 |
} FSMC_Bank1_TypeDef; |
928 |
} FSMC_Bank1_TypeDef; |
929 |
|
929 |
|
930 |
/** |
930 |
/** |
931 |
* @brief Flexible Static Memory Controller Bank1E |
931 |
* @brief Flexible Static Memory Controller Bank1E |
932 |
*/ |
932 |
*/ |
933 |
|
933 |
|
934 |
typedef struct |
934 |
typedef struct |
935 |
{ |
935 |
{ |
936 |
__IO uint32_t BWTR[7]; |
936 |
__IO uint32_t BWTR[7]; |
937 |
} FSMC_Bank1E_TypeDef; |
937 |
} FSMC_Bank1E_TypeDef; |
938 |
|
938 |
|
939 |
/** |
939 |
/** |
940 |
* @brief Flexible Static Memory Controller Bank2 |
940 |
* @brief Flexible Static Memory Controller Bank2 |
941 |
*/ |
941 |
*/ |
942 |
|
942 |
|
943 |
typedef struct |
943 |
typedef struct |
944 |
{ |
944 |
{ |
945 |
__IO uint32_t PCR2; |
945 |
__IO uint32_t PCR2; |
946 |
__IO uint32_t SR2; |
946 |
__IO uint32_t SR2; |
947 |
__IO uint32_t PMEM2; |
947 |
__IO uint32_t PMEM2; |
948 |
__IO uint32_t PATT2; |
948 |
__IO uint32_t PATT2; |
949 |
uint32_t RESERVED0; |
949 |
uint32_t RESERVED0; |
950 |
__IO uint32_t ECCR2; |
950 |
__IO uint32_t ECCR2; |
951 |
} FSMC_Bank2_TypeDef; |
951 |
} FSMC_Bank2_TypeDef; |
952 |
|
952 |
|
953 |
/** |
953 |
/** |
954 |
* @brief Flexible Static Memory Controller Bank3 |
954 |
* @brief Flexible Static Memory Controller Bank3 |
955 |
*/ |
955 |
*/ |
956 |
|
956 |
|
957 |
typedef struct |
957 |
typedef struct |
958 |
{ |
958 |
{ |
959 |
__IO uint32_t PCR3; |
959 |
__IO uint32_t PCR3; |
960 |
__IO uint32_t SR3; |
960 |
__IO uint32_t SR3; |
961 |
__IO uint32_t PMEM3; |
961 |
__IO uint32_t PMEM3; |
962 |
__IO uint32_t PATT3; |
962 |
__IO uint32_t PATT3; |
963 |
uint32_t RESERVED0; |
963 |
uint32_t RESERVED0; |
964 |
__IO uint32_t ECCR3; |
964 |
__IO uint32_t ECCR3; |
965 |
} FSMC_Bank3_TypeDef; |
965 |
} FSMC_Bank3_TypeDef; |
966 |
|
966 |
|
967 |
/** |
967 |
/** |
968 |
* @brief Flexible Static Memory Controller Bank4 |
968 |
* @brief Flexible Static Memory Controller Bank4 |
969 |
*/ |
969 |
*/ |
970 |
|
970 |
|
971 |
typedef struct |
971 |
typedef struct |
972 |
{ |
972 |
{ |
973 |
__IO uint32_t PCR4; |
973 |
__IO uint32_t PCR4; |
974 |
__IO uint32_t SR4; |
974 |
__IO uint32_t SR4; |
975 |
__IO uint32_t PMEM4; |
975 |
__IO uint32_t PMEM4; |
976 |
__IO uint32_t PATT4; |
976 |
__IO uint32_t PATT4; |
977 |
__IO uint32_t PIO4; |
977 |
__IO uint32_t PIO4; |
978 |
} FSMC_Bank4_TypeDef; |
978 |
} FSMC_Bank4_TypeDef; |
979 |
|
979 |
|
980 |
/** |
980 |
/** |
981 |
* @brief General Purpose I/O |
981 |
* @brief General Purpose I/O |
982 |
*/ |
982 |
*/ |
983 |
|
983 |
|
984 |
typedef struct |
984 |
typedef struct |
985 |
{ |
985 |
{ |
986 |
__IO uint32_t CRL; |
986 |
__IO uint32_t CRL; |
987 |
__IO uint32_t CRH; |
987 |
__IO uint32_t CRH; |
988 |
__IO uint32_t IDR; |
988 |
__IO uint32_t IDR; |
989 |
__IO uint32_t ODR; |
989 |
__IO uint32_t ODR; |
990 |
__IO uint32_t BSRR; |
990 |
__IO uint32_t BSRR; |
991 |
__IO uint32_t BRR; |
991 |
__IO uint32_t BRR; |
992 |
__IO uint32_t LCKR; |
992 |
__IO uint32_t LCKR; |
993 |
} GPIO_TypeDef; |
993 |
} GPIO_TypeDef; |
994 |
|
994 |
|
995 |
/** |
995 |
/** |
996 |
* @brief Alternate Function I/O |
996 |
* @brief Alternate Function I/O |
997 |
*/ |
997 |
*/ |
998 |
|
998 |
|
999 |
typedef struct |
999 |
typedef struct |
1000 |
{ |
1000 |
{ |
1001 |
__IO uint32_t EVCR; |
1001 |
__IO uint32_t EVCR; |
1002 |
__IO uint32_t MAPR; |
1002 |
__IO uint32_t MAPR; |
1003 |
__IO uint32_t EXTICR[4]; |
1003 |
__IO uint32_t EXTICR[4]; |
1004 |
uint32_t RESERVED0; |
1004 |
uint32_t RESERVED0; |
1005 |
__IO uint32_t MAPR2; |
1005 |
__IO uint32_t MAPR2; |
1006 |
} AFIO_TypeDef; |
1006 |
} AFIO_TypeDef; |
1007 |
/** |
1007 |
/** |
1008 |
* @brief Inter-integrated Circuit Interface |
1008 |
* @brief Inter-integrated Circuit Interface |
1009 |
*/ |
1009 |
*/ |
1010 |
|
1010 |
|
1011 |
typedef struct |
1011 |
typedef struct |
1012 |
{ |
1012 |
{ |
1013 |
__IO uint16_t CR1; |
1013 |
__IO uint16_t CR1; |
1014 |
uint16_t RESERVED0; |
1014 |
uint16_t RESERVED0; |
1015 |
__IO uint16_t CR2; |
1015 |
__IO uint16_t CR2; |
1016 |
uint16_t RESERVED1; |
1016 |
uint16_t RESERVED1; |
1017 |
__IO uint16_t OAR1; |
1017 |
__IO uint16_t OAR1; |
1018 |
uint16_t RESERVED2; |
1018 |
uint16_t RESERVED2; |
1019 |
__IO uint16_t OAR2; |
1019 |
__IO uint16_t OAR2; |
1020 |
uint16_t RESERVED3; |
1020 |
uint16_t RESERVED3; |
1021 |
__IO uint16_t DR; |
1021 |
__IO uint16_t DR; |
1022 |
uint16_t RESERVED4; |
1022 |
uint16_t RESERVED4; |
1023 |
__IO uint16_t SR1; |
1023 |
__IO uint16_t SR1; |
1024 |
uint16_t RESERVED5; |
1024 |
uint16_t RESERVED5; |
1025 |
__IO uint16_t SR2; |
1025 |
__IO uint16_t SR2; |
1026 |
uint16_t RESERVED6; |
1026 |
uint16_t RESERVED6; |
1027 |
__IO uint16_t CCR; |
1027 |
__IO uint16_t CCR; |
1028 |
uint16_t RESERVED7; |
1028 |
uint16_t RESERVED7; |
1029 |
__IO uint16_t TRISE; |
1029 |
__IO uint16_t TRISE; |
1030 |
uint16_t RESERVED8; |
1030 |
uint16_t RESERVED8; |
1031 |
} I2C_TypeDef; |
1031 |
} I2C_TypeDef; |
1032 |
|
1032 |
|
1033 |
/** |
1033 |
/** |
1034 |
* @brief Independent WATCHDOG |
1034 |
* @brief Independent WATCHDOG |
1035 |
*/ |
1035 |
*/ |
1036 |
|
1036 |
|
1037 |
typedef struct |
1037 |
typedef struct |
1038 |
{ |
1038 |
{ |
1039 |
__IO uint32_t KR; |
1039 |
__IO uint32_t KR; |
1040 |
__IO uint32_t PR; |
1040 |
__IO uint32_t PR; |
1041 |
__IO uint32_t RLR; |
1041 |
__IO uint32_t RLR; |
1042 |
__IO uint32_t SR; |
1042 |
__IO uint32_t SR; |
1043 |
} IWDG_TypeDef; |
1043 |
} IWDG_TypeDef; |
1044 |
|
1044 |
|
1045 |
/** |
1045 |
/** |
1046 |
* @brief Power Control |
1046 |
* @brief Power Control |
1047 |
*/ |
1047 |
*/ |
1048 |
|
1048 |
|
1049 |
typedef struct |
1049 |
typedef struct |
1050 |
{ |
1050 |
{ |
1051 |
__IO uint32_t CR; |
1051 |
__IO uint32_t CR; |
1052 |
__IO uint32_t CSR; |
1052 |
__IO uint32_t CSR; |
1053 |
} PWR_TypeDef; |
1053 |
} PWR_TypeDef; |
1054 |
|
1054 |
|
1055 |
/** |
1055 |
/** |
1056 |
* @brief Reset and Clock Control |
1056 |
* @brief Reset and Clock Control |
1057 |
*/ |
1057 |
*/ |
1058 |
|
1058 |
|
1059 |
typedef struct |
1059 |
typedef struct |
1060 |
{ |
1060 |
{ |
1061 |
__IO uint32_t CR; |
1061 |
__IO uint32_t CR; |
1062 |
__IO uint32_t CFGR; |
1062 |
__IO uint32_t CFGR; |
1063 |
__IO uint32_t CIR; |
1063 |
__IO uint32_t CIR; |
1064 |
__IO uint32_t APB2RSTR; |
1064 |
__IO uint32_t APB2RSTR; |
1065 |
__IO uint32_t APB1RSTR; |
1065 |
__IO uint32_t APB1RSTR; |
1066 |
__IO uint32_t AHBENR; |
1066 |
__IO uint32_t AHBENR; |
1067 |
__IO uint32_t APB2ENR; |
1067 |
__IO uint32_t APB2ENR; |
1068 |
__IO uint32_t APB1ENR; |
1068 |
__IO uint32_t APB1ENR; |
1069 |
__IO uint32_t BDCR; |
1069 |
__IO uint32_t BDCR; |
1070 |
__IO uint32_t CSR; |
1070 |
__IO uint32_t CSR; |
1071 |
|
1071 |
|
1072 |
#ifdef STM32F10X_CL |
1072 |
#ifdef STM32F10X_CL |
1073 |
__IO uint32_t AHBRSTR; |
1073 |
__IO uint32_t AHBRSTR; |
1074 |
__IO uint32_t CFGR2; |
1074 |
__IO uint32_t CFGR2; |
1075 |
#endif /* STM32F10X_CL */ |
1075 |
#endif /* STM32F10X_CL */ |
1076 |
|
1076 |
|
1077 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
1077 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
1078 |
uint32_t RESERVED0; |
1078 |
uint32_t RESERVED0; |
1079 |
__IO uint32_t CFGR2; |
1079 |
__IO uint32_t CFGR2; |
1080 |
#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ |
1080 |
#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ |
1081 |
} RCC_TypeDef; |
1081 |
} RCC_TypeDef; |
1082 |
|
1082 |
|
1083 |
/** |
1083 |
/** |
1084 |
* @brief Real-Time Clock |
1084 |
* @brief Real-Time Clock |
1085 |
*/ |
1085 |
*/ |
1086 |
|
1086 |
|
1087 |
typedef struct |
1087 |
typedef struct |
1088 |
{ |
1088 |
{ |
1089 |
__IO uint16_t CRH; |
1089 |
__IO uint16_t CRH; |
1090 |
uint16_t RESERVED0; |
1090 |
uint16_t RESERVED0; |
1091 |
__IO uint16_t CRL; |
1091 |
__IO uint16_t CRL; |
1092 |
uint16_t RESERVED1; |
1092 |
uint16_t RESERVED1; |
1093 |
__IO uint16_t PRLH; |
1093 |
__IO uint16_t PRLH; |
1094 |
uint16_t RESERVED2; |
1094 |
uint16_t RESERVED2; |
1095 |
__IO uint16_t PRLL; |
1095 |
__IO uint16_t PRLL; |
1096 |
uint16_t RESERVED3; |
1096 |
uint16_t RESERVED3; |
1097 |
__IO uint16_t DIVH; |
1097 |
__IO uint16_t DIVH; |
1098 |
uint16_t RESERVED4; |
1098 |
uint16_t RESERVED4; |
1099 |
__IO uint16_t DIVL; |
1099 |
__IO uint16_t DIVL; |
1100 |
uint16_t RESERVED5; |
1100 |
uint16_t RESERVED5; |
1101 |
__IO uint16_t CNTH; |
1101 |
__IO uint16_t CNTH; |
1102 |
uint16_t RESERVED6; |
1102 |
uint16_t RESERVED6; |
1103 |
__IO uint16_t CNTL; |
1103 |
__IO uint16_t CNTL; |
1104 |
uint16_t RESERVED7; |
1104 |
uint16_t RESERVED7; |
1105 |
__IO uint16_t ALRH; |
1105 |
__IO uint16_t ALRH; |
1106 |
uint16_t RESERVED8; |
1106 |
uint16_t RESERVED8; |
1107 |
__IO uint16_t ALRL; |
1107 |
__IO uint16_t ALRL; |
1108 |
uint16_t RESERVED9; |
1108 |
uint16_t RESERVED9; |
1109 |
} RTC_TypeDef; |
1109 |
} RTC_TypeDef; |
1110 |
|
1110 |
|
1111 |
/** |
1111 |
/** |
1112 |
* @brief SD host Interface |
1112 |
* @brief SD host Interface |
1113 |
*/ |
1113 |
*/ |
1114 |
|
1114 |
|
1115 |
typedef struct |
1115 |
typedef struct |
1116 |
{ |
1116 |
{ |
1117 |
__IO uint32_t POWER; |
1117 |
__IO uint32_t POWER; |
1118 |
__IO uint32_t CLKCR; |
1118 |
__IO uint32_t CLKCR; |
1119 |
__IO uint32_t ARG; |
1119 |
__IO uint32_t ARG; |
1120 |
__IO uint32_t CMD; |
1120 |
__IO uint32_t CMD; |
1121 |
__I uint32_t RESPCMD; |
1121 |
__I uint32_t RESPCMD; |
1122 |
__I uint32_t RESP1; |
1122 |
__I uint32_t RESP1; |
1123 |
__I uint32_t RESP2; |
1123 |
__I uint32_t RESP2; |
1124 |
__I uint32_t RESP3; |
1124 |
__I uint32_t RESP3; |
1125 |
__I uint32_t RESP4; |
1125 |
__I uint32_t RESP4; |
1126 |
__IO uint32_t DTIMER; |
1126 |
__IO uint32_t DTIMER; |
1127 |
__IO uint32_t DLEN; |
1127 |
__IO uint32_t DLEN; |
1128 |
__IO uint32_t DCTRL; |
1128 |
__IO uint32_t DCTRL; |
1129 |
__I uint32_t DCOUNT; |
1129 |
__I uint32_t DCOUNT; |
1130 |
__I uint32_t STA; |
1130 |
__I uint32_t STA; |
1131 |
__IO uint32_t ICR; |
1131 |
__IO uint32_t ICR; |
1132 |
__IO uint32_t MASK; |
1132 |
__IO uint32_t MASK; |
1133 |
uint32_t RESERVED0[2]; |
1133 |
uint32_t RESERVED0[2]; |
1134 |
__I uint32_t FIFOCNT; |
1134 |
__I uint32_t FIFOCNT; |
1135 |
uint32_t RESERVED1[13]; |
1135 |
uint32_t RESERVED1[13]; |
1136 |
__IO uint32_t FIFO; |
1136 |
__IO uint32_t FIFO; |
1137 |
} SDIO_TypeDef; |
1137 |
} SDIO_TypeDef; |
1138 |
|
1138 |
|
1139 |
/** |
1139 |
/** |
1140 |
* @brief Serial Peripheral Interface |
1140 |
* @brief Serial Peripheral Interface |
1141 |
*/ |
1141 |
*/ |
1142 |
|
1142 |
|
1143 |
typedef struct |
1143 |
typedef struct |
1144 |
{ |
1144 |
{ |
1145 |
__IO uint16_t CR1; |
1145 |
__IO uint16_t CR1; |
1146 |
uint16_t RESERVED0; |
1146 |
uint16_t RESERVED0; |
1147 |
__IO uint16_t CR2; |
1147 |
__IO uint16_t CR2; |
1148 |
uint16_t RESERVED1; |
1148 |
uint16_t RESERVED1; |
1149 |
__IO uint16_t SR; |
1149 |
__IO uint16_t SR; |
1150 |
uint16_t RESERVED2; |
1150 |
uint16_t RESERVED2; |
1151 |
__IO uint16_t DR; |
1151 |
__IO uint16_t DR; |
1152 |
uint16_t RESERVED3; |
1152 |
uint16_t RESERVED3; |
1153 |
__IO uint16_t CRCPR; |
1153 |
__IO uint16_t CRCPR; |
1154 |
uint16_t RESERVED4; |
1154 |
uint16_t RESERVED4; |
1155 |
__IO uint16_t RXCRCR; |
1155 |
__IO uint16_t RXCRCR; |
1156 |
uint16_t RESERVED5; |
1156 |
uint16_t RESERVED5; |
1157 |
__IO uint16_t TXCRCR; |
1157 |
__IO uint16_t TXCRCR; |
1158 |
uint16_t RESERVED6; |
1158 |
uint16_t RESERVED6; |
1159 |
__IO uint16_t I2SCFGR; |
1159 |
__IO uint16_t I2SCFGR; |
1160 |
uint16_t RESERVED7; |
1160 |
uint16_t RESERVED7; |
1161 |
__IO uint16_t I2SPR; |
1161 |
__IO uint16_t I2SPR; |
1162 |
uint16_t RESERVED8; |
1162 |
uint16_t RESERVED8; |
1163 |
} SPI_TypeDef; |
1163 |
} SPI_TypeDef; |
1164 |
|
1164 |
|
1165 |
/** |
1165 |
/** |
1166 |
* @brief TIM |
1166 |
* @brief TIM |
1167 |
*/ |
1167 |
*/ |
1168 |
|
1168 |
|
1169 |
typedef struct |
1169 |
typedef struct |
1170 |
{ |
1170 |
{ |
1171 |
__IO uint16_t CR1; |
1171 |
__IO uint16_t CR1; |
1172 |
uint16_t RESERVED0; |
1172 |
uint16_t RESERVED0; |
1173 |
__IO uint16_t CR2; |
1173 |
__IO uint16_t CR2; |
1174 |
uint16_t RESERVED1; |
1174 |
uint16_t RESERVED1; |
1175 |
__IO uint16_t SMCR; |
1175 |
__IO uint16_t SMCR; |
1176 |
uint16_t RESERVED2; |
1176 |
uint16_t RESERVED2; |
1177 |
__IO uint16_t DIER; |
1177 |
__IO uint16_t DIER; |
1178 |
uint16_t RESERVED3; |
1178 |
uint16_t RESERVED3; |
1179 |
__IO uint16_t SR; |
1179 |
__IO uint16_t SR; |
1180 |
uint16_t RESERVED4; |
1180 |
uint16_t RESERVED4; |
1181 |
__IO uint16_t EGR; |
1181 |
__IO uint16_t EGR; |
1182 |
uint16_t RESERVED5; |
1182 |
uint16_t RESERVED5; |
1183 |
__IO uint16_t CCMR1; |
1183 |
__IO uint16_t CCMR1; |
1184 |
uint16_t RESERVED6; |
1184 |
uint16_t RESERVED6; |
1185 |
__IO uint16_t CCMR2; |
1185 |
__IO uint16_t CCMR2; |
1186 |
uint16_t RESERVED7; |
1186 |
uint16_t RESERVED7; |
1187 |
__IO uint16_t CCER; |
1187 |
__IO uint16_t CCER; |
1188 |
uint16_t RESERVED8; |
1188 |
uint16_t RESERVED8; |
1189 |
__IO uint16_t CNT; |
1189 |
__IO uint16_t CNT; |
1190 |
uint16_t RESERVED9; |
1190 |
uint16_t RESERVED9; |
1191 |
__IO uint16_t PSC; |
1191 |
__IO uint16_t PSC; |
1192 |
uint16_t RESERVED10; |
1192 |
uint16_t RESERVED10; |
1193 |
__IO uint16_t ARR; |
1193 |
__IO uint16_t ARR; |
1194 |
uint16_t RESERVED11; |
1194 |
uint16_t RESERVED11; |
1195 |
__IO uint16_t RCR; |
1195 |
__IO uint16_t RCR; |
1196 |
uint16_t RESERVED12; |
1196 |
uint16_t RESERVED12; |
1197 |
__IO uint16_t CCR1; |
1197 |
__IO uint16_t CCR1; |
1198 |
uint16_t RESERVED13; |
1198 |
uint16_t RESERVED13; |
1199 |
__IO uint16_t CCR2; |
1199 |
__IO uint16_t CCR2; |
1200 |
uint16_t RESERVED14; |
1200 |
uint16_t RESERVED14; |
1201 |
__IO uint16_t CCR3; |
1201 |
__IO uint16_t CCR3; |
1202 |
uint16_t RESERVED15; |
1202 |
uint16_t RESERVED15; |
1203 |
__IO uint16_t CCR4; |
1203 |
__IO uint16_t CCR4; |
1204 |
uint16_t RESERVED16; |
1204 |
uint16_t RESERVED16; |
1205 |
__IO uint16_t BDTR; |
1205 |
__IO uint16_t BDTR; |
1206 |
uint16_t RESERVED17; |
1206 |
uint16_t RESERVED17; |
1207 |
__IO uint16_t DCR; |
1207 |
__IO uint16_t DCR; |
1208 |
uint16_t RESERVED18; |
1208 |
uint16_t RESERVED18; |
1209 |
__IO uint16_t DMAR; |
1209 |
__IO uint16_t DMAR; |
1210 |
uint16_t RESERVED19; |
1210 |
uint16_t RESERVED19; |
1211 |
} TIM_TypeDef; |
1211 |
} TIM_TypeDef; |
1212 |
|
1212 |
|
1213 |
/** |
1213 |
/** |
1214 |
* @brief Universal Synchronous Asynchronous Receiver Transmitter |
1214 |
* @brief Universal Synchronous Asynchronous Receiver Transmitter |
1215 |
*/ |
1215 |
*/ |
1216 |
|
1216 |
|
1217 |
typedef struct |
1217 |
typedef struct |
1218 |
{ |
1218 |
{ |
1219 |
__IO uint16_t SR; |
1219 |
__IO uint16_t SR; |
1220 |
uint16_t RESERVED0; |
1220 |
uint16_t RESERVED0; |
1221 |
__IO uint16_t DR; |
1221 |
__IO uint16_t DR; |
1222 |
uint16_t RESERVED1; |
1222 |
uint16_t RESERVED1; |
1223 |
__IO uint16_t BRR; |
1223 |
__IO uint16_t BRR; |
1224 |
uint16_t RESERVED2; |
1224 |
uint16_t RESERVED2; |
1225 |
__IO uint16_t CR1; |
1225 |
__IO uint16_t CR1; |
1226 |
uint16_t RESERVED3; |
1226 |
uint16_t RESERVED3; |
1227 |
__IO uint16_t CR2; |
1227 |
__IO uint16_t CR2; |
1228 |
uint16_t RESERVED4; |
1228 |
uint16_t RESERVED4; |
1229 |
__IO uint16_t CR3; |
1229 |
__IO uint16_t CR3; |
1230 |
uint16_t RESERVED5; |
1230 |
uint16_t RESERVED5; |
1231 |
__IO uint16_t GTPR; |
1231 |
__IO uint16_t GTPR; |
1232 |
uint16_t RESERVED6; |
1232 |
uint16_t RESERVED6; |
1233 |
} USART_TypeDef; |
1233 |
} USART_TypeDef; |
1234 |
|
1234 |
|
1235 |
/** |
1235 |
/** |
1236 |
* @brief Window WATCHDOG |
1236 |
* @brief Window WATCHDOG |
1237 |
*/ |
1237 |
*/ |
1238 |
|
1238 |
|
1239 |
typedef struct |
1239 |
typedef struct |
1240 |
{ |
1240 |
{ |
1241 |
__IO uint32_t CR; |
1241 |
__IO uint32_t CR; |
1242 |
__IO uint32_t CFR; |
1242 |
__IO uint32_t CFR; |
1243 |
__IO uint32_t SR; |
1243 |
__IO uint32_t SR; |
1244 |
} WWDG_TypeDef; |
1244 |
} WWDG_TypeDef; |
1245 |
|
1245 |
|
1246 |
/** |
1246 |
/** |
1247 |
* @} |
1247 |
* @} |
1248 |
*/ |
1248 |
*/ |
1249 |
|
1249 |
|
1250 |
/** @addtogroup Peripheral_memory_map |
1250 |
/** @addtogroup Peripheral_memory_map |
1251 |
* @{ |
1251 |
* @{ |
1252 |
*/ |
1252 |
*/ |
1253 |
|
1253 |
|
1254 |
|
1254 |
|
1255 |
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ |
1255 |
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ |
1256 |
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ |
1256 |
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ |
1257 |
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
1257 |
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
1258 |
|
1258 |
|
1259 |
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ |
1259 |
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ |
1260 |
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
1260 |
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
1261 |
|
1261 |
|
1262 |
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ |
1262 |
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ |
1263 |
|
1263 |
|
1264 |
/*!< Peripheral memory map */ |
1264 |
/*!< Peripheral memory map */ |
1265 |
#define APB1PERIPH_BASE PERIPH_BASE |
1265 |
#define APB1PERIPH_BASE PERIPH_BASE |
1266 |
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
1266 |
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
1267 |
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
1267 |
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
1268 |
|
1268 |
|
1269 |
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
1269 |
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
1270 |
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
1270 |
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
1271 |
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
1271 |
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
1272 |
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
1272 |
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
1273 |
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
1273 |
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
1274 |
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
1274 |
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
1275 |
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
1275 |
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
1276 |
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
1276 |
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
1277 |
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
1277 |
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
1278 |
#define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
1278 |
#define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
1279 |
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
1279 |
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
1280 |
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
1280 |
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
1281 |
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
1281 |
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
1282 |
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
1282 |
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
1283 |
#define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
1283 |
#define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
1284 |
#define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
1284 |
#define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
1285 |
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
1285 |
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
1286 |
#define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
1286 |
#define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
1287 |
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
1287 |
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
1288 |
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
1288 |
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
1289 |
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
1289 |
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
1290 |
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
1290 |
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
1291 |
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
1291 |
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
1292 |
#define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
1292 |
#define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
1293 |
#define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
1293 |
#define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
1294 |
#define CEC_BASE (APB1PERIPH_BASE + 0x7800) |
1294 |
#define CEC_BASE (APB1PERIPH_BASE + 0x7800) |
1295 |
|
1295 |
|
1296 |
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
1296 |
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
1297 |
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
1297 |
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
1298 |
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
1298 |
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
1299 |
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
1299 |
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
1300 |
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
1300 |
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
1301 |
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
1301 |
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
1302 |
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
1302 |
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
1303 |
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
1303 |
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
1304 |
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
1304 |
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
1305 |
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
1305 |
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
1306 |
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
1306 |
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
1307 |
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
1307 |
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
1308 |
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
1308 |
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
1309 |
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
1309 |
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
1310 |
#define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
1310 |
#define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
1311 |
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
1311 |
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
1312 |
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
1312 |
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
1313 |
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
1313 |
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
1314 |
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
1314 |
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
1315 |
#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
1315 |
#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
1316 |
#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
1316 |
#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
1317 |
#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
1317 |
#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
1318 |
|
1318 |
|
1319 |
#define SDIO_BASE (PERIPH_BASE + 0x18000) |
1319 |
#define SDIO_BASE (PERIPH_BASE + 0x18000) |
1320 |
|
1320 |
|
1321 |
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
1321 |
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
1322 |
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
1322 |
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
1323 |
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
1323 |
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
1324 |
#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
1324 |
#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
1325 |
#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
1325 |
#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
1326 |
#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
1326 |
#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
1327 |
#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
1327 |
#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
1328 |
#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
1328 |
#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
1329 |
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
1329 |
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
1330 |
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
1330 |
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
1331 |
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
1331 |
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
1332 |
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
1332 |
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
1333 |
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
1333 |
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
1334 |
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
1334 |
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
1335 |
#define RCC_BASE (AHBPERIPH_BASE + 0x1000) |
1335 |
#define RCC_BASE (AHBPERIPH_BASE + 0x1000) |
1336 |
#define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
1336 |
#define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
1337 |
|
1337 |
|
1338 |
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ |
1338 |
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ |
1339 |
#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ |
1339 |
#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ |
1340 |
|
1340 |
|
1341 |
#define ETH_BASE (AHBPERIPH_BASE + 0x8000) |
1341 |
#define ETH_BASE (AHBPERIPH_BASE + 0x8000) |
1342 |
#define ETH_MAC_BASE (ETH_BASE) |
1342 |
#define ETH_MAC_BASE (ETH_BASE) |
1343 |
#define ETH_MMC_BASE (ETH_BASE + 0x0100) |
1343 |
#define ETH_MMC_BASE (ETH_BASE + 0x0100) |
1344 |
#define ETH_PTP_BASE (ETH_BASE + 0x0700) |
1344 |
#define ETH_PTP_BASE (ETH_BASE + 0x0700) |
1345 |
#define ETH_DMA_BASE (ETH_BASE + 0x1000) |
1345 |
#define ETH_DMA_BASE (ETH_BASE + 0x1000) |
1346 |
|
1346 |
|
1347 |
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ |
1347 |
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ |
1348 |
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ |
1348 |
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ |
1349 |
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ |
1349 |
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ |
1350 |
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ |
1350 |
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ |
1351 |
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ |
1351 |
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ |
1352 |
|
1352 |
|
1353 |
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ |
1353 |
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ |
1354 |
|
1354 |
|
1355 |
/** |
1355 |
/** |
1356 |
* @} |
1356 |
* @} |
1357 |
*/ |
1357 |
*/ |
1358 |
|
1358 |
|
1359 |
/** @addtogroup Peripheral_declaration |
1359 |
/** @addtogroup Peripheral_declaration |
1360 |
* @{ |
1360 |
* @{ |
1361 |
*/ |
1361 |
*/ |
1362 |
|
1362 |
|
1363 |
#define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
1363 |
#define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
1364 |
#define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
1364 |
#define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
1365 |
#define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
1365 |
#define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
1366 |
#define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
1366 |
#define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
1367 |
#define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
1367 |
#define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
1368 |
#define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
1368 |
#define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
1369 |
#define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
1369 |
#define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
1370 |
#define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
1370 |
#define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
1371 |
#define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
1371 |
#define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
1372 |
#define RTC ((RTC_TypeDef *) RTC_BASE) |
1372 |
#define RTC ((RTC_TypeDef *) RTC_BASE) |
1373 |
#define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
1373 |
#define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
1374 |
#define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
1374 |
#define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
1375 |
#define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
1375 |
#define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
1376 |
#define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
1376 |
#define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
1377 |
#define USART2 ((USART_TypeDef *) USART2_BASE) |
1377 |
#define USART2 ((USART_TypeDef *) USART2_BASE) |
1378 |
#define USART3 ((USART_TypeDef *) USART3_BASE) |
1378 |
#define USART3 ((USART_TypeDef *) USART3_BASE) |
1379 |
#define UART4 ((USART_TypeDef *) UART4_BASE) |
1379 |
#define UART4 ((USART_TypeDef *) UART4_BASE) |
1380 |
#define UART5 ((USART_TypeDef *) UART5_BASE) |
1380 |
#define UART5 ((USART_TypeDef *) UART5_BASE) |
1381 |
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
1381 |
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
1382 |
#define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
1382 |
#define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
1383 |
#define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
1383 |
#define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
1384 |
#define CAN2 ((CAN_TypeDef *) CAN2_BASE) |
1384 |
#define CAN2 ((CAN_TypeDef *) CAN2_BASE) |
1385 |
#define BKP ((BKP_TypeDef *) BKP_BASE) |
1385 |
#define BKP ((BKP_TypeDef *) BKP_BASE) |
1386 |
#define PWR ((PWR_TypeDef *) PWR_BASE) |
1386 |
#define PWR ((PWR_TypeDef *) PWR_BASE) |
1387 |
#define DAC ((DAC_TypeDef *) DAC_BASE) |
1387 |
#define DAC ((DAC_TypeDef *) DAC_BASE) |
1388 |
#define CEC ((CEC_TypeDef *) CEC_BASE) |
1388 |
#define CEC ((CEC_TypeDef *) CEC_BASE) |
1389 |
#define AFIO ((AFIO_TypeDef *) AFIO_BASE) |
1389 |
#define AFIO ((AFIO_TypeDef *) AFIO_BASE) |
1390 |
#define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
1390 |
#define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
1391 |
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
1391 |
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
1392 |
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
1392 |
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
1393 |
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
1393 |
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
1394 |
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
1394 |
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
1395 |
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
1395 |
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
1396 |
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
1396 |
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
1397 |
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
1397 |
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
1398 |
#define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
1398 |
#define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
1399 |
#define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
1399 |
#define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
1400 |
#define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
1400 |
#define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
1401 |
#define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
1401 |
#define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
1402 |
#define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
1402 |
#define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
1403 |
#define USART1 ((USART_TypeDef *) USART1_BASE) |
1403 |
#define USART1 ((USART_TypeDef *) USART1_BASE) |
1404 |
#define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
1404 |
#define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
1405 |
#define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
1405 |
#define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
1406 |
#define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
1406 |
#define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
1407 |
#define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
1407 |
#define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
1408 |
#define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
1408 |
#define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
1409 |
#define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
1409 |
#define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
1410 |
#define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
1410 |
#define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
1411 |
#define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
1411 |
#define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
1412 |
#define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
1412 |
#define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
1413 |
#define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
1413 |
#define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
1414 |
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
1414 |
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
1415 |
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
1415 |
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
1416 |
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
1416 |
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
1417 |
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
1417 |
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
1418 |
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
1418 |
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
1419 |
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
1419 |
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
1420 |
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
1420 |
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
1421 |
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
1421 |
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
1422 |
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
1422 |
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
1423 |
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
1423 |
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
1424 |
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
1424 |
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
1425 |
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
1425 |
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
1426 |
#define RCC ((RCC_TypeDef *) RCC_BASE) |
1426 |
#define RCC ((RCC_TypeDef *) RCC_BASE) |
1427 |
#define CRC ((CRC_TypeDef *) CRC_BASE) |
1427 |
#define CRC ((CRC_TypeDef *) CRC_BASE) |
1428 |
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
1428 |
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
1429 |
#define OB ((OB_TypeDef *) OB_BASE) |
1429 |
#define OB ((OB_TypeDef *) OB_BASE) |
1430 |
#define ETH ((ETH_TypeDef *) ETH_BASE) |
1430 |
#define ETH ((ETH_TypeDef *) ETH_BASE) |
1431 |
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) |
1431 |
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) |
1432 |
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) |
1432 |
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) |
1433 |
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) |
1433 |
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) |
1434 |
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) |
1434 |
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) |
1435 |
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) |
1435 |
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) |
1436 |
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
1436 |
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
1437 |
|
1437 |
|
1438 |
/** |
1438 |
/** |
1439 |
* @} |
1439 |
* @} |
1440 |
*/ |
1440 |
*/ |
1441 |
|
1441 |
|
1442 |
/** @addtogroup Exported_constants |
1442 |
/** @addtogroup Exported_constants |
1443 |
* @{ |
1443 |
* @{ |
1444 |
*/ |
1444 |
*/ |
1445 |
|
1445 |
|
1446 |
/** @addtogroup Peripheral_Registers_Bits_Definition |
1446 |
/** @addtogroup Peripheral_Registers_Bits_Definition |
1447 |
* @{ |
1447 |
* @{ |
1448 |
*/ |
1448 |
*/ |
1449 |
|
1449 |
|
1450 |
/******************************************************************************/ |
1450 |
/******************************************************************************/ |
1451 |
/* Peripheral Registers_Bits_Definition */ |
1451 |
/* Peripheral Registers_Bits_Definition */ |
1452 |
/******************************************************************************/ |
1452 |
/******************************************************************************/ |
1453 |
|
1453 |
|
1454 |
/******************************************************************************/ |
1454 |
/******************************************************************************/ |
1455 |
/* */ |
1455 |
/* */ |
1456 |
/* CRC calculation unit */ |
1456 |
/* CRC calculation unit */ |
1457 |
/* */ |
1457 |
/* */ |
1458 |
/******************************************************************************/ |
1458 |
/******************************************************************************/ |
1459 |
|
1459 |
|
1460 |
/******************* Bit definition for CRC_DR register *********************/ |
1460 |
/******************* Bit definition for CRC_DR register *********************/ |
1461 |
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
1461 |
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
1462 |
|
1462 |
|
1463 |
|
1463 |
|
1464 |
/******************* Bit definition for CRC_IDR register ********************/ |
1464 |
/******************* Bit definition for CRC_IDR register ********************/ |
1465 |
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
1465 |
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
1466 |
|
1466 |
|
1467 |
|
1467 |
|
1468 |
/******************** Bit definition for CRC_CR register ********************/ |
1468 |
/******************** Bit definition for CRC_CR register ********************/ |
1469 |
#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ |
1469 |
#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ |
1470 |
|
1470 |
|
1471 |
/******************************************************************************/ |
1471 |
/******************************************************************************/ |
1472 |
/* */ |
1472 |
/* */ |
1473 |
/* Power Control */ |
1473 |
/* Power Control */ |
1474 |
/* */ |
1474 |
/* */ |
1475 |
/******************************************************************************/ |
1475 |
/******************************************************************************/ |
1476 |
|
1476 |
|
1477 |
/******************** Bit definition for PWR_CR register ********************/ |
1477 |
/******************** Bit definition for PWR_CR register ********************/ |
1478 |
#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ |
1478 |
#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ |
1479 |
#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ |
1479 |
#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ |
1480 |
#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ |
1480 |
#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ |
1481 |
#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ |
1481 |
#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ |
1482 |
#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ |
1482 |
#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ |
1483 |
|
1483 |
|
1484 |
#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ |
1484 |
#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ |
1485 |
#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ |
1485 |
#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ |
1486 |
#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ |
1486 |
#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ |
1487 |
#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ |
1487 |
#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ |
1488 |
|
1488 |
|
1489 |
/*!< PVD level configuration */ |
1489 |
/*!< PVD level configuration */ |
1490 |
#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ |
1490 |
#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ |
1491 |
#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ |
1491 |
#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ |
1492 |
#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ |
1492 |
#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ |
1493 |
#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ |
1493 |
#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ |
1494 |
#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ |
1494 |
#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ |
1495 |
#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ |
1495 |
#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ |
1496 |
#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ |
1496 |
#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ |
1497 |
#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ |
1497 |
#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ |
1498 |
|
1498 |
|
1499 |
#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ |
1499 |
#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ |
1500 |
|
1500 |
|
1501 |
|
1501 |
|
1502 |
/******************* Bit definition for PWR_CSR register ********************/ |
1502 |
/******************* Bit definition for PWR_CSR register ********************/ |
1503 |
#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ |
1503 |
#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ |
1504 |
#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ |
1504 |
#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ |
1505 |
#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ |
1505 |
#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ |
1506 |
#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ |
1506 |
#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ |
1507 |
|
1507 |
|
1508 |
/******************************************************************************/ |
1508 |
/******************************************************************************/ |
1509 |
/* */ |
1509 |
/* */ |
1510 |
/* Backup registers */ |
1510 |
/* Backup registers */ |
1511 |
/* */ |
1511 |
/* */ |
1512 |
/******************************************************************************/ |
1512 |
/******************************************************************************/ |
1513 |
|
1513 |
|
1514 |
/******************* Bit definition for BKP_DR1 register ********************/ |
1514 |
/******************* Bit definition for BKP_DR1 register ********************/ |
1515 |
#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1515 |
#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1516 |
|
1516 |
|
1517 |
/******************* Bit definition for BKP_DR2 register ********************/ |
1517 |
/******************* Bit definition for BKP_DR2 register ********************/ |
1518 |
#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1518 |
#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1519 |
|
1519 |
|
1520 |
/******************* Bit definition for BKP_DR3 register ********************/ |
1520 |
/******************* Bit definition for BKP_DR3 register ********************/ |
1521 |
#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1521 |
#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1522 |
|
1522 |
|
1523 |
/******************* Bit definition for BKP_DR4 register ********************/ |
1523 |
/******************* Bit definition for BKP_DR4 register ********************/ |
1524 |
#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1524 |
#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1525 |
|
1525 |
|
1526 |
/******************* Bit definition for BKP_DR5 register ********************/ |
1526 |
/******************* Bit definition for BKP_DR5 register ********************/ |
1527 |
#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1527 |
#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1528 |
|
1528 |
|
1529 |
/******************* Bit definition for BKP_DR6 register ********************/ |
1529 |
/******************* Bit definition for BKP_DR6 register ********************/ |
1530 |
#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1530 |
#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1531 |
|
1531 |
|
1532 |
/******************* Bit definition for BKP_DR7 register ********************/ |
1532 |
/******************* Bit definition for BKP_DR7 register ********************/ |
1533 |
#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1533 |
#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1534 |
|
1534 |
|
1535 |
/******************* Bit definition for BKP_DR8 register ********************/ |
1535 |
/******************* Bit definition for BKP_DR8 register ********************/ |
1536 |
#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1536 |
#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1537 |
|
1537 |
|
1538 |
/******************* Bit definition for BKP_DR9 register ********************/ |
1538 |
/******************* Bit definition for BKP_DR9 register ********************/ |
1539 |
#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1539 |
#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1540 |
|
1540 |
|
1541 |
/******************* Bit definition for BKP_DR10 register *******************/ |
1541 |
/******************* Bit definition for BKP_DR10 register *******************/ |
1542 |
#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1542 |
#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1543 |
|
1543 |
|
1544 |
/******************* Bit definition for BKP_DR11 register *******************/ |
1544 |
/******************* Bit definition for BKP_DR11 register *******************/ |
1545 |
#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1545 |
#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1546 |
|
1546 |
|
1547 |
/******************* Bit definition for BKP_DR12 register *******************/ |
1547 |
/******************* Bit definition for BKP_DR12 register *******************/ |
1548 |
#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1548 |
#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1549 |
|
1549 |
|
1550 |
/******************* Bit definition for BKP_DR13 register *******************/ |
1550 |
/******************* Bit definition for BKP_DR13 register *******************/ |
1551 |
#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1551 |
#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1552 |
|
1552 |
|
1553 |
/******************* Bit definition for BKP_DR14 register *******************/ |
1553 |
/******************* Bit definition for BKP_DR14 register *******************/ |
1554 |
#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1554 |
#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1555 |
|
1555 |
|
1556 |
/******************* Bit definition for BKP_DR15 register *******************/ |
1556 |
/******************* Bit definition for BKP_DR15 register *******************/ |
1557 |
#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1557 |
#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1558 |
|
1558 |
|
1559 |
/******************* Bit definition for BKP_DR16 register *******************/ |
1559 |
/******************* Bit definition for BKP_DR16 register *******************/ |
1560 |
#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1560 |
#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1561 |
|
1561 |
|
1562 |
/******************* Bit definition for BKP_DR17 register *******************/ |
1562 |
/******************* Bit definition for BKP_DR17 register *******************/ |
1563 |
#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1563 |
#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1564 |
|
1564 |
|
1565 |
/****************** Bit definition for BKP_DR18 register ********************/ |
1565 |
/****************** Bit definition for BKP_DR18 register ********************/ |
1566 |
#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1566 |
#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1567 |
|
1567 |
|
1568 |
/******************* Bit definition for BKP_DR19 register *******************/ |
1568 |
/******************* Bit definition for BKP_DR19 register *******************/ |
1569 |
#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1569 |
#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1570 |
|
1570 |
|
1571 |
/******************* Bit definition for BKP_DR20 register *******************/ |
1571 |
/******************* Bit definition for BKP_DR20 register *******************/ |
1572 |
#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1572 |
#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1573 |
|
1573 |
|
1574 |
/******************* Bit definition for BKP_DR21 register *******************/ |
1574 |
/******************* Bit definition for BKP_DR21 register *******************/ |
1575 |
#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1575 |
#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1576 |
|
1576 |
|
1577 |
/******************* Bit definition for BKP_DR22 register *******************/ |
1577 |
/******************* Bit definition for BKP_DR22 register *******************/ |
1578 |
#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1578 |
#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1579 |
|
1579 |
|
1580 |
/******************* Bit definition for BKP_DR23 register *******************/ |
1580 |
/******************* Bit definition for BKP_DR23 register *******************/ |
1581 |
#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1581 |
#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1582 |
|
1582 |
|
1583 |
/******************* Bit definition for BKP_DR24 register *******************/ |
1583 |
/******************* Bit definition for BKP_DR24 register *******************/ |
1584 |
#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1584 |
#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1585 |
|
1585 |
|
1586 |
/******************* Bit definition for BKP_DR25 register *******************/ |
1586 |
/******************* Bit definition for BKP_DR25 register *******************/ |
1587 |
#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1587 |
#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1588 |
|
1588 |
|
1589 |
/******************* Bit definition for BKP_DR26 register *******************/ |
1589 |
/******************* Bit definition for BKP_DR26 register *******************/ |
1590 |
#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1590 |
#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1591 |
|
1591 |
|
1592 |
/******************* Bit definition for BKP_DR27 register *******************/ |
1592 |
/******************* Bit definition for BKP_DR27 register *******************/ |
1593 |
#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1593 |
#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1594 |
|
1594 |
|
1595 |
/******************* Bit definition for BKP_DR28 register *******************/ |
1595 |
/******************* Bit definition for BKP_DR28 register *******************/ |
1596 |
#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1596 |
#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1597 |
|
1597 |
|
1598 |
/******************* Bit definition for BKP_DR29 register *******************/ |
1598 |
/******************* Bit definition for BKP_DR29 register *******************/ |
1599 |
#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1599 |
#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1600 |
|
1600 |
|
1601 |
/******************* Bit definition for BKP_DR30 register *******************/ |
1601 |
/******************* Bit definition for BKP_DR30 register *******************/ |
1602 |
#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1602 |
#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1603 |
|
1603 |
|
1604 |
/******************* Bit definition for BKP_DR31 register *******************/ |
1604 |
/******************* Bit definition for BKP_DR31 register *******************/ |
1605 |
#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1605 |
#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1606 |
|
1606 |
|
1607 |
/******************* Bit definition for BKP_DR32 register *******************/ |
1607 |
/******************* Bit definition for BKP_DR32 register *******************/ |
1608 |
#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1608 |
#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1609 |
|
1609 |
|
1610 |
/******************* Bit definition for BKP_DR33 register *******************/ |
1610 |
/******************* Bit definition for BKP_DR33 register *******************/ |
1611 |
#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1611 |
#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1612 |
|
1612 |
|
1613 |
/******************* Bit definition for BKP_DR34 register *******************/ |
1613 |
/******************* Bit definition for BKP_DR34 register *******************/ |
1614 |
#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1614 |
#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1615 |
|
1615 |
|
1616 |
/******************* Bit definition for BKP_DR35 register *******************/ |
1616 |
/******************* Bit definition for BKP_DR35 register *******************/ |
1617 |
#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1617 |
#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1618 |
|
1618 |
|
1619 |
/******************* Bit definition for BKP_DR36 register *******************/ |
1619 |
/******************* Bit definition for BKP_DR36 register *******************/ |
1620 |
#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1620 |
#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1621 |
|
1621 |
|
1622 |
/******************* Bit definition for BKP_DR37 register *******************/ |
1622 |
/******************* Bit definition for BKP_DR37 register *******************/ |
1623 |
#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1623 |
#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1624 |
|
1624 |
|
1625 |
/******************* Bit definition for BKP_DR38 register *******************/ |
1625 |
/******************* Bit definition for BKP_DR38 register *******************/ |
1626 |
#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1626 |
#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1627 |
|
1627 |
|
1628 |
/******************* Bit definition for BKP_DR39 register *******************/ |
1628 |
/******************* Bit definition for BKP_DR39 register *******************/ |
1629 |
#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1629 |
#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1630 |
|
1630 |
|
1631 |
/******************* Bit definition for BKP_DR40 register *******************/ |
1631 |
/******************* Bit definition for BKP_DR40 register *******************/ |
1632 |
#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1632 |
#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1633 |
|
1633 |
|
1634 |
/******************* Bit definition for BKP_DR41 register *******************/ |
1634 |
/******************* Bit definition for BKP_DR41 register *******************/ |
1635 |
#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1635 |
#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1636 |
|
1636 |
|
1637 |
/******************* Bit definition for BKP_DR42 register *******************/ |
1637 |
/******************* Bit definition for BKP_DR42 register *******************/ |
1638 |
#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1638 |
#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ |
1639 |
|
1639 |
|
1640 |
/****************** Bit definition for BKP_RTCCR register *******************/ |
1640 |
/****************** Bit definition for BKP_RTCCR register *******************/ |
1641 |
#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ |
1641 |
#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ |
1642 |
#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ |
1642 |
#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ |
1643 |
#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ |
1643 |
#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ |
1644 |
#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ |
1644 |
#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ |
1645 |
|
1645 |
|
1646 |
/******************** Bit definition for BKP_CR register ********************/ |
1646 |
/******************** Bit definition for BKP_CR register ********************/ |
1647 |
#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ |
1647 |
#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ |
1648 |
#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ |
1648 |
#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ |
1649 |
|
1649 |
|
1650 |
/******************* Bit definition for BKP_CSR register ********************/ |
1650 |
/******************* Bit definition for BKP_CSR register ********************/ |
1651 |
#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ |
1651 |
#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ |
1652 |
#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ |
1652 |
#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ |
1653 |
#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ |
1653 |
#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ |
1654 |
#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ |
1654 |
#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ |
1655 |
#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ |
1655 |
#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ |
1656 |
|
1656 |
|
1657 |
/******************************************************************************/ |
1657 |
/******************************************************************************/ |
1658 |
/* */ |
1658 |
/* */ |
1659 |
/* Reset and Clock Control */ |
1659 |
/* Reset and Clock Control */ |
1660 |
/* */ |
1660 |
/* */ |
1661 |
/******************************************************************************/ |
1661 |
/******************************************************************************/ |
1662 |
|
1662 |
|
1663 |
/******************** Bit definition for RCC_CR register ********************/ |
1663 |
/******************** Bit definition for RCC_CR register ********************/ |
1664 |
#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ |
1664 |
#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ |
1665 |
#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ |
1665 |
#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ |
1666 |
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ |
1666 |
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ |
1667 |
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ |
1667 |
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ |
1668 |
#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ |
1668 |
#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ |
1669 |
#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ |
1669 |
#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ |
1670 |
#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ |
1670 |
#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ |
1671 |
#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ |
1671 |
#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ |
1672 |
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ |
1672 |
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ |
1673 |
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ |
1673 |
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ |
1674 |
|
1674 |
|
1675 |
#ifdef STM32F10X_CL |
1675 |
#ifdef STM32F10X_CL |
1676 |
#define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ |
1676 |
#define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ |
1677 |
#define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ |
1677 |
#define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ |
1678 |
#define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ |
1678 |
#define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ |
1679 |
#define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ |
1679 |
#define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ |
1680 |
#endif /* STM32F10X_CL */ |
1680 |
#endif /* STM32F10X_CL */ |
1681 |
|
1681 |
|
1682 |
/******************* Bit definition for RCC_CFGR register *******************/ |
1682 |
/******************* Bit definition for RCC_CFGR register *******************/ |
1683 |
/*!< SW configuration */ |
1683 |
/*!< SW configuration */ |
1684 |
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
1684 |
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
1685 |
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
1685 |
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
1686 |
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
1686 |
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
1687 |
|
1687 |
|
1688 |
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
1688 |
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
1689 |
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
1689 |
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
1690 |
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ |
1690 |
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ |
1691 |
|
1691 |
|
1692 |
/*!< SWS configuration */ |
1692 |
/*!< SWS configuration */ |
1693 |
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
1693 |
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
1694 |
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
1694 |
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
1695 |
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
1695 |
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
1696 |
|
1696 |
|
1697 |
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
1697 |
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
1698 |
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
1698 |
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
1699 |
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ |
1699 |
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ |
1700 |
|
1700 |
|
1701 |
/*!< HPRE configuration */ |
1701 |
/*!< HPRE configuration */ |
1702 |
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
1702 |
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
1703 |
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
1703 |
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
1704 |
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
1704 |
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
1705 |
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
1705 |
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
1706 |
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
1706 |
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
1707 |
|
1707 |
|
1708 |
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
1708 |
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
1709 |
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
1709 |
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
1710 |
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
1710 |
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
1711 |
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
1711 |
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
1712 |
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
1712 |
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
1713 |
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
1713 |
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
1714 |
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
1714 |
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
1715 |
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
1715 |
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
1716 |
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
1716 |
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
1717 |
|
1717 |
|
1718 |
/*!< PPRE1 configuration */ |
1718 |
/*!< PPRE1 configuration */ |
1719 |
#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ |
1719 |
#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ |
1720 |
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
1720 |
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
1721 |
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
1721 |
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
1722 |
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
1722 |
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
1723 |
|
1723 |
|
1724 |
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
1724 |
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
1725 |
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ |
1725 |
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ |
1726 |
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ |
1726 |
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ |
1727 |
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ |
1727 |
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ |
1728 |
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ |
1728 |
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ |
1729 |
|
1729 |
|
1730 |
/*!< PPRE2 configuration */ |
1730 |
/*!< PPRE2 configuration */ |
1731 |
#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
1731 |
#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
1732 |
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ |
1732 |
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ |
1733 |
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ |
1733 |
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ |
1734 |
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ |
1734 |
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ |
1735 |
|
1735 |
|
1736 |
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
1736 |
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
1737 |
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ |
1737 |
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ |
1738 |
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ |
1738 |
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ |
1739 |
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ |
1739 |
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ |
1740 |
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ |
1740 |
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ |
1741 |
|
1741 |
|
1742 |
/*!< ADCPPRE configuration */ |
1742 |
/*!< ADCPPRE configuration */ |
1743 |
#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
1743 |
#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
1744 |
#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
1744 |
#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
1745 |
#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
1745 |
#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
1746 |
|
1746 |
|
1747 |
#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ |
1747 |
#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ |
1748 |
#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ |
1748 |
#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ |
1749 |
#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ |
1749 |
#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ |
1750 |
#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ |
1750 |
#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ |
1751 |
|
1751 |
|
1752 |
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ |
1752 |
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ |
1753 |
|
1753 |
|
1754 |
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ |
1754 |
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ |
1755 |
|
1755 |
|
1756 |
/*!< PLLMUL configuration */ |
1756 |
/*!< PLLMUL configuration */ |
1757 |
#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
1757 |
#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
1758 |
#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
1758 |
#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
1759 |
#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
1759 |
#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
1760 |
#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
1760 |
#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
1761 |
#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ |
1761 |
#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ |
1762 |
|
1762 |
|
1763 |
#ifdef STM32F10X_CL |
1763 |
#ifdef STM32F10X_CL |
1764 |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
1764 |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
1765 |
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ |
1765 |
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ |
1766 |
|
1766 |
|
1767 |
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ |
1767 |
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ |
1768 |
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ |
1768 |
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ |
1769 |
|
1769 |
|
1770 |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ |
1770 |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ |
1771 |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ |
1771 |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ |
1772 |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ |
1772 |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ |
1773 |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ |
1773 |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ |
1774 |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ |
1774 |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ |
1775 |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ |
1775 |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ |
1776 |
#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ |
1776 |
#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ |
1777 |
|
1777 |
|
1778 |
#define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ |
1778 |
#define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ |
1779 |
|
1779 |
|
1780 |
/*!< MCO configuration */ |
1780 |
/*!< MCO configuration */ |
1781 |
#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ |
1781 |
#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ |
1782 |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
1782 |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
1783 |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
1783 |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
1784 |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
1784 |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
1785 |
#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
1785 |
#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
1786 |
|
1786 |
|
1787 |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
1787 |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
1788 |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
1788 |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
1789 |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
1789 |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
1790 |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
1790 |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
1791 |
#define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
1791 |
#define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
1792 |
#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ |
1792 |
#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ |
1793 |
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ |
1793 |
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ |
1794 |
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ |
1794 |
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ |
1795 |
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ |
1795 |
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ |
1796 |
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
1796 |
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
1797 |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
1797 |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
1798 |
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ |
1798 |
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ |
1799 |
|
1799 |
|
1800 |
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ |
1800 |
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ |
1801 |
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ |
1801 |
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ |
1802 |
|
1802 |
|
1803 |
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
1803 |
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
1804 |
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
1804 |
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
1805 |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
1805 |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
1806 |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
1806 |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
1807 |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
1807 |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
1808 |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
1808 |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
1809 |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
1809 |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
1810 |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
1810 |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
1811 |
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
1811 |
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
1812 |
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
1812 |
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
1813 |
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
1813 |
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
1814 |
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
1814 |
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
1815 |
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
1815 |
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
1816 |
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
1816 |
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
1817 |
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
1817 |
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
1818 |
|
1818 |
|
1819 |
/*!< MCO configuration */ |
1819 |
/*!< MCO configuration */ |
1820 |
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
1820 |
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
1821 |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
1821 |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
1822 |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
1822 |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
1823 |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
1823 |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
1824 |
|
1824 |
|
1825 |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
1825 |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
1826 |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
1826 |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
1827 |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
1827 |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
1828 |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
1828 |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
1829 |
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
1829 |
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
1830 |
#else |
1830 |
#else |
1831 |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
1831 |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
1832 |
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ |
1832 |
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ |
1833 |
|
1833 |
|
1834 |
#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ |
1834 |
#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ |
1835 |
#define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ |
1835 |
#define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ |
1836 |
|
1836 |
|
1837 |
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
1837 |
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
1838 |
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
1838 |
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
1839 |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
1839 |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
1840 |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
1840 |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
1841 |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
1841 |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
1842 |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
1842 |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
1843 |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
1843 |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
1844 |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
1844 |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
1845 |
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
1845 |
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
1846 |
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
1846 |
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
1847 |
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
1847 |
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
1848 |
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
1848 |
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
1849 |
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
1849 |
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
1850 |
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
1850 |
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
1851 |
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
1851 |
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
1852 |
#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ |
1852 |
#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ |
1853 |
|
1853 |
|
1854 |
/*!< MCO configuration */ |
1854 |
/*!< MCO configuration */ |
1855 |
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
1855 |
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
1856 |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
1856 |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
1857 |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
1857 |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
1858 |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
1858 |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
1859 |
|
1859 |
|
1860 |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
1860 |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
1861 |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
1861 |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
1862 |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
1862 |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
1863 |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
1863 |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
1864 |
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
1864 |
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
1865 |
#endif /* STM32F10X_CL */ |
1865 |
#endif /* STM32F10X_CL */ |
1866 |
|
1866 |
|
1867 |
/*!<****************** Bit definition for RCC_CIR register ********************/ |
1867 |
/*!<****************** Bit definition for RCC_CIR register ********************/ |
1868 |
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ |
1868 |
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ |
1869 |
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ |
1869 |
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ |
1870 |
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ |
1870 |
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ |
1871 |
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ |
1871 |
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ |
1872 |
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ |
1872 |
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ |
1873 |
#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ |
1873 |
#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ |
1874 |
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ |
1874 |
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ |
1875 |
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ |
1875 |
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ |
1876 |
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ |
1876 |
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ |
1877 |
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ |
1877 |
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ |
1878 |
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ |
1878 |
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ |
1879 |
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ |
1879 |
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ |
1880 |
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ |
1880 |
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ |
1881 |
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ |
1881 |
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ |
1882 |
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ |
1882 |
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ |
1883 |
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ |
1883 |
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ |
1884 |
#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ |
1884 |
#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ |
1885 |
|
1885 |
|
1886 |
#ifdef STM32F10X_CL |
1886 |
#ifdef STM32F10X_CL |
1887 |
#define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ |
1887 |
#define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ |
1888 |
#define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ |
1888 |
#define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ |
1889 |
#define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ |
1889 |
#define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ |
1890 |
#define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ |
1890 |
#define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ |
1891 |
#define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ |
1891 |
#define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ |
1892 |
#define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ |
1892 |
#define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ |
1893 |
#endif /* STM32F10X_CL */ |
1893 |
#endif /* STM32F10X_CL */ |
1894 |
|
1894 |
|
1895 |
/***************** Bit definition for RCC_APB2RSTR register *****************/ |
1895 |
/***************** Bit definition for RCC_APB2RSTR register *****************/ |
1896 |
#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ |
1896 |
#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ |
1897 |
#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ |
1897 |
#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ |
1898 |
#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ |
1898 |
#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ |
1899 |
#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ |
1899 |
#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ |
1900 |
#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ |
1900 |
#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ |
1901 |
#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ |
1901 |
#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ |
1902 |
|
1902 |
|
1903 |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
1903 |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
1904 |
#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ |
1904 |
#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ |
1905 |
#endif |
1905 |
#endif |
1906 |
|
1906 |
|
1907 |
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ |
1907 |
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ |
1908 |
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ |
1908 |
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ |
1909 |
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ |
1909 |
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ |
1910 |
|
1910 |
|
1911 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
1911 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
1912 |
#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ |
1912 |
#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ |
1913 |
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ |
1913 |
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ |
1914 |
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ |
1914 |
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ |
1915 |
#endif |
1915 |
#endif |
1916 |
|
1916 |
|
1917 |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
1917 |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
1918 |
#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ |
1918 |
#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ |
1919 |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
1919 |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
1920 |
|
1920 |
|
1921 |
#if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
1921 |
#if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
1922 |
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ |
1922 |
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ |
1923 |
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ |
1923 |
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ |
1924 |
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ |
1924 |
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ |
1925 |
#define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ |
1925 |
#define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ |
1926 |
#endif |
1926 |
#endif |
1927 |
|
1927 |
|
1928 |
#if defined (STM32F10X_HD_VL) |
1928 |
#if defined (STM32F10X_HD_VL) |
1929 |
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ |
1929 |
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ |
1930 |
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ |
1930 |
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ |
1931 |
#endif |
1931 |
#endif |
1932 |
|
1932 |
|
1933 |
#ifdef STM32F10X_XL |
1933 |
#ifdef STM32F10X_XL |
1934 |
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ |
1934 |
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ |
1935 |
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ |
1935 |
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ |
1936 |
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ |
1936 |
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ |
1937 |
#endif /* STM32F10X_XL */ |
1937 |
#endif /* STM32F10X_XL */ |
1938 |
|
1938 |
|
1939 |
/***************** Bit definition for RCC_APB1RSTR register *****************/ |
1939 |
/***************** Bit definition for RCC_APB1RSTR register *****************/ |
1940 |
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ |
1940 |
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ |
1941 |
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ |
1941 |
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ |
1942 |
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ |
1942 |
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ |
1943 |
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ |
1943 |
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ |
1944 |
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ |
1944 |
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ |
1945 |
|
1945 |
|
1946 |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
1946 |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
1947 |
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ |
1947 |
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ |
1948 |
#endif |
1948 |
#endif |
1949 |
|
1949 |
|
1950 |
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ |
1950 |
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ |
1951 |
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ |
1951 |
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ |
1952 |
|
1952 |
|
1953 |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
1953 |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
1954 |
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ |
1954 |
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ |
1955 |
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ |
1955 |
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ |
1956 |
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ |
1956 |
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ |
1957 |
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ |
1957 |
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ |
1958 |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
1958 |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
1959 |
|
1959 |
|
1960 |
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) |
1960 |
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) |
1961 |
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ |
1961 |
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ |
1962 |
#endif |
1962 |
#endif |
1963 |
|
1963 |
|
1964 |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) |
1964 |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) |
1965 |
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ |
1965 |
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ |
1966 |
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
1966 |
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
1967 |
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
1967 |
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
1968 |
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ |
1968 |
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ |
1969 |
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ |
1969 |
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ |
1970 |
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ |
1970 |
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ |
1971 |
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ |
1971 |
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ |
1972 |
#endif |
1972 |
#endif |
1973 |
|
1973 |
|
1974 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
1974 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
1975 |
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
1975 |
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
1976 |
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
1976 |
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
1977 |
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ |
1977 |
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ |
1978 |
#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ |
1978 |
#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ |
1979 |
#endif |
1979 |
#endif |
1980 |
|
1980 |
|
1981 |
#if defined (STM32F10X_HD_VL) |
1981 |
#if defined (STM32F10X_HD_VL) |
1982 |
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ |
1982 |
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ |
1983 |
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ |
1983 |
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ |
1984 |
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ |
1984 |
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ |
1985 |
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ |
1985 |
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ |
1986 |
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ |
1986 |
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ |
1987 |
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ |
1987 |
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ |
1988 |
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ |
1988 |
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ |
1989 |
#endif |
1989 |
#endif |
1990 |
|
1990 |
|
1991 |
#ifdef STM32F10X_CL |
1991 |
#ifdef STM32F10X_CL |
1992 |
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ |
1992 |
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ |
1993 |
#endif /* STM32F10X_CL */ |
1993 |
#endif /* STM32F10X_CL */ |
1994 |
|
1994 |
|
1995 |
#ifdef STM32F10X_XL |
1995 |
#ifdef STM32F10X_XL |
1996 |
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ |
1996 |
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ |
1997 |
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ |
1997 |
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ |
1998 |
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ |
1998 |
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ |
1999 |
#endif /* STM32F10X_XL */ |
1999 |
#endif /* STM32F10X_XL */ |
2000 |
|
2000 |
|
2001 |
/****************** Bit definition for RCC_AHBENR register ******************/ |
2001 |
/****************** Bit definition for RCC_AHBENR register ******************/ |
2002 |
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ |
2002 |
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ |
2003 |
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ |
2003 |
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ |
2004 |
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ |
2004 |
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ |
2005 |
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ |
2005 |
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ |
2006 |
|
2006 |
|
2007 |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) |
2007 |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) |
2008 |
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ |
2008 |
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ |
2009 |
#endif |
2009 |
#endif |
2010 |
|
2010 |
|
2011 |
#if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
2011 |
#if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
2012 |
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ |
2012 |
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ |
2013 |
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ |
2013 |
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ |
2014 |
#endif |
2014 |
#endif |
2015 |
|
2015 |
|
2016 |
#if defined (STM32F10X_HD_VL) |
2016 |
#if defined (STM32F10X_HD_VL) |
2017 |
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ |
2017 |
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ |
2018 |
#endif |
2018 |
#endif |
2019 |
|
2019 |
|
2020 |
#ifdef STM32F10X_CL |
2020 |
#ifdef STM32F10X_CL |
2021 |
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ |
2021 |
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ |
2022 |
#define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ |
2022 |
#define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ |
2023 |
#define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ |
2023 |
#define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ |
2024 |
#define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ |
2024 |
#define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ |
2025 |
#endif /* STM32F10X_CL */ |
2025 |
#endif /* STM32F10X_CL */ |
2026 |
|
2026 |
|
2027 |
/****************** Bit definition for RCC_APB2ENR register *****************/ |
2027 |
/****************** Bit definition for RCC_APB2ENR register *****************/ |
2028 |
#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ |
2028 |
#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ |
2029 |
#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ |
2029 |
#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ |
2030 |
#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ |
2030 |
#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ |
2031 |
#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ |
2031 |
#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ |
2032 |
#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ |
2032 |
#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ |
2033 |
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ |
2033 |
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ |
2034 |
|
2034 |
|
2035 |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
2035 |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
2036 |
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ |
2036 |
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ |
2037 |
#endif |
2037 |
#endif |
2038 |
|
2038 |
|
2039 |
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ |
2039 |
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ |
2040 |
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ |
2040 |
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ |
2041 |
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ |
2041 |
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ |
2042 |
|
2042 |
|
2043 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
2043 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
2044 |
#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ |
2044 |
#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ |
2045 |
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ |
2045 |
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ |
2046 |
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ |
2046 |
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ |
2047 |
#endif |
2047 |
#endif |
2048 |
|
2048 |
|
2049 |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
2049 |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
2050 |
#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ |
2050 |
#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ |
2051 |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
2051 |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
2052 |
|
2052 |
|
2053 |
#if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
2053 |
#if defined (STM32F10X_HD) || defined (STM32F10X_XL) |
2054 |
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ |
2054 |
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ |
2055 |
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ |
2055 |
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ |
2056 |
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ |
2056 |
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ |
2057 |
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ |
2057 |
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ |
2058 |
#endif |
2058 |
#endif |
2059 |
|
2059 |
|
2060 |
#if defined (STM32F10X_HD_VL) |
2060 |
#if defined (STM32F10X_HD_VL) |
2061 |
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ |
2061 |
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ |
2062 |
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ |
2062 |
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ |
2063 |
#endif |
2063 |
#endif |
2064 |
|
2064 |
|
2065 |
#ifdef STM32F10X_XL |
2065 |
#ifdef STM32F10X_XL |
2066 |
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ |
2066 |
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ |
2067 |
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ |
2067 |
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ |
2068 |
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ |
2068 |
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ |
2069 |
#endif |
2069 |
#endif |
2070 |
|
2070 |
|
2071 |
/***************** Bit definition for RCC_APB1ENR register ******************/ |
2071 |
/***************** Bit definition for RCC_APB1ENR register ******************/ |
2072 |
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ |
2072 |
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ |
2073 |
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ |
2073 |
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ |
2074 |
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ |
2074 |
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ |
2075 |
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ |
2075 |
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ |
2076 |
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ |
2076 |
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ |
2077 |
|
2077 |
|
2078 |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
2078 |
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) |
2079 |
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ |
2079 |
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ |
2080 |
#endif |
2080 |
#endif |
2081 |
|
2081 |
|
2082 |
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ |
2082 |
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ |
2083 |
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ |
2083 |
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ |
2084 |
|
2084 |
|
2085 |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
2085 |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) |
2086 |
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ |
2086 |
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ |
2087 |
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ |
2087 |
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ |
2088 |
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ |
2088 |
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ |
2089 |
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ |
2089 |
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ |
2090 |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
2090 |
#endif /* STM32F10X_LD && STM32F10X_LD_VL */ |
2091 |
|
2091 |
|
2092 |
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) |
2092 |
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) |
2093 |
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ |
2093 |
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ |
2094 |
#endif |
2094 |
#endif |
2095 |
|
2095 |
|
2096 |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) |
2096 |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) |
2097 |
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ |
2097 |
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ |
2098 |
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
2098 |
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
2099 |
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
2099 |
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
2100 |
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ |
2100 |
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ |
2101 |
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ |
2101 |
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ |
2102 |
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ |
2102 |
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ |
2103 |
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ |
2103 |
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ |
2104 |
#endif |
2104 |
#endif |
2105 |
|
2105 |
|
2106 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
2106 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
2107 |
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
2107 |
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
2108 |
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
2108 |
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
2109 |
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ |
2109 |
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ |
2110 |
#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ |
2110 |
#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ |
2111 |
#endif |
2111 |
#endif |
2112 |
|
2112 |
|
2113 |
#ifdef STM32F10X_HD_VL |
2113 |
#ifdef STM32F10X_HD_VL |
2114 |
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ |
2114 |
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ |
2115 |
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ |
2115 |
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ |
2116 |
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ |
2116 |
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ |
2117 |
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ |
2117 |
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ |
2118 |
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ |
2118 |
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ |
2119 |
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ |
2119 |
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ |
2120 |
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ |
2120 |
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ |
2121 |
#endif /* STM32F10X_HD_VL */ |
2121 |
#endif /* STM32F10X_HD_VL */ |
2122 |
|
2122 |
|
2123 |
#ifdef STM32F10X_CL |
2123 |
#ifdef STM32F10X_CL |
2124 |
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ |
2124 |
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ |
2125 |
#endif /* STM32F10X_CL */ |
2125 |
#endif /* STM32F10X_CL */ |
2126 |
|
2126 |
|
2127 |
#ifdef STM32F10X_XL |
2127 |
#ifdef STM32F10X_XL |
2128 |
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ |
2128 |
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ |
2129 |
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ |
2129 |
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ |
2130 |
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ |
2130 |
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ |
2131 |
#endif /* STM32F10X_XL */ |
2131 |
#endif /* STM32F10X_XL */ |
2132 |
|
2132 |
|
2133 |
/******************* Bit definition for RCC_BDCR register *******************/ |
2133 |
/******************* Bit definition for RCC_BDCR register *******************/ |
2134 |
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ |
2134 |
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ |
2135 |
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ |
2135 |
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ |
2136 |
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ |
2136 |
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ |
2137 |
|
2137 |
|
2138 |
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
2138 |
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
2139 |
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2139 |
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2140 |
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2140 |
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2141 |
|
2141 |
|
2142 |
/*!< RTC congiguration */ |
2142 |
/*!< RTC congiguration */ |
2143 |
#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
2143 |
#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
2144 |
#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ |
2144 |
#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ |
2145 |
#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ |
2145 |
#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ |
2146 |
#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
2146 |
#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
2147 |
|
2147 |
|
2148 |
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ |
2148 |
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ |
2149 |
#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ |
2149 |
#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ |
2150 |
|
2150 |
|
2151 |
/******************* Bit definition for RCC_CSR register ********************/ |
2151 |
/******************* Bit definition for RCC_CSR register ********************/ |
2152 |
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ |
2152 |
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ |
2153 |
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ |
2153 |
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ |
2154 |
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ |
2154 |
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ |
2155 |
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ |
2155 |
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ |
2156 |
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ |
2156 |
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ |
2157 |
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ |
2157 |
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ |
2158 |
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ |
2158 |
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ |
2159 |
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ |
2159 |
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ |
2160 |
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ |
2160 |
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ |
2161 |
|
2161 |
|
2162 |
#ifdef STM32F10X_CL |
2162 |
#ifdef STM32F10X_CL |
2163 |
/******************* Bit definition for RCC_AHBRSTR register ****************/ |
2163 |
/******************* Bit definition for RCC_AHBRSTR register ****************/ |
2164 |
#define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ |
2164 |
#define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ |
2165 |
#define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ |
2165 |
#define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ |
2166 |
|
2166 |
|
2167 |
/******************* Bit definition for RCC_CFGR2 register ******************/ |
2167 |
/******************* Bit definition for RCC_CFGR2 register ******************/ |
2168 |
/*!< PREDIV1 configuration */ |
2168 |
/*!< PREDIV1 configuration */ |
2169 |
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ |
2169 |
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ |
2170 |
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
2170 |
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
2171 |
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
2171 |
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
2172 |
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
2172 |
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
2173 |
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
2173 |
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
2174 |
|
2174 |
|
2175 |
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ |
2175 |
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ |
2176 |
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ |
2176 |
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ |
2177 |
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ |
2177 |
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ |
2178 |
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ |
2178 |
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ |
2179 |
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ |
2179 |
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ |
2180 |
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ |
2180 |
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ |
2181 |
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ |
2181 |
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ |
2182 |
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ |
2182 |
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ |
2183 |
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ |
2183 |
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ |
2184 |
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ |
2184 |
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ |
2185 |
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ |
2185 |
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ |
2186 |
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ |
2186 |
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ |
2187 |
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ |
2187 |
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ |
2188 |
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ |
2188 |
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ |
2189 |
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ |
2189 |
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ |
2190 |
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ |
2190 |
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ |
2191 |
|
2191 |
|
2192 |
/*!< PREDIV2 configuration */ |
2192 |
/*!< PREDIV2 configuration */ |
2193 |
#define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ |
2193 |
#define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ |
2194 |
#define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
2194 |
#define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
2195 |
#define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
2195 |
#define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
2196 |
#define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
2196 |
#define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
2197 |
#define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
2197 |
#define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
2198 |
|
2198 |
|
2199 |
#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ |
2199 |
#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ |
2200 |
#define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ |
2200 |
#define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ |
2201 |
#define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ |
2201 |
#define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ |
2202 |
#define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ |
2202 |
#define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ |
2203 |
#define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ |
2203 |
#define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ |
2204 |
#define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ |
2204 |
#define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ |
2205 |
#define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ |
2205 |
#define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ |
2206 |
#define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ |
2206 |
#define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ |
2207 |
#define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ |
2207 |
#define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ |
2208 |
#define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ |
2208 |
#define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ |
2209 |
#define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ |
2209 |
#define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ |
2210 |
#define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ |
2210 |
#define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ |
2211 |
#define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ |
2211 |
#define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ |
2212 |
#define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ |
2212 |
#define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ |
2213 |
#define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ |
2213 |
#define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ |
2214 |
#define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ |
2214 |
#define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ |
2215 |
|
2215 |
|
2216 |
/*!< PLL2MUL configuration */ |
2216 |
/*!< PLL2MUL configuration */ |
2217 |
#define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ |
2217 |
#define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ |
2218 |
#define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2218 |
#define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2219 |
#define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2219 |
#define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2220 |
#define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
2220 |
#define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
2221 |
#define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
2221 |
#define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
2222 |
|
2222 |
|
2223 |
#define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ |
2223 |
#define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ |
2224 |
#define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ |
2224 |
#define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ |
2225 |
#define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ |
2225 |
#define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ |
2226 |
#define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ |
2226 |
#define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ |
2227 |
#define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ |
2227 |
#define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ |
2228 |
#define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ |
2228 |
#define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ |
2229 |
#define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ |
2229 |
#define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ |
2230 |
#define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ |
2230 |
#define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ |
2231 |
#define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ |
2231 |
#define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ |
2232 |
|
2232 |
|
2233 |
/*!< PLL3MUL configuration */ |
2233 |
/*!< PLL3MUL configuration */ |
2234 |
#define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ |
2234 |
#define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ |
2235 |
#define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
2235 |
#define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
2236 |
#define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
2236 |
#define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
2237 |
#define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
2237 |
#define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
2238 |
#define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ |
2238 |
#define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ |
2239 |
|
2239 |
|
2240 |
#define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ |
2240 |
#define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ |
2241 |
#define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ |
2241 |
#define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ |
2242 |
#define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ |
2242 |
#define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ |
2243 |
#define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ |
2243 |
#define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ |
2244 |
#define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ |
2244 |
#define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ |
2245 |
#define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ |
2245 |
#define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ |
2246 |
#define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ |
2246 |
#define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ |
2247 |
#define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ |
2247 |
#define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ |
2248 |
#define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ |
2248 |
#define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ |
2249 |
|
2249 |
|
2250 |
#define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ |
2250 |
#define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ |
2251 |
#define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ |
2251 |
#define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ |
2252 |
#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ |
2252 |
#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ |
2253 |
#define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ |
2253 |
#define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ |
2254 |
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ |
2254 |
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ |
2255 |
#endif /* STM32F10X_CL */ |
2255 |
#endif /* STM32F10X_CL */ |
2256 |
|
2256 |
|
2257 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
2257 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
2258 |
/******************* Bit definition for RCC_CFGR2 register ******************/ |
2258 |
/******************* Bit definition for RCC_CFGR2 register ******************/ |
2259 |
/*!< PREDIV1 configuration */ |
2259 |
/*!< PREDIV1 configuration */ |
2260 |
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ |
2260 |
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ |
2261 |
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
2261 |
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
2262 |
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
2262 |
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
2263 |
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
2263 |
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
2264 |
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
2264 |
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
2265 |
|
2265 |
|
2266 |
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ |
2266 |
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ |
2267 |
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ |
2267 |
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ |
2268 |
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ |
2268 |
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ |
2269 |
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ |
2269 |
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ |
2270 |
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ |
2270 |
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ |
2271 |
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ |
2271 |
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ |
2272 |
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ |
2272 |
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ |
2273 |
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ |
2273 |
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ |
2274 |
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ |
2274 |
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ |
2275 |
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ |
2275 |
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ |
2276 |
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ |
2276 |
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ |
2277 |
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ |
2277 |
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ |
2278 |
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ |
2278 |
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ |
2279 |
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ |
2279 |
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ |
2280 |
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ |
2280 |
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ |
2281 |
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ |
2281 |
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ |
2282 |
#endif |
2282 |
#endif |
2283 |
|
2283 |
|
2284 |
/******************************************************************************/ |
2284 |
/******************************************************************************/ |
2285 |
/* */ |
2285 |
/* */ |
2286 |
/* General Purpose and Alternate Function I/O */ |
2286 |
/* General Purpose and Alternate Function I/O */ |
2287 |
/* */ |
2287 |
/* */ |
2288 |
/******************************************************************************/ |
2288 |
/******************************************************************************/ |
2289 |
|
2289 |
|
2290 |
/******************* Bit definition for GPIO_CRL register *******************/ |
2290 |
/******************* Bit definition for GPIO_CRL register *******************/ |
2291 |
#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
2291 |
#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
2292 |
|
2292 |
|
2293 |
#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
2293 |
#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
2294 |
#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
2294 |
#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
2295 |
#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
2295 |
#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
2296 |
|
2296 |
|
2297 |
#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
2297 |
#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
2298 |
#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
2298 |
#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
2299 |
#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
2299 |
#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
2300 |
|
2300 |
|
2301 |
#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
2301 |
#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
2302 |
#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2302 |
#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2303 |
#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2303 |
#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2304 |
|
2304 |
|
2305 |
#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
2305 |
#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
2306 |
#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
2306 |
#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
2307 |
#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
2307 |
#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
2308 |
|
2308 |
|
2309 |
#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
2309 |
#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
2310 |
#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
2310 |
#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
2311 |
#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
2311 |
#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
2312 |
|
2312 |
|
2313 |
#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
2313 |
#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
2314 |
#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
2314 |
#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
2315 |
#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
2315 |
#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
2316 |
|
2316 |
|
2317 |
#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
2317 |
#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
2318 |
#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
2318 |
#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
2319 |
#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
2319 |
#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
2320 |
|
2320 |
|
2321 |
#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
2321 |
#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
2322 |
#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
2322 |
#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
2323 |
#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
2323 |
#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
2324 |
|
2324 |
|
2325 |
#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
2325 |
#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
2326 |
|
2326 |
|
2327 |
#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
2327 |
#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
2328 |
#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
2328 |
#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
2329 |
#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
2329 |
#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
2330 |
|
2330 |
|
2331 |
#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
2331 |
#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
2332 |
#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
2332 |
#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
2333 |
#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
2333 |
#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
2334 |
|
2334 |
|
2335 |
#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
2335 |
#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
2336 |
#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
2336 |
#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
2337 |
#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
2337 |
#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
2338 |
|
2338 |
|
2339 |
#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
2339 |
#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
2340 |
#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
2340 |
#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
2341 |
#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
2341 |
#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
2342 |
|
2342 |
|
2343 |
#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
2343 |
#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
2344 |
#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
2344 |
#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
2345 |
#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
2345 |
#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
2346 |
|
2346 |
|
2347 |
#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
2347 |
#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
2348 |
#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
2348 |
#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
2349 |
#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
2349 |
#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
2350 |
|
2350 |
|
2351 |
#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
2351 |
#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
2352 |
#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
2352 |
#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
2353 |
#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
2353 |
#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
2354 |
|
2354 |
|
2355 |
#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
2355 |
#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
2356 |
#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
2356 |
#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
2357 |
#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
2357 |
#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
2358 |
|
2358 |
|
2359 |
/******************* Bit definition for GPIO_CRH register *******************/ |
2359 |
/******************* Bit definition for GPIO_CRH register *******************/ |
2360 |
#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
2360 |
#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
2361 |
|
2361 |
|
2362 |
#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
2362 |
#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
2363 |
#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
2363 |
#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
2364 |
#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
2364 |
#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
2365 |
|
2365 |
|
2366 |
#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
2366 |
#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
2367 |
#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
2367 |
#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
2368 |
#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
2368 |
#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
2369 |
|
2369 |
|
2370 |
#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
2370 |
#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
2371 |
#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2371 |
#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2372 |
#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2372 |
#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2373 |
|
2373 |
|
2374 |
#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
2374 |
#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
2375 |
#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
2375 |
#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
2376 |
#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
2376 |
#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
2377 |
|
2377 |
|
2378 |
#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
2378 |
#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
2379 |
#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
2379 |
#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
2380 |
#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
2380 |
#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
2381 |
|
2381 |
|
2382 |
#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
2382 |
#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
2383 |
#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
2383 |
#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
2384 |
#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
2384 |
#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
2385 |
|
2385 |
|
2386 |
#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
2386 |
#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
2387 |
#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
2387 |
#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
2388 |
#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
2388 |
#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
2389 |
|
2389 |
|
2390 |
#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
2390 |
#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
2391 |
#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
2391 |
#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
2392 |
#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
2392 |
#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
2393 |
|
2393 |
|
2394 |
#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
2394 |
#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
2395 |
|
2395 |
|
2396 |
#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
2396 |
#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
2397 |
#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
2397 |
#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
2398 |
#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
2398 |
#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
2399 |
|
2399 |
|
2400 |
#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
2400 |
#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
2401 |
#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
2401 |
#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
2402 |
#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
2402 |
#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
2403 |
|
2403 |
|
2404 |
#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
2404 |
#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
2405 |
#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
2405 |
#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
2406 |
#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
2406 |
#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
2407 |
|
2407 |
|
2408 |
#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
2408 |
#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
2409 |
#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
2409 |
#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
2410 |
#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
2410 |
#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
2411 |
|
2411 |
|
2412 |
#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
2412 |
#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
2413 |
#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
2413 |
#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
2414 |
#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
2414 |
#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
2415 |
|
2415 |
|
2416 |
#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
2416 |
#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
2417 |
#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
2417 |
#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
2418 |
#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
2418 |
#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
2419 |
|
2419 |
|
2420 |
#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
2420 |
#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
2421 |
#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
2421 |
#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
2422 |
#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
2422 |
#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
2423 |
|
2423 |
|
2424 |
#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
2424 |
#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
2425 |
#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
2425 |
#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
2426 |
#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
2426 |
#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
2427 |
|
2427 |
|
2428 |
/*!<****************** Bit definition for GPIO_IDR register *******************/ |
2428 |
/*!<****************** Bit definition for GPIO_IDR register *******************/ |
2429 |
#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ |
2429 |
#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ |
2430 |
#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ |
2430 |
#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ |
2431 |
#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ |
2431 |
#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ |
2432 |
#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ |
2432 |
#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ |
2433 |
#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ |
2433 |
#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ |
2434 |
#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ |
2434 |
#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ |
2435 |
#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ |
2435 |
#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ |
2436 |
#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ |
2436 |
#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ |
2437 |
#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ |
2437 |
#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ |
2438 |
#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ |
2438 |
#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ |
2439 |
#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ |
2439 |
#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ |
2440 |
#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ |
2440 |
#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ |
2441 |
#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ |
2441 |
#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ |
2442 |
#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ |
2442 |
#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ |
2443 |
#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ |
2443 |
#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ |
2444 |
#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ |
2444 |
#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ |
2445 |
|
2445 |
|
2446 |
/******************* Bit definition for GPIO_ODR register *******************/ |
2446 |
/******************* Bit definition for GPIO_ODR register *******************/ |
2447 |
#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ |
2447 |
#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ |
2448 |
#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ |
2448 |
#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ |
2449 |
#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ |
2449 |
#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ |
2450 |
#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ |
2450 |
#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ |
2451 |
#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ |
2451 |
#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ |
2452 |
#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ |
2452 |
#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ |
2453 |
#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ |
2453 |
#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ |
2454 |
#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ |
2454 |
#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ |
2455 |
#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ |
2455 |
#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ |
2456 |
#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ |
2456 |
#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ |
2457 |
#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ |
2457 |
#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ |
2458 |
#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ |
2458 |
#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ |
2459 |
#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ |
2459 |
#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ |
2460 |
#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ |
2460 |
#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ |
2461 |
#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ |
2461 |
#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ |
2462 |
#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ |
2462 |
#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ |
2463 |
|
2463 |
|
2464 |
/****************** Bit definition for GPIO_BSRR register *******************/ |
2464 |
/****************** Bit definition for GPIO_BSRR register *******************/ |
2465 |
#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ |
2465 |
#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ |
2466 |
#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ |
2466 |
#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ |
2467 |
#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ |
2467 |
#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ |
2468 |
#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ |
2468 |
#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ |
2469 |
#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ |
2469 |
#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ |
2470 |
#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ |
2470 |
#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ |
2471 |
#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ |
2471 |
#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ |
2472 |
#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ |
2472 |
#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ |
2473 |
#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ |
2473 |
#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ |
2474 |
#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ |
2474 |
#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ |
2475 |
#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ |
2475 |
#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ |
2476 |
#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ |
2476 |
#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ |
2477 |
#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ |
2477 |
#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ |
2478 |
#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ |
2478 |
#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ |
2479 |
#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ |
2479 |
#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ |
2480 |
#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ |
2480 |
#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ |
2481 |
|
2481 |
|
2482 |
#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ |
2482 |
#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ |
2483 |
#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ |
2483 |
#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ |
2484 |
#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ |
2484 |
#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ |
2485 |
#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ |
2485 |
#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ |
2486 |
#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ |
2486 |
#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ |
2487 |
#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ |
2487 |
#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ |
2488 |
#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ |
2488 |
#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ |
2489 |
#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ |
2489 |
#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ |
2490 |
#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ |
2490 |
#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ |
2491 |
#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ |
2491 |
#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ |
2492 |
#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ |
2492 |
#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ |
2493 |
#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ |
2493 |
#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ |
2494 |
#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ |
2494 |
#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ |
2495 |
#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ |
2495 |
#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ |
2496 |
#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ |
2496 |
#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ |
2497 |
#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ |
2497 |
#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ |
2498 |
|
2498 |
|
2499 |
/******************* Bit definition for GPIO_BRR register *******************/ |
2499 |
/******************* Bit definition for GPIO_BRR register *******************/ |
2500 |
#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ |
2500 |
#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ |
2501 |
#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ |
2501 |
#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ |
2502 |
#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ |
2502 |
#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ |
2503 |
#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ |
2503 |
#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ |
2504 |
#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ |
2504 |
#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ |
2505 |
#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ |
2505 |
#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ |
2506 |
#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ |
2506 |
#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ |
2507 |
#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ |
2507 |
#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ |
2508 |
#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ |
2508 |
#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ |
2509 |
#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ |
2509 |
#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ |
2510 |
#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ |
2510 |
#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ |
2511 |
#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ |
2511 |
#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ |
2512 |
#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ |
2512 |
#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ |
2513 |
#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ |
2513 |
#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ |
2514 |
#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ |
2514 |
#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ |
2515 |
#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ |
2515 |
#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ |
2516 |
|
2516 |
|
2517 |
/****************** Bit definition for GPIO_LCKR register *******************/ |
2517 |
/****************** Bit definition for GPIO_LCKR register *******************/ |
2518 |
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ |
2518 |
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ |
2519 |
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ |
2519 |
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ |
2520 |
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ |
2520 |
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ |
2521 |
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ |
2521 |
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ |
2522 |
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ |
2522 |
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ |
2523 |
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ |
2523 |
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ |
2524 |
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ |
2524 |
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ |
2525 |
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ |
2525 |
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ |
2526 |
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ |
2526 |
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ |
2527 |
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ |
2527 |
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ |
2528 |
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ |
2528 |
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ |
2529 |
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ |
2529 |
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ |
2530 |
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ |
2530 |
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ |
2531 |
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ |
2531 |
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ |
2532 |
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ |
2532 |
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ |
2533 |
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ |
2533 |
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ |
2534 |
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ |
2534 |
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ |
2535 |
|
2535 |
|
2536 |
/*----------------------------------------------------------------------------*/ |
2536 |
/*----------------------------------------------------------------------------*/ |
2537 |
|
2537 |
|
2538 |
/****************** Bit definition for AFIO_EVCR register *******************/ |
2538 |
/****************** Bit definition for AFIO_EVCR register *******************/ |
2539 |
#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ |
2539 |
#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ |
2540 |
#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ |
2540 |
#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ |
2541 |
#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ |
2541 |
#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ |
2542 |
#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ |
2542 |
#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ |
2543 |
#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ |
2543 |
#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ |
2544 |
|
2544 |
|
2545 |
/*!< PIN configuration */ |
2545 |
/*!< PIN configuration */ |
2546 |
#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ |
2546 |
#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ |
2547 |
#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ |
2547 |
#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ |
2548 |
#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ |
2548 |
#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ |
2549 |
#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ |
2549 |
#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ |
2550 |
#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ |
2550 |
#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ |
2551 |
#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ |
2551 |
#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ |
2552 |
#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ |
2552 |
#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ |
2553 |
#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ |
2553 |
#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ |
2554 |
#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ |
2554 |
#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ |
2555 |
#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ |
2555 |
#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ |
2556 |
#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ |
2556 |
#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ |
2557 |
#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ |
2557 |
#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ |
2558 |
#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ |
2558 |
#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ |
2559 |
#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ |
2559 |
#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ |
2560 |
#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ |
2560 |
#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ |
2561 |
#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ |
2561 |
#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ |
2562 |
|
2562 |
|
2563 |
#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ |
2563 |
#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ |
2564 |
#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ |
2564 |
#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ |
2565 |
#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ |
2565 |
#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ |
2566 |
#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ |
2566 |
#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ |
2567 |
|
2567 |
|
2568 |
/*!< PORT configuration */ |
2568 |
/*!< PORT configuration */ |
2569 |
#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ |
2569 |
#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ |
2570 |
#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ |
2570 |
#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ |
2571 |
#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ |
2571 |
#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ |
2572 |
#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ |
2572 |
#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ |
2573 |
#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ |
2573 |
#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ |
2574 |
|
2574 |
|
2575 |
#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ |
2575 |
#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ |
2576 |
|
2576 |
|
2577 |
/****************** Bit definition for AFIO_MAPR register *******************/ |
2577 |
/****************** Bit definition for AFIO_MAPR register *******************/ |
2578 |
#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ |
2578 |
#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ |
2579 |
#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ |
2579 |
#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ |
2580 |
#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ |
2580 |
#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ |
2581 |
#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ |
2581 |
#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ |
2582 |
|
2582 |
|
2583 |
#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
2583 |
#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
2584 |
#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
2584 |
#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
2585 |
#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
2585 |
#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
2586 |
|
2586 |
|
2587 |
/* USART3_REMAP configuration */ |
2587 |
/* USART3_REMAP configuration */ |
2588 |
#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
2588 |
#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
2589 |
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
2589 |
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
2590 |
#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
2590 |
#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
2591 |
|
2591 |
|
2592 |
#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
2592 |
#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
2593 |
#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
2593 |
#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
2594 |
#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
2594 |
#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
2595 |
|
2595 |
|
2596 |
/*!< TIM1_REMAP configuration */ |
2596 |
/*!< TIM1_REMAP configuration */ |
2597 |
#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
2597 |
#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
2598 |
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
2598 |
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
2599 |
#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
2599 |
#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
2600 |
|
2600 |
|
2601 |
#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
2601 |
#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
2602 |
#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2602 |
#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
2603 |
#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2603 |
#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
2604 |
|
2604 |
|
2605 |
/*!< TIM2_REMAP configuration */ |
2605 |
/*!< TIM2_REMAP configuration */ |
2606 |
#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
2606 |
#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
2607 |
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
2607 |
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
2608 |
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
2608 |
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
2609 |
#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
2609 |
#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
2610 |
|
2610 |
|
2611 |
#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
2611 |
#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
2612 |
#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
2612 |
#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
2613 |
#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
2613 |
#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
2614 |
|
2614 |
|
2615 |
/*!< TIM3_REMAP configuration */ |
2615 |
/*!< TIM3_REMAP configuration */ |
2616 |
#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
2616 |
#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
2617 |
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
2617 |
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
2618 |
#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
2618 |
#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
2619 |
|
2619 |
|
2620 |
#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ |
2620 |
#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ |
2621 |
|
2621 |
|
2622 |
#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ |
2622 |
#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ |
2623 |
#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
2623 |
#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
2624 |
#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
2624 |
#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
2625 |
|
2625 |
|
2626 |
/*!< CAN_REMAP configuration */ |
2626 |
/*!< CAN_REMAP configuration */ |
2627 |
#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ |
2627 |
#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ |
2628 |
#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ |
2628 |
#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ |
2629 |
#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ |
2629 |
#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ |
2630 |
|
2630 |
|
2631 |
#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
2631 |
#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
2632 |
#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ |
2632 |
#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ |
2633 |
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ |
2633 |
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ |
2634 |
#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ |
2634 |
#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ |
2635 |
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ |
2635 |
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ |
2636 |
#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ |
2636 |
#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ |
2637 |
|
2637 |
|
2638 |
/*!< SWJ_CFG configuration */ |
2638 |
/*!< SWJ_CFG configuration */ |
2639 |
#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
2639 |
#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
2640 |
#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
2640 |
#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
2641 |
#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
2641 |
#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
2642 |
#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
2642 |
#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
2643 |
|
2643 |
|
2644 |
#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
2644 |
#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
2645 |
#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
2645 |
#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
2646 |
#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ |
2646 |
#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ |
2647 |
#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ |
2647 |
#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ |
2648 |
|
2648 |
|
2649 |
#ifdef STM32F10X_CL |
2649 |
#ifdef STM32F10X_CL |
2650 |
/*!< ETH_REMAP configuration */ |
2650 |
/*!< ETH_REMAP configuration */ |
2651 |
#define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ |
2651 |
#define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ |
2652 |
|
2652 |
|
2653 |
/*!< CAN2_REMAP configuration */ |
2653 |
/*!< CAN2_REMAP configuration */ |
2654 |
#define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ |
2654 |
#define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ |
2655 |
|
2655 |
|
2656 |
/*!< MII_RMII_SEL configuration */ |
2656 |
/*!< MII_RMII_SEL configuration */ |
2657 |
#define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ |
2657 |
#define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ |
2658 |
|
2658 |
|
2659 |
/*!< SPI3_REMAP configuration */ |
2659 |
/*!< SPI3_REMAP configuration */ |
2660 |
#define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ |
2660 |
#define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ |
2661 |
|
2661 |
|
2662 |
/*!< TIM2ITR1_IREMAP configuration */ |
2662 |
/*!< TIM2ITR1_IREMAP configuration */ |
2663 |
#define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ |
2663 |
#define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ |
2664 |
|
2664 |
|
2665 |
/*!< PTP_PPS_REMAP configuration */ |
2665 |
/*!< PTP_PPS_REMAP configuration */ |
2666 |
#define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ |
2666 |
#define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ |
2667 |
#endif |
2667 |
#endif |
2668 |
|
2668 |
|
2669 |
/***************** Bit definition for AFIO_EXTICR1 register *****************/ |
2669 |
/***************** Bit definition for AFIO_EXTICR1 register *****************/ |
2670 |
#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ |
2670 |
#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ |
2671 |
#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ |
2671 |
#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ |
2672 |
#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ |
2672 |
#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ |
2673 |
#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ |
2673 |
#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ |
2674 |
|
2674 |
|
2675 |
/*!< EXTI0 configuration */ |
2675 |
/*!< EXTI0 configuration */ |
2676 |
#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ |
2676 |
#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ |
2677 |
#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ |
2677 |
#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ |
2678 |
#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ |
2678 |
#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ |
2679 |
#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ |
2679 |
#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ |
2680 |
#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ |
2680 |
#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ |
2681 |
#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ |
2681 |
#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ |
2682 |
#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ |
2682 |
#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ |
2683 |
|
2683 |
|
2684 |
/*!< EXTI1 configuration */ |
2684 |
/*!< EXTI1 configuration */ |
2685 |
#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ |
2685 |
#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ |
2686 |
#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ |
2686 |
#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ |
2687 |
#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ |
2687 |
#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ |
2688 |
#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ |
2688 |
#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ |
2689 |
#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ |
2689 |
#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ |
2690 |
#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ |
2690 |
#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ |
2691 |
#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ |
2691 |
#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ |
2692 |
|
2692 |
|
2693 |
/*!< EXTI2 configuration */ |
2693 |
/*!< EXTI2 configuration */ |
2694 |
#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ |
2694 |
#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ |
2695 |
#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ |
2695 |
#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ |
2696 |
#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ |
2696 |
#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ |
2697 |
#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ |
2697 |
#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ |
2698 |
#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ |
2698 |
#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ |
2699 |
#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ |
2699 |
#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ |
2700 |
#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ |
2700 |
#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ |
2701 |
|
2701 |
|
2702 |
/*!< EXTI3 configuration */ |
2702 |
/*!< EXTI3 configuration */ |
2703 |
#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ |
2703 |
#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ |
2704 |
#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ |
2704 |
#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ |
2705 |
#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ |
2705 |
#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ |
2706 |
#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ |
2706 |
#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ |
2707 |
#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ |
2707 |
#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ |
2708 |
#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ |
2708 |
#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ |
2709 |
#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ |
2709 |
#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ |
2710 |
|
2710 |
|
2711 |
/***************** Bit definition for AFIO_EXTICR2 register *****************/ |
2711 |
/***************** Bit definition for AFIO_EXTICR2 register *****************/ |
2712 |
#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ |
2712 |
#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ |
2713 |
#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ |
2713 |
#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ |
2714 |
#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ |
2714 |
#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ |
2715 |
#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ |
2715 |
#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ |
2716 |
|
2716 |
|
2717 |
/*!< EXTI4 configuration */ |
2717 |
/*!< EXTI4 configuration */ |
2718 |
#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ |
2718 |
#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ |
2719 |
#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ |
2719 |
#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ |
2720 |
#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ |
2720 |
#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ |
2721 |
#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ |
2721 |
#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ |
2722 |
#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ |
2722 |
#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ |
2723 |
#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ |
2723 |
#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ |
2724 |
#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ |
2724 |
#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ |
2725 |
|
2725 |
|
2726 |
/* EXTI5 configuration */ |
2726 |
/* EXTI5 configuration */ |
2727 |
#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ |
2727 |
#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ |
2728 |
#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ |
2728 |
#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ |
2729 |
#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ |
2729 |
#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ |
2730 |
#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ |
2730 |
#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ |
2731 |
#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ |
2731 |
#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ |
2732 |
#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ |
2732 |
#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ |
2733 |
#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ |
2733 |
#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ |
2734 |
|
2734 |
|
2735 |
/*!< EXTI6 configuration */ |
2735 |
/*!< EXTI6 configuration */ |
2736 |
#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ |
2736 |
#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ |
2737 |
#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ |
2737 |
#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ |
2738 |
#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ |
2738 |
#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ |
2739 |
#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ |
2739 |
#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ |
2740 |
#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ |
2740 |
#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ |
2741 |
#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ |
2741 |
#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ |
2742 |
#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ |
2742 |
#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ |
2743 |
|
2743 |
|
2744 |
/*!< EXTI7 configuration */ |
2744 |
/*!< EXTI7 configuration */ |
2745 |
#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ |
2745 |
#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ |
2746 |
#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ |
2746 |
#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ |
2747 |
#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ |
2747 |
#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ |
2748 |
#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ |
2748 |
#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ |
2749 |
#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ |
2749 |
#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ |
2750 |
#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ |
2750 |
#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ |
2751 |
#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ |
2751 |
#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ |
2752 |
|
2752 |
|
2753 |
/***************** Bit definition for AFIO_EXTICR3 register *****************/ |
2753 |
/***************** Bit definition for AFIO_EXTICR3 register *****************/ |
2754 |
#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ |
2754 |
#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ |
2755 |
#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ |
2755 |
#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ |
2756 |
#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ |
2756 |
#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ |
2757 |
#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ |
2757 |
#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ |
2758 |
|
2758 |
|
2759 |
/*!< EXTI8 configuration */ |
2759 |
/*!< EXTI8 configuration */ |
2760 |
#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ |
2760 |
#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ |
2761 |
#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ |
2761 |
#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ |
2762 |
#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ |
2762 |
#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ |
2763 |
#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ |
2763 |
#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ |
2764 |
#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ |
2764 |
#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ |
2765 |
#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ |
2765 |
#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ |
2766 |
#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ |
2766 |
#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ |
2767 |
|
2767 |
|
2768 |
/*!< EXTI9 configuration */ |
2768 |
/*!< EXTI9 configuration */ |
2769 |
#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ |
2769 |
#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ |
2770 |
#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ |
2770 |
#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ |
2771 |
#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ |
2771 |
#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ |
2772 |
#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ |
2772 |
#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ |
2773 |
#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ |
2773 |
#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ |
2774 |
#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ |
2774 |
#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ |
2775 |
#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ |
2775 |
#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ |
2776 |
|
2776 |
|
2777 |
/*!< EXTI10 configuration */ |
2777 |
/*!< EXTI10 configuration */ |
2778 |
#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ |
2778 |
#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ |
2779 |
#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ |
2779 |
#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ |
2780 |
#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ |
2780 |
#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ |
2781 |
#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ |
2781 |
#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ |
2782 |
#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ |
2782 |
#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ |
2783 |
#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ |
2783 |
#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ |
2784 |
#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ |
2784 |
#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ |
2785 |
|
2785 |
|
2786 |
/*!< EXTI11 configuration */ |
2786 |
/*!< EXTI11 configuration */ |
2787 |
#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ |
2787 |
#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ |
2788 |
#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ |
2788 |
#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ |
2789 |
#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ |
2789 |
#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ |
2790 |
#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ |
2790 |
#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ |
2791 |
#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ |
2791 |
#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ |
2792 |
#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ |
2792 |
#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ |
2793 |
#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ |
2793 |
#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ |
2794 |
|
2794 |
|
2795 |
/***************** Bit definition for AFIO_EXTICR4 register *****************/ |
2795 |
/***************** Bit definition for AFIO_EXTICR4 register *****************/ |
2796 |
#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ |
2796 |
#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ |
2797 |
#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ |
2797 |
#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ |
2798 |
#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ |
2798 |
#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ |
2799 |
#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ |
2799 |
#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ |
2800 |
|
2800 |
|
2801 |
/* EXTI12 configuration */ |
2801 |
/* EXTI12 configuration */ |
2802 |
#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ |
2802 |
#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ |
2803 |
#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ |
2803 |
#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ |
2804 |
#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ |
2804 |
#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ |
2805 |
#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ |
2805 |
#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ |
2806 |
#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ |
2806 |
#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ |
2807 |
#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ |
2807 |
#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ |
2808 |
#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ |
2808 |
#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ |
2809 |
|
2809 |
|
2810 |
/* EXTI13 configuration */ |
2810 |
/* EXTI13 configuration */ |
2811 |
#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ |
2811 |
#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ |
2812 |
#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ |
2812 |
#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ |
2813 |
#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ |
2813 |
#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ |
2814 |
#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ |
2814 |
#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ |
2815 |
#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ |
2815 |
#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ |
2816 |
#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ |
2816 |
#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ |
2817 |
#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ |
2817 |
#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ |
2818 |
|
2818 |
|
2819 |
/*!< EXTI14 configuration */ |
2819 |
/*!< EXTI14 configuration */ |
2820 |
#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ |
2820 |
#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ |
2821 |
#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ |
2821 |
#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ |
2822 |
#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ |
2822 |
#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ |
2823 |
#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ |
2823 |
#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ |
2824 |
#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ |
2824 |
#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ |
2825 |
#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ |
2825 |
#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ |
2826 |
#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ |
2826 |
#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ |
2827 |
|
2827 |
|
2828 |
/*!< EXTI15 configuration */ |
2828 |
/*!< EXTI15 configuration */ |
2829 |
#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ |
2829 |
#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ |
2830 |
#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ |
2830 |
#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ |
2831 |
#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ |
2831 |
#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ |
2832 |
#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ |
2832 |
#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ |
2833 |
#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ |
2833 |
#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ |
2834 |
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ |
2834 |
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ |
2835 |
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ |
2835 |
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ |
2836 |
|
2836 |
|
2837 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
2837 |
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
2838 |
/****************** Bit definition for AFIO_MAPR2 register ******************/ |
2838 |
/****************** Bit definition for AFIO_MAPR2 register ******************/ |
2839 |
#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ |
2839 |
#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ |
2840 |
#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ |
2840 |
#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ |
2841 |
#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ |
2841 |
#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ |
2842 |
#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ |
2842 |
#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ |
2843 |
#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ |
2843 |
#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ |
2844 |
#endif |
2844 |
#endif |
2845 |
|
2845 |
|
2846 |
#ifdef STM32F10X_HD_VL |
2846 |
#ifdef STM32F10X_HD_VL |
2847 |
#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ |
2847 |
#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ |
2848 |
#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ |
2848 |
#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ |
2849 |
#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ |
2849 |
#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ |
2850 |
#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ |
2850 |
#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ |
2851 |
#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ |
2851 |
#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ |
2852 |
#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ |
2852 |
#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ |
2853 |
#endif |
2853 |
#endif |
2854 |
|
2854 |
|
2855 |
#ifdef STM32F10X_XL |
2855 |
#ifdef STM32F10X_XL |
2856 |
/****************** Bit definition for AFIO_MAPR2 register ******************/ |
2856 |
/****************** Bit definition for AFIO_MAPR2 register ******************/ |
2857 |
#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ |
2857 |
#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ |
2858 |
#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ |
2858 |
#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ |
2859 |
#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ |
2859 |
#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ |
2860 |
#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ |
2860 |
#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ |
2861 |
#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ |
2861 |
#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ |
2862 |
#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ |
2862 |
#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ |
2863 |
#endif |
2863 |
#endif |
2864 |
|
2864 |
|
2865 |
/******************************************************************************/ |
2865 |
/******************************************************************************/ |
2866 |
/* */ |
2866 |
/* */ |
2867 |
/* SystemTick */ |
2867 |
/* SystemTick */ |
2868 |
/* */ |
2868 |
/* */ |
2869 |
/******************************************************************************/ |
2869 |
/******************************************************************************/ |
2870 |
|
2870 |
|
2871 |
/***************** Bit definition for SysTick_CTRL register *****************/ |
2871 |
/***************** Bit definition for SysTick_CTRL register *****************/ |
2872 |
#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ |
2872 |
#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ |
2873 |
#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ |
2873 |
#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ |
2874 |
#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ |
2874 |
#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ |
2875 |
#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ |
2875 |
#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ |
2876 |
|
2876 |
|
2877 |
/***************** Bit definition for SysTick_LOAD register *****************/ |
2877 |
/***************** Bit definition for SysTick_LOAD register *****************/ |
2878 |
#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ |
2878 |
#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ |
2879 |
|
2879 |
|
2880 |
/***************** Bit definition for SysTick_VAL register ******************/ |
2880 |
/***************** Bit definition for SysTick_VAL register ******************/ |
2881 |
#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ |
2881 |
#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ |
2882 |
|
2882 |
|
2883 |
/***************** Bit definition for SysTick_CALIB register ****************/ |
2883 |
/***************** Bit definition for SysTick_CALIB register ****************/ |
2884 |
#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ |
2884 |
#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ |
2885 |
#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ |
2885 |
#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ |
2886 |
#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ |
2886 |
#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ |
2887 |
|
2887 |
|
2888 |
/******************************************************************************/ |
2888 |
/******************************************************************************/ |
2889 |
/* */ |
2889 |
/* */ |
2890 |
/* Nested Vectored Interrupt Controller */ |
2890 |
/* Nested Vectored Interrupt Controller */ |
2891 |
/* */ |
2891 |
/* */ |
2892 |
/******************************************************************************/ |
2892 |
/******************************************************************************/ |
2893 |
|
2893 |
|
2894 |
/****************** Bit definition for NVIC_ISER register *******************/ |
2894 |
/****************** Bit definition for NVIC_ISER register *******************/ |
2895 |
#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ |
2895 |
#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ |
2896 |
#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
2896 |
#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
2897 |
#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
2897 |
#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
2898 |
#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
2898 |
#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
2899 |
#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
2899 |
#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
2900 |
#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
2900 |
#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
2901 |
#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
2901 |
#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
2902 |
#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
2902 |
#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
2903 |
#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
2903 |
#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
2904 |
#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
2904 |
#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
2905 |
#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
2905 |
#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
2906 |
#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
2906 |
#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
2907 |
#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
2907 |
#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
2908 |
#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
2908 |
#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
2909 |
#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
2909 |
#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
2910 |
#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
2910 |
#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
2911 |
#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
2911 |
#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
2912 |
#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
2912 |
#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
2913 |
#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
2913 |
#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
2914 |
#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
2914 |
#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
2915 |
#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
2915 |
#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
2916 |
#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
2916 |
#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
2917 |
#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
2917 |
#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
2918 |
#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
2918 |
#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
2919 |
#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
2919 |
#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
2920 |
#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
2920 |
#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
2921 |
#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
2921 |
#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
2922 |
#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
2922 |
#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
2923 |
#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
2923 |
#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
2924 |
#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
2924 |
#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
2925 |
#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
2925 |
#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
2926 |
#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
2926 |
#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
2927 |
#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
2927 |
#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
2928 |
|
2928 |
|
2929 |
/****************** Bit definition for NVIC_ICER register *******************/ |
2929 |
/****************** Bit definition for NVIC_ICER register *******************/ |
2930 |
#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ |
2930 |
#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ |
2931 |
#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
2931 |
#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
2932 |
#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
2932 |
#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
2933 |
#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
2933 |
#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
2934 |
#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
2934 |
#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
2935 |
#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
2935 |
#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
2936 |
#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
2936 |
#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
2937 |
#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
2937 |
#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
2938 |
#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
2938 |
#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
2939 |
#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
2939 |
#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
2940 |
#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
2940 |
#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
2941 |
#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
2941 |
#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
2942 |
#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
2942 |
#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
2943 |
#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
2943 |
#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
2944 |
#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
2944 |
#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
2945 |
#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
2945 |
#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
2946 |
#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
2946 |
#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
2947 |
#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
2947 |
#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
2948 |
#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
2948 |
#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
2949 |
#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
2949 |
#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
2950 |
#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
2950 |
#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
2951 |
#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
2951 |
#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
2952 |
#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
2952 |
#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
2953 |
#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
2953 |
#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
2954 |
#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
2954 |
#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
2955 |
#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
2955 |
#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
2956 |
#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
2956 |
#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
2957 |
#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
2957 |
#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
2958 |
#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
2958 |
#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
2959 |
#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
2959 |
#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
2960 |
#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
2960 |
#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
2961 |
#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
2961 |
#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
2962 |
#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
2962 |
#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
2963 |
|
2963 |
|
2964 |
/****************** Bit definition for NVIC_ISPR register *******************/ |
2964 |
/****************** Bit definition for NVIC_ISPR register *******************/ |
2965 |
#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ |
2965 |
#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ |
2966 |
#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
2966 |
#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
2967 |
#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
2967 |
#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
2968 |
#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
2968 |
#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
2969 |
#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
2969 |
#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
2970 |
#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
2970 |
#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
2971 |
#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
2971 |
#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
2972 |
#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
2972 |
#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
2973 |
#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
2973 |
#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
2974 |
#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
2974 |
#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
2975 |
#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
2975 |
#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
2976 |
#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
2976 |
#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
2977 |
#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
2977 |
#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
2978 |
#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
2978 |
#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
2979 |
#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
2979 |
#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
2980 |
#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
2980 |
#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
2981 |
#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
2981 |
#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
2982 |
#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
2982 |
#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
2983 |
#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
2983 |
#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
2984 |
#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
2984 |
#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
2985 |
#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
2985 |
#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
2986 |
#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
2986 |
#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
2987 |
#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
2987 |
#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
2988 |
#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
2988 |
#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
2989 |
#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
2989 |
#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
2990 |
#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
2990 |
#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
2991 |
#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
2991 |
#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
2992 |
#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
2992 |
#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
2993 |
#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
2993 |
#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
2994 |
#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
2994 |
#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
2995 |
#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
2995 |
#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
2996 |
#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
2996 |
#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
2997 |
#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
2997 |
#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
2998 |
|
2998 |
|
2999 |
/****************** Bit definition for NVIC_ICPR register *******************/ |
2999 |
/****************** Bit definition for NVIC_ICPR register *******************/ |
3000 |
#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ |
3000 |
#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ |
3001 |
#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
3001 |
#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
3002 |
#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
3002 |
#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
3003 |
#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
3003 |
#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
3004 |
#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
3004 |
#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
3005 |
#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
3005 |
#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
3006 |
#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
3006 |
#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
3007 |
#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
3007 |
#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
3008 |
#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
3008 |
#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
3009 |
#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
3009 |
#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
3010 |
#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
3010 |
#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
3011 |
#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
3011 |
#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
3012 |
#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
3012 |
#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
3013 |
#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
3013 |
#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
3014 |
#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
3014 |
#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
3015 |
#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
3015 |
#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
3016 |
#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
3016 |
#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
3017 |
#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
3017 |
#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
3018 |
#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
3018 |
#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
3019 |
#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
3019 |
#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
3020 |
#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
3020 |
#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
3021 |
#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
3021 |
#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
3022 |
#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
3022 |
#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
3023 |
#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
3023 |
#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
3024 |
#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
3024 |
#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
3025 |
#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
3025 |
#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
3026 |
#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
3026 |
#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
3027 |
#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
3027 |
#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
3028 |
#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
3028 |
#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
3029 |
#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
3029 |
#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
3030 |
#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
3030 |
#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
3031 |
#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
3031 |
#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
3032 |
#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
3032 |
#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
3033 |
|
3033 |
|
3034 |
/****************** Bit definition for NVIC_IABR register *******************/ |
3034 |
/****************** Bit definition for NVIC_IABR register *******************/ |
3035 |
#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ |
3035 |
#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ |
3036 |
#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
3036 |
#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
3037 |
#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
3037 |
#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
3038 |
#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
3038 |
#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
3039 |
#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
3039 |
#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
3040 |
#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
3040 |
#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
3041 |
#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
3041 |
#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
3042 |
#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
3042 |
#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
3043 |
#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
3043 |
#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
3044 |
#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
3044 |
#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
3045 |
#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
3045 |
#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
3046 |
#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
3046 |
#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
3047 |
#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
3047 |
#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
3048 |
#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
3048 |
#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
3049 |
#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
3049 |
#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
3050 |
#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
3050 |
#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
3051 |
#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
3051 |
#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
3052 |
#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
3052 |
#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
3053 |
#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
3053 |
#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
3054 |
#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
3054 |
#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
3055 |
#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
3055 |
#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
3056 |
#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
3056 |
#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
3057 |
#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
3057 |
#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
3058 |
#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
3058 |
#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
3059 |
#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
3059 |
#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
3060 |
#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
3060 |
#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
3061 |
#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
3061 |
#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
3062 |
#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
3062 |
#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
3063 |
#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
3063 |
#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
3064 |
#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
3064 |
#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
3065 |
#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
3065 |
#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
3066 |
#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
3066 |
#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
3067 |
#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
3067 |
#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
3068 |
|
3068 |
|
3069 |
/****************** Bit definition for NVIC_PRI0 register *******************/ |
3069 |
/****************** Bit definition for NVIC_PRI0 register *******************/ |
3070 |
#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ |
3070 |
#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ |
3071 |
#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ |
3071 |
#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ |
3072 |
#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ |
3072 |
#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ |
3073 |
#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ |
3073 |
#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ |
3074 |
|
3074 |
|
3075 |
/****************** Bit definition for NVIC_PRI1 register *******************/ |
3075 |
/****************** Bit definition for NVIC_PRI1 register *******************/ |
3076 |
#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ |
3076 |
#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ |
3077 |
#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ |
3077 |
#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ |
3078 |
#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ |
3078 |
#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ |
3079 |
#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ |
3079 |
#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ |
3080 |
|
3080 |
|
3081 |
/****************** Bit definition for NVIC_PRI2 register *******************/ |
3081 |
/****************** Bit definition for NVIC_PRI2 register *******************/ |
3082 |
#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ |
3082 |
#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ |
3083 |
#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ |
3083 |
#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ |
3084 |
#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ |
3084 |
#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ |
3085 |
#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ |
3085 |
#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ |
3086 |
|
3086 |
|
3087 |
/****************** Bit definition for NVIC_PRI3 register *******************/ |
3087 |
/****************** Bit definition for NVIC_PRI3 register *******************/ |
3088 |
#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ |
3088 |
#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ |
3089 |
#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ |
3089 |
#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ |
3090 |
#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ |
3090 |
#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ |
3091 |
#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ |
3091 |
#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ |
3092 |
|
3092 |
|
3093 |
/****************** Bit definition for NVIC_PRI4 register *******************/ |
3093 |
/****************** Bit definition for NVIC_PRI4 register *******************/ |
3094 |
#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ |
3094 |
#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ |
3095 |
#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ |
3095 |
#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ |
3096 |
#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ |
3096 |
#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ |
3097 |
#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ |
3097 |
#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ |
3098 |
|
3098 |
|
3099 |
/****************** Bit definition for NVIC_PRI5 register *******************/ |
3099 |
/****************** Bit definition for NVIC_PRI5 register *******************/ |
3100 |
#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ |
3100 |
#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ |
3101 |
#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ |
3101 |
#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ |
3102 |
#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ |
3102 |
#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ |
3103 |
#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ |
3103 |
#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ |
3104 |
|
3104 |
|
3105 |
/****************** Bit definition for NVIC_PRI6 register *******************/ |
3105 |
/****************** Bit definition for NVIC_PRI6 register *******************/ |
3106 |
#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ |
3106 |
#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ |
3107 |
#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ |
3107 |
#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ |
3108 |
#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ |
3108 |
#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ |
3109 |
#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ |
3109 |
#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ |
3110 |
|
3110 |
|
3111 |
/****************** Bit definition for NVIC_PRI7 register *******************/ |
3111 |
/****************** Bit definition for NVIC_PRI7 register *******************/ |
3112 |
#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ |
3112 |
#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ |
3113 |
#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ |
3113 |
#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ |
3114 |
#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ |
3114 |
#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ |
3115 |
#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ |
3115 |
#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ |
3116 |
|
3116 |
|
3117 |
/****************** Bit definition for SCB_CPUID register *******************/ |
3117 |
/****************** Bit definition for SCB_CPUID register *******************/ |
3118 |
#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ |
3118 |
#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ |
3119 |
#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ |
3119 |
#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ |
3120 |
#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ |
3120 |
#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ |
3121 |
#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ |
3121 |
#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ |
3122 |
#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ |
3122 |
#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ |
3123 |
|
3123 |
|
3124 |
/******************* Bit definition for SCB_ICSR register *******************/ |
3124 |
/******************* Bit definition for SCB_ICSR register *******************/ |
3125 |
#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ |
3125 |
#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ |
3126 |
#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ |
3126 |
#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ |
3127 |
#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ |
3127 |
#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ |
3128 |
#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ |
3128 |
#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ |
3129 |
#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ |
3129 |
#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ |
3130 |
#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ |
3130 |
#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ |
3131 |
#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ |
3131 |
#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ |
3132 |
#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ |
3132 |
#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ |
3133 |
#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ |
3133 |
#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ |
3134 |
#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ |
3134 |
#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ |
3135 |
|
3135 |
|
3136 |
/******************* Bit definition for SCB_VTOR register *******************/ |
3136 |
/******************* Bit definition for SCB_VTOR register *******************/ |
3137 |
#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ |
3137 |
#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ |
3138 |
#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ |
3138 |
#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ |
3139 |
|
3139 |
|
3140 |
/*!<***************** Bit definition for SCB_AIRCR register *******************/ |
3140 |
/*!<***************** Bit definition for SCB_AIRCR register *******************/ |
3141 |
#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ |
3141 |
#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ |
3142 |
#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ |
3142 |
#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ |
3143 |
#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ |
3143 |
#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ |
3144 |
|
3144 |
|
3145 |
#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ |
3145 |
#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ |
3146 |
#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
3146 |
#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
3147 |
#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
3147 |
#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
3148 |
#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
3148 |
#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
3149 |
|
3149 |
|
3150 |
/* prority group configuration */ |
3150 |
/* prority group configuration */ |
3151 |
#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ |
3151 |
#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ |
3152 |
#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ |
3152 |
#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ |
3153 |
#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ |
3153 |
#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ |
3154 |
#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ |
3154 |
#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ |
3155 |
#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ |
3155 |
#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ |
3156 |
#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ |
3156 |
#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ |
3157 |
#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ |
3157 |
#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ |
3158 |
#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ |
3158 |
#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ |
3159 |
|
3159 |
|
3160 |
#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ |
3160 |
#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ |
3161 |
#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ |
3161 |
#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ |
3162 |
|
3162 |
|
3163 |
/******************* Bit definition for SCB_SCR register ********************/ |
3163 |
/******************* Bit definition for SCB_SCR register ********************/ |
3164 |
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ |
3164 |
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ |
3165 |
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ |
3165 |
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ |
3166 |
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ |
3166 |
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ |
3167 |
|
3167 |
|
3168 |
/******************** Bit definition for SCB_CCR register *******************/ |
3168 |
/******************** Bit definition for SCB_CCR register *******************/ |
3169 |
#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ |
3169 |
#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ |
3170 |
#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ |
3170 |
#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ |
3171 |
#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ |
3171 |
#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ |
3172 |
#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ |
3172 |
#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ |
3173 |
#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ |
3173 |
#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ |
3174 |
#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ |
3174 |
#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ |
3175 |
|
3175 |
|
3176 |
/******************* Bit definition for SCB_SHPR register ********************/ |
3176 |
/******************* Bit definition for SCB_SHPR register ********************/ |
3177 |
#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ |
3177 |
#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ |
3178 |
#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ |
3178 |
#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ |
3179 |
#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ |
3179 |
#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ |
3180 |
#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ |
3180 |
#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ |
3181 |
|
3181 |
|
3182 |
/****************** Bit definition for SCB_SHCSR register *******************/ |
3182 |
/****************** Bit definition for SCB_SHCSR register *******************/ |
3183 |
#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ |
3183 |
#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ |
3184 |
#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ |
3184 |
#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ |
3185 |
#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ |
3185 |
#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ |
3186 |
#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ |
3186 |
#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ |
3187 |
#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ |
3187 |
#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ |
3188 |
#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ |
3188 |
#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ |
3189 |
#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ |
3189 |
#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ |
3190 |
#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ |
3190 |
#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ |
3191 |
#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ |
3191 |
#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ |
3192 |
#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ |
3192 |
#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ |
3193 |
#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ |
3193 |
#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ |
3194 |
#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ |
3194 |
#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ |
3195 |
#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ |
3195 |
#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ |
3196 |
#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ |
3196 |
#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ |
3197 |
|
3197 |
|
3198 |
/******************* Bit definition for SCB_CFSR register *******************/ |
3198 |
/******************* Bit definition for SCB_CFSR register *******************/ |
3199 |
/*!< MFSR */ |
3199 |
/*!< MFSR */ |
3200 |
#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ |
3200 |
#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ |
3201 |
#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ |
3201 |
#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ |
3202 |
#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ |
3202 |
#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ |
3203 |
#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ |
3203 |
#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ |
3204 |
#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ |
3204 |
#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ |
3205 |
/*!< BFSR */ |
3205 |
/*!< BFSR */ |
3206 |
#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ |
3206 |
#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ |
3207 |
#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ |
3207 |
#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ |
3208 |
#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ |
3208 |
#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ |
3209 |
#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ |
3209 |
#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ |
3210 |
#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ |
3210 |
#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ |
3211 |
#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ |
3211 |
#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ |
3212 |
/*!< UFSR */ |
3212 |
/*!< UFSR */ |
3213 |
#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ |
3213 |
#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ |
3214 |
#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ |
3214 |
#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ |
3215 |
#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ |
3215 |
#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ |
3216 |
#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ |
3216 |
#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ |
3217 |
#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ |
3217 |
#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ |
3218 |
#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ |
3218 |
#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ |
3219 |
|
3219 |
|
3220 |
/******************* Bit definition for SCB_HFSR register *******************/ |
3220 |
/******************* Bit definition for SCB_HFSR register *******************/ |
3221 |
#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ |
3221 |
#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ |
3222 |
#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ |
3222 |
#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ |
3223 |
#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ |
3223 |
#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ |
3224 |
|
3224 |
|
3225 |
/******************* Bit definition for SCB_DFSR register *******************/ |
3225 |
/******************* Bit definition for SCB_DFSR register *******************/ |
3226 |
#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ |
3226 |
#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ |
3227 |
#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ |
3227 |
#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ |
3228 |
#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ |
3228 |
#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ |
3229 |
#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ |
3229 |
#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ |
3230 |
#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ |
3230 |
#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ |
3231 |
|
3231 |
|
3232 |
/******************* Bit definition for SCB_MMFAR register ******************/ |
3232 |
/******************* Bit definition for SCB_MMFAR register ******************/ |
3233 |
#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ |
3233 |
#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ |
3234 |
|
3234 |
|
3235 |
/******************* Bit definition for SCB_BFAR register *******************/ |
3235 |
/******************* Bit definition for SCB_BFAR register *******************/ |
3236 |
#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ |
3236 |
#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ |
3237 |
|
3237 |
|
3238 |
/******************* Bit definition for SCB_afsr register *******************/ |
3238 |
/******************* Bit definition for SCB_afsr register *******************/ |
3239 |
#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ |
3239 |
#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ |
3240 |
|
3240 |
|
3241 |
/******************************************************************************/ |
3241 |
/******************************************************************************/ |
3242 |
/* */ |
3242 |
/* */ |
3243 |
/* External Interrupt/Event Controller */ |
3243 |
/* External Interrupt/Event Controller */ |
3244 |
/* */ |
3244 |
/* */ |
3245 |
/******************************************************************************/ |
3245 |
/******************************************************************************/ |
3246 |
|
3246 |
|
3247 |
/******************* Bit definition for EXTI_IMR register *******************/ |
3247 |
/******************* Bit definition for EXTI_IMR register *******************/ |
3248 |
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
3248 |
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
3249 |
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
3249 |
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
3250 |
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
3250 |
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
3251 |
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
3251 |
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
3252 |
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
3252 |
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
3253 |
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
3253 |
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
3254 |
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
3254 |
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
3255 |
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
3255 |
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
3256 |
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
3256 |
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
3257 |
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
3257 |
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
3258 |
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
3258 |
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
3259 |
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
3259 |
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
3260 |
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
3260 |
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
3261 |
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
3261 |
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
3262 |
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
3262 |
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
3263 |
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
3263 |
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
3264 |
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
3264 |
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
3265 |
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
3265 |
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
3266 |
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
3266 |
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
3267 |
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
3267 |
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
3268 |
|
3268 |
|
3269 |
/******************* Bit definition for EXTI_EMR register *******************/ |
3269 |
/******************* Bit definition for EXTI_EMR register *******************/ |
3270 |
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
3270 |
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
3271 |
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
3271 |
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
3272 |
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
3272 |
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
3273 |
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
3273 |
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
3274 |
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
3274 |
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
3275 |
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
3275 |
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
3276 |
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
3276 |
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
3277 |
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
3277 |
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
3278 |
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
3278 |
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
3279 |
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
3279 |
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
3280 |
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
3280 |
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
3281 |
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
3281 |
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
3282 |
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
3282 |
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
3283 |
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
3283 |
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
3284 |
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
3284 |
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
3285 |
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
3285 |
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
3286 |
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
3286 |
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
3287 |
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
3287 |
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
3288 |
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
3288 |
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
3289 |
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
3289 |
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
3290 |
|
3290 |
|
3291 |
/****************** Bit definition for EXTI_RTSR register *******************/ |
3291 |
/****************** Bit definition for EXTI_RTSR register *******************/ |
3292 |
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
3292 |
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
3293 |
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
3293 |
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
3294 |
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
3294 |
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
3295 |
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
3295 |
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
3296 |
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
3296 |
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
3297 |
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
3297 |
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
3298 |
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
3298 |
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
3299 |
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
3299 |
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
3300 |
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
3300 |
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
3301 |
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
3301 |
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
3302 |
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
3302 |
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
3303 |
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
3303 |
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
3304 |
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
3304 |
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
3305 |
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
3305 |
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
3306 |
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
3306 |
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
3307 |
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
3307 |
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
3308 |
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
3308 |
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
3309 |
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ |
3309 |
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ |
3310 |
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
3310 |
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
3311 |
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
3311 |
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
3312 |
|
3312 |
|
3313 |
/****************** Bit definition for EXTI_FTSR register *******************/ |
3313 |
/****************** Bit definition for EXTI_FTSR register *******************/ |
3314 |
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
3314 |
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
3315 |
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
3315 |
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
3316 |
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
3316 |
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
3317 |
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
3317 |
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
3318 |
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
3318 |
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
3319 |
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
3319 |
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
3320 |
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
3320 |
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
3321 |
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
3321 |
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
3322 |
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
3322 |
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
3323 |
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
3323 |
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
3324 |
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
3324 |
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
3325 |
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
3325 |
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
3326 |
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
3326 |
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
3327 |
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
3327 |
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
3328 |
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
3328 |
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
3329 |
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
3329 |
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
3330 |
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
3330 |
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
3331 |
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ |
3331 |
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ |
3332 |
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
3332 |
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
3333 |
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
3333 |
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
3334 |
|
3334 |
|
3335 |
/****************** Bit definition for EXTI_SWIER register ******************/ |
3335 |
/****************** Bit definition for EXTI_SWIER register ******************/ |
3336 |
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
3336 |
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
3337 |
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
3337 |
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
3338 |
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
3338 |
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
3339 |
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
3339 |
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
3340 |
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
3340 |
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
3341 |
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
3341 |
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
3342 |
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
3342 |
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
3343 |
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
3343 |
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
3344 |
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
3344 |
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
3345 |
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
3345 |
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
3346 |
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
3346 |
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
3347 |
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
3347 |
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
3348 |
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
3348 |
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
3349 |
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
3349 |
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
3350 |
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
3350 |
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
3351 |
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
3351 |
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
3352 |
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
3352 |
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
3353 |
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ |
3353 |
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ |
3354 |
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
3354 |
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
3355 |
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
3355 |
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
3356 |
|
3356 |
|
3357 |
/******************* Bit definition for EXTI_PR register ********************/ |
3357 |
/******************* Bit definition for EXTI_PR register ********************/ |
3358 |
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
3358 |
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
3359 |
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
3359 |
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
3360 |
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
3360 |
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
3361 |
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
3361 |
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
3362 |
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
3362 |
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
3363 |
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
3363 |
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
3364 |
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
3364 |
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
3365 |
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
3365 |
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
3366 |
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
3366 |
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
3367 |
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
3367 |
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
3368 |
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
3368 |
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
3369 |
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
3369 |
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
3370 |
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
3370 |
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
3371 |
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
3371 |
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
3372 |
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
3372 |
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
3373 |
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
3373 |
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
3374 |
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
3374 |
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
3375 |
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ |
3375 |
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ |
3376 |
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
3376 |
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
3377 |
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
3377 |
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
3378 |
|
3378 |
|
3379 |
/******************************************************************************/ |
3379 |
/******************************************************************************/ |
3380 |
/* */ |
3380 |
/* */ |
3381 |
/* DMA Controller */ |
3381 |
/* DMA Controller */ |
3382 |
/* */ |
3382 |
/* */ |
3383 |
/******************************************************************************/ |
3383 |
/******************************************************************************/ |
3384 |
|
3384 |
|
3385 |
/******************* Bit definition for DMA_ISR register ********************/ |
3385 |
/******************* Bit definition for DMA_ISR register ********************/ |
3386 |
#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ |
3386 |
#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ |
3387 |
#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ |
3387 |
#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ |
3388 |
#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ |
3388 |
#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ |
3389 |
#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ |
3389 |
#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ |
3390 |
#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ |
3390 |
#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ |
3391 |
#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ |
3391 |
#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ |
3392 |
#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ |
3392 |
#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ |
3393 |
#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ |
3393 |
#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ |
3394 |
#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ |
3394 |
#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ |
3395 |
#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ |
3395 |
#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ |
3396 |
#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ |
3396 |
#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ |
3397 |
#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ |
3397 |
#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ |
3398 |
#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ |
3398 |
#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ |
3399 |
#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ |
3399 |
#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ |
3400 |
#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ |
3400 |
#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ |
3401 |
#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ |
3401 |
#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ |
3402 |
#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ |
3402 |
#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ |
3403 |
#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ |
3403 |
#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ |
3404 |
#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ |
3404 |
#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ |
3405 |
#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ |
3405 |
#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ |
3406 |
#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ |
3406 |
#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ |
3407 |
#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ |
3407 |
#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ |
3408 |
#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ |
3408 |
#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ |
3409 |
#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ |
3409 |
#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ |
3410 |
#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ |
3410 |
#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ |
3411 |
#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ |
3411 |
#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ |
3412 |
#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ |
3412 |
#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ |
3413 |
#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ |
3413 |
#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ |
3414 |
|
3414 |
|
3415 |
/******************* Bit definition for DMA_IFCR register *******************/ |
3415 |
/******************* Bit definition for DMA_IFCR register *******************/ |
3416 |
#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ |
3416 |
#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ |
3417 |
#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ |
3417 |
#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ |
3418 |
#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ |
3418 |
#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ |
3419 |
#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ |
3419 |
#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ |
3420 |
#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ |
3420 |
#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ |
3421 |
#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ |
3421 |
#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ |
3422 |
#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ |
3422 |
#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ |
3423 |
#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ |
3423 |
#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ |
3424 |
#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ |
3424 |
#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ |
3425 |
#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ |
3425 |
#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ |
3426 |
#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ |
3426 |
#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ |
3427 |
#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ |
3427 |
#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ |
3428 |
#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ |
3428 |
#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ |
3429 |
#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ |
3429 |
#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ |
3430 |
#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ |
3430 |
#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ |
3431 |
#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ |
3431 |
#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ |
3432 |
#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ |
3432 |
#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ |
3433 |
#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ |
3433 |
#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ |
3434 |
#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ |
3434 |
#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ |
3435 |
#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ |
3435 |
#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ |
3436 |
#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ |
3436 |
#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ |
3437 |
#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ |
3437 |
#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ |
3438 |
#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ |
3438 |
#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ |
3439 |
#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ |
3439 |
#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ |
3440 |
#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ |
3440 |
#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ |
3441 |
#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ |
3441 |
#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ |
3442 |
#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ |
3442 |
#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ |
3443 |
#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ |
3443 |
#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ |
3444 |
|
3444 |
|
3445 |
/******************* Bit definition for DMA_CCR1 register *******************/ |
3445 |
/******************* Bit definition for DMA_CCR1 register *******************/ |
3446 |
#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ |
3446 |
#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ |
3447 |
#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
3447 |
#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
3448 |
#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
3448 |
#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
3449 |
#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
3449 |
#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
3450 |
#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
3450 |
#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
3451 |
#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
3451 |
#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
3452 |
#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
3452 |
#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
3453 |
#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
3453 |
#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
3454 |
|
3454 |
|
3455 |
#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
3455 |
#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
3456 |
#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
3456 |
#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
3457 |
#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
3457 |
#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
3458 |
|
3458 |
|
3459 |
#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
3459 |
#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
3460 |
#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
3460 |
#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
3461 |
#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
3461 |
#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
3462 |
|
3462 |
|
3463 |
#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ |
3463 |
#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ |
3464 |
#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
3464 |
#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
3465 |
#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
3465 |
#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
3466 |
|
3466 |
|
3467 |
#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
3467 |
#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
3468 |
|
3468 |
|
3469 |
/******************* Bit definition for DMA_CCR2 register *******************/ |
3469 |
/******************* Bit definition for DMA_CCR2 register *******************/ |
3470 |
#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ |
3470 |
#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ |
3471 |
#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ |
3471 |
#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ |
3472 |
#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
3472 |
#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
3473 |
#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
3473 |
#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
3474 |
#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
3474 |
#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
3475 |
#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
3475 |
#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
3476 |
#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
3476 |
#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
3477 |
#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
3477 |
#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
3478 |
|
3478 |
|
3479 |
#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
3479 |
#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
3480 |
#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
3480 |
#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
3481 |
#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
3481 |
#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
3482 |
|
3482 |
|
3483 |
#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
3483 |
#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
3484 |
#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
3484 |
#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
3485 |
#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
3485 |
#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
3486 |
|
3486 |
|
3487 |
#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
3487 |
#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
3488 |
#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
3488 |
#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
3489 |
#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
3489 |
#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
3490 |
|
3490 |
|
3491 |
#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
3491 |
#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
3492 |
|
3492 |
|
3493 |
/******************* Bit definition for DMA_CCR3 register *******************/ |
3493 |
/******************* Bit definition for DMA_CCR3 register *******************/ |
3494 |
#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ |
3494 |
#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ |
3495 |
#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
3495 |
#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ |
3496 |
#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
3496 |
#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ |
3497 |
#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
3497 |
#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ |
3498 |
#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
3498 |
#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ |
3499 |
#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
3499 |
#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ |
3500 |
#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
3500 |
#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ |
3501 |
#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
3501 |
#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ |
3502 |
|
3502 |
|
3503 |
#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
3503 |
#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
3504 |
#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
3504 |
#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ |
3505 |
#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
3505 |
#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ |
3506 |
|
3506 |
|
3507 |
#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
3507 |
#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ |
3508 |
#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
3508 |
#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ |
3509 |
#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
3509 |
#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ |
3510 |
|
3510 |
|
3511 |
#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
3511 |
#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ |
3512 |
#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
3512 |
#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ |
3513 |
#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
3513 |
#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ |
3514 |
|
3514 |
|
3515 |
#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
3515 |
#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ |
3516 |
|
3516 |
|
3517 |
/*!<****************** Bit definition for DMA_CCR4 register *******************/ |
3517 |
/*!<****************** Bit definition for DMA_CCR4 register *******************/ |
3518 |
#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */ |
3518 |
#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */ |
3519 |
#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
3519 |
#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
3520 |
#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
3520 |
#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
3521 |
#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
3521 |
#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
3522 |
#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
3522 |
#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
3523 |
#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
3523 |
#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
3524 |
#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
3524 |
#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
3525 |
#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
3525 |
#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
3526 |
|
3526 |
|
3527 |
#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
3527 |
#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
3528 |
#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
3528 |
#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
3529 |
#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
3529 |
#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
3530 |
|
3530 |
|
3531 |
#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
3531 |
#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
3532 |
#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
3532 |
#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
3533 |
#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
3533 |
#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
3534 |
|
3534 |
|
3535 |
#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
3535 |
#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
3536 |
#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
3536 |
#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
3537 |
#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
3537 |
#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
3538 |
|
3538 |
|
3539 |
#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */ |
3539 |
#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */ |
3540 |
|
3540 |
|
3541 |
/****************** Bit definition for DMA_CCR5 register *******************/ |
3541 |
/****************** Bit definition for DMA_CCR5 register *******************/ |
3542 |
#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */ |
3542 |
#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */ |
3543 |
#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
3543 |
#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
3544 |
#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
3544 |
#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
3545 |
#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
3545 |
#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
3546 |
#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
3546 |
#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
3547 |
#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
3547 |
#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
3548 |
#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
3548 |
#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
3549 |
#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
3549 |
#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
3550 |
|
3550 |
|
3551 |
#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
3551 |
#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
3552 |
#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
3552 |
#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
3553 |
#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
3553 |
#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
3554 |
|
3554 |
|
3555 |
#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
3555 |
#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
3556 |
#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
3556 |
#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
3557 |
#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
3557 |
#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
3558 |
|
3558 |
|
3559 |
#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
3559 |
#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
3560 |
#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
3560 |
#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
3561 |
#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
3561 |
#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
3562 |
|
3562 |
|
3563 |
#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */ |
3563 |
#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */ |
3564 |
|
3564 |
|
3565 |
/******************* Bit definition for DMA_CCR6 register *******************/ |
3565 |
/******************* Bit definition for DMA_CCR6 register *******************/ |
3566 |
#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */ |
3566 |
#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */ |
3567 |
#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
3567 |
#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
3568 |
#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
3568 |
#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
3569 |
#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
3569 |
#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
3570 |
#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
3570 |
#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
3571 |
#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
3571 |
#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
3572 |
#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
3572 |
#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
3573 |
#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
3573 |
#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
3574 |
|
3574 |
|
3575 |
#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
3575 |
#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
3576 |
#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
3576 |
#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
3577 |
#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
3577 |
#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
3578 |
|
3578 |
|
3579 |
#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
3579 |
#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
3580 |
#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
3580 |
#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
3581 |
#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
3581 |
#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
3582 |
|
3582 |
|
3583 |
#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
3583 |
#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
3584 |
#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
3584 |
#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
3585 |
#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
3585 |
#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
3586 |
|
3586 |
|
3587 |
#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */ |
3587 |
#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */ |
3588 |
|
3588 |
|
3589 |
/******************* Bit definition for DMA_CCR7 register *******************/ |
3589 |
/******************* Bit definition for DMA_CCR7 register *******************/ |
3590 |
#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */ |
3590 |
#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */ |
3591 |
#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
3591 |
#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */ |
3592 |
#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
3592 |
#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */ |
3593 |
#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
3593 |
#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */ |
3594 |
#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
3594 |
#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */ |
3595 |
#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
3595 |
#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */ |
3596 |
#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
3596 |
#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */ |
3597 |
#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
3597 |
#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */ |
3598 |
|
3598 |
|
3599 |
#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
3599 |
#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */ |
3600 |
#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
3600 |
#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
3601 |
#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
3601 |
#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
3602 |
|
3602 |
|
3603 |
#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
3603 |
#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */ |
3604 |
#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
3604 |
#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
3605 |
#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
3605 |
#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
3606 |
|
3606 |
|
3607 |
#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
3607 |
#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */ |
3608 |
#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
3608 |
#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
3609 |
#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
3609 |
#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
3610 |
|
3610 |
|
3611 |
#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */ |
3611 |
#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */ |
3612 |
|
3612 |
|
3613 |
/****************** Bit definition for DMA_CNDTR1 register ******************/ |
3613 |
/****************** Bit definition for DMA_CNDTR1 register ******************/ |
3614 |
#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3614 |
#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3615 |
|
3615 |
|
3616 |
/****************** Bit definition for DMA_CNDTR2 register ******************/ |
3616 |
/****************** Bit definition for DMA_CNDTR2 register ******************/ |
3617 |
#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3617 |
#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3618 |
|
3618 |
|
3619 |
/****************** Bit definition for DMA_CNDTR3 register ******************/ |
3619 |
/****************** Bit definition for DMA_CNDTR3 register ******************/ |
3620 |
#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3620 |
#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3621 |
|
3621 |
|
3622 |
/****************** Bit definition for DMA_CNDTR4 register ******************/ |
3622 |
/****************** Bit definition for DMA_CNDTR4 register ******************/ |
3623 |
#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3623 |
#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3624 |
|
3624 |
|
3625 |
/****************** Bit definition for DMA_CNDTR5 register ******************/ |
3625 |
/****************** Bit definition for DMA_CNDTR5 register ******************/ |
3626 |
#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3626 |
#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3627 |
|
3627 |
|
3628 |
/****************** Bit definition for DMA_CNDTR6 register ******************/ |
3628 |
/****************** Bit definition for DMA_CNDTR6 register ******************/ |
3629 |
#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3629 |
#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3630 |
|
3630 |
|
3631 |
/****************** Bit definition for DMA_CNDTR7 register ******************/ |
3631 |
/****************** Bit definition for DMA_CNDTR7 register ******************/ |
3632 |
#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3632 |
#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */ |
3633 |
|
3633 |
|
3634 |
/****************** Bit definition for DMA_CPAR1 register *******************/ |
3634 |
/****************** Bit definition for DMA_CPAR1 register *******************/ |
3635 |
#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3635 |
#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3636 |
|
3636 |
|
3637 |
/****************** Bit definition for DMA_CPAR2 register *******************/ |
3637 |
/****************** Bit definition for DMA_CPAR2 register *******************/ |
3638 |
#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3638 |
#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3639 |
|
3639 |
|
3640 |
/****************** Bit definition for DMA_CPAR3 register *******************/ |
3640 |
/****************** Bit definition for DMA_CPAR3 register *******************/ |
3641 |
#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3641 |
#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3642 |
|
3642 |
|
3643 |
|
3643 |
|
3644 |
/****************** Bit definition for DMA_CPAR4 register *******************/ |
3644 |
/****************** Bit definition for DMA_CPAR4 register *******************/ |
3645 |
#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3645 |
#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3646 |
|
3646 |
|
3647 |
/****************** Bit definition for DMA_CPAR5 register *******************/ |
3647 |
/****************** Bit definition for DMA_CPAR5 register *******************/ |
3648 |
#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3648 |
#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3649 |
|
3649 |
|
3650 |
/****************** Bit definition for DMA_CPAR6 register *******************/ |
3650 |
/****************** Bit definition for DMA_CPAR6 register *******************/ |
3651 |
#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3651 |
#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3652 |
|
3652 |
|
3653 |
|
3653 |
|
3654 |
/****************** Bit definition for DMA_CPAR7 register *******************/ |
3654 |
/****************** Bit definition for DMA_CPAR7 register *******************/ |
3655 |
#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3655 |
#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */ |
3656 |
|
3656 |
|
3657 |
/****************** Bit definition for DMA_CMAR1 register *******************/ |
3657 |
/****************** Bit definition for DMA_CMAR1 register *******************/ |
3658 |
#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3658 |
#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3659 |
|
3659 |
|
3660 |
/****************** Bit definition for DMA_CMAR2 register *******************/ |
3660 |
/****************** Bit definition for DMA_CMAR2 register *******************/ |
3661 |
#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3661 |
#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3662 |
|
3662 |
|
3663 |
/****************** Bit definition for DMA_CMAR3 register *******************/ |
3663 |
/****************** Bit definition for DMA_CMAR3 register *******************/ |
3664 |
#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3664 |
#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3665 |
|
3665 |
|
3666 |
|
3666 |
|
3667 |
/****************** Bit definition for DMA_CMAR4 register *******************/ |
3667 |
/****************** Bit definition for DMA_CMAR4 register *******************/ |
3668 |
#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3668 |
#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3669 |
|
3669 |
|
3670 |
/****************** Bit definition for DMA_CMAR5 register *******************/ |
3670 |
/****************** Bit definition for DMA_CMAR5 register *******************/ |
3671 |
#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3671 |
#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3672 |
|
3672 |
|
3673 |
/****************** Bit definition for DMA_CMAR6 register *******************/ |
3673 |
/****************** Bit definition for DMA_CMAR6 register *******************/ |
3674 |
#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3674 |
#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3675 |
|
3675 |
|
3676 |
/****************** Bit definition for DMA_CMAR7 register *******************/ |
3676 |
/****************** Bit definition for DMA_CMAR7 register *******************/ |
3677 |
#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3677 |
#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */ |
3678 |
|
3678 |
|
3679 |
/******************************************************************************/ |
3679 |
/******************************************************************************/ |
3680 |
/* */ |
3680 |
/* */ |
3681 |
/* Analog to Digital Converter */ |
3681 |
/* Analog to Digital Converter */ |
3682 |
/* */ |
3682 |
/* */ |
3683 |
/******************************************************************************/ |
3683 |
/******************************************************************************/ |
3684 |
|
3684 |
|
3685 |
/******************** Bit definition for ADC_SR register ********************/ |
3685 |
/******************** Bit definition for ADC_SR register ********************/ |
3686 |
#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */ |
3686 |
#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */ |
3687 |
#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */ |
3687 |
#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */ |
3688 |
#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */ |
3688 |
#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */ |
3689 |
#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */ |
3689 |
#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */ |
3690 |
#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */ |
3690 |
#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */ |
3691 |
|
3691 |
|
3692 |
/******************* Bit definition for ADC_CR1 register ********************/ |
3692 |
/******************* Bit definition for ADC_CR1 register ********************/ |
3693 |
#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
3693 |
#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
3694 |
#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3694 |
#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3695 |
#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3695 |
#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3696 |
#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3696 |
#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3697 |
#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3697 |
#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3698 |
#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3698 |
#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3699 |
|
3699 |
|
3700 |
#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */ |
3700 |
#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */ |
3701 |
#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */ |
3701 |
#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */ |
3702 |
#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */ |
3702 |
#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */ |
3703 |
#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */ |
3703 |
#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */ |
3704 |
#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */ |
3704 |
#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */ |
3705 |
#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */ |
3705 |
#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */ |
3706 |
#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */ |
3706 |
#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */ |
3707 |
#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */ |
3707 |
#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */ |
3708 |
|
3708 |
|
3709 |
#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
3709 |
#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
3710 |
#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
3710 |
#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
3711 |
#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
3711 |
#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
3712 |
#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
3712 |
#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
3713 |
|
3713 |
|
3714 |
#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */ |
3714 |
#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */ |
3715 |
#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
3715 |
#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
3716 |
#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
3716 |
#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
3717 |
#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
3717 |
#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
3718 |
#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
3718 |
#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
3719 |
|
3719 |
|
3720 |
#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */ |
3720 |
#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */ |
3721 |
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */ |
3721 |
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */ |
3722 |
|
3722 |
|
3723 |
|
3723 |
|
3724 |
/******************* Bit definition for ADC_CR2 register ********************/ |
3724 |
/******************* Bit definition for ADC_CR2 register ********************/ |
3725 |
#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */ |
3725 |
#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */ |
3726 |
#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */ |
3726 |
#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */ |
3727 |
#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */ |
3727 |
#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */ |
3728 |
#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */ |
3728 |
#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */ |
3729 |
#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */ |
3729 |
#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */ |
3730 |
#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */ |
3730 |
#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */ |
3731 |
|
3731 |
|
3732 |
#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */ |
3732 |
#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */ |
3733 |
#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
3733 |
#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
3734 |
#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
3734 |
#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
3735 |
#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
3735 |
#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
3736 |
|
3736 |
|
3737 |
#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */ |
3737 |
#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */ |
3738 |
|
3738 |
|
3739 |
#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */ |
3739 |
#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */ |
3740 |
#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
3740 |
#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
3741 |
#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
3741 |
#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
3742 |
#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
3742 |
#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
3743 |
|
3743 |
|
3744 |
#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */ |
3744 |
#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */ |
3745 |
#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */ |
3745 |
#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */ |
3746 |
#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */ |
3746 |
#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */ |
3747 |
#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */ |
3747 |
#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */ |
3748 |
|
3748 |
|
3749 |
/****************** Bit definition for ADC_SMPR1 register *******************/ |
3749 |
/****************** Bit definition for ADC_SMPR1 register *******************/ |
3750 |
#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ |
3750 |
#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ |
3751 |
#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3751 |
#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3752 |
#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3752 |
#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3753 |
#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3753 |
#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3754 |
|
3754 |
|
3755 |
#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ |
3755 |
#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ |
3756 |
#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
3756 |
#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
3757 |
#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
3757 |
#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
3758 |
#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
3758 |
#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
3759 |
|
3759 |
|
3760 |
#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ |
3760 |
#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ |
3761 |
#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
3761 |
#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
3762 |
#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
3762 |
#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
3763 |
#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
3763 |
#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
3764 |
|
3764 |
|
3765 |
#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ |
3765 |
#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ |
3766 |
#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
3766 |
#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
3767 |
#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
3767 |
#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
3768 |
#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
3768 |
#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
3769 |
|
3769 |
|
3770 |
#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ |
3770 |
#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ |
3771 |
#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
3771 |
#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
3772 |
#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
3772 |
#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
3773 |
#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
3773 |
#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
3774 |
|
3774 |
|
3775 |
#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ |
3775 |
#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ |
3776 |
#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3776 |
#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3777 |
#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3777 |
#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3778 |
#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3778 |
#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3779 |
|
3779 |
|
3780 |
#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ |
3780 |
#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ |
3781 |
#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
3781 |
#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
3782 |
#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
3782 |
#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
3783 |
#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */ |
3783 |
#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */ |
3784 |
|
3784 |
|
3785 |
#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ |
3785 |
#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ |
3786 |
#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
3786 |
#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
3787 |
#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
3787 |
#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
3788 |
#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
3788 |
#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
3789 |
|
3789 |
|
3790 |
/****************** Bit definition for ADC_SMPR2 register *******************/ |
3790 |
/****************** Bit definition for ADC_SMPR2 register *******************/ |
3791 |
#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ |
3791 |
#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ |
3792 |
#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3792 |
#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3793 |
#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3793 |
#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3794 |
#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3794 |
#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3795 |
|
3795 |
|
3796 |
#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ |
3796 |
#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ |
3797 |
#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
3797 |
#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
3798 |
#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
3798 |
#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
3799 |
#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
3799 |
#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
3800 |
|
3800 |
|
3801 |
#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ |
3801 |
#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ |
3802 |
#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
3802 |
#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
3803 |
#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
3803 |
#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
3804 |
#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
3804 |
#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
3805 |
|
3805 |
|
3806 |
#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ |
3806 |
#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ |
3807 |
#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
3807 |
#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
3808 |
#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
3808 |
#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
3809 |
#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
3809 |
#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
3810 |
|
3810 |
|
3811 |
#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ |
3811 |
#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ |
3812 |
#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
3812 |
#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
3813 |
#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
3813 |
#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
3814 |
#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
3814 |
#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
3815 |
|
3815 |
|
3816 |
#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ |
3816 |
#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ |
3817 |
#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3817 |
#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3818 |
#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3818 |
#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3819 |
#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3819 |
#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3820 |
|
3820 |
|
3821 |
#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ |
3821 |
#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ |
3822 |
#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
3822 |
#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
3823 |
#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
3823 |
#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
3824 |
#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */ |
3824 |
#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */ |
3825 |
|
3825 |
|
3826 |
#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ |
3826 |
#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ |
3827 |
#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
3827 |
#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
3828 |
#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
3828 |
#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
3829 |
#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
3829 |
#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
3830 |
|
3830 |
|
3831 |
#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ |
3831 |
#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ |
3832 |
#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
3832 |
#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
3833 |
#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
3833 |
#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
3834 |
#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
3834 |
#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
3835 |
|
3835 |
|
3836 |
#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ |
3836 |
#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ |
3837 |
#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */ |
3837 |
#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */ |
3838 |
#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */ |
3838 |
#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */ |
3839 |
#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */ |
3839 |
#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */ |
3840 |
|
3840 |
|
3841 |
/****************** Bit definition for ADC_JOFR1 register *******************/ |
3841 |
/****************** Bit definition for ADC_JOFR1 register *******************/ |
3842 |
#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */ |
3842 |
#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */ |
3843 |
|
3843 |
|
3844 |
/****************** Bit definition for ADC_JOFR2 register *******************/ |
3844 |
/****************** Bit definition for ADC_JOFR2 register *******************/ |
3845 |
#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */ |
3845 |
#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */ |
3846 |
|
3846 |
|
3847 |
/****************** Bit definition for ADC_JOFR3 register *******************/ |
3847 |
/****************** Bit definition for ADC_JOFR3 register *******************/ |
3848 |
#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */ |
3848 |
#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */ |
3849 |
|
3849 |
|
3850 |
/****************** Bit definition for ADC_JOFR4 register *******************/ |
3850 |
/****************** Bit definition for ADC_JOFR4 register *******************/ |
3851 |
#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */ |
3851 |
#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */ |
3852 |
|
3852 |
|
3853 |
/******************* Bit definition for ADC_HTR register ********************/ |
3853 |
/******************* Bit definition for ADC_HTR register ********************/ |
3854 |
#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */ |
3854 |
#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */ |
3855 |
|
3855 |
|
3856 |
/******************* Bit definition for ADC_LTR register ********************/ |
3856 |
/******************* Bit definition for ADC_LTR register ********************/ |
3857 |
#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */ |
3857 |
#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */ |
3858 |
|
3858 |
|
3859 |
/******************* Bit definition for ADC_SQR1 register *******************/ |
3859 |
/******************* Bit definition for ADC_SQR1 register *******************/ |
3860 |
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ |
3860 |
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ |
3861 |
#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3861 |
#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3862 |
#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3862 |
#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3863 |
#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3863 |
#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3864 |
#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3864 |
#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3865 |
#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3865 |
#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3866 |
|
3866 |
|
3867 |
#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ |
3867 |
#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ |
3868 |
#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
3868 |
#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
3869 |
#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
3869 |
#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
3870 |
#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
3870 |
#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
3871 |
#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
3871 |
#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
3872 |
#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
3872 |
#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
3873 |
|
3873 |
|
3874 |
#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ |
3874 |
#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ |
3875 |
#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
3875 |
#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
3876 |
#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
3876 |
#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
3877 |
#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
3877 |
#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
3878 |
#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
3878 |
#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
3879 |
#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
3879 |
#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
3880 |
|
3880 |
|
3881 |
#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ |
3881 |
#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ |
3882 |
#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3882 |
#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3883 |
#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3883 |
#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3884 |
#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3884 |
#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3885 |
#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
3885 |
#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
3886 |
#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
3886 |
#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
3887 |
|
3887 |
|
3888 |
#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */ |
3888 |
#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */ |
3889 |
#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
3889 |
#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
3890 |
#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
3890 |
#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
3891 |
#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
3891 |
#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
3892 |
#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
3892 |
#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
3893 |
|
3893 |
|
3894 |
/******************* Bit definition for ADC_SQR2 register *******************/ |
3894 |
/******************* Bit definition for ADC_SQR2 register *******************/ |
3895 |
#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ |
3895 |
#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ |
3896 |
#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3896 |
#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3897 |
#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3897 |
#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3898 |
#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3898 |
#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3899 |
#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3899 |
#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3900 |
#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3900 |
#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3901 |
|
3901 |
|
3902 |
#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ |
3902 |
#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ |
3903 |
#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
3903 |
#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
3904 |
#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
3904 |
#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
3905 |
#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
3905 |
#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
3906 |
#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
3906 |
#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
3907 |
#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
3907 |
#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
3908 |
|
3908 |
|
3909 |
#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ |
3909 |
#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ |
3910 |
#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
3910 |
#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
3911 |
#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
3911 |
#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
3912 |
#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
3912 |
#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
3913 |
#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
3913 |
#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
3914 |
#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
3914 |
#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
3915 |
|
3915 |
|
3916 |
#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ |
3916 |
#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ |
3917 |
#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3917 |
#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3918 |
#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3918 |
#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3919 |
#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3919 |
#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3920 |
#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
3920 |
#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
3921 |
#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
3921 |
#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
3922 |
|
3922 |
|
3923 |
#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ |
3923 |
#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ |
3924 |
#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
3924 |
#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
3925 |
#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
3925 |
#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
3926 |
#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
3926 |
#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
3927 |
#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
3927 |
#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
3928 |
#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */ |
3928 |
#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */ |
3929 |
|
3929 |
|
3930 |
#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ |
3930 |
#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ |
3931 |
#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */ |
3931 |
#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */ |
3932 |
#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */ |
3932 |
#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */ |
3933 |
#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */ |
3933 |
#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */ |
3934 |
#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */ |
3934 |
#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */ |
3935 |
#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */ |
3935 |
#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */ |
3936 |
|
3936 |
|
3937 |
/******************* Bit definition for ADC_SQR3 register *******************/ |
3937 |
/******************* Bit definition for ADC_SQR3 register *******************/ |
3938 |
#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ |
3938 |
#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ |
3939 |
#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3939 |
#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3940 |
#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3940 |
#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3941 |
#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3941 |
#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3942 |
#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3942 |
#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3943 |
#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3943 |
#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3944 |
|
3944 |
|
3945 |
#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ |
3945 |
#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ |
3946 |
#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
3946 |
#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
3947 |
#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
3947 |
#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
3948 |
#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
3948 |
#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
3949 |
#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
3949 |
#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
3950 |
#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
3950 |
#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
3951 |
|
3951 |
|
3952 |
#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ |
3952 |
#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ |
3953 |
#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
3953 |
#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
3954 |
#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
3954 |
#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
3955 |
#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
3955 |
#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
3956 |
#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
3956 |
#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
3957 |
#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
3957 |
#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
3958 |
|
3958 |
|
3959 |
#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ |
3959 |
#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ |
3960 |
#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3960 |
#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
3961 |
#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3961 |
#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
3962 |
#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3962 |
#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
3963 |
#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
3963 |
#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
3964 |
#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
3964 |
#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
3965 |
|
3965 |
|
3966 |
#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ |
3966 |
#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ |
3967 |
#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
3967 |
#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
3968 |
#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
3968 |
#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
3969 |
#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
3969 |
#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
3970 |
#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
3970 |
#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
3971 |
#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */ |
3971 |
#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */ |
3972 |
|
3972 |
|
3973 |
#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ |
3973 |
#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ |
3974 |
#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */ |
3974 |
#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */ |
3975 |
#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */ |
3975 |
#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */ |
3976 |
#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */ |
3976 |
#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */ |
3977 |
#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */ |
3977 |
#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */ |
3978 |
#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */ |
3978 |
#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */ |
3979 |
|
3979 |
|
3980 |
/******************* Bit definition for ADC_JSQR register *******************/ |
3980 |
/******************* Bit definition for ADC_JSQR register *******************/ |
3981 |
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ |
3981 |
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ |
3982 |
#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3982 |
#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
3983 |
#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3983 |
#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
3984 |
#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3984 |
#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
3985 |
#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3985 |
#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
3986 |
#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3986 |
#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
3987 |
|
3987 |
|
3988 |
#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
3988 |
#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
3989 |
#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
3989 |
#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
3990 |
#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
3990 |
#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
3991 |
#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
3991 |
#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
3992 |
#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
3992 |
#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ |
3993 |
#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
3993 |
#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ |
3994 |
|
3994 |
|
3995 |
#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
3995 |
#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
3996 |
#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
3996 |
#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
3997 |
#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
3997 |
#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
3998 |
#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
3998 |
#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
3999 |
#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
3999 |
#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
4000 |
#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
4000 |
#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
4001 |
|
4001 |
|
4002 |
#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ |
4002 |
#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ |
4003 |
#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
4003 |
#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
4004 |
#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
4004 |
#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
4005 |
#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
4005 |
#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ |
4006 |
#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
4006 |
#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ |
4007 |
#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
4007 |
#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ |
4008 |
|
4008 |
|
4009 |
#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */ |
4009 |
#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */ |
4010 |
#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4010 |
#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4011 |
#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4011 |
#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4012 |
|
4012 |
|
4013 |
/******************* Bit definition for ADC_JDR1 register *******************/ |
4013 |
/******************* Bit definition for ADC_JDR1 register *******************/ |
4014 |
#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
4014 |
#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
4015 |
|
4015 |
|
4016 |
/******************* Bit definition for ADC_JDR2 register *******************/ |
4016 |
/******************* Bit definition for ADC_JDR2 register *******************/ |
4017 |
#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
4017 |
#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
4018 |
|
4018 |
|
4019 |
/******************* Bit definition for ADC_JDR3 register *******************/ |
4019 |
/******************* Bit definition for ADC_JDR3 register *******************/ |
4020 |
#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
4020 |
#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
4021 |
|
4021 |
|
4022 |
/******************* Bit definition for ADC_JDR4 register *******************/ |
4022 |
/******************* Bit definition for ADC_JDR4 register *******************/ |
4023 |
#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
4023 |
#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ |
4024 |
|
4024 |
|
4025 |
/******************** Bit definition for ADC_DR register ********************/ |
4025 |
/******************** Bit definition for ADC_DR register ********************/ |
4026 |
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */ |
4026 |
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */ |
4027 |
#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */ |
4027 |
#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */ |
4028 |
|
4028 |
|
4029 |
/******************************************************************************/ |
4029 |
/******************************************************************************/ |
4030 |
/* */ |
4030 |
/* */ |
4031 |
/* Digital to Analog Converter */ |
4031 |
/* Digital to Analog Converter */ |
4032 |
/* */ |
4032 |
/* */ |
4033 |
/******************************************************************************/ |
4033 |
/******************************************************************************/ |
4034 |
|
4034 |
|
4035 |
/******************** Bit definition for DAC_CR register ********************/ |
4035 |
/******************** Bit definition for DAC_CR register ********************/ |
4036 |
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */ |
4036 |
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */ |
4037 |
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */ |
4037 |
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */ |
4038 |
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */ |
4038 |
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */ |
4039 |
|
4039 |
|
4040 |
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ |
4040 |
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ |
4041 |
#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
4041 |
#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
4042 |
#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
4042 |
#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
4043 |
#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
4043 |
#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
4044 |
|
4044 |
|
4045 |
#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
4045 |
#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
4046 |
#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
4046 |
#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
4047 |
#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
4047 |
#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
4048 |
|
4048 |
|
4049 |
#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
4049 |
#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
4050 |
#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4050 |
#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4051 |
#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4051 |
#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4052 |
#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4052 |
#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4053 |
#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4053 |
#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4054 |
|
4054 |
|
4055 |
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */ |
4055 |
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */ |
4056 |
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */ |
4056 |
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */ |
4057 |
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */ |
4057 |
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */ |
4058 |
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */ |
4058 |
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */ |
4059 |
|
4059 |
|
4060 |
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ |
4060 |
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ |
4061 |
#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */ |
4061 |
#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */ |
4062 |
#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */ |
4062 |
#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */ |
4063 |
#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */ |
4063 |
#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */ |
4064 |
|
4064 |
|
4065 |
#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
4065 |
#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
4066 |
#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */ |
4066 |
#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */ |
4067 |
#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */ |
4067 |
#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */ |
4068 |
|
4068 |
|
4069 |
#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
4069 |
#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
4070 |
#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4070 |
#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4071 |
#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4071 |
#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4072 |
#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4072 |
#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4073 |
#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4073 |
#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4074 |
|
4074 |
|
4075 |
#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */ |
4075 |
#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */ |
4076 |
|
4076 |
|
4077 |
/***************** Bit definition for DAC_SWTRIGR register ******************/ |
4077 |
/***************** Bit definition for DAC_SWTRIGR register ******************/ |
4078 |
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */ |
4078 |
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */ |
4079 |
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */ |
4079 |
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */ |
4080 |
|
4080 |
|
4081 |
/***************** Bit definition for DAC_DHR12R1 register ******************/ |
4081 |
/***************** Bit definition for DAC_DHR12R1 register ******************/ |
4082 |
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */ |
4082 |
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */ |
4083 |
|
4083 |
|
4084 |
/***************** Bit definition for DAC_DHR12L1 register ******************/ |
4084 |
/***************** Bit definition for DAC_DHR12L1 register ******************/ |
4085 |
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */ |
4085 |
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */ |
4086 |
|
4086 |
|
4087 |
/****************** Bit definition for DAC_DHR8R1 register ******************/ |
4087 |
/****************** Bit definition for DAC_DHR8R1 register ******************/ |
4088 |
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */ |
4088 |
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */ |
4089 |
|
4089 |
|
4090 |
/***************** Bit definition for DAC_DHR12R2 register ******************/ |
4090 |
/***************** Bit definition for DAC_DHR12R2 register ******************/ |
4091 |
#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */ |
4091 |
#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */ |
4092 |
|
4092 |
|
4093 |
/***************** Bit definition for DAC_DHR12L2 register ******************/ |
4093 |
/***************** Bit definition for DAC_DHR12L2 register ******************/ |
4094 |
#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */ |
4094 |
#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */ |
4095 |
|
4095 |
|
4096 |
/****************** Bit definition for DAC_DHR8R2 register ******************/ |
4096 |
/****************** Bit definition for DAC_DHR8R2 register ******************/ |
4097 |
#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */ |
4097 |
#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */ |
4098 |
|
4098 |
|
4099 |
/***************** Bit definition for DAC_DHR12RD register ******************/ |
4099 |
/***************** Bit definition for DAC_DHR12RD register ******************/ |
4100 |
#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */ |
4100 |
#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */ |
4101 |
#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */ |
4101 |
#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */ |
4102 |
|
4102 |
|
4103 |
/***************** Bit definition for DAC_DHR12LD register ******************/ |
4103 |
/***************** Bit definition for DAC_DHR12LD register ******************/ |
4104 |
#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */ |
4104 |
#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */ |
4105 |
#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */ |
4105 |
#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */ |
4106 |
|
4106 |
|
4107 |
/****************** Bit definition for DAC_DHR8RD register ******************/ |
4107 |
/****************** Bit definition for DAC_DHR8RD register ******************/ |
4108 |
#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */ |
4108 |
#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */ |
4109 |
#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */ |
4109 |
#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */ |
4110 |
|
4110 |
|
4111 |
/******************* Bit definition for DAC_DOR1 register *******************/ |
4111 |
/******************* Bit definition for DAC_DOR1 register *******************/ |
4112 |
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */ |
4112 |
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */ |
4113 |
|
4113 |
|
4114 |
/******************* Bit definition for DAC_DOR2 register *******************/ |
4114 |
/******************* Bit definition for DAC_DOR2 register *******************/ |
4115 |
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */ |
4115 |
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */ |
4116 |
|
4116 |
|
4117 |
/******************** Bit definition for DAC_SR register ********************/ |
4117 |
/******************** Bit definition for DAC_SR register ********************/ |
4118 |
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */ |
4118 |
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */ |
4119 |
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */ |
4119 |
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */ |
4120 |
|
4120 |
|
4121 |
/******************************************************************************/ |
4121 |
/******************************************************************************/ |
4122 |
/* */ |
4122 |
/* */ |
4123 |
/* CEC */ |
4123 |
/* CEC */ |
4124 |
/* */ |
4124 |
/* */ |
4125 |
/******************************************************************************/ |
4125 |
/******************************************************************************/ |
4126 |
/******************** Bit definition for CEC_CFGR register ******************/ |
4126 |
/******************** Bit definition for CEC_CFGR register ******************/ |
4127 |
#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ |
4127 |
#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ |
4128 |
#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ |
4128 |
#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ |
4129 |
#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ |
4129 |
#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ |
4130 |
#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ |
4130 |
#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ |
4131 |
|
4131 |
|
4132 |
/******************** Bit definition for CEC_OAR register ******************/ |
4132 |
/******************** Bit definition for CEC_OAR register ******************/ |
4133 |
#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ |
4133 |
#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ |
4134 |
#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
4134 |
#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ |
4135 |
#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
4135 |
#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ |
4136 |
#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ |
4136 |
#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ |
4137 |
#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ |
4137 |
#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ |
4138 |
|
4138 |
|
4139 |
/******************** Bit definition for CEC_PRES register ******************/ |
4139 |
/******************** Bit definition for CEC_PRES register ******************/ |
4140 |
#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ |
4140 |
#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ |
4141 |
|
4141 |
|
4142 |
/******************** Bit definition for CEC_ESR register ******************/ |
4142 |
/******************** Bit definition for CEC_ESR register ******************/ |
4143 |
#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ |
4143 |
#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ |
4144 |
#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ |
4144 |
#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ |
4145 |
#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ |
4145 |
#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ |
4146 |
#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ |
4146 |
#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ |
4147 |
#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ |
4147 |
#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ |
4148 |
#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ |
4148 |
#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ |
4149 |
#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */ |
4149 |
#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */ |
4150 |
|
4150 |
|
4151 |
/******************** Bit definition for CEC_CSR register ******************/ |
4151 |
/******************** Bit definition for CEC_CSR register ******************/ |
4152 |
#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ |
4152 |
#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ |
4153 |
#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ |
4153 |
#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ |
4154 |
#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ |
4154 |
#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ |
4155 |
#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ |
4155 |
#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ |
4156 |
#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ |
4156 |
#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ |
4157 |
#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ |
4157 |
#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ |
4158 |
#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ |
4158 |
#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ |
4159 |
#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ |
4159 |
#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ |
4160 |
|
4160 |
|
4161 |
/******************** Bit definition for CEC_TXD register ******************/ |
4161 |
/******************** Bit definition for CEC_TXD register ******************/ |
4162 |
#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ |
4162 |
#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ |
4163 |
|
4163 |
|
4164 |
/******************** Bit definition for CEC_RXD register ******************/ |
4164 |
/******************** Bit definition for CEC_RXD register ******************/ |
4165 |
#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ |
4165 |
#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ |
4166 |
|
4166 |
|
4167 |
/******************************************************************************/ |
4167 |
/******************************************************************************/ |
4168 |
/* */ |
4168 |
/* */ |
4169 |
/* TIM */ |
4169 |
/* TIM */ |
4170 |
/* */ |
4170 |
/* */ |
4171 |
/******************************************************************************/ |
4171 |
/******************************************************************************/ |
4172 |
|
4172 |
|
4173 |
/******************* Bit definition for TIM_CR1 register ********************/ |
4173 |
/******************* Bit definition for TIM_CR1 register ********************/ |
4174 |
#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */ |
4174 |
#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */ |
4175 |
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ |
4175 |
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ |
4176 |
#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */ |
4176 |
#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */ |
4177 |
#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */ |
4177 |
#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */ |
4178 |
#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */ |
4178 |
#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */ |
4179 |
|
4179 |
|
4180 |
#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
4180 |
#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
4181 |
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */ |
4181 |
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */ |
4182 |
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */ |
4182 |
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */ |
4183 |
|
4183 |
|
4184 |
#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */ |
4184 |
#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */ |
4185 |
|
4185 |
|
4186 |
#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ |
4186 |
#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ |
4187 |
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4187 |
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4188 |
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4188 |
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4189 |
|
4189 |
|
4190 |
/******************* Bit definition for TIM_CR2 register ********************/ |
4190 |
/******************* Bit definition for TIM_CR2 register ********************/ |
4191 |
#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */ |
4191 |
#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */ |
4192 |
#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */ |
4192 |
#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */ |
4193 |
#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */ |
4193 |
#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */ |
4194 |
|
4194 |
|
4195 |
#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */ |
4195 |
#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */ |
4196 |
#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4196 |
#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4197 |
#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4197 |
#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4198 |
#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4198 |
#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4199 |
|
4199 |
|
4200 |
#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */ |
4200 |
#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */ |
4201 |
#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ |
4201 |
#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ |
4202 |
#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ |
4202 |
#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ |
4203 |
#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ |
4203 |
#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ |
4204 |
#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ |
4204 |
#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ |
4205 |
#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ |
4205 |
#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ |
4206 |
#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ |
4206 |
#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ |
4207 |
#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ |
4207 |
#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ |
4208 |
|
4208 |
|
4209 |
/******************* Bit definition for TIM_SMCR register *******************/ |
4209 |
/******************* Bit definition for TIM_SMCR register *******************/ |
4210 |
#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */ |
4210 |
#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */ |
4211 |
#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4211 |
#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4212 |
#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4212 |
#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4213 |
#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
4213 |
#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
4214 |
|
4214 |
|
4215 |
#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */ |
4215 |
#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */ |
4216 |
#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4216 |
#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4217 |
#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4217 |
#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4218 |
#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4218 |
#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4219 |
|
4219 |
|
4220 |
#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */ |
4220 |
#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */ |
4221 |
|
4221 |
|
4222 |
#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */ |
4222 |
#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */ |
4223 |
#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4223 |
#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4224 |
#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4224 |
#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4225 |
#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */ |
4225 |
#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */ |
4226 |
#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */ |
4226 |
#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */ |
4227 |
|
4227 |
|
4228 |
#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */ |
4228 |
#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */ |
4229 |
#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4229 |
#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4230 |
#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4230 |
#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4231 |
|
4231 |
|
4232 |
#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */ |
4232 |
#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */ |
4233 |
#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */ |
4233 |
#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */ |
4234 |
|
4234 |
|
4235 |
/******************* Bit definition for TIM_DIER register *******************/ |
4235 |
/******************* Bit definition for TIM_DIER register *******************/ |
4236 |
#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */ |
4236 |
#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */ |
4237 |
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ |
4237 |
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ |
4238 |
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ |
4238 |
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ |
4239 |
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ |
4239 |
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ |
4240 |
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ |
4240 |
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ |
4241 |
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */ |
4241 |
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */ |
4242 |
#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */ |
4242 |
#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */ |
4243 |
#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */ |
4243 |
#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */ |
4244 |
#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */ |
4244 |
#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */ |
4245 |
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ |
4245 |
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ |
4246 |
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ |
4246 |
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ |
4247 |
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ |
4247 |
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ |
4248 |
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ |
4248 |
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ |
4249 |
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */ |
4249 |
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */ |
4250 |
#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */ |
4250 |
#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */ |
4251 |
|
4251 |
|
4252 |
/******************** Bit definition for TIM_SR register ********************/ |
4252 |
/******************** Bit definition for TIM_SR register ********************/ |
4253 |
#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */ |
4253 |
#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */ |
4254 |
#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ |
4254 |
#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ |
4255 |
#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ |
4255 |
#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ |
4256 |
#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ |
4256 |
#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ |
4257 |
#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ |
4257 |
#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ |
4258 |
#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */ |
4258 |
#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */ |
4259 |
#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */ |
4259 |
#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */ |
4260 |
#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */ |
4260 |
#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */ |
4261 |
#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ |
4261 |
#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ |
4262 |
#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ |
4262 |
#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ |
4263 |
#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ |
4263 |
#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ |
4264 |
#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ |
4264 |
#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ |
4265 |
|
4265 |
|
4266 |
/******************* Bit definition for TIM_EGR register ********************/ |
4266 |
/******************* Bit definition for TIM_EGR register ********************/ |
4267 |
#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */ |
4267 |
#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */ |
4268 |
#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */ |
4268 |
#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */ |
4269 |
#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */ |
4269 |
#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */ |
4270 |
#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */ |
4270 |
#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */ |
4271 |
#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */ |
4271 |
#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */ |
4272 |
#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */ |
4272 |
#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */ |
4273 |
#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */ |
4273 |
#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */ |
4274 |
#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */ |
4274 |
#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */ |
4275 |
|
4275 |
|
4276 |
/****************** Bit definition for TIM_CCMR1 register *******************/ |
4276 |
/****************** Bit definition for TIM_CCMR1 register *******************/ |
4277 |
#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
4277 |
#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
4278 |
#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4278 |
#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4279 |
#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4279 |
#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4280 |
|
4280 |
|
4281 |
#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */ |
4281 |
#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */ |
4282 |
#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */ |
4282 |
#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */ |
4283 |
|
4283 |
|
4284 |
#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
4284 |
#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
4285 |
#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4285 |
#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4286 |
#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4286 |
#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4287 |
#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4287 |
#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4288 |
|
4288 |
|
4289 |
#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */ |
4289 |
#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */ |
4290 |
|
4290 |
|
4291 |
#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
4291 |
#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
4292 |
#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4292 |
#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4293 |
#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4293 |
#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4294 |
|
4294 |
|
4295 |
#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */ |
4295 |
#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */ |
4296 |
#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */ |
4296 |
#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */ |
4297 |
|
4297 |
|
4298 |
#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
4298 |
#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
4299 |
#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4299 |
#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4300 |
#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4300 |
#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4301 |
#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
4301 |
#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
4302 |
|
4302 |
|
4303 |
#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */ |
4303 |
#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */ |
4304 |
|
4304 |
|
4305 |
/*----------------------------------------------------------------------------*/ |
4305 |
/*----------------------------------------------------------------------------*/ |
4306 |
|
4306 |
|
4307 |
#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
4307 |
#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
4308 |
#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ |
4308 |
#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ |
4309 |
#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ |
4309 |
#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ |
4310 |
|
4310 |
|
4311 |
#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
4311 |
#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
4312 |
#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4312 |
#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4313 |
#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4313 |
#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4314 |
#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4314 |
#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4315 |
#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
4315 |
#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
4316 |
|
4316 |
|
4317 |
#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
4317 |
#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
4318 |
#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
4318 |
#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
4319 |
#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
4319 |
#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
4320 |
|
4320 |
|
4321 |
#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
4321 |
#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
4322 |
#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4322 |
#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4323 |
#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4323 |
#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4324 |
#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
4324 |
#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
4325 |
#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */ |
4325 |
#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */ |
4326 |
|
4326 |
|
4327 |
/****************** Bit definition for TIM_CCMR2 register *******************/ |
4327 |
/****************** Bit definition for TIM_CCMR2 register *******************/ |
4328 |
#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
4328 |
#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
4329 |
#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4329 |
#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4330 |
#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4330 |
#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4331 |
|
4331 |
|
4332 |
#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */ |
4332 |
#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */ |
4333 |
#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */ |
4333 |
#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */ |
4334 |
|
4334 |
|
4335 |
#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
4335 |
#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
4336 |
#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4336 |
#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4337 |
#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4337 |
#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4338 |
#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4338 |
#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4339 |
|
4339 |
|
4340 |
#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */ |
4340 |
#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */ |
4341 |
|
4341 |
|
4342 |
#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
4342 |
#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
4343 |
#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4343 |
#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4344 |
#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4344 |
#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4345 |
|
4345 |
|
4346 |
#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */ |
4346 |
#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */ |
4347 |
#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */ |
4347 |
#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */ |
4348 |
|
4348 |
|
4349 |
#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
4349 |
#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
4350 |
#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4350 |
#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4351 |
#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4351 |
#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4352 |
#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
4352 |
#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
4353 |
|
4353 |
|
4354 |
#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */ |
4354 |
#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */ |
4355 |
|
4355 |
|
4356 |
/*----------------------------------------------------------------------------*/ |
4356 |
/*----------------------------------------------------------------------------*/ |
4357 |
|
4357 |
|
4358 |
#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
4358 |
#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
4359 |
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ |
4359 |
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ |
4360 |
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ |
4360 |
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ |
4361 |
|
4361 |
|
4362 |
#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
4362 |
#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
4363 |
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4363 |
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
4364 |
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4364 |
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
4365 |
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4365 |
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
4366 |
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
4366 |
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
4367 |
|
4367 |
|
4368 |
#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
4368 |
#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
4369 |
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
4369 |
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
4370 |
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
4370 |
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
4371 |
|
4371 |
|
4372 |
#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
4372 |
#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
4373 |
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4373 |
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
4374 |
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4374 |
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
4375 |
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
4375 |
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */ |
4376 |
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */ |
4376 |
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */ |
4377 |
|
4377 |
|
4378 |
/******************* Bit definition for TIM_CCER register *******************/ |
4378 |
/******************* Bit definition for TIM_CCER register *******************/ |
4379 |
#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */ |
4379 |
#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */ |
4380 |
#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */ |
4380 |
#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */ |
4381 |
#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ |
4381 |
#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ |
4382 |
#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ |
4382 |
#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ |
4383 |
#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */ |
4383 |
#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */ |
4384 |
#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */ |
4384 |
#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */ |
4385 |
#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ |
4385 |
#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ |
4386 |
#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ |
4386 |
#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ |
4387 |
#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */ |
4387 |
#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */ |
4388 |
#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */ |
4388 |
#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */ |
4389 |
#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ |
4389 |
#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ |
4390 |
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ |
4390 |
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ |
4391 |
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */ |
4391 |
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */ |
4392 |
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */ |
4392 |
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */ |
4393 |
#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ |
4393 |
#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ |
4394 |
|
4394 |
|
4395 |
/******************* Bit definition for TIM_CNT register ********************/ |
4395 |
/******************* Bit definition for TIM_CNT register ********************/ |
4396 |
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */ |
4396 |
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */ |
4397 |
|
4397 |
|
4398 |
/******************* Bit definition for TIM_PSC register ********************/ |
4398 |
/******************* Bit definition for TIM_PSC register ********************/ |
4399 |
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */ |
4399 |
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */ |
4400 |
|
4400 |
|
4401 |
/******************* Bit definition for TIM_ARR register ********************/ |
4401 |
/******************* Bit definition for TIM_ARR register ********************/ |
4402 |
#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */ |
4402 |
#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */ |
4403 |
|
4403 |
|
4404 |
/******************* Bit definition for TIM_RCR register ********************/ |
4404 |
/******************* Bit definition for TIM_RCR register ********************/ |
4405 |
#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */ |
4405 |
#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */ |
4406 |
|
4406 |
|
4407 |
/******************* Bit definition for TIM_CCR1 register *******************/ |
4407 |
/******************* Bit definition for TIM_CCR1 register *******************/ |
4408 |
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ |
4408 |
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ |
4409 |
|
4409 |
|
4410 |
/******************* Bit definition for TIM_CCR2 register *******************/ |
4410 |
/******************* Bit definition for TIM_CCR2 register *******************/ |
4411 |
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ |
4411 |
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ |
4412 |
|
4412 |
|
4413 |
/******************* Bit definition for TIM_CCR3 register *******************/ |
4413 |
/******************* Bit definition for TIM_CCR3 register *******************/ |
4414 |
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ |
4414 |
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ |
4415 |
|
4415 |
|
4416 |
/******************* Bit definition for TIM_CCR4 register *******************/ |
4416 |
/******************* Bit definition for TIM_CCR4 register *******************/ |
4417 |
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ |
4417 |
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ |
4418 |
|
4418 |
|
4419 |
/******************* Bit definition for TIM_BDTR register *******************/ |
4419 |
/******************* Bit definition for TIM_BDTR register *******************/ |
4420 |
#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
4420 |
#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
4421 |
#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4421 |
#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4422 |
#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4422 |
#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4423 |
#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
4423 |
#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
4424 |
#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
4424 |
#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
4425 |
#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
4425 |
#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
4426 |
#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */ |
4426 |
#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */ |
4427 |
#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */ |
4427 |
#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */ |
4428 |
#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */ |
4428 |
#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */ |
4429 |
|
4429 |
|
4430 |
#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */ |
4430 |
#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */ |
4431 |
#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4431 |
#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4432 |
#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4432 |
#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4433 |
|
4433 |
|
4434 |
#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */ |
4434 |
#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */ |
4435 |
#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */ |
4435 |
#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */ |
4436 |
#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */ |
4436 |
#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */ |
4437 |
#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */ |
4437 |
#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */ |
4438 |
#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */ |
4438 |
#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */ |
4439 |
#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */ |
4439 |
#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */ |
4440 |
|
4440 |
|
4441 |
/******************* Bit definition for TIM_DCR register ********************/ |
4441 |
/******************* Bit definition for TIM_DCR register ********************/ |
4442 |
#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ |
4442 |
#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ |
4443 |
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4443 |
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4444 |
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4444 |
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4445 |
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
4445 |
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
4446 |
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
4446 |
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
4447 |
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
4447 |
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
4448 |
|
4448 |
|
4449 |
#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ |
4449 |
#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ |
4450 |
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4450 |
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
4451 |
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4451 |
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
4452 |
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */ |
4452 |
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */ |
4453 |
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */ |
4453 |
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */ |
4454 |
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */ |
4454 |
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */ |
4455 |
|
4455 |
|
4456 |
/******************* Bit definition for TIM_DMAR register *******************/ |
4456 |
/******************* Bit definition for TIM_DMAR register *******************/ |
4457 |
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ |
4457 |
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ |
4458 |
|
4458 |
|
4459 |
/******************************************************************************/ |
4459 |
/******************************************************************************/ |
4460 |
/* */ |
4460 |
/* */ |
4461 |
/* Real-Time Clock */ |
4461 |
/* Real-Time Clock */ |
4462 |
/* */ |
4462 |
/* */ |
4463 |
/******************************************************************************/ |
4463 |
/******************************************************************************/ |
4464 |
|
4464 |
|
4465 |
/******************* Bit definition for RTC_CRH register ********************/ |
4465 |
/******************* Bit definition for RTC_CRH register ********************/ |
4466 |
#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */ |
4466 |
#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */ |
4467 |
#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */ |
4467 |
#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */ |
4468 |
#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */ |
4468 |
#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */ |
4469 |
|
4469 |
|
4470 |
/******************* Bit definition for RTC_CRL register ********************/ |
4470 |
/******************* Bit definition for RTC_CRL register ********************/ |
4471 |
#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */ |
4471 |
#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */ |
4472 |
#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */ |
4472 |
#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */ |
4473 |
#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */ |
4473 |
#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */ |
4474 |
#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */ |
4474 |
#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */ |
4475 |
#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */ |
4475 |
#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */ |
4476 |
#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */ |
4476 |
#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */ |
4477 |
|
4477 |
|
4478 |
/******************* Bit definition for RTC_PRLH register *******************/ |
4478 |
/******************* Bit definition for RTC_PRLH register *******************/ |
4479 |
#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */ |
4479 |
#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */ |
4480 |
|
4480 |
|
4481 |
/******************* Bit definition for RTC_PRLL register *******************/ |
4481 |
/******************* Bit definition for RTC_PRLL register *******************/ |
4482 |
#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */ |
4482 |
#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */ |
4483 |
|
4483 |
|
4484 |
/******************* Bit definition for RTC_DIVH register *******************/ |
4484 |
/******************* Bit definition for RTC_DIVH register *******************/ |
4485 |
#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */ |
4485 |
#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */ |
4486 |
|
4486 |
|
4487 |
/******************* Bit definition for RTC_DIVL register *******************/ |
4487 |
/******************* Bit definition for RTC_DIVL register *******************/ |
4488 |
#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */ |
4488 |
#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */ |
4489 |
|
4489 |
|
4490 |
/******************* Bit definition for RTC_CNTH register *******************/ |
4490 |
/******************* Bit definition for RTC_CNTH register *******************/ |
4491 |
#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */ |
4491 |
#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */ |
4492 |
|
4492 |
|
4493 |
/******************* Bit definition for RTC_CNTL register *******************/ |
4493 |
/******************* Bit definition for RTC_CNTL register *******************/ |
4494 |
#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */ |
4494 |
#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */ |
4495 |
|
4495 |
|
4496 |
/******************* Bit definition for RTC_ALRH register *******************/ |
4496 |
/******************* Bit definition for RTC_ALRH register *******************/ |
4497 |
#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */ |
4497 |
#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */ |
4498 |
|
4498 |
|
4499 |
/******************* Bit definition for RTC_ALRL register *******************/ |
4499 |
/******************* Bit definition for RTC_ALRL register *******************/ |
4500 |
#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */ |
4500 |
#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */ |
4501 |
|
4501 |
|
4502 |
/******************************************************************************/ |
4502 |
/******************************************************************************/ |
4503 |
/* */ |
4503 |
/* */ |
4504 |
/* Independent WATCHDOG */ |
4504 |
/* Independent WATCHDOG */ |
4505 |
/* */ |
4505 |
/* */ |
4506 |
/******************************************************************************/ |
4506 |
/******************************************************************************/ |
4507 |
|
4507 |
|
4508 |
/******************* Bit definition for IWDG_KR register ********************/ |
4508 |
/******************* Bit definition for IWDG_KR register ********************/ |
4509 |
#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */ |
4509 |
#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */ |
4510 |
|
4510 |
|
4511 |
/******************* Bit definition for IWDG_PR register ********************/ |
4511 |
/******************* Bit definition for IWDG_PR register ********************/ |
4512 |
#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */ |
4512 |
#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */ |
4513 |
#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */ |
4513 |
#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */ |
4514 |
#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */ |
4514 |
#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */ |
4515 |
#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */ |
4515 |
#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */ |
4516 |
|
4516 |
|
4517 |
/******************* Bit definition for IWDG_RLR register *******************/ |
4517 |
/******************* Bit definition for IWDG_RLR register *******************/ |
4518 |
#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */ |
4518 |
#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */ |
4519 |
|
4519 |
|
4520 |
/******************* Bit definition for IWDG_SR register ********************/ |
4520 |
/******************* Bit definition for IWDG_SR register ********************/ |
4521 |
#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */ |
4521 |
#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */ |
4522 |
#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */ |
4522 |
#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */ |
4523 |
|
4523 |
|
4524 |
/******************************************************************************/ |
4524 |
/******************************************************************************/ |
4525 |
/* */ |
4525 |
/* */ |
4526 |
/* Window WATCHDOG */ |
4526 |
/* Window WATCHDOG */ |
4527 |
/* */ |
4527 |
/* */ |
4528 |
/******************************************************************************/ |
4528 |
/******************************************************************************/ |
4529 |
|
4529 |
|
4530 |
/******************* Bit definition for WWDG_CR register ********************/ |
4530 |
/******************* Bit definition for WWDG_CR register ********************/ |
4531 |
#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
4531 |
#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
4532 |
#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */ |
4532 |
#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */ |
4533 |
#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */ |
4533 |
#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */ |
4534 |
#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */ |
4534 |
#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */ |
4535 |
#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */ |
4535 |
#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */ |
4536 |
#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */ |
4536 |
#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */ |
4537 |
#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */ |
4537 |
#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */ |
4538 |
#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */ |
4538 |
#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */ |
4539 |
|
4539 |
|
4540 |
#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */ |
4540 |
#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */ |
4541 |
|
4541 |
|
4542 |
/******************* Bit definition for WWDG_CFR register *******************/ |
4542 |
/******************* Bit definition for WWDG_CFR register *******************/ |
4543 |
#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */ |
4543 |
#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */ |
4544 |
#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4544 |
#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */ |
4545 |
#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4545 |
#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */ |
4546 |
#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */ |
4546 |
#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */ |
4547 |
#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */ |
4547 |
#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */ |
4548 |
#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */ |
4548 |
#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */ |
4549 |
#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */ |
4549 |
#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */ |
4550 |
#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */ |
4550 |
#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */ |
4551 |
|
4551 |
|
4552 |
#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */ |
4552 |
#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */ |
4553 |
#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */ |
4553 |
#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */ |
4554 |
#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */ |
4554 |
#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */ |
4555 |
|
4555 |
|
4556 |
#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */ |
4556 |
#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */ |
4557 |
|
4557 |
|
4558 |
/******************* Bit definition for WWDG_SR register ********************/ |
4558 |
/******************* Bit definition for WWDG_SR register ********************/ |
4559 |
#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */ |
4559 |
#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */ |
4560 |
|
4560 |
|
4561 |
/******************************************************************************/ |
4561 |
/******************************************************************************/ |
4562 |
/* */ |
4562 |
/* */ |
4563 |
/* Flexible Static Memory Controller */ |
4563 |
/* Flexible Static Memory Controller */ |
4564 |
/* */ |
4564 |
/* */ |
4565 |
/******************************************************************************/ |
4565 |
/******************************************************************************/ |
4566 |
|
4566 |
|
4567 |
/****************** Bit definition for FSMC_BCR1 register *******************/ |
4567 |
/****************** Bit definition for FSMC_BCR1 register *******************/ |
4568 |
#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
4568 |
#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
4569 |
#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
4569 |
#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
4570 |
|
4570 |
|
4571 |
#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
4571 |
#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
4572 |
#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
4572 |
#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
4573 |
#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
4573 |
#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
4574 |
|
4574 |
|
4575 |
#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
4575 |
#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
4576 |
#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4576 |
#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4577 |
#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4577 |
#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4578 |
|
4578 |
|
4579 |
#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
4579 |
#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
4580 |
#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
4580 |
#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
4581 |
#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
4581 |
#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
4582 |
#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
4582 |
#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
4583 |
#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
4583 |
#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
4584 |
#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
4584 |
#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
4585 |
#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
4585 |
#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
4586 |
#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
4586 |
#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
4587 |
#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
4587 |
#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
4588 |
#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
4588 |
#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
4589 |
|
4589 |
|
4590 |
/****************** Bit definition for FSMC_BCR2 register *******************/ |
4590 |
/****************** Bit definition for FSMC_BCR2 register *******************/ |
4591 |
#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
4591 |
#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
4592 |
#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
4592 |
#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
4593 |
|
4593 |
|
4594 |
#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
4594 |
#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
4595 |
#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
4595 |
#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
4596 |
#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
4596 |
#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
4597 |
|
4597 |
|
4598 |
#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
4598 |
#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
4599 |
#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4599 |
#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4600 |
#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4600 |
#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4601 |
|
4601 |
|
4602 |
#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
4602 |
#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
4603 |
#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
4603 |
#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
4604 |
#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
4604 |
#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
4605 |
#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
4605 |
#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
4606 |
#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
4606 |
#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
4607 |
#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
4607 |
#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
4608 |
#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
4608 |
#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
4609 |
#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
4609 |
#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
4610 |
#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
4610 |
#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
4611 |
#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
4611 |
#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
4612 |
|
4612 |
|
4613 |
/****************** Bit definition for FSMC_BCR3 register *******************/ |
4613 |
/****************** Bit definition for FSMC_BCR3 register *******************/ |
4614 |
#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
4614 |
#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
4615 |
#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
4615 |
#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
4616 |
|
4616 |
|
4617 |
#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
4617 |
#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
4618 |
#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
4618 |
#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
4619 |
#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
4619 |
#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
4620 |
|
4620 |
|
4621 |
#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
4621 |
#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
4622 |
#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4622 |
#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4623 |
#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4623 |
#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4624 |
|
4624 |
|
4625 |
#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
4625 |
#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
4626 |
#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
4626 |
#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
4627 |
#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */ |
4627 |
#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */ |
4628 |
#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
4628 |
#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
4629 |
#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
4629 |
#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
4630 |
#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
4630 |
#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
4631 |
#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
4631 |
#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
4632 |
#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
4632 |
#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
4633 |
#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
4633 |
#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
4634 |
#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
4634 |
#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
4635 |
|
4635 |
|
4636 |
/****************** Bit definition for FSMC_BCR4 register *******************/ |
4636 |
/****************** Bit definition for FSMC_BCR4 register *******************/ |
4637 |
#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
4637 |
#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
4638 |
#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
4638 |
#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
4639 |
|
4639 |
|
4640 |
#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
4640 |
#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
4641 |
#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
4641 |
#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
4642 |
#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
4642 |
#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
4643 |
|
4643 |
|
4644 |
#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
4644 |
#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
4645 |
#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4645 |
#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4646 |
#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4646 |
#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4647 |
|
4647 |
|
4648 |
#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
4648 |
#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
4649 |
#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
4649 |
#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
4650 |
#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
4650 |
#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
4651 |
#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
4651 |
#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ |
4652 |
#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
4652 |
#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
4653 |
#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
4653 |
#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
4654 |
#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
4654 |
#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
4655 |
#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
4655 |
#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
4656 |
#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
4656 |
#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
4657 |
#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
4657 |
#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
4658 |
|
4658 |
|
4659 |
/****************** Bit definition for FSMC_BTR1 register ******************/ |
4659 |
/****************** Bit definition for FSMC_BTR1 register ******************/ |
4660 |
#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4660 |
#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4661 |
#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4661 |
#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4662 |
#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4662 |
#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4663 |
#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4663 |
#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4664 |
#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4664 |
#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4665 |
|
4665 |
|
4666 |
#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4666 |
#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4667 |
#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4667 |
#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4668 |
#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4668 |
#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4669 |
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4669 |
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4670 |
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4670 |
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4671 |
|
4671 |
|
4672 |
#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4672 |
#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4673 |
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4673 |
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4674 |
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4674 |
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4675 |
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4675 |
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4676 |
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4676 |
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4677 |
|
4677 |
|
4678 |
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
4678 |
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
4679 |
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
4679 |
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
4680 |
#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
4680 |
#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
4681 |
#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
4681 |
#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
4682 |
#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
4682 |
#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
4683 |
|
4683 |
|
4684 |
#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4684 |
#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4685 |
#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4685 |
#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4686 |
#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4686 |
#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4687 |
#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4687 |
#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4688 |
#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4688 |
#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4689 |
|
4689 |
|
4690 |
#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4690 |
#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4691 |
#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4691 |
#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4692 |
#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4692 |
#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4693 |
#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4693 |
#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4694 |
#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4694 |
#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4695 |
|
4695 |
|
4696 |
#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4696 |
#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4697 |
#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4697 |
#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4698 |
#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4698 |
#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4699 |
|
4699 |
|
4700 |
/****************** Bit definition for FSMC_BTR2 register *******************/ |
4700 |
/****************** Bit definition for FSMC_BTR2 register *******************/ |
4701 |
#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4701 |
#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4702 |
#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4702 |
#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4703 |
#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4703 |
#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4704 |
#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4704 |
#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4705 |
#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4705 |
#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4706 |
|
4706 |
|
4707 |
#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4707 |
#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4708 |
#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4708 |
#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4709 |
#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4709 |
#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4710 |
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4710 |
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4711 |
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4711 |
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4712 |
|
4712 |
|
4713 |
#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4713 |
#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4714 |
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4714 |
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4715 |
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4715 |
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4716 |
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4716 |
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4717 |
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4717 |
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4718 |
|
4718 |
|
4719 |
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
4719 |
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
4720 |
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
4720 |
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
4721 |
#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
4721 |
#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
4722 |
#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
4722 |
#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
4723 |
#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
4723 |
#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
4724 |
|
4724 |
|
4725 |
#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4725 |
#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4726 |
#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4726 |
#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4727 |
#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4727 |
#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4728 |
#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4728 |
#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4729 |
#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4729 |
#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4730 |
|
4730 |
|
4731 |
#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4731 |
#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4732 |
#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4732 |
#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4733 |
#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4733 |
#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4734 |
#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4734 |
#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4735 |
#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4735 |
#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4736 |
|
4736 |
|
4737 |
#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4737 |
#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4738 |
#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4738 |
#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4739 |
#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4739 |
#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4740 |
|
4740 |
|
4741 |
/******************* Bit definition for FSMC_BTR3 register *******************/ |
4741 |
/******************* Bit definition for FSMC_BTR3 register *******************/ |
4742 |
#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4742 |
#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4743 |
#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4743 |
#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4744 |
#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4744 |
#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4745 |
#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4745 |
#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4746 |
#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4746 |
#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4747 |
|
4747 |
|
4748 |
#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4748 |
#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4749 |
#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4749 |
#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4750 |
#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4750 |
#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4751 |
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4751 |
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4752 |
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4752 |
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4753 |
|
4753 |
|
4754 |
#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4754 |
#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4755 |
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4755 |
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4756 |
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4756 |
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4757 |
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4757 |
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4758 |
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4758 |
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4759 |
|
4759 |
|
4760 |
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
4760 |
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
4761 |
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
4761 |
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
4762 |
#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
4762 |
#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
4763 |
#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
4763 |
#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
4764 |
#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
4764 |
#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
4765 |
|
4765 |
|
4766 |
#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4766 |
#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4767 |
#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4767 |
#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4768 |
#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4768 |
#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4769 |
#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4769 |
#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4770 |
#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4770 |
#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4771 |
|
4771 |
|
4772 |
#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4772 |
#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4773 |
#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4773 |
#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4774 |
#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4774 |
#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4775 |
#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4775 |
#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4776 |
#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4776 |
#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4777 |
|
4777 |
|
4778 |
#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4778 |
#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4779 |
#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4779 |
#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4780 |
#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4780 |
#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4781 |
|
4781 |
|
4782 |
/****************** Bit definition for FSMC_BTR4 register *******************/ |
4782 |
/****************** Bit definition for FSMC_BTR4 register *******************/ |
4783 |
#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4783 |
#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4784 |
#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4784 |
#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4785 |
#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4785 |
#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4786 |
#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4786 |
#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4787 |
#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4787 |
#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4788 |
|
4788 |
|
4789 |
#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4789 |
#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4790 |
#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4790 |
#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4791 |
#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4791 |
#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4792 |
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4792 |
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4793 |
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4793 |
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4794 |
|
4794 |
|
4795 |
#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4795 |
#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4796 |
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4796 |
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4797 |
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4797 |
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4798 |
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4798 |
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4799 |
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4799 |
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4800 |
|
4800 |
|
4801 |
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
4801 |
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
4802 |
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
4802 |
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
4803 |
#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
4803 |
#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
4804 |
#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
4804 |
#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
4805 |
#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
4805 |
#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
4806 |
|
4806 |
|
4807 |
#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4807 |
#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4808 |
#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4808 |
#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4809 |
#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4809 |
#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4810 |
#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4810 |
#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4811 |
#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4811 |
#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4812 |
|
4812 |
|
4813 |
#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4813 |
#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4814 |
#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4814 |
#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4815 |
#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4815 |
#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4816 |
#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4816 |
#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4817 |
#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4817 |
#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4818 |
|
4818 |
|
4819 |
#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4819 |
#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4820 |
#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4820 |
#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4821 |
#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4821 |
#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4822 |
|
4822 |
|
4823 |
/****************** Bit definition for FSMC_BWTR1 register ******************/ |
4823 |
/****************** Bit definition for FSMC_BWTR1 register ******************/ |
4824 |
#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4824 |
#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4825 |
#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4825 |
#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4826 |
#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4826 |
#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4827 |
#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4827 |
#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4828 |
#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4828 |
#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4829 |
|
4829 |
|
4830 |
#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4830 |
#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4831 |
#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4831 |
#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4832 |
#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4832 |
#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4833 |
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4833 |
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4834 |
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4834 |
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4835 |
|
4835 |
|
4836 |
#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4836 |
#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4837 |
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4837 |
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4838 |
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4838 |
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4839 |
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4839 |
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4840 |
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4840 |
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4841 |
|
4841 |
|
4842 |
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4842 |
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4843 |
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4843 |
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4844 |
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4844 |
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4845 |
#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4845 |
#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4846 |
#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4846 |
#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4847 |
|
4847 |
|
4848 |
#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4848 |
#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4849 |
#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4849 |
#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4850 |
#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4850 |
#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4851 |
#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4851 |
#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4852 |
#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4852 |
#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4853 |
|
4853 |
|
4854 |
#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4854 |
#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4855 |
#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4855 |
#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4856 |
#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4856 |
#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4857 |
|
4857 |
|
4858 |
/****************** Bit definition for FSMC_BWTR2 register ******************/ |
4858 |
/****************** Bit definition for FSMC_BWTR2 register ******************/ |
4859 |
#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4859 |
#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4860 |
#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4860 |
#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4861 |
#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4861 |
#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4862 |
#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4862 |
#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4863 |
#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4863 |
#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4864 |
|
4864 |
|
4865 |
#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4865 |
#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4866 |
#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4866 |
#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4867 |
#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4867 |
#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4868 |
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4868 |
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4869 |
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4869 |
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4870 |
|
4870 |
|
4871 |
#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4871 |
#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4872 |
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4872 |
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4873 |
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4873 |
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4874 |
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4874 |
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4875 |
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4875 |
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4876 |
|
4876 |
|
4877 |
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4877 |
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4878 |
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4878 |
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4879 |
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ |
4879 |
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ |
4880 |
#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4880 |
#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4881 |
#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4881 |
#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4882 |
|
4882 |
|
4883 |
#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4883 |
#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4884 |
#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4884 |
#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4885 |
#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4885 |
#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4886 |
#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4886 |
#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4887 |
#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4887 |
#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4888 |
|
4888 |
|
4889 |
#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4889 |
#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4890 |
#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4890 |
#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4891 |
#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4891 |
#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4892 |
|
4892 |
|
4893 |
/****************** Bit definition for FSMC_BWTR3 register ******************/ |
4893 |
/****************** Bit definition for FSMC_BWTR3 register ******************/ |
4894 |
#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4894 |
#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4895 |
#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4895 |
#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4896 |
#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4896 |
#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4897 |
#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4897 |
#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4898 |
#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4898 |
#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4899 |
|
4899 |
|
4900 |
#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4900 |
#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4901 |
#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4901 |
#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4902 |
#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4902 |
#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4903 |
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4903 |
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4904 |
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4904 |
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4905 |
|
4905 |
|
4906 |
#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4906 |
#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4907 |
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4907 |
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4908 |
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4908 |
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4909 |
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4909 |
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4910 |
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4910 |
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4911 |
|
4911 |
|
4912 |
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4912 |
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4913 |
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4913 |
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4914 |
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4914 |
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4915 |
#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4915 |
#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4916 |
#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4916 |
#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4917 |
|
4917 |
|
4918 |
#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4918 |
#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4919 |
#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4919 |
#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4920 |
#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4920 |
#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4921 |
#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4921 |
#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4922 |
#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4922 |
#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4923 |
|
4923 |
|
4924 |
#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4924 |
#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4925 |
#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4925 |
#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4926 |
#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4926 |
#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4927 |
|
4927 |
|
4928 |
/****************** Bit definition for FSMC_BWTR4 register ******************/ |
4928 |
/****************** Bit definition for FSMC_BWTR4 register ******************/ |
4929 |
#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4929 |
#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
4930 |
#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4930 |
#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
4931 |
#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4931 |
#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
4932 |
#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4932 |
#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
4933 |
#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4933 |
#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
4934 |
|
4934 |
|
4935 |
#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4935 |
#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
4936 |
#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4936 |
#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4937 |
#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4937 |
#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4938 |
#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4938 |
#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
4939 |
#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4939 |
#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
4940 |
|
4940 |
|
4941 |
#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4941 |
#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
4942 |
#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4942 |
#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
4943 |
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4943 |
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
4944 |
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4944 |
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
4945 |
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4945 |
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
4946 |
|
4946 |
|
4947 |
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4947 |
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
4948 |
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4948 |
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
4949 |
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4949 |
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
4950 |
#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4950 |
#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
4951 |
#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4951 |
#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
4952 |
|
4952 |
|
4953 |
#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4953 |
#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
4954 |
#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4954 |
#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
4955 |
#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4955 |
#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
4956 |
#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4956 |
#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
4957 |
#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4957 |
#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
4958 |
|
4958 |
|
4959 |
#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4959 |
#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
4960 |
#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4960 |
#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
4961 |
#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4961 |
#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
4962 |
|
4962 |
|
4963 |
/****************** Bit definition for FSMC_PCR2 register *******************/ |
4963 |
/****************** Bit definition for FSMC_PCR2 register *******************/ |
4964 |
#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
4964 |
#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
4965 |
#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
4965 |
#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
4966 |
#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
4966 |
#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
4967 |
|
4967 |
|
4968 |
#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
4968 |
#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
4969 |
#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4969 |
#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4970 |
#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4970 |
#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4971 |
|
4971 |
|
4972 |
#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
4972 |
#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
4973 |
|
4973 |
|
4974 |
#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
4974 |
#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
4975 |
#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
4975 |
#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
4976 |
#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
4976 |
#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
4977 |
#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
4977 |
#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
4978 |
#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
4978 |
#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
4979 |
|
4979 |
|
4980 |
#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
4980 |
#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
4981 |
#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
4981 |
#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
4982 |
#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
4982 |
#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
4983 |
#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
4983 |
#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
4984 |
#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
4984 |
#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
4985 |
|
4985 |
|
4986 |
#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */ |
4986 |
#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */ |
4987 |
#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
4987 |
#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
4988 |
#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
4988 |
#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
4989 |
#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
4989 |
#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
4990 |
|
4990 |
|
4991 |
/****************** Bit definition for FSMC_PCR3 register *******************/ |
4991 |
/****************** Bit definition for FSMC_PCR3 register *******************/ |
4992 |
#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
4992 |
#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
4993 |
#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
4993 |
#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
4994 |
#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
4994 |
#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
4995 |
|
4995 |
|
4996 |
#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
4996 |
#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
4997 |
#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4997 |
#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
4998 |
#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4998 |
#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
4999 |
|
4999 |
|
5000 |
#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
5000 |
#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
5001 |
|
5001 |
|
5002 |
#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
5002 |
#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
5003 |
#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
5003 |
#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
5004 |
#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
5004 |
#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
5005 |
#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
5005 |
#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
5006 |
#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
5006 |
#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
5007 |
|
5007 |
|
5008 |
#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
5008 |
#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
5009 |
#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
5009 |
#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
5010 |
#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
5010 |
#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
5011 |
#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
5011 |
#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
5012 |
#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
5012 |
#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
5013 |
|
5013 |
|
5014 |
#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ |
5014 |
#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ |
5015 |
#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
5015 |
#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
5016 |
#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
5016 |
#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
5017 |
#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
5017 |
#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
5018 |
|
5018 |
|
5019 |
/****************** Bit definition for FSMC_PCR4 register *******************/ |
5019 |
/****************** Bit definition for FSMC_PCR4 register *******************/ |
5020 |
#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
5020 |
#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
5021 |
#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
5021 |
#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ |
5022 |
#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
5022 |
#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
5023 |
|
5023 |
|
5024 |
#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
5024 |
#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
5025 |
#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
5025 |
#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
5026 |
#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
5026 |
#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
5027 |
|
5027 |
|
5028 |
#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
5028 |
#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
5029 |
|
5029 |
|
5030 |
#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
5030 |
#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
5031 |
#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
5031 |
#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
5032 |
#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
5032 |
#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
5033 |
#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
5033 |
#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
5034 |
#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
5034 |
#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
5035 |
|
5035 |
|
5036 |
#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
5036 |
#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
5037 |
#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
5037 |
#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
5038 |
#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
5038 |
#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
5039 |
#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
5039 |
#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
5040 |
#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
5040 |
#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
5041 |
|
5041 |
|
5042 |
#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ |
5042 |
#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ |
5043 |
#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
5043 |
#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
5044 |
#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
5044 |
#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
5045 |
#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
5045 |
#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
5046 |
|
5046 |
|
5047 |
/******************* Bit definition for FSMC_SR2 register *******************/ |
5047 |
/******************* Bit definition for FSMC_SR2 register *******************/ |
5048 |
#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ |
5048 |
#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ |
5049 |
#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ |
5049 |
#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ |
5050 |
#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ |
5050 |
#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ |
5051 |
#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
5051 |
#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
5052 |
#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ |
5052 |
#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ |
5053 |
#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
5053 |
#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
5054 |
#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ |
5054 |
#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ |
5055 |
|
5055 |
|
5056 |
/******************* Bit definition for FSMC_SR3 register *******************/ |
5056 |
/******************* Bit definition for FSMC_SR3 register *******************/ |
5057 |
#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ |
5057 |
#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ |
5058 |
#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ |
5058 |
#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ |
5059 |
#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ |
5059 |
#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ |
5060 |
#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
5060 |
#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
5061 |
#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ |
5061 |
#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ |
5062 |
#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
5062 |
#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
5063 |
#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ |
5063 |
#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ |
5064 |
|
5064 |
|
5065 |
/******************* Bit definition for FSMC_SR4 register *******************/ |
5065 |
/******************* Bit definition for FSMC_SR4 register *******************/ |
5066 |
#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ |
5066 |
#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ |
5067 |
#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ |
5067 |
#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ |
5068 |
#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ |
5068 |
#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ |
5069 |
#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
5069 |
#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ |
5070 |
#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ |
5070 |
#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ |
5071 |
#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
5071 |
#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ |
5072 |
#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ |
5072 |
#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ |
5073 |
|
5073 |
|
5074 |
/****************** Bit definition for FSMC_PMEM2 register ******************/ |
5074 |
/****************** Bit definition for FSMC_PMEM2 register ******************/ |
5075 |
#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ |
5075 |
#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ |
5076 |
#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5076 |
#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5077 |
#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5077 |
#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5078 |
#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5078 |
#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5079 |
#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5079 |
#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5080 |
#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5080 |
#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5081 |
#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5081 |
#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5082 |
#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5082 |
#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5083 |
#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5083 |
#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5084 |
|
5084 |
|
5085 |
#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ |
5085 |
#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ |
5086 |
#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5086 |
#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5087 |
#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5087 |
#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5088 |
#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5088 |
#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5089 |
#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5089 |
#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5090 |
#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5090 |
#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5091 |
#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5091 |
#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5092 |
#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5092 |
#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5093 |
#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5093 |
#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5094 |
|
5094 |
|
5095 |
#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ |
5095 |
#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ |
5096 |
#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5096 |
#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5097 |
#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5097 |
#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5098 |
#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5098 |
#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5099 |
#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5099 |
#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5100 |
#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5100 |
#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5101 |
#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5101 |
#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5102 |
#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5102 |
#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5103 |
#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5103 |
#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5104 |
|
5104 |
|
5105 |
#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ |
5105 |
#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ |
5106 |
#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5106 |
#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5107 |
#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5107 |
#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5108 |
#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5108 |
#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5109 |
#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5109 |
#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5110 |
#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5110 |
#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5111 |
#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5111 |
#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5112 |
#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5112 |
#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5113 |
#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5113 |
#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5114 |
|
5114 |
|
5115 |
/****************** Bit definition for FSMC_PMEM3 register ******************/ |
5115 |
/****************** Bit definition for FSMC_PMEM3 register ******************/ |
5116 |
#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */ |
5116 |
#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */ |
5117 |
#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5117 |
#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5118 |
#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5118 |
#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5119 |
#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5119 |
#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5120 |
#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5120 |
#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5121 |
#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5121 |
#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5122 |
#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5122 |
#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5123 |
#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5123 |
#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5124 |
#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5124 |
#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5125 |
|
5125 |
|
5126 |
#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */ |
5126 |
#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */ |
5127 |
#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5127 |
#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5128 |
#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5128 |
#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5129 |
#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5129 |
#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5130 |
#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5130 |
#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5131 |
#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5131 |
#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5132 |
#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5132 |
#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5133 |
#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5133 |
#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5134 |
#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5134 |
#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5135 |
|
5135 |
|
5136 |
#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */ |
5136 |
#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */ |
5137 |
#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5137 |
#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5138 |
#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5138 |
#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5139 |
#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5139 |
#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5140 |
#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5140 |
#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5141 |
#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5141 |
#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5142 |
#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5142 |
#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5143 |
#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5143 |
#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5144 |
#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5144 |
#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5145 |
|
5145 |
|
5146 |
#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ |
5146 |
#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ |
5147 |
#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5147 |
#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5148 |
#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5148 |
#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5149 |
#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5149 |
#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5150 |
#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5150 |
#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5151 |
#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5151 |
#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5152 |
#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5152 |
#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5153 |
#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5153 |
#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5154 |
#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5154 |
#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5155 |
|
5155 |
|
5156 |
/****************** Bit definition for FSMC_PMEM4 register ******************/ |
5156 |
/****************** Bit definition for FSMC_PMEM4 register ******************/ |
5157 |
#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */ |
5157 |
#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */ |
5158 |
#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5158 |
#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5159 |
#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5159 |
#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5160 |
#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5160 |
#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5161 |
#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5161 |
#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5162 |
#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5162 |
#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5163 |
#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5163 |
#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5164 |
#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5164 |
#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5165 |
#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5165 |
#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5166 |
|
5166 |
|
5167 |
#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */ |
5167 |
#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */ |
5168 |
#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5168 |
#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5169 |
#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5169 |
#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5170 |
#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5170 |
#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5171 |
#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5171 |
#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5172 |
#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5172 |
#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5173 |
#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5173 |
#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5174 |
#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5174 |
#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5175 |
#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5175 |
#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5176 |
|
5176 |
|
5177 |
#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */ |
5177 |
#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */ |
5178 |
#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5178 |
#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5179 |
#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5179 |
#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5180 |
#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5180 |
#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5181 |
#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5181 |
#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5182 |
#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5182 |
#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5183 |
#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5183 |
#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5184 |
#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5184 |
#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5185 |
#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5185 |
#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5186 |
|
5186 |
|
5187 |
#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ |
5187 |
#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ |
5188 |
#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5188 |
#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5189 |
#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5189 |
#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5190 |
#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5190 |
#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5191 |
#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5191 |
#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5192 |
#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5192 |
#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5193 |
#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5193 |
#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5194 |
#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5194 |
#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5195 |
#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5195 |
#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5196 |
|
5196 |
|
5197 |
/****************** Bit definition for FSMC_PATT2 register ******************/ |
5197 |
/****************** Bit definition for FSMC_PATT2 register ******************/ |
5198 |
#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ |
5198 |
#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ |
5199 |
#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5199 |
#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5200 |
#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5200 |
#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5201 |
#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5201 |
#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5202 |
#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5202 |
#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5203 |
#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5203 |
#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5204 |
#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5204 |
#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5205 |
#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5205 |
#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5206 |
#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5206 |
#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5207 |
|
5207 |
|
5208 |
#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ |
5208 |
#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ |
5209 |
#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5209 |
#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5210 |
#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5210 |
#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5211 |
#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5211 |
#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5212 |
#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5212 |
#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5213 |
#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5213 |
#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5214 |
#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5214 |
#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5215 |
#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5215 |
#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5216 |
#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5216 |
#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5217 |
|
5217 |
|
5218 |
#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ |
5218 |
#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ |
5219 |
#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5219 |
#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5220 |
#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5220 |
#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5221 |
#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5221 |
#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5222 |
#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5222 |
#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5223 |
#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5223 |
#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5224 |
#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5224 |
#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5225 |
#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5225 |
#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5226 |
#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5226 |
#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5227 |
|
5227 |
|
5228 |
#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ |
5228 |
#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ |
5229 |
#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5229 |
#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5230 |
#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5230 |
#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5231 |
#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5231 |
#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5232 |
#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5232 |
#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5233 |
#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5233 |
#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5234 |
#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5234 |
#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5235 |
#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5235 |
#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5236 |
#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5236 |
#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5237 |
|
5237 |
|
5238 |
/****************** Bit definition for FSMC_PATT3 register ******************/ |
5238 |
/****************** Bit definition for FSMC_PATT3 register ******************/ |
5239 |
#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */ |
5239 |
#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */ |
5240 |
#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5240 |
#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5241 |
#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5241 |
#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5242 |
#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5242 |
#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5243 |
#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5243 |
#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5244 |
#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5244 |
#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5245 |
#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5245 |
#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5246 |
#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5246 |
#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5247 |
#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5247 |
#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5248 |
|
5248 |
|
5249 |
#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ |
5249 |
#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ |
5250 |
#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5250 |
#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5251 |
#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5251 |
#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5252 |
#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5252 |
#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5253 |
#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5253 |
#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5254 |
#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5254 |
#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5255 |
#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5255 |
#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5256 |
#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5256 |
#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5257 |
#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5257 |
#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5258 |
|
5258 |
|
5259 |
#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ |
5259 |
#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ |
5260 |
#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5260 |
#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5261 |
#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5261 |
#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5262 |
#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5262 |
#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5263 |
#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5263 |
#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5264 |
#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5264 |
#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5265 |
#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5265 |
#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5266 |
#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5266 |
#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5267 |
#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5267 |
#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5268 |
|
5268 |
|
5269 |
#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ |
5269 |
#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ |
5270 |
#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5270 |
#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5271 |
#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5271 |
#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5272 |
#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5272 |
#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5273 |
#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5273 |
#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5274 |
#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5274 |
#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5275 |
#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5275 |
#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5276 |
#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5276 |
#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5277 |
#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5277 |
#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5278 |
|
5278 |
|
5279 |
/****************** Bit definition for FSMC_PATT4 register ******************/ |
5279 |
/****************** Bit definition for FSMC_PATT4 register ******************/ |
5280 |
#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */ |
5280 |
#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */ |
5281 |
#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5281 |
#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5282 |
#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5282 |
#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5283 |
#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5283 |
#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5284 |
#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5284 |
#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5285 |
#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5285 |
#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5286 |
#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5286 |
#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5287 |
#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5287 |
#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5288 |
#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5288 |
#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5289 |
|
5289 |
|
5290 |
#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ |
5290 |
#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ |
5291 |
#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5291 |
#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5292 |
#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5292 |
#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5293 |
#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5293 |
#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5294 |
#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5294 |
#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5295 |
#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5295 |
#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5296 |
#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5296 |
#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5297 |
#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5297 |
#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5298 |
#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5298 |
#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5299 |
|
5299 |
|
5300 |
#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ |
5300 |
#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ |
5301 |
#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5301 |
#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5302 |
#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5302 |
#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5303 |
#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5303 |
#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5304 |
#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5304 |
#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5305 |
#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5305 |
#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5306 |
#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5306 |
#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5307 |
#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5307 |
#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5308 |
#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5308 |
#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5309 |
|
5309 |
|
5310 |
#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ |
5310 |
#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ |
5311 |
#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5311 |
#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5312 |
#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5312 |
#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5313 |
#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5313 |
#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5314 |
#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5314 |
#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5315 |
#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5315 |
#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5316 |
#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5316 |
#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5317 |
#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5317 |
#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5318 |
#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5318 |
#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5319 |
|
5319 |
|
5320 |
/****************** Bit definition for FSMC_PIO4 register *******************/ |
5320 |
/****************** Bit definition for FSMC_PIO4 register *******************/ |
5321 |
#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */ |
5321 |
#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */ |
5322 |
#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5322 |
#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
5323 |
#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5323 |
#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
5324 |
#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5324 |
#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
5325 |
#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5325 |
#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
5326 |
#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5326 |
#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
5327 |
#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5327 |
#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
5328 |
#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5328 |
#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
5329 |
#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5329 |
#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
5330 |
|
5330 |
|
5331 |
#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */ |
5331 |
#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */ |
5332 |
#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5332 |
#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
5333 |
#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5333 |
#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
5334 |
#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5334 |
#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
5335 |
#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5335 |
#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
5336 |
#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5336 |
#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
5337 |
#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5337 |
#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
5338 |
#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5338 |
#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
5339 |
#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5339 |
#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
5340 |
|
5340 |
|
5341 |
#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */ |
5341 |
#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */ |
5342 |
#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5342 |
#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
5343 |
#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5343 |
#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
5344 |
#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5344 |
#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
5345 |
#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5345 |
#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
5346 |
#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5346 |
#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
5347 |
#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5347 |
#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
5348 |
#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5348 |
#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
5349 |
#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5349 |
#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
5350 |
|
5350 |
|
5351 |
#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ |
5351 |
#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ |
5352 |
#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5352 |
#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
5353 |
#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5353 |
#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
5354 |
#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5354 |
#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
5355 |
#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5355 |
#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
5356 |
#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5356 |
#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
5357 |
#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5357 |
#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
5358 |
#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5358 |
#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
5359 |
#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5359 |
#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
5360 |
|
5360 |
|
5361 |
/****************** Bit definition for FSMC_ECCR2 register ******************/ |
5361 |
/****************** Bit definition for FSMC_ECCR2 register ******************/ |
5362 |
#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ |
5362 |
#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ |
5363 |
|
5363 |
|
5364 |
/****************** Bit definition for FSMC_ECCR3 register ******************/ |
5364 |
/****************** Bit definition for FSMC_ECCR3 register ******************/ |
5365 |
#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ |
5365 |
#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ |
5366 |
|
5366 |
|
5367 |
/******************************************************************************/ |
5367 |
/******************************************************************************/ |
5368 |
/* */ |
5368 |
/* */ |
5369 |
/* SD host Interface */ |
5369 |
/* SD host Interface */ |
5370 |
/* */ |
5370 |
/* */ |
5371 |
/******************************************************************************/ |
5371 |
/******************************************************************************/ |
5372 |
|
5372 |
|
5373 |
/****************** Bit definition for SDIO_POWER register ******************/ |
5373 |
/****************** Bit definition for SDIO_POWER register ******************/ |
5374 |
#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */ |
5374 |
#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */ |
5375 |
#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */ |
5375 |
#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */ |
5376 |
#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */ |
5376 |
#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */ |
5377 |
|
5377 |
|
5378 |
/****************** Bit definition for SDIO_CLKCR register ******************/ |
5378 |
/****************** Bit definition for SDIO_CLKCR register ******************/ |
5379 |
#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */ |
5379 |
#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */ |
5380 |
#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */ |
5380 |
#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */ |
5381 |
#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */ |
5381 |
#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */ |
5382 |
#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */ |
5382 |
#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */ |
5383 |
|
5383 |
|
5384 |
#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
5384 |
#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
5385 |
#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */ |
5385 |
#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */ |
5386 |
#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */ |
5386 |
#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */ |
5387 |
|
5387 |
|
5388 |
#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */ |
5388 |
#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */ |
5389 |
#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */ |
5389 |
#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */ |
5390 |
|
5390 |
|
5391 |
/******************* Bit definition for SDIO_ARG register *******************/ |
5391 |
/******************* Bit definition for SDIO_ARG register *******************/ |
5392 |
#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */ |
5392 |
#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */ |
5393 |
|
5393 |
|
5394 |
/******************* Bit definition for SDIO_CMD register *******************/ |
5394 |
/******************* Bit definition for SDIO_CMD register *******************/ |
5395 |
#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */ |
5395 |
#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */ |
5396 |
|
5396 |
|
5397 |
#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */ |
5397 |
#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */ |
5398 |
#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ |
5398 |
#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ |
5399 |
#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ |
5399 |
#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ |
5400 |
|
5400 |
|
5401 |
#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */ |
5401 |
#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */ |
5402 |
#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
5402 |
#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
5403 |
#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */ |
5403 |
#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */ |
5404 |
#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */ |
5404 |
#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */ |
5405 |
#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */ |
5405 |
#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */ |
5406 |
#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */ |
5406 |
#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */ |
5407 |
#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */ |
5407 |
#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */ |
5408 |
|
5408 |
|
5409 |
/***************** Bit definition for SDIO_RESPCMD register *****************/ |
5409 |
/***************** Bit definition for SDIO_RESPCMD register *****************/ |
5410 |
#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */ |
5410 |
#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */ |
5411 |
|
5411 |
|
5412 |
/****************** Bit definition for SDIO_RESP0 register ******************/ |
5412 |
/****************** Bit definition for SDIO_RESP0 register ******************/ |
5413 |
#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5413 |
#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5414 |
|
5414 |
|
5415 |
/****************** Bit definition for SDIO_RESP1 register ******************/ |
5415 |
/****************** Bit definition for SDIO_RESP1 register ******************/ |
5416 |
#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5416 |
#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5417 |
|
5417 |
|
5418 |
/****************** Bit definition for SDIO_RESP2 register ******************/ |
5418 |
/****************** Bit definition for SDIO_RESP2 register ******************/ |
5419 |
#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5419 |
#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5420 |
|
5420 |
|
5421 |
/****************** Bit definition for SDIO_RESP3 register ******************/ |
5421 |
/****************** Bit definition for SDIO_RESP3 register ******************/ |
5422 |
#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5422 |
#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5423 |
|
5423 |
|
5424 |
/****************** Bit definition for SDIO_RESP4 register ******************/ |
5424 |
/****************** Bit definition for SDIO_RESP4 register ******************/ |
5425 |
#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5425 |
#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
5426 |
|
5426 |
|
5427 |
/****************** Bit definition for SDIO_DTIMER register *****************/ |
5427 |
/****************** Bit definition for SDIO_DTIMER register *****************/ |
5428 |
#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */ |
5428 |
#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */ |
5429 |
|
5429 |
|
5430 |
/****************** Bit definition for SDIO_DLEN register *******************/ |
5430 |
/****************** Bit definition for SDIO_DLEN register *******************/ |
5431 |
#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */ |
5431 |
#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */ |
5432 |
|
5432 |
|
5433 |
/****************** Bit definition for SDIO_DCTRL register ******************/ |
5433 |
/****************** Bit definition for SDIO_DCTRL register ******************/ |
5434 |
#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */ |
5434 |
#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */ |
5435 |
#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */ |
5435 |
#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */ |
5436 |
#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */ |
5436 |
#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */ |
5437 |
#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */ |
5437 |
#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */ |
5438 |
|
5438 |
|
5439 |
#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */ |
5439 |
#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */ |
5440 |
#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5440 |
#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5441 |
#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5441 |
#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5442 |
#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
5442 |
#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
5443 |
#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
5443 |
#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
5444 |
|
5444 |
|
5445 |
#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */ |
5445 |
#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */ |
5446 |
#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */ |
5446 |
#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */ |
5447 |
#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */ |
5447 |
#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */ |
5448 |
#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */ |
5448 |
#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */ |
5449 |
|
5449 |
|
5450 |
/****************** Bit definition for SDIO_DCOUNT register *****************/ |
5450 |
/****************** Bit definition for SDIO_DCOUNT register *****************/ |
5451 |
#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */ |
5451 |
#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */ |
5452 |
|
5452 |
|
5453 |
/****************** Bit definition for SDIO_STA register ********************/ |
5453 |
/****************** Bit definition for SDIO_STA register ********************/ |
5454 |
#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */ |
5454 |
#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */ |
5455 |
#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */ |
5455 |
#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */ |
5456 |
#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */ |
5456 |
#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */ |
5457 |
#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */ |
5457 |
#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */ |
5458 |
#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */ |
5458 |
#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */ |
5459 |
#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */ |
5459 |
#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */ |
5460 |
#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */ |
5460 |
#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */ |
5461 |
#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */ |
5461 |
#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */ |
5462 |
#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */ |
5462 |
#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */ |
5463 |
#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */ |
5463 |
#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */ |
5464 |
#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */ |
5464 |
#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */ |
5465 |
#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */ |
5465 |
#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */ |
5466 |
#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */ |
5466 |
#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */ |
5467 |
#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */ |
5467 |
#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */ |
5468 |
#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
5468 |
#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
5469 |
#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
5469 |
#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
5470 |
#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */ |
5470 |
#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */ |
5471 |
#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */ |
5471 |
#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */ |
5472 |
#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */ |
5472 |
#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */ |
5473 |
#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */ |
5473 |
#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */ |
5474 |
#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */ |
5474 |
#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */ |
5475 |
#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */ |
5475 |
#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */ |
5476 |
#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */ |
5476 |
#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */ |
5477 |
#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */ |
5477 |
#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */ |
5478 |
|
5478 |
|
5479 |
/******************* Bit definition for SDIO_ICR register *******************/ |
5479 |
/******************* Bit definition for SDIO_ICR register *******************/ |
5480 |
#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */ |
5480 |
#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */ |
5481 |
#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */ |
5481 |
#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */ |
5482 |
#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */ |
5482 |
#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */ |
5483 |
#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */ |
5483 |
#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */ |
5484 |
#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */ |
5484 |
#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */ |
5485 |
#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */ |
5485 |
#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */ |
5486 |
#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */ |
5486 |
#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */ |
5487 |
#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */ |
5487 |
#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */ |
5488 |
#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */ |
5488 |
#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */ |
5489 |
#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */ |
5489 |
#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */ |
5490 |
#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */ |
5490 |
#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */ |
5491 |
#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */ |
5491 |
#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */ |
5492 |
#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */ |
5492 |
#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */ |
5493 |
|
5493 |
|
5494 |
/****************** Bit definition for SDIO_MASK register *******************/ |
5494 |
/****************** Bit definition for SDIO_MASK register *******************/ |
5495 |
#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */ |
5495 |
#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */ |
5496 |
#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */ |
5496 |
#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */ |
5497 |
#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */ |
5497 |
#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */ |
5498 |
#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */ |
5498 |
#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */ |
5499 |
#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */ |
5499 |
#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */ |
5500 |
#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */ |
5500 |
#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */ |
5501 |
#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */ |
5501 |
#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */ |
5502 |
#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */ |
5502 |
#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */ |
5503 |
#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */ |
5503 |
#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */ |
5504 |
#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */ |
5504 |
#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */ |
5505 |
#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */ |
5505 |
#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */ |
5506 |
#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */ |
5506 |
#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */ |
5507 |
#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */ |
5507 |
#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */ |
5508 |
#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */ |
5508 |
#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */ |
5509 |
#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */ |
5509 |
#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */ |
5510 |
#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */ |
5510 |
#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */ |
5511 |
#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */ |
5511 |
#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */ |
5512 |
#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */ |
5512 |
#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */ |
5513 |
#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */ |
5513 |
#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */ |
5514 |
#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */ |
5514 |
#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */ |
5515 |
#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */ |
5515 |
#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */ |
5516 |
#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */ |
5516 |
#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */ |
5517 |
#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */ |
5517 |
#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */ |
5518 |
#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */ |
5518 |
#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */ |
5519 |
|
5519 |
|
5520 |
/***************** Bit definition for SDIO_FIFOCNT register *****************/ |
5520 |
/***************** Bit definition for SDIO_FIFOCNT register *****************/ |
5521 |
#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */ |
5521 |
#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */ |
5522 |
|
5522 |
|
5523 |
/****************** Bit definition for SDIO_FIFO register *******************/ |
5523 |
/****************** Bit definition for SDIO_FIFO register *******************/ |
5524 |
#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */ |
5524 |
#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */ |
5525 |
|
5525 |
|
5526 |
/******************************************************************************/ |
5526 |
/******************************************************************************/ |
5527 |
/* */ |
5527 |
/* */ |
5528 |
/* USB Device FS */ |
5528 |
/* USB Device FS */ |
5529 |
/* */ |
5529 |
/* */ |
5530 |
/******************************************************************************/ |
5530 |
/******************************************************************************/ |
5531 |
|
5531 |
|
5532 |
/*!<Endpoint-specific registers */ |
5532 |
/*!<Endpoint-specific registers */ |
5533 |
/******************* Bit definition for USB_EP0R register *******************/ |
5533 |
/******************* Bit definition for USB_EP0R register *******************/ |
5534 |
#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5534 |
#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5535 |
|
5535 |
|
5536 |
#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5536 |
#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5537 |
#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5537 |
#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5538 |
#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5538 |
#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5539 |
|
5539 |
|
5540 |
#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5540 |
#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5541 |
#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5541 |
#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5542 |
#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5542 |
#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5543 |
|
5543 |
|
5544 |
#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5544 |
#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5545 |
#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5545 |
#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5546 |
#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5546 |
#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5547 |
|
5547 |
|
5548 |
#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5548 |
#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5549 |
|
5549 |
|
5550 |
#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5550 |
#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5551 |
#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5551 |
#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5552 |
#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5552 |
#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5553 |
|
5553 |
|
5554 |
#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5554 |
#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5555 |
#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5555 |
#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5556 |
|
5556 |
|
5557 |
/******************* Bit definition for USB_EP1R register *******************/ |
5557 |
/******************* Bit definition for USB_EP1R register *******************/ |
5558 |
#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5558 |
#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5559 |
|
5559 |
|
5560 |
#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5560 |
#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5561 |
#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5561 |
#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5562 |
#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5562 |
#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5563 |
|
5563 |
|
5564 |
#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5564 |
#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5565 |
#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5565 |
#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5566 |
#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5566 |
#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5567 |
|
5567 |
|
5568 |
#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5568 |
#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5569 |
#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5569 |
#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5570 |
#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5570 |
#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5571 |
|
5571 |
|
5572 |
#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5572 |
#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5573 |
|
5573 |
|
5574 |
#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5574 |
#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5575 |
#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5575 |
#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5576 |
#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5576 |
#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5577 |
|
5577 |
|
5578 |
#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5578 |
#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5579 |
#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5579 |
#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5580 |
|
5580 |
|
5581 |
/******************* Bit definition for USB_EP2R register *******************/ |
5581 |
/******************* Bit definition for USB_EP2R register *******************/ |
5582 |
#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5582 |
#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5583 |
|
5583 |
|
5584 |
#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5584 |
#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5585 |
#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5585 |
#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5586 |
#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5586 |
#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5587 |
|
5587 |
|
5588 |
#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5588 |
#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5589 |
#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5589 |
#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5590 |
#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5590 |
#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5591 |
|
5591 |
|
5592 |
#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5592 |
#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5593 |
#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5593 |
#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5594 |
#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5594 |
#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5595 |
|
5595 |
|
5596 |
#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5596 |
#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5597 |
|
5597 |
|
5598 |
#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5598 |
#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5599 |
#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5599 |
#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5600 |
#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5600 |
#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5601 |
|
5601 |
|
5602 |
#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5602 |
#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5603 |
#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5603 |
#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5604 |
|
5604 |
|
5605 |
/******************* Bit definition for USB_EP3R register *******************/ |
5605 |
/******************* Bit definition for USB_EP3R register *******************/ |
5606 |
#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5606 |
#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5607 |
|
5607 |
|
5608 |
#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5608 |
#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5609 |
#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5609 |
#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5610 |
#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5610 |
#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5611 |
|
5611 |
|
5612 |
#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5612 |
#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5613 |
#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5613 |
#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5614 |
#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5614 |
#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5615 |
|
5615 |
|
5616 |
#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5616 |
#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5617 |
#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5617 |
#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5618 |
#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5618 |
#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5619 |
|
5619 |
|
5620 |
#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5620 |
#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5621 |
|
5621 |
|
5622 |
#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5622 |
#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5623 |
#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5623 |
#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5624 |
#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5624 |
#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5625 |
|
5625 |
|
5626 |
#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5626 |
#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5627 |
#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5627 |
#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5628 |
|
5628 |
|
5629 |
/******************* Bit definition for USB_EP4R register *******************/ |
5629 |
/******************* Bit definition for USB_EP4R register *******************/ |
5630 |
#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5630 |
#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5631 |
|
5631 |
|
5632 |
#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5632 |
#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5633 |
#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5633 |
#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5634 |
#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5634 |
#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5635 |
|
5635 |
|
5636 |
#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5636 |
#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5637 |
#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5637 |
#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5638 |
#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5638 |
#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5639 |
|
5639 |
|
5640 |
#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5640 |
#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5641 |
#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5641 |
#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5642 |
#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5642 |
#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5643 |
|
5643 |
|
5644 |
#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5644 |
#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5645 |
|
5645 |
|
5646 |
#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5646 |
#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5647 |
#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5647 |
#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5648 |
#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5648 |
#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5649 |
|
5649 |
|
5650 |
#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5650 |
#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5651 |
#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5651 |
#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5652 |
|
5652 |
|
5653 |
/******************* Bit definition for USB_EP5R register *******************/ |
5653 |
/******************* Bit definition for USB_EP5R register *******************/ |
5654 |
#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5654 |
#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5655 |
|
5655 |
|
5656 |
#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5656 |
#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5657 |
#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5657 |
#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5658 |
#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5658 |
#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5659 |
|
5659 |
|
5660 |
#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5660 |
#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5661 |
#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5661 |
#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5662 |
#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5662 |
#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5663 |
|
5663 |
|
5664 |
#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5664 |
#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5665 |
#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5665 |
#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5666 |
#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5666 |
#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5667 |
|
5667 |
|
5668 |
#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5668 |
#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5669 |
|
5669 |
|
5670 |
#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5670 |
#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5671 |
#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5671 |
#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5672 |
#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5672 |
#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5673 |
|
5673 |
|
5674 |
#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5674 |
#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5675 |
#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5675 |
#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5676 |
|
5676 |
|
5677 |
/******************* Bit definition for USB_EP6R register *******************/ |
5677 |
/******************* Bit definition for USB_EP6R register *******************/ |
5678 |
#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5678 |
#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5679 |
|
5679 |
|
5680 |
#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5680 |
#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5681 |
#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5681 |
#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5682 |
#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5682 |
#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5683 |
|
5683 |
|
5684 |
#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5684 |
#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5685 |
#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5685 |
#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5686 |
#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5686 |
#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5687 |
|
5687 |
|
5688 |
#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5688 |
#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5689 |
#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5689 |
#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5690 |
#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5690 |
#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5691 |
|
5691 |
|
5692 |
#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5692 |
#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5693 |
|
5693 |
|
5694 |
#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5694 |
#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5695 |
#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5695 |
#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5696 |
#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5696 |
#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5697 |
|
5697 |
|
5698 |
#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5698 |
#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5699 |
#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5699 |
#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5700 |
|
5700 |
|
5701 |
/******************* Bit definition for USB_EP7R register *******************/ |
5701 |
/******************* Bit definition for USB_EP7R register *******************/ |
5702 |
#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5702 |
#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */ |
5703 |
|
5703 |
|
5704 |
#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5704 |
#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
5705 |
#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5705 |
#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
5706 |
#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5706 |
#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
5707 |
|
5707 |
|
5708 |
#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5708 |
#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */ |
5709 |
#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5709 |
#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */ |
5710 |
#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5710 |
#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */ |
5711 |
|
5711 |
|
5712 |
#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5712 |
#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
5713 |
#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5713 |
#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */ |
5714 |
#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5714 |
#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */ |
5715 |
|
5715 |
|
5716 |
#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5716 |
#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */ |
5717 |
|
5717 |
|
5718 |
#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5718 |
#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
5719 |
#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5719 |
#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
5720 |
#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5720 |
#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
5721 |
|
5721 |
|
5722 |
#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5722 |
#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */ |
5723 |
#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5723 |
#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */ |
5724 |
|
5724 |
|
5725 |
/*!<Common registers */ |
5725 |
/*!<Common registers */ |
5726 |
/******************* Bit definition for USB_CNTR register *******************/ |
5726 |
/******************* Bit definition for USB_CNTR register *******************/ |
5727 |
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */ |
5727 |
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */ |
5728 |
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */ |
5728 |
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */ |
5729 |
#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */ |
5729 |
#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */ |
5730 |
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */ |
5730 |
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */ |
5731 |
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */ |
5731 |
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */ |
5732 |
#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */ |
5732 |
#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */ |
5733 |
#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */ |
5733 |
#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */ |
5734 |
#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */ |
5734 |
#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */ |
5735 |
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */ |
5735 |
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */ |
5736 |
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */ |
5736 |
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */ |
5737 |
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */ |
5737 |
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */ |
5738 |
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */ |
5738 |
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */ |
5739 |
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */ |
5739 |
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */ |
5740 |
|
5740 |
|
5741 |
/******************* Bit definition for USB_ISTR register *******************/ |
5741 |
/******************* Bit definition for USB_ISTR register *******************/ |
5742 |
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */ |
5742 |
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */ |
5743 |
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */ |
5743 |
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */ |
5744 |
#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */ |
5744 |
#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */ |
5745 |
#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */ |
5745 |
#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */ |
5746 |
#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */ |
5746 |
#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */ |
5747 |
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */ |
5747 |
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */ |
5748 |
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */ |
5748 |
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */ |
5749 |
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */ |
5749 |
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */ |
5750 |
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */ |
5750 |
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */ |
5751 |
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */ |
5751 |
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */ |
5752 |
|
5752 |
|
5753 |
/******************* Bit definition for USB_FNR register ********************/ |
5753 |
/******************* Bit definition for USB_FNR register ********************/ |
5754 |
#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */ |
5754 |
#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */ |
5755 |
#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */ |
5755 |
#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */ |
5756 |
#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */ |
5756 |
#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */ |
5757 |
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */ |
5757 |
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */ |
5758 |
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */ |
5758 |
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */ |
5759 |
|
5759 |
|
5760 |
/****************** Bit definition for USB_DADDR register *******************/ |
5760 |
/****************** Bit definition for USB_DADDR register *******************/ |
5761 |
#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */ |
5761 |
#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */ |
5762 |
#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */ |
5762 |
#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */ |
5763 |
#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */ |
5763 |
#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */ |
5764 |
#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */ |
5764 |
#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */ |
5765 |
#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */ |
5765 |
#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */ |
5766 |
#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */ |
5766 |
#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */ |
5767 |
#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */ |
5767 |
#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */ |
5768 |
#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */ |
5768 |
#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */ |
5769 |
|
5769 |
|
5770 |
#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */ |
5770 |
#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */ |
5771 |
|
5771 |
|
5772 |
/****************** Bit definition for USB_BTABLE register ******************/ |
5772 |
/****************** Bit definition for USB_BTABLE register ******************/ |
5773 |
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */ |
5773 |
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */ |
5774 |
|
5774 |
|
5775 |
/*!<Buffer descriptor table */ |
5775 |
/*!<Buffer descriptor table */ |
5776 |
/***************** Bit definition for USB_ADDR0_TX register *****************/ |
5776 |
/***************** Bit definition for USB_ADDR0_TX register *****************/ |
5777 |
#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */ |
5777 |
#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */ |
5778 |
|
5778 |
|
5779 |
/***************** Bit definition for USB_ADDR1_TX register *****************/ |
5779 |
/***************** Bit definition for USB_ADDR1_TX register *****************/ |
5780 |
#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */ |
5780 |
#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */ |
5781 |
|
5781 |
|
5782 |
/***************** Bit definition for USB_ADDR2_TX register *****************/ |
5782 |
/***************** Bit definition for USB_ADDR2_TX register *****************/ |
5783 |
#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */ |
5783 |
#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */ |
5784 |
|
5784 |
|
5785 |
/***************** Bit definition for USB_ADDR3_TX register *****************/ |
5785 |
/***************** Bit definition for USB_ADDR3_TX register *****************/ |
5786 |
#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */ |
5786 |
#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */ |
5787 |
|
5787 |
|
5788 |
/***************** Bit definition for USB_ADDR4_TX register *****************/ |
5788 |
/***************** Bit definition for USB_ADDR4_TX register *****************/ |
5789 |
#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */ |
5789 |
#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */ |
5790 |
|
5790 |
|
5791 |
/***************** Bit definition for USB_ADDR5_TX register *****************/ |
5791 |
/***************** Bit definition for USB_ADDR5_TX register *****************/ |
5792 |
#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */ |
5792 |
#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */ |
5793 |
|
5793 |
|
5794 |
/***************** Bit definition for USB_ADDR6_TX register *****************/ |
5794 |
/***************** Bit definition for USB_ADDR6_TX register *****************/ |
5795 |
#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */ |
5795 |
#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */ |
5796 |
|
5796 |
|
5797 |
/***************** Bit definition for USB_ADDR7_TX register *****************/ |
5797 |
/***************** Bit definition for USB_ADDR7_TX register *****************/ |
5798 |
#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */ |
5798 |
#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */ |
5799 |
|
5799 |
|
5800 |
/*----------------------------------------------------------------------------*/ |
5800 |
/*----------------------------------------------------------------------------*/ |
5801 |
|
5801 |
|
5802 |
/***************** Bit definition for USB_COUNT0_TX register ****************/ |
5802 |
/***************** Bit definition for USB_COUNT0_TX register ****************/ |
5803 |
#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */ |
5803 |
#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */ |
5804 |
|
5804 |
|
5805 |
/***************** Bit definition for USB_COUNT1_TX register ****************/ |
5805 |
/***************** Bit definition for USB_COUNT1_TX register ****************/ |
5806 |
#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */ |
5806 |
#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */ |
5807 |
|
5807 |
|
5808 |
/***************** Bit definition for USB_COUNT2_TX register ****************/ |
5808 |
/***************** Bit definition for USB_COUNT2_TX register ****************/ |
5809 |
#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */ |
5809 |
#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */ |
5810 |
|
5810 |
|
5811 |
/***************** Bit definition for USB_COUNT3_TX register ****************/ |
5811 |
/***************** Bit definition for USB_COUNT3_TX register ****************/ |
5812 |
#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */ |
5812 |
#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */ |
5813 |
|
5813 |
|
5814 |
/***************** Bit definition for USB_COUNT4_TX register ****************/ |
5814 |
/***************** Bit definition for USB_COUNT4_TX register ****************/ |
5815 |
#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */ |
5815 |
#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */ |
5816 |
|
5816 |
|
5817 |
/***************** Bit definition for USB_COUNT5_TX register ****************/ |
5817 |
/***************** Bit definition for USB_COUNT5_TX register ****************/ |
5818 |
#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */ |
5818 |
#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */ |
5819 |
|
5819 |
|
5820 |
/***************** Bit definition for USB_COUNT6_TX register ****************/ |
5820 |
/***************** Bit definition for USB_COUNT6_TX register ****************/ |
5821 |
#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */ |
5821 |
#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */ |
5822 |
|
5822 |
|
5823 |
/***************** Bit definition for USB_COUNT7_TX register ****************/ |
5823 |
/***************** Bit definition for USB_COUNT7_TX register ****************/ |
5824 |
#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */ |
5824 |
#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */ |
5825 |
|
5825 |
|
5826 |
/*----------------------------------------------------------------------------*/ |
5826 |
/*----------------------------------------------------------------------------*/ |
5827 |
|
5827 |
|
5828 |
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ |
5828 |
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ |
5829 |
#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */ |
5829 |
#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */ |
5830 |
|
5830 |
|
5831 |
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ |
5831 |
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ |
5832 |
#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */ |
5832 |
#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */ |
5833 |
|
5833 |
|
5834 |
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ |
5834 |
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ |
5835 |
#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */ |
5835 |
#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */ |
5836 |
|
5836 |
|
5837 |
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ |
5837 |
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ |
5838 |
#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */ |
5838 |
#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */ |
5839 |
|
5839 |
|
5840 |
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ |
5840 |
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ |
5841 |
#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */ |
5841 |
#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */ |
5842 |
|
5842 |
|
5843 |
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ |
5843 |
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ |
5844 |
#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */ |
5844 |
#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */ |
5845 |
|
5845 |
|
5846 |
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ |
5846 |
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ |
5847 |
#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */ |
5847 |
#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */ |
5848 |
|
5848 |
|
5849 |
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ |
5849 |
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ |
5850 |
#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */ |
5850 |
#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */ |
5851 |
|
5851 |
|
5852 |
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ |
5852 |
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ |
5853 |
#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */ |
5853 |
#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */ |
5854 |
|
5854 |
|
5855 |
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ |
5855 |
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ |
5856 |
#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */ |
5856 |
#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */ |
5857 |
|
5857 |
|
5858 |
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ |
5858 |
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ |
5859 |
#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */ |
5859 |
#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */ |
5860 |
|
5860 |
|
5861 |
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ |
5861 |
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ |
5862 |
#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */ |
5862 |
#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */ |
5863 |
|
5863 |
|
5864 |
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ |
5864 |
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ |
5865 |
#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */ |
5865 |
#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */ |
5866 |
|
5866 |
|
5867 |
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ |
5867 |
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ |
5868 |
#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */ |
5868 |
#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */ |
5869 |
|
5869 |
|
5870 |
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ |
5870 |
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ |
5871 |
#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */ |
5871 |
#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */ |
5872 |
|
5872 |
|
5873 |
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ |
5873 |
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ |
5874 |
#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */ |
5874 |
#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */ |
5875 |
|
5875 |
|
5876 |
/*----------------------------------------------------------------------------*/ |
5876 |
/*----------------------------------------------------------------------------*/ |
5877 |
|
5877 |
|
5878 |
/***************** Bit definition for USB_ADDR0_RX register *****************/ |
5878 |
/***************** Bit definition for USB_ADDR0_RX register *****************/ |
5879 |
#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */ |
5879 |
#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */ |
5880 |
|
5880 |
|
5881 |
/***************** Bit definition for USB_ADDR1_RX register *****************/ |
5881 |
/***************** Bit definition for USB_ADDR1_RX register *****************/ |
5882 |
#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */ |
5882 |
#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */ |
5883 |
|
5883 |
|
5884 |
/***************** Bit definition for USB_ADDR2_RX register *****************/ |
5884 |
/***************** Bit definition for USB_ADDR2_RX register *****************/ |
5885 |
#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */ |
5885 |
#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */ |
5886 |
|
5886 |
|
5887 |
/***************** Bit definition for USB_ADDR3_RX register *****************/ |
5887 |
/***************** Bit definition for USB_ADDR3_RX register *****************/ |
5888 |
#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */ |
5888 |
#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */ |
5889 |
|
5889 |
|
5890 |
/***************** Bit definition for USB_ADDR4_RX register *****************/ |
5890 |
/***************** Bit definition for USB_ADDR4_RX register *****************/ |
5891 |
#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */ |
5891 |
#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */ |
5892 |
|
5892 |
|
5893 |
/***************** Bit definition for USB_ADDR5_RX register *****************/ |
5893 |
/***************** Bit definition for USB_ADDR5_RX register *****************/ |
5894 |
#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */ |
5894 |
#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */ |
5895 |
|
5895 |
|
5896 |
/***************** Bit definition for USB_ADDR6_RX register *****************/ |
5896 |
/***************** Bit definition for USB_ADDR6_RX register *****************/ |
5897 |
#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */ |
5897 |
#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */ |
5898 |
|
5898 |
|
5899 |
/***************** Bit definition for USB_ADDR7_RX register *****************/ |
5899 |
/***************** Bit definition for USB_ADDR7_RX register *****************/ |
5900 |
#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */ |
5900 |
#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */ |
5901 |
|
5901 |
|
5902 |
/*----------------------------------------------------------------------------*/ |
5902 |
/*----------------------------------------------------------------------------*/ |
5903 |
|
5903 |
|
5904 |
/***************** Bit definition for USB_COUNT0_RX register ****************/ |
5904 |
/***************** Bit definition for USB_COUNT0_RX register ****************/ |
5905 |
#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5905 |
#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5906 |
|
5906 |
|
5907 |
#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5907 |
#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5908 |
#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5908 |
#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5909 |
#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5909 |
#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5910 |
#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5910 |
#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5911 |
#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5911 |
#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5912 |
#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5912 |
#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5913 |
|
5913 |
|
5914 |
#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5914 |
#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5915 |
|
5915 |
|
5916 |
/***************** Bit definition for USB_COUNT1_RX register ****************/ |
5916 |
/***************** Bit definition for USB_COUNT1_RX register ****************/ |
5917 |
#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5917 |
#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5918 |
|
5918 |
|
5919 |
#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5919 |
#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5920 |
#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5920 |
#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5921 |
#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5921 |
#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5922 |
#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5922 |
#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5923 |
#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5923 |
#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5924 |
#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5924 |
#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5925 |
|
5925 |
|
5926 |
#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5926 |
#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5927 |
|
5927 |
|
5928 |
/***************** Bit definition for USB_COUNT2_RX register ****************/ |
5928 |
/***************** Bit definition for USB_COUNT2_RX register ****************/ |
5929 |
#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5929 |
#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5930 |
|
5930 |
|
5931 |
#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5931 |
#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5932 |
#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5932 |
#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5933 |
#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5933 |
#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5934 |
#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5934 |
#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5935 |
#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5935 |
#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5936 |
#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5936 |
#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5937 |
|
5937 |
|
5938 |
#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5938 |
#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5939 |
|
5939 |
|
5940 |
/***************** Bit definition for USB_COUNT3_RX register ****************/ |
5940 |
/***************** Bit definition for USB_COUNT3_RX register ****************/ |
5941 |
#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5941 |
#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5942 |
|
5942 |
|
5943 |
#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5943 |
#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5944 |
#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5944 |
#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5945 |
#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5945 |
#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5946 |
#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5946 |
#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5947 |
#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5947 |
#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5948 |
#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5948 |
#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5949 |
|
5949 |
|
5950 |
#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5950 |
#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5951 |
|
5951 |
|
5952 |
/***************** Bit definition for USB_COUNT4_RX register ****************/ |
5952 |
/***************** Bit definition for USB_COUNT4_RX register ****************/ |
5953 |
#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5953 |
#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5954 |
|
5954 |
|
5955 |
#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5955 |
#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5956 |
#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5956 |
#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5957 |
#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5957 |
#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5958 |
#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5958 |
#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5959 |
#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5959 |
#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5960 |
#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5960 |
#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5961 |
|
5961 |
|
5962 |
#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5962 |
#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5963 |
|
5963 |
|
5964 |
/***************** Bit definition for USB_COUNT5_RX register ****************/ |
5964 |
/***************** Bit definition for USB_COUNT5_RX register ****************/ |
5965 |
#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5965 |
#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5966 |
|
5966 |
|
5967 |
#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5967 |
#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5968 |
#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5968 |
#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5969 |
#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5969 |
#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5970 |
#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5970 |
#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5971 |
#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5971 |
#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5972 |
#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5972 |
#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5973 |
|
5973 |
|
5974 |
#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5974 |
#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5975 |
|
5975 |
|
5976 |
/***************** Bit definition for USB_COUNT6_RX register ****************/ |
5976 |
/***************** Bit definition for USB_COUNT6_RX register ****************/ |
5977 |
#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5977 |
#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5978 |
|
5978 |
|
5979 |
#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5979 |
#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5980 |
#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5980 |
#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5981 |
#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5981 |
#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5982 |
#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5982 |
#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5983 |
#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5983 |
#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5984 |
#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5984 |
#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5985 |
|
5985 |
|
5986 |
#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5986 |
#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5987 |
|
5987 |
|
5988 |
/***************** Bit definition for USB_COUNT7_RX register ****************/ |
5988 |
/***************** Bit definition for USB_COUNT7_RX register ****************/ |
5989 |
#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5989 |
#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */ |
5990 |
|
5990 |
|
5991 |
#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5991 |
#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */ |
5992 |
#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5992 |
#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */ |
5993 |
#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5993 |
#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */ |
5994 |
#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5994 |
#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */ |
5995 |
#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5995 |
#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */ |
5996 |
#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5996 |
#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */ |
5997 |
|
5997 |
|
5998 |
#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5998 |
#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */ |
5999 |
|
5999 |
|
6000 |
/*----------------------------------------------------------------------------*/ |
6000 |
/*----------------------------------------------------------------------------*/ |
6001 |
|
6001 |
|
6002 |
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ |
6002 |
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ |
6003 |
#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6003 |
#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6004 |
|
6004 |
|
6005 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6005 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6006 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6006 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6007 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6007 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6008 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6008 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6009 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6009 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6010 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6010 |
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6011 |
|
6011 |
|
6012 |
#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6012 |
#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6013 |
|
6013 |
|
6014 |
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ |
6014 |
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ |
6015 |
#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6015 |
#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6016 |
|
6016 |
|
6017 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6017 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6018 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */ |
6018 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */ |
6019 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6019 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6020 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6020 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6021 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6021 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6022 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6022 |
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6023 |
|
6023 |
|
6024 |
#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6024 |
#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6025 |
|
6025 |
|
6026 |
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ |
6026 |
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ |
6027 |
#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6027 |
#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6028 |
|
6028 |
|
6029 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6029 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6030 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6030 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6031 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6031 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6032 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6032 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6033 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6033 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6034 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6034 |
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6035 |
|
6035 |
|
6036 |
#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6036 |
#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6037 |
|
6037 |
|
6038 |
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ |
6038 |
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ |
6039 |
#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6039 |
#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6040 |
|
6040 |
|
6041 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6041 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6042 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6042 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6043 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6043 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6044 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6044 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6045 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6045 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6046 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6046 |
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6047 |
|
6047 |
|
6048 |
#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6048 |
#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6049 |
|
6049 |
|
6050 |
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ |
6050 |
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ |
6051 |
#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6051 |
#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6052 |
|
6052 |
|
6053 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6053 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6054 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6054 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6055 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6055 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6056 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6056 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6057 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6057 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6058 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6058 |
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6059 |
|
6059 |
|
6060 |
#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6060 |
#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6061 |
|
6061 |
|
6062 |
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ |
6062 |
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ |
6063 |
#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6063 |
#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6064 |
|
6064 |
|
6065 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6065 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6066 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6066 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6067 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6067 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6068 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6068 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6069 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6069 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6070 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6070 |
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6071 |
|
6071 |
|
6072 |
#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6072 |
#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6073 |
|
6073 |
|
6074 |
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ |
6074 |
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ |
6075 |
#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6075 |
#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6076 |
|
6076 |
|
6077 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6077 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6078 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6078 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6079 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6079 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6080 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6080 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6081 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6081 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6082 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6082 |
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6083 |
|
6083 |
|
6084 |
#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6084 |
#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6085 |
|
6085 |
|
6086 |
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ |
6086 |
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ |
6087 |
#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6087 |
#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6088 |
|
6088 |
|
6089 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6089 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6090 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6090 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6091 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6091 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6092 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6092 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6093 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6093 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6094 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6094 |
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6095 |
|
6095 |
|
6096 |
#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6096 |
#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6097 |
|
6097 |
|
6098 |
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ |
6098 |
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ |
6099 |
#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6099 |
#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6100 |
|
6100 |
|
6101 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6101 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6102 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6102 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6103 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6103 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6104 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6104 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6105 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6105 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6106 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6106 |
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6107 |
|
6107 |
|
6108 |
#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6108 |
#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6109 |
|
6109 |
|
6110 |
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ |
6110 |
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ |
6111 |
#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6111 |
#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6112 |
|
6112 |
|
6113 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6113 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6114 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6114 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6115 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6115 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6116 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6116 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6117 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6117 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6118 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6118 |
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6119 |
|
6119 |
|
6120 |
#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6120 |
#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6121 |
|
6121 |
|
6122 |
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ |
6122 |
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ |
6123 |
#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6123 |
#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6124 |
|
6124 |
|
6125 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6125 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6126 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6126 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6127 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6127 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6128 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6128 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6129 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6129 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6130 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6130 |
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6131 |
|
6131 |
|
6132 |
#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6132 |
#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6133 |
|
6133 |
|
6134 |
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ |
6134 |
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ |
6135 |
#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6135 |
#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6136 |
|
6136 |
|
6137 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6137 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6138 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6138 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6139 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6139 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6140 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6140 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6141 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6141 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6142 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6142 |
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6143 |
|
6143 |
|
6144 |
#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6144 |
#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6145 |
|
6145 |
|
6146 |
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ |
6146 |
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ |
6147 |
#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6147 |
#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6148 |
|
6148 |
|
6149 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6149 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6150 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6150 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6151 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6151 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6152 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6152 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6153 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6153 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6154 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6154 |
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6155 |
|
6155 |
|
6156 |
#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6156 |
#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6157 |
|
6157 |
|
6158 |
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ |
6158 |
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ |
6159 |
#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6159 |
#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6160 |
|
6160 |
|
6161 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6161 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6162 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6162 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6163 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6163 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6164 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6164 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6165 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6165 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6166 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6166 |
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6167 |
|
6167 |
|
6168 |
#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6168 |
#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6169 |
|
6169 |
|
6170 |
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ |
6170 |
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ |
6171 |
#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6171 |
#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */ |
6172 |
|
6172 |
|
6173 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6173 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
6174 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6174 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
6175 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6175 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
6176 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6176 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
6177 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6177 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
6178 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6178 |
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */ |
6179 |
|
6179 |
|
6180 |
#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6180 |
#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */ |
6181 |
|
6181 |
|
6182 |
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ |
6182 |
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ |
6183 |
#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6183 |
#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */ |
6184 |
|
6184 |
|
6185 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6185 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
6186 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6186 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */ |
6187 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6187 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */ |
6188 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6188 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */ |
6189 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6189 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */ |
6190 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6190 |
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */ |
6191 |
|
6191 |
|
6192 |
#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6192 |
#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */ |
6193 |
|
6193 |
|
6194 |
/******************************************************************************/ |
6194 |
/******************************************************************************/ |
6195 |
/* */ |
6195 |
/* */ |
6196 |
/* Controller Area Network */ |
6196 |
/* Controller Area Network */ |
6197 |
/* */ |
6197 |
/* */ |
6198 |
/******************************************************************************/ |
6198 |
/******************************************************************************/ |
6199 |
|
6199 |
|
6200 |
/*!<CAN control and status registers */ |
6200 |
/*!<CAN control and status registers */ |
6201 |
/******************* Bit definition for CAN_MCR register ********************/ |
6201 |
/******************* Bit definition for CAN_MCR register ********************/ |
6202 |
#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */ |
6202 |
#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */ |
6203 |
#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */ |
6203 |
#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */ |
6204 |
#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */ |
6204 |
#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */ |
6205 |
#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */ |
6205 |
#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */ |
6206 |
#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */ |
6206 |
#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */ |
6207 |
#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */ |
6207 |
#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */ |
6208 |
#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */ |
6208 |
#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */ |
6209 |
#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */ |
6209 |
#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */ |
6210 |
#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */ |
6210 |
#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */ |
6211 |
|
6211 |
|
6212 |
/******************* Bit definition for CAN_MSR register ********************/ |
6212 |
/******************* Bit definition for CAN_MSR register ********************/ |
6213 |
#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */ |
6213 |
#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */ |
6214 |
#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */ |
6214 |
#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */ |
6215 |
#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */ |
6215 |
#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */ |
6216 |
#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */ |
6216 |
#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */ |
6217 |
#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */ |
6217 |
#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */ |
6218 |
#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */ |
6218 |
#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */ |
6219 |
#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */ |
6219 |
#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */ |
6220 |
#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */ |
6220 |
#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */ |
6221 |
#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */ |
6221 |
#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */ |
6222 |
|
6222 |
|
6223 |
/******************* Bit definition for CAN_TSR register ********************/ |
6223 |
/******************* Bit definition for CAN_TSR register ********************/ |
6224 |
#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ |
6224 |
#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ |
6225 |
#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ |
6225 |
#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ |
6226 |
#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ |
6226 |
#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ |
6227 |
#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ |
6227 |
#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ |
6228 |
#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ |
6228 |
#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ |
6229 |
#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ |
6229 |
#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ |
6230 |
#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ |
6230 |
#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ |
6231 |
#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ |
6231 |
#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ |
6232 |
#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ |
6232 |
#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ |
6233 |
#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ |
6233 |
#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ |
6234 |
#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ |
6234 |
#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ |
6235 |
#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ |
6235 |
#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ |
6236 |
#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ |
6236 |
#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ |
6237 |
#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ |
6237 |
#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ |
6238 |
#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ |
6238 |
#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ |
6239 |
#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ |
6239 |
#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ |
6240 |
|
6240 |
|
6241 |
#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ |
6241 |
#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ |
6242 |
#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ |
6242 |
#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ |
6243 |
#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ |
6243 |
#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ |
6244 |
#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ |
6244 |
#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ |
6245 |
|
6245 |
|
6246 |
#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ |
6246 |
#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ |
6247 |
#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ |
6247 |
#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ |
6248 |
#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ |
6248 |
#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ |
6249 |
#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ |
6249 |
#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ |
6250 |
|
6250 |
|
6251 |
/******************* Bit definition for CAN_RF0R register *******************/ |
6251 |
/******************* Bit definition for CAN_RF0R register *******************/ |
6252 |
#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */ |
6252 |
#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */ |
6253 |
#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */ |
6253 |
#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */ |
6254 |
#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */ |
6254 |
#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */ |
6255 |
#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */ |
6255 |
#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */ |
6256 |
|
6256 |
|
6257 |
/******************* Bit definition for CAN_RF1R register *******************/ |
6257 |
/******************* Bit definition for CAN_RF1R register *******************/ |
6258 |
#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */ |
6258 |
#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */ |
6259 |
#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */ |
6259 |
#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */ |
6260 |
#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */ |
6260 |
#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */ |
6261 |
#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */ |
6261 |
#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */ |
6262 |
|
6262 |
|
6263 |
/******************** Bit definition for CAN_IER register *******************/ |
6263 |
/******************** Bit definition for CAN_IER register *******************/ |
6264 |
#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ |
6264 |
#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ |
6265 |
#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ |
6265 |
#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ |
6266 |
#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ |
6266 |
#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ |
6267 |
#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ |
6267 |
#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ |
6268 |
#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ |
6268 |
#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ |
6269 |
#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ |
6269 |
#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ |
6270 |
#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ |
6270 |
#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ |
6271 |
#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ |
6271 |
#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ |
6272 |
#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ |
6272 |
#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ |
6273 |
#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ |
6273 |
#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ |
6274 |
#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ |
6274 |
#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ |
6275 |
#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ |
6275 |
#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ |
6276 |
#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ |
6276 |
#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ |
6277 |
#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ |
6277 |
#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ |
6278 |
|
6278 |
|
6279 |
/******************** Bit definition for CAN_ESR register *******************/ |
6279 |
/******************** Bit definition for CAN_ESR register *******************/ |
6280 |
#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ |
6280 |
#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ |
6281 |
#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ |
6281 |
#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ |
6282 |
#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ |
6282 |
#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ |
6283 |
|
6283 |
|
6284 |
#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ |
6284 |
#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ |
6285 |
#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
6285 |
#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
6286 |
#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
6286 |
#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
6287 |
#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
6287 |
#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
6288 |
|
6288 |
|
6289 |
#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
6289 |
#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
6290 |
#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ |
6290 |
#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ |
6291 |
|
6291 |
|
6292 |
/******************* Bit definition for CAN_BTR register ********************/ |
6292 |
/******************* Bit definition for CAN_BTR register ********************/ |
6293 |
#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ |
6293 |
#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ |
6294 |
#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ |
6294 |
#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ |
6295 |
#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ |
6295 |
#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ |
6296 |
#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ |
6296 |
#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ |
6297 |
#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ |
6297 |
#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ |
6298 |
#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ |
6298 |
#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ |
6299 |
|
6299 |
|
6300 |
/*!<Mailbox registers */ |
6300 |
/*!<Mailbox registers */ |
6301 |
/****************** Bit definition for CAN_TI0R register ********************/ |
6301 |
/****************** Bit definition for CAN_TI0R register ********************/ |
6302 |
#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
6302 |
#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
6303 |
#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6303 |
#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6304 |
#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6304 |
#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6305 |
#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
6305 |
#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
6306 |
#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6306 |
#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6307 |
|
6307 |
|
6308 |
/****************** Bit definition for CAN_TDT0R register *******************/ |
6308 |
/****************** Bit definition for CAN_TDT0R register *******************/ |
6309 |
#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6309 |
#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6310 |
#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
6310 |
#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
6311 |
#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6311 |
#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6312 |
|
6312 |
|
6313 |
/****************** Bit definition for CAN_TDL0R register *******************/ |
6313 |
/****************** Bit definition for CAN_TDL0R register *******************/ |
6314 |
#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6314 |
#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6315 |
#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6315 |
#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6316 |
#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6316 |
#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6317 |
#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6317 |
#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6318 |
|
6318 |
|
6319 |
/****************** Bit definition for CAN_TDH0R register *******************/ |
6319 |
/****************** Bit definition for CAN_TDH0R register *******************/ |
6320 |
#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6320 |
#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6321 |
#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6321 |
#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6322 |
#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6322 |
#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6323 |
#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6323 |
#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6324 |
|
6324 |
|
6325 |
/******************* Bit definition for CAN_TI1R register *******************/ |
6325 |
/******************* Bit definition for CAN_TI1R register *******************/ |
6326 |
#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
6326 |
#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
6327 |
#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6327 |
#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6328 |
#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6328 |
#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6329 |
#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
6329 |
#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
6330 |
#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6330 |
#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6331 |
|
6331 |
|
6332 |
/******************* Bit definition for CAN_TDT1R register ******************/ |
6332 |
/******************* Bit definition for CAN_TDT1R register ******************/ |
6333 |
#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6333 |
#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6334 |
#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
6334 |
#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
6335 |
#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6335 |
#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6336 |
|
6336 |
|
6337 |
/******************* Bit definition for CAN_TDL1R register ******************/ |
6337 |
/******************* Bit definition for CAN_TDL1R register ******************/ |
6338 |
#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6338 |
#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6339 |
#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6339 |
#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6340 |
#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6340 |
#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6341 |
#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6341 |
#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6342 |
|
6342 |
|
6343 |
/******************* Bit definition for CAN_TDH1R register ******************/ |
6343 |
/******************* Bit definition for CAN_TDH1R register ******************/ |
6344 |
#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6344 |
#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6345 |
#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6345 |
#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6346 |
#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6346 |
#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6347 |
#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6347 |
#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6348 |
|
6348 |
|
6349 |
/******************* Bit definition for CAN_TI2R register *******************/ |
6349 |
/******************* Bit definition for CAN_TI2R register *******************/ |
6350 |
#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
6350 |
#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
6351 |
#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6351 |
#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6352 |
#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6352 |
#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6353 |
#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
6353 |
#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
6354 |
#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6354 |
#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6355 |
|
6355 |
|
6356 |
/******************* Bit definition for CAN_TDT2R register ******************/ |
6356 |
/******************* Bit definition for CAN_TDT2R register ******************/ |
6357 |
#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6357 |
#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6358 |
#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
6358 |
#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
6359 |
#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6359 |
#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6360 |
|
6360 |
|
6361 |
/******************* Bit definition for CAN_TDL2R register ******************/ |
6361 |
/******************* Bit definition for CAN_TDL2R register ******************/ |
6362 |
#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6362 |
#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6363 |
#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6363 |
#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6364 |
#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6364 |
#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6365 |
#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6365 |
#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6366 |
|
6366 |
|
6367 |
/******************* Bit definition for CAN_TDH2R register ******************/ |
6367 |
/******************* Bit definition for CAN_TDH2R register ******************/ |
6368 |
#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6368 |
#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6369 |
#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6369 |
#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6370 |
#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6370 |
#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6371 |
#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6371 |
#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6372 |
|
6372 |
|
6373 |
/******************* Bit definition for CAN_RI0R register *******************/ |
6373 |
/******************* Bit definition for CAN_RI0R register *******************/ |
6374 |
#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6374 |
#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6375 |
#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6375 |
#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6376 |
#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
6376 |
#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
6377 |
#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6377 |
#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6378 |
|
6378 |
|
6379 |
/******************* Bit definition for CAN_RDT0R register ******************/ |
6379 |
/******************* Bit definition for CAN_RDT0R register ******************/ |
6380 |
#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6380 |
#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6381 |
#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
6381 |
#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
6382 |
#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6382 |
#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6383 |
|
6383 |
|
6384 |
/******************* Bit definition for CAN_RDL0R register ******************/ |
6384 |
/******************* Bit definition for CAN_RDL0R register ******************/ |
6385 |
#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6385 |
#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6386 |
#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6386 |
#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6387 |
#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6387 |
#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6388 |
#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6388 |
#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6389 |
|
6389 |
|
6390 |
/******************* Bit definition for CAN_RDH0R register ******************/ |
6390 |
/******************* Bit definition for CAN_RDH0R register ******************/ |
6391 |
#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6391 |
#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6392 |
#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6392 |
#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6393 |
#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6393 |
#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6394 |
#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6394 |
#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6395 |
|
6395 |
|
6396 |
/******************* Bit definition for CAN_RI1R register *******************/ |
6396 |
/******************* Bit definition for CAN_RI1R register *******************/ |
6397 |
#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6397 |
#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
6398 |
#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6398 |
#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
6399 |
#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
6399 |
#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
6400 |
#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6400 |
#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
6401 |
|
6401 |
|
6402 |
/******************* Bit definition for CAN_RDT1R register ******************/ |
6402 |
/******************* Bit definition for CAN_RDT1R register ******************/ |
6403 |
#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6403 |
#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
6404 |
#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
6404 |
#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
6405 |
#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6405 |
#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
6406 |
|
6406 |
|
6407 |
/******************* Bit definition for CAN_RDL1R register ******************/ |
6407 |
/******************* Bit definition for CAN_RDL1R register ******************/ |
6408 |
#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6408 |
#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
6409 |
#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6409 |
#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
6410 |
#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6410 |
#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
6411 |
#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6411 |
#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
6412 |
|
6412 |
|
6413 |
/******************* Bit definition for CAN_RDH1R register ******************/ |
6413 |
/******************* Bit definition for CAN_RDH1R register ******************/ |
6414 |
#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6414 |
#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
6415 |
#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6415 |
#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
6416 |
#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6416 |
#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
6417 |
#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6417 |
#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
6418 |
|
6418 |
|
6419 |
/*!<CAN filter registers */ |
6419 |
/*!<CAN filter registers */ |
6420 |
/******************* Bit definition for CAN_FMR register ********************/ |
6420 |
/******************* Bit definition for CAN_FMR register ********************/ |
6421 |
#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */ |
6421 |
#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */ |
6422 |
|
6422 |
|
6423 |
/******************* Bit definition for CAN_FM1R register *******************/ |
6423 |
/******************* Bit definition for CAN_FM1R register *******************/ |
6424 |
#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */ |
6424 |
#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */ |
6425 |
#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */ |
6425 |
#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */ |
6426 |
#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */ |
6426 |
#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */ |
6427 |
#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */ |
6427 |
#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */ |
6428 |
#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */ |
6428 |
#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */ |
6429 |
#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */ |
6429 |
#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */ |
6430 |
#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */ |
6430 |
#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */ |
6431 |
#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */ |
6431 |
#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */ |
6432 |
#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */ |
6432 |
#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */ |
6433 |
#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */ |
6433 |
#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */ |
6434 |
#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */ |
6434 |
#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */ |
6435 |
#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */ |
6435 |
#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */ |
6436 |
#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */ |
6436 |
#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */ |
6437 |
#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */ |
6437 |
#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */ |
6438 |
#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */ |
6438 |
#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */ |
6439 |
|
6439 |
|
6440 |
/******************* Bit definition for CAN_FS1R register *******************/ |
6440 |
/******************* Bit definition for CAN_FS1R register *******************/ |
6441 |
#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */ |
6441 |
#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */ |
6442 |
#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */ |
6442 |
#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */ |
6443 |
#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */ |
6443 |
#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */ |
6444 |
#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */ |
6444 |
#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */ |
6445 |
#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */ |
6445 |
#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */ |
6446 |
#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */ |
6446 |
#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */ |
6447 |
#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */ |
6447 |
#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */ |
6448 |
#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */ |
6448 |
#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */ |
6449 |
#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */ |
6449 |
#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */ |
6450 |
#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */ |
6450 |
#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */ |
6451 |
#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */ |
6451 |
#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */ |
6452 |
#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */ |
6452 |
#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */ |
6453 |
#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */ |
6453 |
#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */ |
6454 |
#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */ |
6454 |
#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */ |
6455 |
#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */ |
6455 |
#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */ |
6456 |
|
6456 |
|
6457 |
/****************** Bit definition for CAN_FFA1R register *******************/ |
6457 |
/****************** Bit definition for CAN_FFA1R register *******************/ |
6458 |
#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */ |
6458 |
#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */ |
6459 |
#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ |
6459 |
#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ |
6460 |
#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ |
6460 |
#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ |
6461 |
#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ |
6461 |
#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ |
6462 |
#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ |
6462 |
#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ |
6463 |
#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ |
6463 |
#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ |
6464 |
#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ |
6464 |
#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ |
6465 |
#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ |
6465 |
#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ |
6466 |
#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ |
6466 |
#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ |
6467 |
#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ |
6467 |
#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ |
6468 |
#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ |
6468 |
#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ |
6469 |
#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ |
6469 |
#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ |
6470 |
#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ |
6470 |
#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ |
6471 |
#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ |
6471 |
#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ |
6472 |
#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ |
6472 |
#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ |
6473 |
|
6473 |
|
6474 |
/******************* Bit definition for CAN_FA1R register *******************/ |
6474 |
/******************* Bit definition for CAN_FA1R register *******************/ |
6475 |
#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */ |
6475 |
#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */ |
6476 |
#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */ |
6476 |
#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */ |
6477 |
#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */ |
6477 |
#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */ |
6478 |
#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */ |
6478 |
#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */ |
6479 |
#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */ |
6479 |
#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */ |
6480 |
#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */ |
6480 |
#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */ |
6481 |
#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */ |
6481 |
#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */ |
6482 |
#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */ |
6482 |
#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */ |
6483 |
#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */ |
6483 |
#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */ |
6484 |
#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */ |
6484 |
#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */ |
6485 |
#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */ |
6485 |
#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */ |
6486 |
#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */ |
6486 |
#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */ |
6487 |
#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */ |
6487 |
#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */ |
6488 |
#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */ |
6488 |
#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */ |
6489 |
#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */ |
6489 |
#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */ |
6490 |
|
6490 |
|
6491 |
/******************* Bit definition for CAN_F0R1 register *******************/ |
6491 |
/******************* Bit definition for CAN_F0R1 register *******************/ |
6492 |
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6492 |
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6493 |
#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6493 |
#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6494 |
#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6494 |
#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6495 |
#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6495 |
#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6496 |
#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6496 |
#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6497 |
#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6497 |
#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6498 |
#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6498 |
#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6499 |
#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6499 |
#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6500 |
#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6500 |
#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6501 |
#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6501 |
#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6502 |
#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6502 |
#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6503 |
#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6503 |
#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6504 |
#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6504 |
#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6505 |
#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6505 |
#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6506 |
#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6506 |
#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6507 |
#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6507 |
#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6508 |
#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6508 |
#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6509 |
#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6509 |
#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6510 |
#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6510 |
#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6511 |
#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6511 |
#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6512 |
#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6512 |
#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6513 |
#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6513 |
#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6514 |
#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6514 |
#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6515 |
#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6515 |
#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6516 |
#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6516 |
#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6517 |
#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6517 |
#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6518 |
#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6518 |
#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6519 |
#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6519 |
#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6520 |
#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6520 |
#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6521 |
#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6521 |
#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6522 |
#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6522 |
#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6523 |
#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6523 |
#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6524 |
|
6524 |
|
6525 |
/******************* Bit definition for CAN_F1R1 register *******************/ |
6525 |
/******************* Bit definition for CAN_F1R1 register *******************/ |
6526 |
#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6526 |
#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6527 |
#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6527 |
#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6528 |
#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6528 |
#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6529 |
#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6529 |
#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6530 |
#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6530 |
#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6531 |
#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6531 |
#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6532 |
#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6532 |
#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6533 |
#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6533 |
#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6534 |
#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6534 |
#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6535 |
#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6535 |
#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6536 |
#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6536 |
#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6537 |
#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6537 |
#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6538 |
#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6538 |
#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6539 |
#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6539 |
#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6540 |
#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6540 |
#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6541 |
#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6541 |
#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6542 |
#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6542 |
#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6543 |
#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6543 |
#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6544 |
#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6544 |
#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6545 |
#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6545 |
#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6546 |
#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6546 |
#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6547 |
#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6547 |
#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6548 |
#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6548 |
#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6549 |
#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6549 |
#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6550 |
#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6550 |
#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6551 |
#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6551 |
#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6552 |
#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6552 |
#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6553 |
#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6553 |
#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6554 |
#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6554 |
#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6555 |
#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6555 |
#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6556 |
#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6556 |
#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6557 |
#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6557 |
#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6558 |
|
6558 |
|
6559 |
/******************* Bit definition for CAN_F2R1 register *******************/ |
6559 |
/******************* Bit definition for CAN_F2R1 register *******************/ |
6560 |
#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6560 |
#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6561 |
#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6561 |
#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6562 |
#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6562 |
#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6563 |
#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6563 |
#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6564 |
#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6564 |
#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6565 |
#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6565 |
#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6566 |
#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6566 |
#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6567 |
#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6567 |
#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6568 |
#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6568 |
#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6569 |
#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6569 |
#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6570 |
#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6570 |
#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6571 |
#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6571 |
#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6572 |
#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6572 |
#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6573 |
#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6573 |
#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6574 |
#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6574 |
#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6575 |
#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6575 |
#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6576 |
#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6576 |
#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6577 |
#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6577 |
#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6578 |
#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6578 |
#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6579 |
#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6579 |
#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6580 |
#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6580 |
#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6581 |
#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6581 |
#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6582 |
#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6582 |
#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6583 |
#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6583 |
#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6584 |
#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6584 |
#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6585 |
#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6585 |
#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6586 |
#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6586 |
#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6587 |
#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6587 |
#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6588 |
#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6588 |
#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6589 |
#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6589 |
#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6590 |
#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6590 |
#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6591 |
#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6591 |
#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6592 |
|
6592 |
|
6593 |
/******************* Bit definition for CAN_F3R1 register *******************/ |
6593 |
/******************* Bit definition for CAN_F3R1 register *******************/ |
6594 |
#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6594 |
#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6595 |
#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6595 |
#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6596 |
#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6596 |
#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6597 |
#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6597 |
#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6598 |
#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6598 |
#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6599 |
#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6599 |
#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6600 |
#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6600 |
#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6601 |
#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6601 |
#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6602 |
#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6602 |
#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6603 |
#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6603 |
#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6604 |
#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6604 |
#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6605 |
#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6605 |
#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6606 |
#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6606 |
#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6607 |
#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6607 |
#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6608 |
#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6608 |
#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6609 |
#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6609 |
#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6610 |
#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6610 |
#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6611 |
#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6611 |
#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6612 |
#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6612 |
#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6613 |
#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6613 |
#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6614 |
#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6614 |
#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6615 |
#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6615 |
#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6616 |
#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6616 |
#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6617 |
#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6617 |
#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6618 |
#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6618 |
#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6619 |
#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6619 |
#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6620 |
#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6620 |
#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6621 |
#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6621 |
#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6622 |
#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6622 |
#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6623 |
#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6623 |
#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6624 |
#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6624 |
#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6625 |
#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6625 |
#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6626 |
|
6626 |
|
6627 |
/******************* Bit definition for CAN_F4R1 register *******************/ |
6627 |
/******************* Bit definition for CAN_F4R1 register *******************/ |
6628 |
#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6628 |
#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6629 |
#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6629 |
#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6630 |
#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6630 |
#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6631 |
#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6631 |
#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6632 |
#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6632 |
#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6633 |
#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6633 |
#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6634 |
#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6634 |
#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6635 |
#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6635 |
#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6636 |
#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6636 |
#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6637 |
#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6637 |
#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6638 |
#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6638 |
#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6639 |
#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6639 |
#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6640 |
#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6640 |
#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6641 |
#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6641 |
#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6642 |
#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6642 |
#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6643 |
#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6643 |
#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6644 |
#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6644 |
#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6645 |
#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6645 |
#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6646 |
#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6646 |
#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6647 |
#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6647 |
#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6648 |
#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6648 |
#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6649 |
#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6649 |
#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6650 |
#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6650 |
#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6651 |
#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6651 |
#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6652 |
#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6652 |
#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6653 |
#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6653 |
#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6654 |
#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6654 |
#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6655 |
#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6655 |
#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6656 |
#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6656 |
#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6657 |
#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6657 |
#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6658 |
#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6658 |
#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6659 |
#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6659 |
#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6660 |
|
6660 |
|
6661 |
/******************* Bit definition for CAN_F5R1 register *******************/ |
6661 |
/******************* Bit definition for CAN_F5R1 register *******************/ |
6662 |
#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6662 |
#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6663 |
#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6663 |
#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6664 |
#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6664 |
#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6665 |
#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6665 |
#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6666 |
#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6666 |
#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6667 |
#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6667 |
#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6668 |
#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6668 |
#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6669 |
#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6669 |
#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6670 |
#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6670 |
#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6671 |
#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6671 |
#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6672 |
#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6672 |
#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6673 |
#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6673 |
#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6674 |
#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6674 |
#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6675 |
#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6675 |
#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6676 |
#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6676 |
#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6677 |
#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6677 |
#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6678 |
#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6678 |
#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6679 |
#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6679 |
#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6680 |
#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6680 |
#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6681 |
#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6681 |
#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6682 |
#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6682 |
#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6683 |
#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6683 |
#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6684 |
#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6684 |
#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6685 |
#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6685 |
#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6686 |
#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6686 |
#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6687 |
#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6687 |
#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6688 |
#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6688 |
#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6689 |
#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6689 |
#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6690 |
#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6690 |
#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6691 |
#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6691 |
#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6692 |
#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6692 |
#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6693 |
#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6693 |
#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6694 |
|
6694 |
|
6695 |
/******************* Bit definition for CAN_F6R1 register *******************/ |
6695 |
/******************* Bit definition for CAN_F6R1 register *******************/ |
6696 |
#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6696 |
#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6697 |
#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6697 |
#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6698 |
#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6698 |
#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6699 |
#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6699 |
#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6700 |
#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6700 |
#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6701 |
#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6701 |
#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6702 |
#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6702 |
#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6703 |
#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6703 |
#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6704 |
#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6704 |
#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6705 |
#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6705 |
#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6706 |
#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6706 |
#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6707 |
#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6707 |
#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6708 |
#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6708 |
#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6709 |
#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6709 |
#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6710 |
#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6710 |
#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6711 |
#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6711 |
#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6712 |
#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6712 |
#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6713 |
#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6713 |
#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6714 |
#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6714 |
#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6715 |
#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6715 |
#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6716 |
#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6716 |
#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6717 |
#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6717 |
#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6718 |
#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6718 |
#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6719 |
#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6719 |
#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6720 |
#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6720 |
#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6721 |
#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6721 |
#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6722 |
#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6722 |
#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6723 |
#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6723 |
#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6724 |
#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6724 |
#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6725 |
#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6725 |
#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6726 |
#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6726 |
#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6727 |
#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6727 |
#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6728 |
|
6728 |
|
6729 |
/******************* Bit definition for CAN_F7R1 register *******************/ |
6729 |
/******************* Bit definition for CAN_F7R1 register *******************/ |
6730 |
#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6730 |
#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6731 |
#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6731 |
#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6732 |
#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6732 |
#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6733 |
#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6733 |
#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6734 |
#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6734 |
#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6735 |
#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6735 |
#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6736 |
#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6736 |
#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6737 |
#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6737 |
#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6738 |
#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6738 |
#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6739 |
#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6739 |
#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6740 |
#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6740 |
#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6741 |
#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6741 |
#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6742 |
#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6742 |
#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6743 |
#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6743 |
#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6744 |
#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6744 |
#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6745 |
#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6745 |
#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6746 |
#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6746 |
#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6747 |
#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6747 |
#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6748 |
#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6748 |
#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6749 |
#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6749 |
#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6750 |
#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6750 |
#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6751 |
#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6751 |
#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6752 |
#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6752 |
#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6753 |
#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6753 |
#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6754 |
#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6754 |
#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6755 |
#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6755 |
#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6756 |
#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6756 |
#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6757 |
#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6757 |
#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6758 |
#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6758 |
#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6759 |
#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6759 |
#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6760 |
#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6760 |
#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6761 |
#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6761 |
#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6762 |
|
6762 |
|
6763 |
/******************* Bit definition for CAN_F8R1 register *******************/ |
6763 |
/******************* Bit definition for CAN_F8R1 register *******************/ |
6764 |
#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6764 |
#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6765 |
#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6765 |
#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6766 |
#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6766 |
#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6767 |
#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6767 |
#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6768 |
#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6768 |
#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6769 |
#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6769 |
#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6770 |
#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6770 |
#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6771 |
#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6771 |
#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6772 |
#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6772 |
#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6773 |
#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6773 |
#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6774 |
#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6774 |
#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6775 |
#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6775 |
#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6776 |
#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6776 |
#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6777 |
#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6777 |
#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6778 |
#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6778 |
#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6779 |
#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6779 |
#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6780 |
#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6780 |
#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6781 |
#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6781 |
#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6782 |
#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6782 |
#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6783 |
#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6783 |
#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6784 |
#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6784 |
#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6785 |
#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6785 |
#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6786 |
#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6786 |
#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6787 |
#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6787 |
#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6788 |
#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6788 |
#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6789 |
#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6789 |
#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6790 |
#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6790 |
#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6791 |
#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6791 |
#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6792 |
#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6792 |
#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6793 |
#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6793 |
#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6794 |
#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6794 |
#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6795 |
#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6795 |
#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6796 |
|
6796 |
|
6797 |
/******************* Bit definition for CAN_F9R1 register *******************/ |
6797 |
/******************* Bit definition for CAN_F9R1 register *******************/ |
6798 |
#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6798 |
#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6799 |
#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6799 |
#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6800 |
#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6800 |
#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6801 |
#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6801 |
#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6802 |
#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6802 |
#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6803 |
#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6803 |
#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6804 |
#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6804 |
#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6805 |
#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6805 |
#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6806 |
#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6806 |
#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6807 |
#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6807 |
#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6808 |
#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6808 |
#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6809 |
#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6809 |
#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6810 |
#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6810 |
#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6811 |
#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6811 |
#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6812 |
#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6812 |
#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6813 |
#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6813 |
#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6814 |
#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6814 |
#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6815 |
#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6815 |
#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6816 |
#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6816 |
#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6817 |
#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6817 |
#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6818 |
#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6818 |
#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6819 |
#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6819 |
#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6820 |
#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6820 |
#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6821 |
#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6821 |
#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6822 |
#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6822 |
#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6823 |
#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6823 |
#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6824 |
#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6824 |
#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6825 |
#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6825 |
#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6826 |
#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6826 |
#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6827 |
#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6827 |
#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6828 |
#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6828 |
#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6829 |
#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6829 |
#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6830 |
|
6830 |
|
6831 |
/******************* Bit definition for CAN_F10R1 register ******************/ |
6831 |
/******************* Bit definition for CAN_F10R1 register ******************/ |
6832 |
#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6832 |
#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6833 |
#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6833 |
#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6834 |
#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6834 |
#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6835 |
#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6835 |
#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6836 |
#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6836 |
#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6837 |
#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6837 |
#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6838 |
#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6838 |
#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6839 |
#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6839 |
#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6840 |
#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6840 |
#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6841 |
#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6841 |
#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6842 |
#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6842 |
#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6843 |
#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6843 |
#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6844 |
#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6844 |
#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6845 |
#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6845 |
#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6846 |
#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6846 |
#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6847 |
#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6847 |
#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6848 |
#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6848 |
#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6849 |
#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6849 |
#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6850 |
#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6850 |
#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6851 |
#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6851 |
#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6852 |
#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6852 |
#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6853 |
#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6853 |
#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6854 |
#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6854 |
#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6855 |
#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6855 |
#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6856 |
#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6856 |
#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6857 |
#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6857 |
#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6858 |
#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6858 |
#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6859 |
#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6859 |
#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6860 |
#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6860 |
#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6861 |
#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6861 |
#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6862 |
#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6862 |
#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6863 |
#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6863 |
#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6864 |
|
6864 |
|
6865 |
/******************* Bit definition for CAN_F11R1 register ******************/ |
6865 |
/******************* Bit definition for CAN_F11R1 register ******************/ |
6866 |
#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6866 |
#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6867 |
#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6867 |
#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6868 |
#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6868 |
#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6869 |
#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6869 |
#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6870 |
#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6870 |
#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6871 |
#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6871 |
#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6872 |
#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6872 |
#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6873 |
#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6873 |
#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6874 |
#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6874 |
#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6875 |
#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6875 |
#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6876 |
#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6876 |
#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6877 |
#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6877 |
#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6878 |
#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6878 |
#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6879 |
#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6879 |
#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6880 |
#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6880 |
#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6881 |
#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6881 |
#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6882 |
#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6882 |
#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6883 |
#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6883 |
#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6884 |
#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6884 |
#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6885 |
#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6885 |
#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6886 |
#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6886 |
#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6887 |
#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6887 |
#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6888 |
#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6888 |
#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6889 |
#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6889 |
#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6890 |
#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6890 |
#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6891 |
#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6891 |
#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6892 |
#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6892 |
#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6893 |
#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6893 |
#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6894 |
#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6894 |
#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6895 |
#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6895 |
#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6896 |
#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6896 |
#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6897 |
#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6897 |
#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6898 |
|
6898 |
|
6899 |
/******************* Bit definition for CAN_F12R1 register ******************/ |
6899 |
/******************* Bit definition for CAN_F12R1 register ******************/ |
6900 |
#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6900 |
#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6901 |
#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6901 |
#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6902 |
#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6902 |
#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6903 |
#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6903 |
#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6904 |
#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6904 |
#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6905 |
#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6905 |
#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6906 |
#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6906 |
#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6907 |
#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6907 |
#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6908 |
#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6908 |
#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6909 |
#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6909 |
#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6910 |
#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6910 |
#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6911 |
#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6911 |
#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6912 |
#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6912 |
#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6913 |
#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6913 |
#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6914 |
#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6914 |
#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6915 |
#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6915 |
#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6916 |
#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6916 |
#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6917 |
#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6917 |
#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6918 |
#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6918 |
#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6919 |
#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6919 |
#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6920 |
#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6920 |
#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6921 |
#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6921 |
#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6922 |
#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6922 |
#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6923 |
#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6923 |
#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6924 |
#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6924 |
#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6925 |
#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6925 |
#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6926 |
#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6926 |
#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6927 |
#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6927 |
#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6928 |
#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6928 |
#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6929 |
#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6929 |
#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6930 |
#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6930 |
#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6931 |
#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6931 |
#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6932 |
|
6932 |
|
6933 |
/******************* Bit definition for CAN_F13R1 register ******************/ |
6933 |
/******************* Bit definition for CAN_F13R1 register ******************/ |
6934 |
#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6934 |
#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6935 |
#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6935 |
#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6936 |
#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6936 |
#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6937 |
#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6937 |
#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6938 |
#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6938 |
#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6939 |
#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6939 |
#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6940 |
#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6940 |
#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6941 |
#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6941 |
#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6942 |
#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6942 |
#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6943 |
#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6943 |
#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6944 |
#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6944 |
#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6945 |
#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6945 |
#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6946 |
#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6946 |
#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6947 |
#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6947 |
#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6948 |
#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6948 |
#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6949 |
#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6949 |
#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6950 |
#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6950 |
#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6951 |
#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6951 |
#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6952 |
#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6952 |
#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6953 |
#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6953 |
#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6954 |
#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6954 |
#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6955 |
#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6955 |
#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6956 |
#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6956 |
#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6957 |
#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6957 |
#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6958 |
#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6958 |
#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6959 |
#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6959 |
#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6960 |
#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6960 |
#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6961 |
#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6961 |
#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6962 |
#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6962 |
#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6963 |
#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6963 |
#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6964 |
#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6964 |
#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6965 |
#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6965 |
#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6966 |
|
6966 |
|
6967 |
/******************* Bit definition for CAN_F0R2 register *******************/ |
6967 |
/******************* Bit definition for CAN_F0R2 register *******************/ |
6968 |
#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6968 |
#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
6969 |
#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6969 |
#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
6970 |
#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6970 |
#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
6971 |
#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6971 |
#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
6972 |
#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6972 |
#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
6973 |
#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6973 |
#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
6974 |
#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6974 |
#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
6975 |
#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6975 |
#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
6976 |
#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6976 |
#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
6977 |
#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6977 |
#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
6978 |
#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6978 |
#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
6979 |
#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6979 |
#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
6980 |
#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6980 |
#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
6981 |
#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6981 |
#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
6982 |
#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6982 |
#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
6983 |
#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6983 |
#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
6984 |
#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6984 |
#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
6985 |
#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6985 |
#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
6986 |
#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6986 |
#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
6987 |
#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6987 |
#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
6988 |
#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6988 |
#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
6989 |
#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6989 |
#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
6990 |
#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6990 |
#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
6991 |
#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6991 |
#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
6992 |
#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6992 |
#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
6993 |
#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6993 |
#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
6994 |
#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6994 |
#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
6995 |
#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6995 |
#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
6996 |
#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6996 |
#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
6997 |
#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6997 |
#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
6998 |
#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6998 |
#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
6999 |
#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
6999 |
#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7000 |
|
7000 |
|
7001 |
/******************* Bit definition for CAN_F1R2 register *******************/ |
7001 |
/******************* Bit definition for CAN_F1R2 register *******************/ |
7002 |
#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7002 |
#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7003 |
#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7003 |
#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7004 |
#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7004 |
#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7005 |
#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7005 |
#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7006 |
#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7006 |
#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7007 |
#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7007 |
#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7008 |
#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7008 |
#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7009 |
#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7009 |
#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7010 |
#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7010 |
#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7011 |
#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7011 |
#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7012 |
#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7012 |
#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7013 |
#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7013 |
#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7014 |
#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7014 |
#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7015 |
#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7015 |
#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7016 |
#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7016 |
#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7017 |
#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7017 |
#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7018 |
#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7018 |
#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7019 |
#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7019 |
#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7020 |
#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7020 |
#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7021 |
#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7021 |
#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7022 |
#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7022 |
#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7023 |
#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7023 |
#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7024 |
#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7024 |
#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7025 |
#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7025 |
#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7026 |
#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7026 |
#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7027 |
#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7027 |
#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7028 |
#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7028 |
#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7029 |
#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7029 |
#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7030 |
#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7030 |
#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7031 |
#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7031 |
#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7032 |
#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7032 |
#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7033 |
#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7033 |
#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7034 |
|
7034 |
|
7035 |
/******************* Bit definition for CAN_F2R2 register *******************/ |
7035 |
/******************* Bit definition for CAN_F2R2 register *******************/ |
7036 |
#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7036 |
#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7037 |
#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7037 |
#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7038 |
#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7038 |
#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7039 |
#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7039 |
#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7040 |
#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7040 |
#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7041 |
#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7041 |
#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7042 |
#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7042 |
#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7043 |
#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7043 |
#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7044 |
#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7044 |
#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7045 |
#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7045 |
#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7046 |
#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7046 |
#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7047 |
#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7047 |
#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7048 |
#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7048 |
#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7049 |
#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7049 |
#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7050 |
#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7050 |
#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7051 |
#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7051 |
#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7052 |
#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7052 |
#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7053 |
#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7053 |
#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7054 |
#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7054 |
#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7055 |
#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7055 |
#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7056 |
#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7056 |
#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7057 |
#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7057 |
#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7058 |
#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7058 |
#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7059 |
#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7059 |
#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7060 |
#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7060 |
#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7061 |
#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7061 |
#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7062 |
#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7062 |
#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7063 |
#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7063 |
#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7064 |
#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7064 |
#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7065 |
#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7065 |
#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7066 |
#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7066 |
#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7067 |
#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7067 |
#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7068 |
|
7068 |
|
7069 |
/******************* Bit definition for CAN_F3R2 register *******************/ |
7069 |
/******************* Bit definition for CAN_F3R2 register *******************/ |
7070 |
#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7070 |
#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7071 |
#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7071 |
#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7072 |
#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7072 |
#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7073 |
#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7073 |
#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7074 |
#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7074 |
#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7075 |
#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7075 |
#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7076 |
#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7076 |
#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7077 |
#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7077 |
#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7078 |
#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7078 |
#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7079 |
#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7079 |
#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7080 |
#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7080 |
#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7081 |
#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7081 |
#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7082 |
#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7082 |
#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7083 |
#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7083 |
#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7084 |
#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7084 |
#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7085 |
#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7085 |
#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7086 |
#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7086 |
#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7087 |
#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7087 |
#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7088 |
#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7088 |
#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7089 |
#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7089 |
#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7090 |
#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7090 |
#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7091 |
#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7091 |
#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7092 |
#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7092 |
#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7093 |
#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7093 |
#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7094 |
#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7094 |
#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7095 |
#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7095 |
#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7096 |
#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7096 |
#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7097 |
#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7097 |
#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7098 |
#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7098 |
#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7099 |
#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7099 |
#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7100 |
#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7100 |
#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7101 |
#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7101 |
#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7102 |
|
7102 |
|
7103 |
/******************* Bit definition for CAN_F4R2 register *******************/ |
7103 |
/******************* Bit definition for CAN_F4R2 register *******************/ |
7104 |
#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7104 |
#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7105 |
#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7105 |
#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7106 |
#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7106 |
#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7107 |
#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7107 |
#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7108 |
#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7108 |
#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7109 |
#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7109 |
#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7110 |
#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7110 |
#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7111 |
#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7111 |
#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7112 |
#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7112 |
#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7113 |
#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7113 |
#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7114 |
#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7114 |
#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7115 |
#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7115 |
#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7116 |
#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7116 |
#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7117 |
#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7117 |
#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7118 |
#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7118 |
#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7119 |
#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7119 |
#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7120 |
#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7120 |
#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7121 |
#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7121 |
#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7122 |
#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7122 |
#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7123 |
#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7123 |
#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7124 |
#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7124 |
#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7125 |
#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7125 |
#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7126 |
#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7126 |
#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7127 |
#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7127 |
#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7128 |
#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7128 |
#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7129 |
#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7129 |
#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7130 |
#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7130 |
#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7131 |
#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7131 |
#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7132 |
#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7132 |
#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7133 |
#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7133 |
#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7134 |
#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7134 |
#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7135 |
#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7135 |
#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7136 |
|
7136 |
|
7137 |
/******************* Bit definition for CAN_F5R2 register *******************/ |
7137 |
/******************* Bit definition for CAN_F5R2 register *******************/ |
7138 |
#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7138 |
#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7139 |
#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7139 |
#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7140 |
#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7140 |
#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7141 |
#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7141 |
#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7142 |
#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7142 |
#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7143 |
#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7143 |
#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7144 |
#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7144 |
#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7145 |
#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7145 |
#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7146 |
#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7146 |
#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7147 |
#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7147 |
#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7148 |
#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7148 |
#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7149 |
#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7149 |
#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7150 |
#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7150 |
#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7151 |
#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7151 |
#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7152 |
#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7152 |
#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7153 |
#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7153 |
#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7154 |
#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7154 |
#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7155 |
#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7155 |
#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7156 |
#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7156 |
#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7157 |
#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7157 |
#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7158 |
#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7158 |
#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7159 |
#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7159 |
#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7160 |
#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7160 |
#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7161 |
#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7161 |
#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7162 |
#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7162 |
#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7163 |
#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7163 |
#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7164 |
#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7164 |
#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7165 |
#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7165 |
#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7166 |
#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7166 |
#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7167 |
#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7167 |
#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7168 |
#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7168 |
#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7169 |
#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7169 |
#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7170 |
|
7170 |
|
7171 |
/******************* Bit definition for CAN_F6R2 register *******************/ |
7171 |
/******************* Bit definition for CAN_F6R2 register *******************/ |
7172 |
#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7172 |
#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7173 |
#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7173 |
#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7174 |
#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7174 |
#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7175 |
#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7175 |
#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7176 |
#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7176 |
#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7177 |
#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7177 |
#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7178 |
#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7178 |
#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7179 |
#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7179 |
#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7180 |
#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7180 |
#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7181 |
#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7181 |
#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7182 |
#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7182 |
#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7183 |
#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7183 |
#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7184 |
#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7184 |
#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7185 |
#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7185 |
#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7186 |
#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7186 |
#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7187 |
#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7187 |
#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7188 |
#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7188 |
#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7189 |
#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7189 |
#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7190 |
#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7190 |
#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7191 |
#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7191 |
#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7192 |
#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7192 |
#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7193 |
#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7193 |
#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7194 |
#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7194 |
#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7195 |
#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7195 |
#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7196 |
#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7196 |
#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7197 |
#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7197 |
#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7198 |
#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7198 |
#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7199 |
#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7199 |
#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7200 |
#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7200 |
#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7201 |
#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7201 |
#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7202 |
#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7202 |
#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7203 |
#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7203 |
#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7204 |
|
7204 |
|
7205 |
/******************* Bit definition for CAN_F7R2 register *******************/ |
7205 |
/******************* Bit definition for CAN_F7R2 register *******************/ |
7206 |
#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7206 |
#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7207 |
#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7207 |
#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7208 |
#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7208 |
#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7209 |
#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7209 |
#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7210 |
#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7210 |
#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7211 |
#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7211 |
#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7212 |
#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7212 |
#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7213 |
#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7213 |
#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7214 |
#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7214 |
#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7215 |
#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7215 |
#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7216 |
#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7216 |
#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7217 |
#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7217 |
#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7218 |
#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7218 |
#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7219 |
#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7219 |
#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7220 |
#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7220 |
#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7221 |
#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7221 |
#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7222 |
#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7222 |
#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7223 |
#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7223 |
#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7224 |
#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7224 |
#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7225 |
#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7225 |
#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7226 |
#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7226 |
#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7227 |
#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7227 |
#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7228 |
#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7228 |
#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7229 |
#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7229 |
#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7230 |
#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7230 |
#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7231 |
#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7231 |
#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7232 |
#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7232 |
#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7233 |
#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7233 |
#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7234 |
#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7234 |
#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7235 |
#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7235 |
#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7236 |
#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7236 |
#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7237 |
#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7237 |
#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7238 |
|
7238 |
|
7239 |
/******************* Bit definition for CAN_F8R2 register *******************/ |
7239 |
/******************* Bit definition for CAN_F8R2 register *******************/ |
7240 |
#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7240 |
#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7241 |
#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7241 |
#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7242 |
#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7242 |
#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7243 |
#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7243 |
#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7244 |
#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7244 |
#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7245 |
#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7245 |
#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7246 |
#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7246 |
#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7247 |
#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7247 |
#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7248 |
#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7248 |
#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7249 |
#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7249 |
#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7250 |
#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7250 |
#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7251 |
#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7251 |
#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7252 |
#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7252 |
#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7253 |
#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7253 |
#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7254 |
#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7254 |
#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7255 |
#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7255 |
#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7256 |
#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7256 |
#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7257 |
#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7257 |
#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7258 |
#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7258 |
#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7259 |
#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7259 |
#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7260 |
#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7260 |
#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7261 |
#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7261 |
#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7262 |
#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7262 |
#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7263 |
#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7263 |
#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7264 |
#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7264 |
#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7265 |
#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7265 |
#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7266 |
#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7266 |
#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7267 |
#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7267 |
#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7268 |
#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7268 |
#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7269 |
#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7269 |
#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7270 |
#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7270 |
#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7271 |
#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7271 |
#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7272 |
|
7272 |
|
7273 |
/******************* Bit definition for CAN_F9R2 register *******************/ |
7273 |
/******************* Bit definition for CAN_F9R2 register *******************/ |
7274 |
#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7274 |
#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7275 |
#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7275 |
#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7276 |
#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7276 |
#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7277 |
#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7277 |
#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7278 |
#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7278 |
#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7279 |
#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7279 |
#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7280 |
#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7280 |
#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7281 |
#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7281 |
#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7282 |
#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7282 |
#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7283 |
#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7283 |
#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7284 |
#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7284 |
#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7285 |
#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7285 |
#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7286 |
#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7286 |
#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7287 |
#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7287 |
#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7288 |
#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7288 |
#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7289 |
#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7289 |
#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7290 |
#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7290 |
#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7291 |
#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7291 |
#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7292 |
#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7292 |
#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7293 |
#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7293 |
#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7294 |
#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7294 |
#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7295 |
#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7295 |
#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7296 |
#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7296 |
#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7297 |
#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7297 |
#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7298 |
#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7298 |
#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7299 |
#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7299 |
#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7300 |
#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7300 |
#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7301 |
#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7301 |
#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7302 |
#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7302 |
#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7303 |
#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7303 |
#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7304 |
#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7304 |
#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7305 |
#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7305 |
#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7306 |
|
7306 |
|
7307 |
/******************* Bit definition for CAN_F10R2 register ******************/ |
7307 |
/******************* Bit definition for CAN_F10R2 register ******************/ |
7308 |
#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7308 |
#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7309 |
#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7309 |
#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7310 |
#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7310 |
#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7311 |
#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7311 |
#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7312 |
#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7312 |
#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7313 |
#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7313 |
#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7314 |
#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7314 |
#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7315 |
#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7315 |
#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7316 |
#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7316 |
#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7317 |
#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7317 |
#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7318 |
#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7318 |
#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7319 |
#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7319 |
#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7320 |
#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7320 |
#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7321 |
#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7321 |
#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7322 |
#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7322 |
#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7323 |
#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7323 |
#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7324 |
#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7324 |
#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7325 |
#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7325 |
#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7326 |
#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7326 |
#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7327 |
#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7327 |
#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7328 |
#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7328 |
#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7329 |
#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7329 |
#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7330 |
#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7330 |
#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7331 |
#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7331 |
#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7332 |
#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7332 |
#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7333 |
#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7333 |
#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7334 |
#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7334 |
#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7335 |
#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7335 |
#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7336 |
#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7336 |
#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7337 |
#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7337 |
#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7338 |
#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7338 |
#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7339 |
#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7339 |
#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7340 |
|
7340 |
|
7341 |
/******************* Bit definition for CAN_F11R2 register ******************/ |
7341 |
/******************* Bit definition for CAN_F11R2 register ******************/ |
7342 |
#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7342 |
#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7343 |
#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7343 |
#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7344 |
#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7344 |
#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7345 |
#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7345 |
#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7346 |
#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7346 |
#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7347 |
#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7347 |
#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7348 |
#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7348 |
#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7349 |
#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7349 |
#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7350 |
#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7350 |
#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7351 |
#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7351 |
#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7352 |
#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7352 |
#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7353 |
#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7353 |
#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7354 |
#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7354 |
#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7355 |
#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7355 |
#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7356 |
#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7356 |
#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7357 |
#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7357 |
#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7358 |
#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7358 |
#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7359 |
#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7359 |
#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7360 |
#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7360 |
#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7361 |
#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7361 |
#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7362 |
#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7362 |
#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7363 |
#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7363 |
#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7364 |
#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7364 |
#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7365 |
#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7365 |
#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7366 |
#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7366 |
#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7367 |
#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7367 |
#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7368 |
#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7368 |
#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7369 |
#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7369 |
#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7370 |
#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7370 |
#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7371 |
#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7371 |
#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7372 |
#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7372 |
#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7373 |
#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7373 |
#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7374 |
|
7374 |
|
7375 |
/******************* Bit definition for CAN_F12R2 register ******************/ |
7375 |
/******************* Bit definition for CAN_F12R2 register ******************/ |
7376 |
#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7376 |
#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7377 |
#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7377 |
#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7378 |
#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7378 |
#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7379 |
#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7379 |
#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7380 |
#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7380 |
#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7381 |
#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7381 |
#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7382 |
#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7382 |
#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7383 |
#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7383 |
#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7384 |
#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7384 |
#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7385 |
#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7385 |
#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7386 |
#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7386 |
#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7387 |
#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7387 |
#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7388 |
#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7388 |
#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7389 |
#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7389 |
#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7390 |
#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7390 |
#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7391 |
#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7391 |
#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7392 |
#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7392 |
#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7393 |
#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7393 |
#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7394 |
#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7394 |
#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7395 |
#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7395 |
#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7396 |
#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7396 |
#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7397 |
#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7397 |
#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7398 |
#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7398 |
#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7399 |
#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7399 |
#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7400 |
#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7400 |
#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7401 |
#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7401 |
#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7402 |
#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7402 |
#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7403 |
#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7403 |
#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7404 |
#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7404 |
#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7405 |
#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7405 |
#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7406 |
#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7406 |
#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7407 |
#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7407 |
#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7408 |
|
7408 |
|
7409 |
/******************* Bit definition for CAN_F13R2 register ******************/ |
7409 |
/******************* Bit definition for CAN_F13R2 register ******************/ |
7410 |
#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7410 |
#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
7411 |
#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7411 |
#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
7412 |
#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7412 |
#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
7413 |
#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7413 |
#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
7414 |
#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7414 |
#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
7415 |
#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7415 |
#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
7416 |
#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7416 |
#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
7417 |
#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7417 |
#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
7418 |
#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7418 |
#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
7419 |
#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7419 |
#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
7420 |
#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7420 |
#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
7421 |
#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7421 |
#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
7422 |
#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7422 |
#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
7423 |
#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7423 |
#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
7424 |
#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7424 |
#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
7425 |
#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7425 |
#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
7426 |
#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7426 |
#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
7427 |
#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7427 |
#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
7428 |
#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7428 |
#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
7429 |
#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7429 |
#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
7430 |
#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7430 |
#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
7431 |
#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7431 |
#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
7432 |
#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7432 |
#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
7433 |
#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7433 |
#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
7434 |
#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7434 |
#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
7435 |
#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7435 |
#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
7436 |
#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7436 |
#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
7437 |
#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7437 |
#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
7438 |
#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7438 |
#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
7439 |
#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7439 |
#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
7440 |
#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7440 |
#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
7441 |
#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7441 |
#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
7442 |
|
7442 |
|
7443 |
/******************************************************************************/ |
7443 |
/******************************************************************************/ |
7444 |
/* */ |
7444 |
/* */ |
7445 |
/* Serial Peripheral Interface */ |
7445 |
/* Serial Peripheral Interface */ |
7446 |
/* */ |
7446 |
/* */ |
7447 |
/******************************************************************************/ |
7447 |
/******************************************************************************/ |
7448 |
|
7448 |
|
7449 |
/******************* Bit definition for SPI_CR1 register ********************/ |
7449 |
/******************* Bit definition for SPI_CR1 register ********************/ |
7450 |
#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */ |
7450 |
#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */ |
7451 |
#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */ |
7451 |
#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */ |
7452 |
#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */ |
7452 |
#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */ |
7453 |
|
7453 |
|
7454 |
#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */ |
7454 |
#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */ |
7455 |
#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */ |
7455 |
#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */ |
7456 |
#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */ |
7456 |
#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */ |
7457 |
#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */ |
7457 |
#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */ |
7458 |
|
7458 |
|
7459 |
#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */ |
7459 |
#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */ |
7460 |
#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */ |
7460 |
#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */ |
7461 |
#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */ |
7461 |
#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */ |
7462 |
#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */ |
7462 |
#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */ |
7463 |
#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */ |
7463 |
#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */ |
7464 |
#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */ |
7464 |
#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */ |
7465 |
#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */ |
7465 |
#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */ |
7466 |
#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */ |
7466 |
#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */ |
7467 |
#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */ |
7467 |
#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */ |
7468 |
#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */ |
7468 |
#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */ |
7469 |
|
7469 |
|
7470 |
/******************* Bit definition for SPI_CR2 register ********************/ |
7470 |
/******************* Bit definition for SPI_CR2 register ********************/ |
7471 |
#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */ |
7471 |
#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */ |
7472 |
#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */ |
7472 |
#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */ |
7473 |
#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */ |
7473 |
#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */ |
7474 |
#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */ |
7474 |
#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */ |
7475 |
#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */ |
7475 |
#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */ |
7476 |
#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */ |
7476 |
#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */ |
7477 |
|
7477 |
|
7478 |
/******************** Bit definition for SPI_SR register ********************/ |
7478 |
/******************** Bit definition for SPI_SR register ********************/ |
7479 |
#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */ |
7479 |
#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */ |
7480 |
#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */ |
7480 |
#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */ |
7481 |
#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */ |
7481 |
#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */ |
7482 |
#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */ |
7482 |
#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */ |
7483 |
#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */ |
7483 |
#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */ |
7484 |
#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */ |
7484 |
#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */ |
7485 |
#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */ |
7485 |
#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */ |
7486 |
#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */ |
7486 |
#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */ |
7487 |
|
7487 |
|
7488 |
/******************** Bit definition for SPI_DR register ********************/ |
7488 |
/******************** Bit definition for SPI_DR register ********************/ |
7489 |
#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */ |
7489 |
#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */ |
7490 |
|
7490 |
|
7491 |
/******************* Bit definition for SPI_CRCPR register ******************/ |
7491 |
/******************* Bit definition for SPI_CRCPR register ******************/ |
7492 |
#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */ |
7492 |
#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */ |
7493 |
|
7493 |
|
7494 |
/****************** Bit definition for SPI_RXCRCR register ******************/ |
7494 |
/****************** Bit definition for SPI_RXCRCR register ******************/ |
7495 |
#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */ |
7495 |
#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */ |
7496 |
|
7496 |
|
7497 |
/****************** Bit definition for SPI_TXCRCR register ******************/ |
7497 |
/****************** Bit definition for SPI_TXCRCR register ******************/ |
7498 |
#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */ |
7498 |
#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */ |
7499 |
|
7499 |
|
7500 |
/****************** Bit definition for SPI_I2SCFGR register *****************/ |
7500 |
/****************** Bit definition for SPI_I2SCFGR register *****************/ |
7501 |
#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ |
7501 |
#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ |
7502 |
|
7502 |
|
7503 |
#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ |
7503 |
#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ |
7504 |
#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */ |
7504 |
#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */ |
7505 |
#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */ |
7505 |
#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */ |
7506 |
|
7506 |
|
7507 |
#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */ |
7507 |
#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */ |
7508 |
|
7508 |
|
7509 |
#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ |
7509 |
#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ |
7510 |
#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
7510 |
#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
7511 |
#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
7511 |
#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
7512 |
|
7512 |
|
7513 |
#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */ |
7513 |
#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */ |
7514 |
|
7514 |
|
7515 |
#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ |
7515 |
#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ |
7516 |
#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
7516 |
#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */ |
7517 |
#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
7517 |
#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */ |
7518 |
|
7518 |
|
7519 |
#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */ |
7519 |
#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */ |
7520 |
#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */ |
7520 |
#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */ |
7521 |
|
7521 |
|
7522 |
/****************** Bit definition for SPI_I2SPR register *******************/ |
7522 |
/****************** Bit definition for SPI_I2SPR register *******************/ |
7523 |
#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ |
7523 |
#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ |
7524 |
#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ |
7524 |
#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ |
7525 |
#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */ |
7525 |
#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */ |
7526 |
|
7526 |
|
7527 |
/******************************************************************************/ |
7527 |
/******************************************************************************/ |
7528 |
/* */ |
7528 |
/* */ |
7529 |
/* Inter-integrated Circuit Interface */ |
7529 |
/* Inter-integrated Circuit Interface */ |
7530 |
/* */ |
7530 |
/* */ |
7531 |
/******************************************************************************/ |
7531 |
/******************************************************************************/ |
7532 |
|
7532 |
|
7533 |
/******************* Bit definition for I2C_CR1 register ********************/ |
7533 |
/******************* Bit definition for I2C_CR1 register ********************/ |
7534 |
#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */ |
7534 |
#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */ |
7535 |
#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */ |
7535 |
#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */ |
7536 |
#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */ |
7536 |
#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */ |
7537 |
#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */ |
7537 |
#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */ |
7538 |
#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */ |
7538 |
#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */ |
7539 |
#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */ |
7539 |
#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */ |
7540 |
#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */ |
7540 |
#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */ |
7541 |
#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */ |
7541 |
#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */ |
7542 |
#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */ |
7542 |
#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */ |
7543 |
#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */ |
7543 |
#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */ |
7544 |
#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */ |
7544 |
#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */ |
7545 |
#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */ |
7545 |
#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */ |
7546 |
#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */ |
7546 |
#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */ |
7547 |
#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */ |
7547 |
#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */ |
7548 |
|
7548 |
|
7549 |
/******************* Bit definition for I2C_CR2 register ********************/ |
7549 |
/******************* Bit definition for I2C_CR2 register ********************/ |
7550 |
#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ |
7550 |
#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ |
7551 |
#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
7551 |
#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
7552 |
#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
7552 |
#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
7553 |
#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
7553 |
#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
7554 |
#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
7554 |
#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
7555 |
#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
7555 |
#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
7556 |
#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */ |
7556 |
#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */ |
7557 |
|
7557 |
|
7558 |
#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */ |
7558 |
#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */ |
7559 |
#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */ |
7559 |
#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */ |
7560 |
#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */ |
7560 |
#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */ |
7561 |
#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */ |
7561 |
#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */ |
7562 |
#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */ |
7562 |
#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */ |
7563 |
|
7563 |
|
7564 |
/******************* Bit definition for I2C_OAR1 register *******************/ |
7564 |
/******************* Bit definition for I2C_OAR1 register *******************/ |
7565 |
#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */ |
7565 |
#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */ |
7566 |
#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */ |
7566 |
#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */ |
7567 |
|
7567 |
|
7568 |
#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */ |
7568 |
#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */ |
7569 |
#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */ |
7569 |
#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */ |
7570 |
#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */ |
7570 |
#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */ |
7571 |
#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */ |
7571 |
#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */ |
7572 |
#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */ |
7572 |
#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */ |
7573 |
#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */ |
7573 |
#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */ |
7574 |
#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */ |
7574 |
#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */ |
7575 |
#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */ |
7575 |
#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */ |
7576 |
#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */ |
7576 |
#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */ |
7577 |
#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */ |
7577 |
#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */ |
7578 |
|
7578 |
|
7579 |
#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */ |
7579 |
#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */ |
7580 |
|
7580 |
|
7581 |
/******************* Bit definition for I2C_OAR2 register *******************/ |
7581 |
/******************* Bit definition for I2C_OAR2 register *******************/ |
7582 |
#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */ |
7582 |
#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */ |
7583 |
#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */ |
7583 |
#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */ |
7584 |
|
7584 |
|
7585 |
/******************** Bit definition for I2C_DR register ********************/ |
7585 |
/******************** Bit definition for I2C_DR register ********************/ |
7586 |
#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */ |
7586 |
#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */ |
7587 |
|
7587 |
|
7588 |
/******************* Bit definition for I2C_SR1 register ********************/ |
7588 |
/******************* Bit definition for I2C_SR1 register ********************/ |
7589 |
#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */ |
7589 |
#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */ |
7590 |
#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */ |
7590 |
#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */ |
7591 |
#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */ |
7591 |
#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */ |
7592 |
#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */ |
7592 |
#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */ |
7593 |
#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */ |
7593 |
#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */ |
7594 |
#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */ |
7594 |
#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */ |
7595 |
#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */ |
7595 |
#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */ |
7596 |
#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */ |
7596 |
#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */ |
7597 |
#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */ |
7597 |
#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */ |
7598 |
#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */ |
7598 |
#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */ |
7599 |
#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */ |
7599 |
#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */ |
7600 |
#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */ |
7600 |
#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */ |
7601 |
#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */ |
7601 |
#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */ |
7602 |
#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */ |
7602 |
#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */ |
7603 |
|
7603 |
|
7604 |
/******************* Bit definition for I2C_SR2 register ********************/ |
7604 |
/******************* Bit definition for I2C_SR2 register ********************/ |
7605 |
#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */ |
7605 |
#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */ |
7606 |
#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */ |
7606 |
#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */ |
7607 |
#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */ |
7607 |
#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */ |
7608 |
#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */ |
7608 |
#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */ |
7609 |
#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */ |
7609 |
#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */ |
7610 |
#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */ |
7610 |
#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */ |
7611 |
#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */ |
7611 |
#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */ |
7612 |
#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */ |
7612 |
#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */ |
7613 |
|
7613 |
|
7614 |
/******************* Bit definition for I2C_CCR register ********************/ |
7614 |
/******************* Bit definition for I2C_CCR register ********************/ |
7615 |
#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */ |
7615 |
#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */ |
7616 |
#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */ |
7616 |
#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */ |
7617 |
#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */ |
7617 |
#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */ |
7618 |
|
7618 |
|
7619 |
/****************** Bit definition for I2C_TRISE register *******************/ |
7619 |
/****************** Bit definition for I2C_TRISE register *******************/ |
7620 |
#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ |
7620 |
#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ |
7621 |
|
7621 |
|
7622 |
/******************************************************************************/ |
7622 |
/******************************************************************************/ |
7623 |
/* */ |
7623 |
/* */ |
7624 |
/* Universal Synchronous Asynchronous Receiver Transmitter */ |
7624 |
/* Universal Synchronous Asynchronous Receiver Transmitter */ |
7625 |
/* */ |
7625 |
/* */ |
7626 |
/******************************************************************************/ |
7626 |
/******************************************************************************/ |
7627 |
|
7627 |
|
7628 |
/******************* Bit definition for USART_SR register *******************/ |
7628 |
/******************* Bit definition for USART_SR register *******************/ |
7629 |
#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */ |
7629 |
#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */ |
7630 |
#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */ |
7630 |
#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */ |
7631 |
#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */ |
7631 |
#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */ |
7632 |
#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */ |
7632 |
#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */ |
7633 |
#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */ |
7633 |
#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */ |
7634 |
#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */ |
7634 |
#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */ |
7635 |
#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */ |
7635 |
#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */ |
7636 |
#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */ |
7636 |
#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */ |
7637 |
#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */ |
7637 |
#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */ |
7638 |
#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */ |
7638 |
#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */ |
7639 |
|
7639 |
|
7640 |
/******************* Bit definition for USART_DR register *******************/ |
7640 |
/******************* Bit definition for USART_DR register *******************/ |
7641 |
#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */ |
7641 |
#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */ |
7642 |
|
7642 |
|
7643 |
/****************** Bit definition for USART_BRR register *******************/ |
7643 |
/****************** Bit definition for USART_BRR register *******************/ |
7644 |
#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */ |
7644 |
#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */ |
7645 |
#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */ |
7645 |
#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */ |
7646 |
|
7646 |
|
7647 |
/****************** Bit definition for USART_CR1 register *******************/ |
7647 |
/****************** Bit definition for USART_CR1 register *******************/ |
7648 |
#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */ |
7648 |
#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */ |
7649 |
#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */ |
7649 |
#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */ |
7650 |
#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */ |
7650 |
#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */ |
7651 |
#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */ |
7651 |
#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */ |
7652 |
#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */ |
7652 |
#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */ |
7653 |
#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */ |
7653 |
#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */ |
7654 |
#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */ |
7654 |
#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */ |
7655 |
#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */ |
7655 |
#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */ |
7656 |
#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */ |
7656 |
#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */ |
7657 |
#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */ |
7657 |
#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */ |
7658 |
#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */ |
7658 |
#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */ |
7659 |
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */ |
7659 |
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */ |
7660 |
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */ |
7660 |
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */ |
7661 |
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */ |
7661 |
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */ |
7662 |
#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */ |
7662 |
#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */ |
7663 |
|
7663 |
|
7664 |
/****************** Bit definition for USART_CR2 register *******************/ |
7664 |
/****************** Bit definition for USART_CR2 register *******************/ |
7665 |
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */ |
7665 |
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */ |
7666 |
#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */ |
7666 |
#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */ |
7667 |
#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */ |
7667 |
#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */ |
7668 |
#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */ |
7668 |
#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */ |
7669 |
#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */ |
7669 |
#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */ |
7670 |
#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */ |
7670 |
#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */ |
7671 |
#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */ |
7671 |
#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */ |
7672 |
|
7672 |
|
7673 |
#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */ |
7673 |
#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */ |
7674 |
#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
7674 |
#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */ |
7675 |
#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
7675 |
#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */ |
7676 |
|
7676 |
|
7677 |
#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */ |
7677 |
#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */ |
7678 |
|
7678 |
|
7679 |
/****************** Bit definition for USART_CR3 register *******************/ |
7679 |
/****************** Bit definition for USART_CR3 register *******************/ |
7680 |
#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */ |
7680 |
#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */ |
7681 |
#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */ |
7681 |
#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */ |
7682 |
#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */ |
7682 |
#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */ |
7683 |
#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */ |
7683 |
#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */ |
7684 |
#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */ |
7684 |
#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */ |
7685 |
#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */ |
7685 |
#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */ |
7686 |
#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */ |
7686 |
#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */ |
7687 |
#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */ |
7687 |
#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */ |
7688 |
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */ |
7688 |
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */ |
7689 |
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */ |
7689 |
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */ |
7690 |
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */ |
7690 |
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */ |
7691 |
#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */ |
7691 |
#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */ |
7692 |
|
7692 |
|
7693 |
/****************** Bit definition for USART_GTPR register ******************/ |
7693 |
/****************** Bit definition for USART_GTPR register ******************/ |
7694 |
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */ |
7694 |
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */ |
7695 |
#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
7695 |
#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */ |
7696 |
#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
7696 |
#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */ |
7697 |
#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
7697 |
#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */ |
7698 |
#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
7698 |
#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */ |
7699 |
#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
7699 |
#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */ |
7700 |
#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */ |
7700 |
#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */ |
7701 |
#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */ |
7701 |
#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */ |
7702 |
#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */ |
7702 |
#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */ |
7703 |
|
7703 |
|
7704 |
#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */ |
7704 |
#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */ |
7705 |
|
7705 |
|
7706 |
/******************************************************************************/ |
7706 |
/******************************************************************************/ |
7707 |
/* */ |
7707 |
/* */ |
7708 |
/* Debug MCU */ |
7708 |
/* Debug MCU */ |
7709 |
/* */ |
7709 |
/* */ |
7710 |
/******************************************************************************/ |
7710 |
/******************************************************************************/ |
7711 |
|
7711 |
|
7712 |
/**************** Bit definition for DBGMCU_IDCODE register *****************/ |
7712 |
/**************** Bit definition for DBGMCU_IDCODE register *****************/ |
7713 |
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */ |
7713 |
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */ |
7714 |
|
7714 |
|
7715 |
#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */ |
7715 |
#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */ |
7716 |
#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
7716 |
#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
7717 |
#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
7717 |
#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
7718 |
#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
7718 |
#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
7719 |
#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
7719 |
#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
7720 |
#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
7720 |
#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
7721 |
#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
7721 |
#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
7722 |
#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
7722 |
#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
7723 |
#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
7723 |
#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
7724 |
#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */ |
7724 |
#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */ |
7725 |
#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */ |
7725 |
#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */ |
7726 |
#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */ |
7726 |
#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */ |
7727 |
#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */ |
7727 |
#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */ |
7728 |
#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */ |
7728 |
#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */ |
7729 |
#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */ |
7729 |
#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */ |
7730 |
#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */ |
7730 |
#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */ |
7731 |
#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */ |
7731 |
#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */ |
7732 |
|
7732 |
|
7733 |
/****************** Bit definition for DBGMCU_CR register *******************/ |
7733 |
/****************** Bit definition for DBGMCU_CR register *******************/ |
7734 |
#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */ |
7734 |
#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */ |
7735 |
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */ |
7735 |
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */ |
7736 |
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */ |
7736 |
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */ |
7737 |
#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */ |
7737 |
#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */ |
7738 |
|
7738 |
|
7739 |
#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
7739 |
#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
7740 |
#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
7740 |
#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
7741 |
#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
7741 |
#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
7742 |
|
7742 |
|
7743 |
#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */ |
7743 |
#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */ |
7744 |
#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */ |
7744 |
#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */ |
7745 |
#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */ |
7745 |
#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */ |
7746 |
#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */ |
7746 |
#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */ |
7747 |
#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */ |
7747 |
#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */ |
7748 |
#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */ |
7748 |
#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */ |
7749 |
#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */ |
7749 |
#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */ |
7750 |
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */ |
7750 |
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */ |
7751 |
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */ |
7751 |
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */ |
7752 |
#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */ |
7752 |
#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */ |
7753 |
#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */ |
7753 |
#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */ |
7754 |
#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */ |
7754 |
#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */ |
7755 |
#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */ |
7755 |
#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */ |
7756 |
#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */ |
7756 |
#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */ |
7757 |
#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */ |
7757 |
#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */ |
7758 |
#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */ |
7758 |
#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */ |
7759 |
#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */ |
7759 |
#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */ |
7760 |
#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */ |
7760 |
#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */ |
7761 |
#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */ |
7761 |
#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */ |
7762 |
#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */ |
7762 |
#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */ |
7763 |
#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */ |
7763 |
#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */ |
7764 |
#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */ |
7764 |
#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */ |
7765 |
#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */ |
7765 |
#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */ |
7766 |
|
7766 |
|
7767 |
/******************************************************************************/ |
7767 |
/******************************************************************************/ |
7768 |
/* */ |
7768 |
/* */ |
7769 |
/* FLASH and Option Bytes Registers */ |
7769 |
/* FLASH and Option Bytes Registers */ |
7770 |
/* */ |
7770 |
/* */ |
7771 |
/******************************************************************************/ |
7771 |
/******************************************************************************/ |
7772 |
|
7772 |
|
7773 |
/******************* Bit definition for FLASH_ACR register ******************/ |
7773 |
/******************* Bit definition for FLASH_ACR register ******************/ |
7774 |
#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */ |
7774 |
#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */ |
7775 |
#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */ |
7775 |
#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */ |
7776 |
#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */ |
7776 |
#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */ |
7777 |
#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */ |
7777 |
#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */ |
7778 |
|
7778 |
|
7779 |
#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */ |
7779 |
#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */ |
7780 |
#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */ |
7780 |
#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */ |
7781 |
#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */ |
7781 |
#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */ |
7782 |
|
7782 |
|
7783 |
/****************** Bit definition for FLASH_KEYR register ******************/ |
7783 |
/****************** Bit definition for FLASH_KEYR register ******************/ |
7784 |
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */ |
7784 |
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */ |
7785 |
|
7785 |
|
7786 |
/***************** Bit definition for FLASH_OPTKEYR register ****************/ |
7786 |
/***************** Bit definition for FLASH_OPTKEYR register ****************/ |
7787 |
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */ |
7787 |
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */ |
7788 |
|
7788 |
|
7789 |
/****************** Bit definition for FLASH_SR register *******************/ |
7789 |
/****************** Bit definition for FLASH_SR register *******************/ |
7790 |
#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */ |
7790 |
#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */ |
7791 |
#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */ |
7791 |
#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */ |
7792 |
#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */ |
7792 |
#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */ |
7793 |
#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */ |
7793 |
#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */ |
7794 |
|
7794 |
|
7795 |
/******************* Bit definition for FLASH_CR register *******************/ |
7795 |
/******************* Bit definition for FLASH_CR register *******************/ |
7796 |
#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */ |
7796 |
#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */ |
7797 |
#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */ |
7797 |
#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */ |
7798 |
#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */ |
7798 |
#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */ |
7799 |
#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */ |
7799 |
#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */ |
7800 |
#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */ |
7800 |
#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */ |
7801 |
#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */ |
7801 |
#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */ |
7802 |
#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */ |
7802 |
#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */ |
7803 |
#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */ |
7803 |
#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */ |
7804 |
#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */ |
7804 |
#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */ |
7805 |
#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */ |
7805 |
#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */ |
7806 |
|
7806 |
|
7807 |
/******************* Bit definition for FLASH_AR register *******************/ |
7807 |
/******************* Bit definition for FLASH_AR register *******************/ |
7808 |
#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */ |
7808 |
#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */ |
7809 |
|
7809 |
|
7810 |
/****************** Bit definition for FLASH_OBR register *******************/ |
7810 |
/****************** Bit definition for FLASH_OBR register *******************/ |
7811 |
#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */ |
7811 |
#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */ |
7812 |
#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */ |
7812 |
#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */ |
7813 |
|
7813 |
|
7814 |
#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */ |
7814 |
#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */ |
7815 |
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */ |
7815 |
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */ |
7816 |
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */ |
7816 |
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */ |
7817 |
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */ |
7817 |
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */ |
7818 |
#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */ |
7818 |
#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */ |
7819 |
|
7819 |
|
7820 |
/****************** Bit definition for FLASH_WRPR register ******************/ |
7820 |
/****************** Bit definition for FLASH_WRPR register ******************/ |
7821 |
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */ |
7821 |
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */ |
7822 |
|
7822 |
|
7823 |
/*----------------------------------------------------------------------------*/ |
7823 |
/*----------------------------------------------------------------------------*/ |
7824 |
|
7824 |
|
7825 |
/****************** Bit definition for FLASH_RDP register *******************/ |
7825 |
/****************** Bit definition for FLASH_RDP register *******************/ |
7826 |
#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */ |
7826 |
#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */ |
7827 |
#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */ |
7827 |
#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */ |
7828 |
|
7828 |
|
7829 |
/****************** Bit definition for FLASH_USER register ******************/ |
7829 |
/****************** Bit definition for FLASH_USER register ******************/ |
7830 |
#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */ |
7830 |
#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */ |
7831 |
#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */ |
7831 |
#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */ |
7832 |
|
7832 |
|
7833 |
/****************** Bit definition for FLASH_Data0 register *****************/ |
7833 |
/****************** Bit definition for FLASH_Data0 register *****************/ |
7834 |
#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */ |
7834 |
#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */ |
7835 |
#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */ |
7835 |
#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */ |
7836 |
|
7836 |
|
7837 |
/****************** Bit definition for FLASH_Data1 register *****************/ |
7837 |
/****************** Bit definition for FLASH_Data1 register *****************/ |
7838 |
#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */ |
7838 |
#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */ |
7839 |
#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */ |
7839 |
#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */ |
7840 |
|
7840 |
|
7841 |
/****************** Bit definition for FLASH_WRP0 register ******************/ |
7841 |
/****************** Bit definition for FLASH_WRP0 register ******************/ |
7842 |
#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */ |
7842 |
#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */ |
7843 |
#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */ |
7843 |
#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */ |
7844 |
|
7844 |
|
7845 |
/****************** Bit definition for FLASH_WRP1 register ******************/ |
7845 |
/****************** Bit definition for FLASH_WRP1 register ******************/ |
7846 |
#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */ |
7846 |
#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */ |
7847 |
#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */ |
7847 |
#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */ |
7848 |
|
7848 |
|
7849 |
/****************** Bit definition for FLASH_WRP2 register ******************/ |
7849 |
/****************** Bit definition for FLASH_WRP2 register ******************/ |
7850 |
#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */ |
7850 |
#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */ |
7851 |
#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */ |
7851 |
#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */ |
7852 |
|
7852 |
|
7853 |
/****************** Bit definition for FLASH_WRP3 register ******************/ |
7853 |
/****************** Bit definition for FLASH_WRP3 register ******************/ |
7854 |
#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */ |
7854 |
#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */ |
7855 |
#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */ |
7855 |
#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */ |
7856 |
|
7856 |
|
7857 |
#ifdef STM32F10X_CL |
7857 |
#ifdef STM32F10X_CL |
7858 |
/******************************************************************************/ |
7858 |
/******************************************************************************/ |
7859 |
/* Ethernet MAC Registers bits definitions */ |
7859 |
/* Ethernet MAC Registers bits definitions */ |
7860 |
/******************************************************************************/ |
7860 |
/******************************************************************************/ |
7861 |
/* Bit definition for Ethernet MAC Control Register register */ |
7861 |
/* Bit definition for Ethernet MAC Control Register register */ |
7862 |
#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
7862 |
#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
7863 |
#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
7863 |
#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
7864 |
#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
7864 |
#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
7865 |
#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
7865 |
#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
7866 |
#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
7866 |
#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
7867 |
#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
7867 |
#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
7868 |
#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
7868 |
#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
7869 |
#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
7869 |
#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
7870 |
#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
7870 |
#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
7871 |
#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
7871 |
#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
7872 |
#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
7872 |
#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
7873 |
#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
7873 |
#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
7874 |
#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
7874 |
#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
7875 |
#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
7875 |
#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
7876 |
#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
7876 |
#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
7877 |
#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
7877 |
#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
7878 |
#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
7878 |
#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
7879 |
#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
7879 |
#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
7880 |
#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
7880 |
#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
7881 |
#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling |
7881 |
#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling |
7882 |
a transmission attempt during retries after a collision: 0 =< r <2^k */ |
7882 |
a transmission attempt during retries after a collision: 0 =< r <2^k */ |
7883 |
#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
7883 |
#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
7884 |
#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
7884 |
#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
7885 |
#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
7885 |
#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
7886 |
#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
7886 |
#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
7887 |
#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
7887 |
#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
7888 |
#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
7888 |
#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
7889 |
#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
7889 |
#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
7890 |
|
7890 |
|
7891 |
/* Bit definition for Ethernet MAC Frame Filter Register */ |
7891 |
/* Bit definition for Ethernet MAC Frame Filter Register */ |
7892 |
#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
7892 |
#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
7893 |
#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
7893 |
#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
7894 |
#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
7894 |
#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
7895 |
#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
7895 |
#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
7896 |
#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
7896 |
#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
7897 |
#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
7897 |
#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
7898 |
#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
7898 |
#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
7899 |
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
7899 |
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
7900 |
#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
7900 |
#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
7901 |
#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
7901 |
#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
7902 |
#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
7902 |
#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
7903 |
#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
7903 |
#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
7904 |
#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
7904 |
#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
7905 |
#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
7905 |
#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
7906 |
|
7906 |
|
7907 |
/* Bit definition for Ethernet MAC Hash Table High Register */ |
7907 |
/* Bit definition for Ethernet MAC Hash Table High Register */ |
7908 |
#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
7908 |
#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
7909 |
|
7909 |
|
7910 |
/* Bit definition for Ethernet MAC Hash Table Low Register */ |
7910 |
/* Bit definition for Ethernet MAC Hash Table Low Register */ |
7911 |
#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
7911 |
#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
7912 |
|
7912 |
|
7913 |
/* Bit definition for Ethernet MAC MII Address Register */ |
7913 |
/* Bit definition for Ethernet MAC MII Address Register */ |
7914 |
#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
7914 |
#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
7915 |
#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
7915 |
#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
7916 |
#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
7916 |
#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
7917 |
#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ |
7917 |
#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ |
7918 |
#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
7918 |
#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
7919 |
#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
7919 |
#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
7920 |
#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
7920 |
#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
7921 |
#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
7921 |
#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
7922 |
|
7922 |
|
7923 |
/* Bit definition for Ethernet MAC MII Data Register */ |
7923 |
/* Bit definition for Ethernet MAC MII Data Register */ |
7924 |
#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
7924 |
#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
7925 |
|
7925 |
|
7926 |
/* Bit definition for Ethernet MAC Flow Control Register */ |
7926 |
/* Bit definition for Ethernet MAC Flow Control Register */ |
7927 |
#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
7927 |
#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
7928 |
#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
7928 |
#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
7929 |
#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
7929 |
#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
7930 |
#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
7930 |
#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
7931 |
#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
7931 |
#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
7932 |
#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
7932 |
#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
7933 |
#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
7933 |
#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
7934 |
#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
7934 |
#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
7935 |
#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
7935 |
#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
7936 |
#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
7936 |
#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
7937 |
#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
7937 |
#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
7938 |
|
7938 |
|
7939 |
/* Bit definition for Ethernet MAC VLAN Tag Register */ |
7939 |
/* Bit definition for Ethernet MAC VLAN Tag Register */ |
7940 |
#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
7940 |
#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
7941 |
#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
7941 |
#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
7942 |
|
7942 |
|
7943 |
/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ |
7943 |
/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ |
7944 |
#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
7944 |
#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
7945 |
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. |
7945 |
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. |
7946 |
Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ |
7946 |
Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ |
7947 |
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask |
7947 |
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask |
7948 |
Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask |
7948 |
Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask |
7949 |
Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask |
7949 |
Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask |
7950 |
Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask |
7950 |
Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask |
7951 |
Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - |
7951 |
Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - |
7952 |
RSVD - Filter1 Command - RSVD - Filter0 Command |
7952 |
RSVD - Filter1 Command - RSVD - Filter0 Command |
7953 |
Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset |
7953 |
Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset |
7954 |
Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 |
7954 |
Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 |
7955 |
Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ |
7955 |
Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ |
7956 |
|
7956 |
|
7957 |
/* Bit definition for Ethernet MAC PMT Control and Status Register */ |
7957 |
/* Bit definition for Ethernet MAC PMT Control and Status Register */ |
7958 |
#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
7958 |
#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
7959 |
#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
7959 |
#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
7960 |
#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
7960 |
#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
7961 |
#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
7961 |
#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
7962 |
#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
7962 |
#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
7963 |
#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
7963 |
#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
7964 |
#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
7964 |
#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
7965 |
|
7965 |
|
7966 |
/* Bit definition for Ethernet MAC Status Register */ |
7966 |
/* Bit definition for Ethernet MAC Status Register */ |
7967 |
#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
7967 |
#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
7968 |
#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
7968 |
#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
7969 |
#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
7969 |
#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
7970 |
#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
7970 |
#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
7971 |
#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
7971 |
#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
7972 |
|
7972 |
|
7973 |
/* Bit definition for Ethernet MAC Interrupt Mask Register */ |
7973 |
/* Bit definition for Ethernet MAC Interrupt Mask Register */ |
7974 |
#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
7974 |
#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
7975 |
#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
7975 |
#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
7976 |
|
7976 |
|
7977 |
/* Bit definition for Ethernet MAC Address0 High Register */ |
7977 |
/* Bit definition for Ethernet MAC Address0 High Register */ |
7978 |
#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
7978 |
#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
7979 |
|
7979 |
|
7980 |
/* Bit definition for Ethernet MAC Address0 Low Register */ |
7980 |
/* Bit definition for Ethernet MAC Address0 Low Register */ |
7981 |
#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
7981 |
#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
7982 |
|
7982 |
|
7983 |
/* Bit definition for Ethernet MAC Address1 High Register */ |
7983 |
/* Bit definition for Ethernet MAC Address1 High Register */ |
7984 |
#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
7984 |
#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
7985 |
#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
7985 |
#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
7986 |
#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
7986 |
#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
7987 |
#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
7987 |
#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
7988 |
#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
7988 |
#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
7989 |
#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
7989 |
#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
7990 |
#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
7990 |
#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
7991 |
#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
7991 |
#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
7992 |
#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
7992 |
#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
7993 |
#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
7993 |
#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
7994 |
|
7994 |
|
7995 |
/* Bit definition for Ethernet MAC Address1 Low Register */ |
7995 |
/* Bit definition for Ethernet MAC Address1 Low Register */ |
7996 |
#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
7996 |
#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
7997 |
|
7997 |
|
7998 |
/* Bit definition for Ethernet MAC Address2 High Register */ |
7998 |
/* Bit definition for Ethernet MAC Address2 High Register */ |
7999 |
#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
7999 |
#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
8000 |
#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
8000 |
#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
8001 |
#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
8001 |
#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
8002 |
#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
8002 |
#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
8003 |
#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
8003 |
#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
8004 |
#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
8004 |
#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
8005 |
#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
8005 |
#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
8006 |
#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
8006 |
#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
8007 |
#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
8007 |
#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
8008 |
#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
8008 |
#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
8009 |
|
8009 |
|
8010 |
/* Bit definition for Ethernet MAC Address2 Low Register */ |
8010 |
/* Bit definition for Ethernet MAC Address2 Low Register */ |
8011 |
#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
8011 |
#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
8012 |
|
8012 |
|
8013 |
/* Bit definition for Ethernet MAC Address3 High Register */ |
8013 |
/* Bit definition for Ethernet MAC Address3 High Register */ |
8014 |
#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
8014 |
#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
8015 |
#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
8015 |
#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
8016 |
#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
8016 |
#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
8017 |
#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
8017 |
#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
8018 |
#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
8018 |
#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
8019 |
#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
8019 |
#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
8020 |
#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
8020 |
#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
8021 |
#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
8021 |
#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
8022 |
#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
8022 |
#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
8023 |
#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
8023 |
#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
8024 |
|
8024 |
|
8025 |
/* Bit definition for Ethernet MAC Address3 Low Register */ |
8025 |
/* Bit definition for Ethernet MAC Address3 Low Register */ |
8026 |
#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
8026 |
#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
8027 |
|
8027 |
|
8028 |
/******************************************************************************/ |
8028 |
/******************************************************************************/ |
8029 |
/* Ethernet MMC Registers bits definition */ |
8029 |
/* Ethernet MMC Registers bits definition */ |
8030 |
/******************************************************************************/ |
8030 |
/******************************************************************************/ |
8031 |
|
8031 |
|
8032 |
/* Bit definition for Ethernet MMC Contol Register */ |
8032 |
/* Bit definition for Ethernet MMC Contol Register */ |
8033 |
#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
8033 |
#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
8034 |
#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
8034 |
#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
8035 |
#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
8035 |
#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
8036 |
#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
8036 |
#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
8037 |
|
8037 |
|
8038 |
/* Bit definition for Ethernet MMC Receive Interrupt Register */ |
8038 |
/* Bit definition for Ethernet MMC Receive Interrupt Register */ |
8039 |
#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
8039 |
#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
8040 |
#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
8040 |
#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
8041 |
#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
8041 |
#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
8042 |
|
8042 |
|
8043 |
/* Bit definition for Ethernet MMC Transmit Interrupt Register */ |
8043 |
/* Bit definition for Ethernet MMC Transmit Interrupt Register */ |
8044 |
#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
8044 |
#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
8045 |
#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
8045 |
#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
8046 |
#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
8046 |
#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
8047 |
|
8047 |
|
8048 |
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ |
8048 |
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ |
8049 |
#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
8049 |
#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
8050 |
#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
8050 |
#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
8051 |
#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
8051 |
#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
8052 |
|
8052 |
|
8053 |
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ |
8053 |
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ |
8054 |
#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
8054 |
#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
8055 |
#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
8055 |
#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
8056 |
#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
8056 |
#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
8057 |
|
8057 |
|
8058 |
/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ |
8058 |
/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ |
8059 |
#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
8059 |
#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
8060 |
|
8060 |
|
8061 |
/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ |
8061 |
/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ |
8062 |
#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
8062 |
#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
8063 |
|
8063 |
|
8064 |
/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ |
8064 |
/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ |
8065 |
#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
8065 |
#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
8066 |
|
8066 |
|
8067 |
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ |
8067 |
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ |
8068 |
#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
8068 |
#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
8069 |
|
8069 |
|
8070 |
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ |
8070 |
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ |
8071 |
#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
8071 |
#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
8072 |
|
8072 |
|
8073 |
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ |
8073 |
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ |
8074 |
#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
8074 |
#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
8075 |
|
8075 |
|
8076 |
/******************************************************************************/ |
8076 |
/******************************************************************************/ |
8077 |
/* Ethernet PTP Registers bits definition */ |
8077 |
/* Ethernet PTP Registers bits definition */ |
8078 |
/******************************************************************************/ |
8078 |
/******************************************************************************/ |
8079 |
|
8079 |
|
8080 |
/* Bit definition for Ethernet PTP Time Stamp Contol Register */ |
8080 |
/* Bit definition for Ethernet PTP Time Stamp Contol Register */ |
8081 |
#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
8081 |
#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
8082 |
#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
8082 |
#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
8083 |
#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
8083 |
#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
8084 |
#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
8084 |
#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
8085 |
#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
8085 |
#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
8086 |
#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
8086 |
#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
8087 |
|
8087 |
|
8088 |
/* Bit definition for Ethernet PTP Sub-Second Increment Register */ |
8088 |
/* Bit definition for Ethernet PTP Sub-Second Increment Register */ |
8089 |
#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
8089 |
#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
8090 |
|
8090 |
|
8091 |
/* Bit definition for Ethernet PTP Time Stamp High Register */ |
8091 |
/* Bit definition for Ethernet PTP Time Stamp High Register */ |
8092 |
#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
8092 |
#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
8093 |
|
8093 |
|
8094 |
/* Bit definition for Ethernet PTP Time Stamp Low Register */ |
8094 |
/* Bit definition for Ethernet PTP Time Stamp Low Register */ |
8095 |
#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
8095 |
#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
8096 |
#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
8096 |
#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
8097 |
|
8097 |
|
8098 |
/* Bit definition for Ethernet PTP Time Stamp High Update Register */ |
8098 |
/* Bit definition for Ethernet PTP Time Stamp High Update Register */ |
8099 |
#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
8099 |
#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
8100 |
|
8100 |
|
8101 |
/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ |
8101 |
/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ |
8102 |
#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
8102 |
#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
8103 |
#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
8103 |
#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
8104 |
|
8104 |
|
8105 |
/* Bit definition for Ethernet PTP Time Stamp Addend Register */ |
8105 |
/* Bit definition for Ethernet PTP Time Stamp Addend Register */ |
8106 |
#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
8106 |
#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
8107 |
|
8107 |
|
8108 |
/* Bit definition for Ethernet PTP Target Time High Register */ |
8108 |
/* Bit definition for Ethernet PTP Target Time High Register */ |
8109 |
#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
8109 |
#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
8110 |
|
8110 |
|
8111 |
/* Bit definition for Ethernet PTP Target Time Low Register */ |
8111 |
/* Bit definition for Ethernet PTP Target Time Low Register */ |
8112 |
#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
8112 |
#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
8113 |
|
8113 |
|
8114 |
/******************************************************************************/ |
8114 |
/******************************************************************************/ |
8115 |
/* Ethernet DMA Registers bits definition */ |
8115 |
/* Ethernet DMA Registers bits definition */ |
8116 |
/******************************************************************************/ |
8116 |
/******************************************************************************/ |
8117 |
|
8117 |
|
8118 |
/* Bit definition for Ethernet DMA Bus Mode Register */ |
8118 |
/* Bit definition for Ethernet DMA Bus Mode Register */ |
8119 |
#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
8119 |
#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
8120 |
#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
8120 |
#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
8121 |
#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
8121 |
#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
8122 |
#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
8122 |
#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
8123 |
#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
8123 |
#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
8124 |
#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
8124 |
#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
8125 |
#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
8125 |
#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
8126 |
#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
8126 |
#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
8127 |
#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
8127 |
#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
8128 |
#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
8128 |
#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
8129 |
#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
8129 |
#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
8130 |
#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
8130 |
#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
8131 |
#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
8131 |
#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
8132 |
#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
8132 |
#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
8133 |
#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
8133 |
#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
8134 |
#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
8134 |
#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
8135 |
#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
8135 |
#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
8136 |
#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
8136 |
#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
8137 |
#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
8137 |
#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
8138 |
#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
8138 |
#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
8139 |
#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
8139 |
#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
8140 |
#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
8140 |
#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
8141 |
#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
8141 |
#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
8142 |
#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
8142 |
#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
8143 |
#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
8143 |
#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
8144 |
#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
8144 |
#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
8145 |
#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
8145 |
#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
8146 |
#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
8146 |
#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
8147 |
#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
8147 |
#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
8148 |
#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
8148 |
#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
8149 |
#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
8149 |
#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
8150 |
#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
8150 |
#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
8151 |
#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
8151 |
#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
8152 |
#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
8152 |
#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
8153 |
#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
8153 |
#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
8154 |
#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
8154 |
#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
8155 |
#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
8155 |
#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
8156 |
#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
8156 |
#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
8157 |
|
8157 |
|
8158 |
/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ |
8158 |
/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ |
8159 |
#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
8159 |
#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
8160 |
|
8160 |
|
8161 |
/* Bit definition for Ethernet DMA Receive Poll Demand Register */ |
8161 |
/* Bit definition for Ethernet DMA Receive Poll Demand Register */ |
8162 |
#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
8162 |
#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
8163 |
|
8163 |
|
8164 |
/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ |
8164 |
/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ |
8165 |
#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
8165 |
#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
8166 |
|
8166 |
|
8167 |
/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ |
8167 |
/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ |
8168 |
#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
8168 |
#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
8169 |
|
8169 |
|
8170 |
/* Bit definition for Ethernet DMA Status Register */ |
8170 |
/* Bit definition for Ethernet DMA Status Register */ |
8171 |
#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
8171 |
#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
8172 |
#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
8172 |
#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
8173 |
#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
8173 |
#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
8174 |
#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
8174 |
#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
8175 |
/* combination with EBS[2:0] for GetFlagStatus function */ |
8175 |
/* combination with EBS[2:0] for GetFlagStatus function */ |
8176 |
#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
8176 |
#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
8177 |
#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
8177 |
#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
8178 |
#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
8178 |
#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
8179 |
#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
8179 |
#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
8180 |
#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
8180 |
#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
8181 |
#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
8181 |
#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
8182 |
#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
8182 |
#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
8183 |
#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
8183 |
#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
8184 |
#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
8184 |
#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
8185 |
#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
8185 |
#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
8186 |
#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
8186 |
#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
8187 |
#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
8187 |
#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
8188 |
#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
8188 |
#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
8189 |
#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
8189 |
#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
8190 |
#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
8190 |
#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
8191 |
#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
8191 |
#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
8192 |
#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
8192 |
#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
8193 |
#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
8193 |
#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
8194 |
#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
8194 |
#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
8195 |
#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
8195 |
#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
8196 |
#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
8196 |
#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
8197 |
#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
8197 |
#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
8198 |
#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
8198 |
#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
8199 |
#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
8199 |
#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
8200 |
#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
8200 |
#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
8201 |
#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
8201 |
#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
8202 |
#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
8202 |
#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
8203 |
#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
8203 |
#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
8204 |
#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
8204 |
#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
8205 |
#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
8205 |
#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
8206 |
#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
8206 |
#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
8207 |
#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
8207 |
#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
8208 |
|
8208 |
|
8209 |
/* Bit definition for Ethernet DMA Operation Mode Register */ |
8209 |
/* Bit definition for Ethernet DMA Operation Mode Register */ |
8210 |
#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
8210 |
#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
8211 |
#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
8211 |
#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
8212 |
#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
8212 |
#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
8213 |
#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
8213 |
#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
8214 |
#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
8214 |
#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
8215 |
#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
8215 |
#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
8216 |
#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
8216 |
#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
8217 |
#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
8217 |
#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
8218 |
#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
8218 |
#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
8219 |
#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
8219 |
#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
8220 |
#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
8220 |
#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
8221 |
#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
8221 |
#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
8222 |
#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
8222 |
#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
8223 |
#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
8223 |
#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
8224 |
#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
8224 |
#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
8225 |
#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
8225 |
#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
8226 |
#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
8226 |
#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
8227 |
#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
8227 |
#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
8228 |
#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
8228 |
#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
8229 |
#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
8229 |
#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
8230 |
#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
8230 |
#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
8231 |
#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
8231 |
#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
8232 |
#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
8232 |
#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
8233 |
#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
8233 |
#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
8234 |
|
8234 |
|
8235 |
/* Bit definition for Ethernet DMA Interrupt Enable Register */ |
8235 |
/* Bit definition for Ethernet DMA Interrupt Enable Register */ |
8236 |
#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
8236 |
#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
8237 |
#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
8237 |
#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
8238 |
#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
8238 |
#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
8239 |
#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
8239 |
#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
8240 |
#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
8240 |
#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
8241 |
#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
8241 |
#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
8242 |
#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
8242 |
#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
8243 |
#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
8243 |
#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
8244 |
#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
8244 |
#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
8245 |
#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
8245 |
#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
8246 |
#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
8246 |
#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
8247 |
#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
8247 |
#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
8248 |
#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
8248 |
#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
8249 |
#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
8249 |
#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
8250 |
#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
8250 |
#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
8251 |
|
8251 |
|
8252 |
/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ |
8252 |
/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ |
8253 |
#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
8253 |
#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
8254 |
#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
8254 |
#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
8255 |
#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
8255 |
#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
8256 |
#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
8256 |
#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
8257 |
|
8257 |
|
8258 |
/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ |
8258 |
/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ |
8259 |
#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
8259 |
#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
8260 |
|
8260 |
|
8261 |
/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ |
8261 |
/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ |
8262 |
#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
8262 |
#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
8263 |
|
8263 |
|
8264 |
/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ |
8264 |
/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ |
8265 |
#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
8265 |
#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
8266 |
|
8266 |
|
8267 |
/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ |
8267 |
/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ |
8268 |
#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
8268 |
#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
8269 |
#endif /* STM32F10X_CL */ |
8269 |
#endif /* STM32F10X_CL */ |
8270 |
|
8270 |
|
8271 |
/** |
8271 |
/** |
8272 |
* @} |
8272 |
* @} |
8273 |
*/ |
8273 |
*/ |
8274 |
|
8274 |
|
8275 |
/** |
8275 |
/** |
8276 |
* @} |
8276 |
* @} |
8277 |
*/ |
8277 |
*/ |
8278 |
|
8278 |
|
8279 |
#ifdef USE_STDPERIPH_DRIVER |
8279 |
#ifdef USE_STDPERIPH_DRIVER |
8280 |
#include "stm32f10x_conf.h" |
8280 |
#include "stm32f10x_conf.h" |
8281 |
#endif |
8281 |
#endif |
8282 |
|
8282 |
|
8283 |
/** @addtogroup Exported_macro |
8283 |
/** @addtogroup Exported_macro |
8284 |
* @{ |
8284 |
* @{ |
8285 |
*/ |
8285 |
*/ |
8286 |
|
8286 |
|
8287 |
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
8287 |
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
8288 |
|
8288 |
|
8289 |
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
8289 |
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
8290 |
|
8290 |
|
8291 |
#define READ_BIT(REG, BIT) ((REG) & (BIT)) |
8291 |
#define READ_BIT(REG, BIT) ((REG) & (BIT)) |
8292 |
|
8292 |
|
8293 |
#define CLEAR_REG(REG) ((REG) = (0x0)) |
8293 |
#define CLEAR_REG(REG) ((REG) = (0x0)) |
8294 |
|
8294 |
|
8295 |
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
8295 |
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
8296 |
|
8296 |
|
8297 |
#define READ_REG(REG) ((REG)) |
8297 |
#define READ_REG(REG) ((REG)) |
8298 |
|
8298 |
|
8299 |
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
8299 |
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
8300 |
|
8300 |
|
8301 |
/** |
8301 |
/** |
8302 |
* @} |
8302 |
* @} |
8303 |
*/ |
8303 |
*/ |
8304 |
|
8304 |
|
8305 |
#ifdef __cplusplus |
8305 |
#ifdef __cplusplus |
8306 |
} |
8306 |
} |
8307 |
#endif |
8307 |
#endif |
8308 |
|
8308 |
|
8309 |
#endif /* __STM32F10x_H */ |
8309 |
#endif /* __STM32F10x_H */ |
8310 |
|
8310 |
|
8311 |
/** |
8311 |
/** |
8312 |
* @} |
8312 |
* @} |
8313 |
*/ |
8313 |
*/ |
8314 |
|
8314 |
|
8315 |
/** |
8315 |
/** |
8316 |
* @} |
8316 |
* @} |
8317 |
*/ |
8317 |
*/ |
8318 |
|
8318 |
|
8319 |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |
8319 |
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ |