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//struct { |
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//struct { |
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unsigned int8 firenum=TDC_FIRENUM_0; |
3 |
unsigned int8 firenum=TDC_FIRENUM_0; |
4 |
unsigned int8 div_fire=TDC_DIV_FIRE_2; |
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unsigned int8 div_fire=TDC_DIV_FIRE_2; |
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unsigned int8 calresnum=TDC_CALPERIODS_2; |
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unsigned int8 calresnum=TDC_CALPERIODS_2; |
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unsigned int8 clkhsdiv=TDC_CLKHSDIV_1; |
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unsigned int8 clkhsdiv=TDC_CLKHSDIV_1; |
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unsigned int8 start_clkhs=TDC_CLKHS_ON; |
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unsigned int8 start_clkhs=TDC_CLKHS_ON; |
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unsigned int1 portnum=TDC_TPORTNUM_4; |
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unsigned int1 portnum=TDC_TPORTNUM_4; |
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unsigned int1 Tcycle=TDC_TCYCLE_SHORT; |
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unsigned int1 Tcycle=TDC_TCYCLE_SHORT; |
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unsigned int1 fakenum=TDC_TFAKENUM_2; |
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unsigned int1 fakenum=TDC_TFAKENUM_2; |
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unsigned int1 selclkT=TDC_TSELCLK_128HS; |
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unsigned int1 selclkT=TDC_TSELCLK_128HS; |
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unsigned int1 calibrate=TDC_CALIBRATE_EN; |
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unsigned int1 calibrate=TDC_CALIBRATE_EN; |
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unsigned int1 disautocal=TDC_AUTOCAL_EN; |
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unsigned int1 disautocal=TDC_AUTOCAL_EN; |
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unsigned int1 MRange=TDC_MRANGE2; |
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unsigned int1 MRange=TDC_MRANGE2; |
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unsigned int1 neg_stop2=TDC_NEG_STOP2; |
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unsigned int1 neg_stop2=TDC_NEG_STOP2; |
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unsigned int1 neg_stop1=TDC_NEG_STOP1; |
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unsigned int1 neg_stop1=TDC_NEG_STOP1; |
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unsigned int1 neg_start=TDC_NEG_START; |
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unsigned int1 neg_start=TDC_NEG_START; |
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//}reg0; |
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//}reg0; |
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|
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|
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//struct { |
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//struct { |
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unsigned int hit2=TDC_MRANGE1_HIT2_NOAC; |
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unsigned int hit2=TDC_MRANGE1_HIT2_NOAC; |
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unsigned int hit1=TDC_MRANGE1_HIT1_NOAC; |
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unsigned int hit1=TDC_MRANGE1_HIT1_NOAC; |
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unsigned int1 fast_init=TDC_FAST_INIT_DIS; |
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unsigned int1 fast_init=TDC_FAST_INIT_DIS; |
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unsigned int hitin2=TDC_HITIN2_0; |
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unsigned int hitin2=TDC_HITIN2_0; |
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unsigned int hitin1=TDC_HITIN1_0; |
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unsigned int hitin1=TDC_HITIN1_0; |
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//}reg1; |
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//}reg1; |
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|
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|
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//struct { |
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//struct { |
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unsigned int en_int=TDC_INT_ALU; |
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unsigned int en_int=TDC_INT_ALU; |
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unsigned int1 rfedge2=TDC_CH2EDGE_RIS; |
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unsigned int1 rfedge2=TDC_CH2EDGE_RIS; |
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unsigned int1 rfedge1=TDC_CH1EDGE_RIS; |
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unsigned int1 rfedge1=TDC_CH1EDGE_RIS; |
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unsigned int32 delval1=0; |
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unsigned int32 delval1=0; |
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//}reg2; |
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//}reg2; |
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|
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|
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//struct { |
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//struct { |
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unsigned int1 en_err_val=TDC_ERRVAL_DIS; |
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unsigned int1 en_err_val=TDC_ERRVAL_DIS; |
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unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS; |
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unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS; |
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unsigned int32 delval2=0; |
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unsigned int32 delval2=0; |
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//}reg3; |
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//}reg3; |
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|
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|
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//reg4 |
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//reg4 |
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unsigned int32 delval3=0; |
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unsigned int32 delval3=0; |
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|
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|
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//reg5 |
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//reg5 |
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unsigned int conf_fire=0; |
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unsigned int conf_fire=0; |
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unsigned int1 en_startnoise=TDC_STARTNOISE_DIS; |
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unsigned int1 en_startnoise=TDC_STARTNOISE_DIS; |
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unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS; |
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unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS; |
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unsigned int repeat_fire=TDC_REPEAT_FIRE_0; |
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unsigned int repeat_fire=TDC_REPEAT_FIRE_0; |
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unsigned int16 phase_fire; |
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unsigned int16 phase_fire; |
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|
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|
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//}TDC_registers; |
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//}TDC_registers; |
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|
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|
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|
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|
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void TDC_init() |
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void TDC_init() |
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{ |
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{ |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x70); |
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spi_xfer(TDC_stream,0x70,8); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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} |
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} |
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|
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|
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void TDC_reset() |
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void TDC_reset() |
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{ |
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{ |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x50); |
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spi_xfer(TDC_stream,0x50,8); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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} |
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} |
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|
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|
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void TDC_start_cycle() |
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void TDC_start_cycle() |
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{ |
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{ |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x01); |
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spi_xfer(TDC_stream,0x01,8); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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} |
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} |
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|
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|
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void TDC_start_temp() |
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void TDC_start_temp() |
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{ |
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{ |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x02); |
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spi_xfer(TDC_stream,0x02,8); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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} |
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} |
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|
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|
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void TDC_start_cal_resonator() |
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void TDC_start_cal_resonator() |
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{ |
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{ |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x03); |
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spi_xfer(TDC_stream,0x03,8); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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} |
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} |
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|
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|
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void TDC_start_cal() |
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void TDC_start_cal() |
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{ |
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{ |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x04); |
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spi_xfer(TDC_stream,0x04,8); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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} |
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} |
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|
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|
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unsigned int32 TDC_get_measurement(int num) |
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unsigned int32 TDC_get_measurement(int num) |
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{ |
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{ |
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unsigned int32 ret; |
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unsigned int32 ret; |
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|
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|
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0xB0 + num - 1); |
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spi_xfer(TDC_stream,0xB0 + num - 1); |
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ret=spi_xfer(TDC_stream,0,32); |
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ret=spi_xfer(TDC_stream,0,32); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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return ret; |
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return ret; |
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} |
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} |
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|
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|
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unsigned int16 TDC_get_status() |
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unsigned int16 TDC_get_status() |
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{ |
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{ |
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unsigned int16 ret; |
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unsigned int16 ret; |
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|
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|
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0xB4,8); |
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spi_xfer(TDC_stream,0xB4,8); |
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ret=spi_xfer(TDC_stream,0,16); |
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ret=spi_xfer(TDC_stream,0,16); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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return ret; |
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return ret; |
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} |
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} |
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|
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|
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unsigned int8 TDC_get_reg1() |
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unsigned int8 TDC_get_reg1() |
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{ |
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{ |
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unsigned int8 ret; |
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unsigned int8 ret; |
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|
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|
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0xB5,8); |
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spi_xfer(TDC_stream,0xB5,8); |
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ret=spi_xfer(TDC_stream,0,8); |
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ret=spi_xfer(TDC_stream,0,8); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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return ret; |
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return ret; |
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} |
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} |
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|
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|
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void TDC_update_registers() |
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void TDC_update_registers() |
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{ |
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{ |
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//update reg0 |
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//update reg0 |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x80,8); |
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spi_xfer(TDC_stream,0x80,8); |
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spi_xfer(TDC_stream,firenum,4); |
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spi_xfer(TDC_stream,firenum,4); |
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spi_xfer(TDC_stream,div_fire,4); |
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spi_xfer(TDC_stream,div_fire,4); |
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spi_xfer(TDC_stream,calresnum,2); |
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spi_xfer(TDC_stream,calresnum,2); |
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spi_xfer(TDC_stream,clkhsdiv,2); |
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spi_xfer(TDC_stream,clkhsdiv,2); |
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spi_xfer(TDC_stream,start_clkhs,2); |
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spi_xfer(TDC_stream,start_clkhs,2); |
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spi_xfer(TDC_stream,portnum,1); |
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spi_xfer(TDC_stream,portnum,1); |
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spi_xfer(TDC_stream,Tcycle,1); |
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spi_xfer(TDC_stream,Tcycle,1); |
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spi_xfer(TDC_stream,fakenum,1); |
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spi_xfer(TDC_stream,fakenum,1); |
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spi_xfer(TDC_stream,selclkT,1); |
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spi_xfer(TDC_stream,selclkT,1); |
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spi_xfer(TDC_stream,calibrate,1); |
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spi_xfer(TDC_stream,calibrate,1); |
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spi_xfer(TDC_stream,disautocal,1); |
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spi_xfer(TDC_stream,disautocal,1); |
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spi_xfer(TDC_stream,MRange,1); |
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spi_xfer(TDC_stream,MRange,1); |
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spi_xfer(TDC_stream,neg_stop2,1); |
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spi_xfer(TDC_stream,neg_stop2,1); |
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spi_xfer(TDC_stream,neg_stop1,1); |
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spi_xfer(TDC_stream,neg_stop1,1); |
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spi_xfer(TDC_stream,neg_start,1); |
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spi_xfer(TDC_stream,neg_start,1); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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|
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|
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// update reg1 |
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// update reg1 |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x81,8); |
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spi_xfer(TDC_stream,0x81,8); |
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spi_xfer(TDC_stream,hit2,4); |
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spi_xfer(TDC_stream,hit2,4); |
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spi_xfer(TDC_stream,hit1,4); |
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spi_xfer(TDC_stream,hit1,4); |
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spi_xfer(TDC_stream,fast_init,1); |
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spi_xfer(TDC_stream,fast_init,1); |
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spi_xfer(TDC_stream,1,1); |
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spi_xfer(TDC_stream,1,1); |
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spi_xfer(TDC_stream,hitin2,3); |
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spi_xfer(TDC_stream,hitin2,3); |
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spi_xfer(TDC_stream,hitin1,3); |
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spi_xfer(TDC_stream,hitin1,3); |
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spi_xfer(TDC_stream,0,8); |
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spi_xfer(TDC_stream,0,8); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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|
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|
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// update reg2 |
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// update reg2 |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x82); |
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spi_xfer(TDC_stream,0x82); |
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spi_xfer(TDC_stream,en_int,3); |
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spi_xfer(TDC_stream,en_int,3); |
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spi_xfer(TDC_stream,rfedge2,1); |
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spi_xfer(TDC_stream,rfedge2,1); |
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spi_xfer(TDC_stream,rfedge1,1); |
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spi_xfer(TDC_stream,rfedge1,1); |
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spi_xfer(TDC_stream,delval1,19); |
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spi_xfer(TDC_stream,delval1,19); |
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output_high(TDC_ENABLE); |
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output_high(TDC_ENABLE); |
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|
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|
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// update reg3 |
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// update reg3 |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x83); |
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spi_xfer(TDC_stream,0x83); |
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spi_xfer(TDC_stream,0,2); |
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spi_xfer(TDC_stream,0,2); |
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spi_xfer(TDC_stream,en_err_val,1); |
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spi_xfer(TDC_stream,en_err_val,1); |
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spi_xfer(TDC_stream,tim0_mr2,2); |
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spi_xfer(TDC_stream,tim0_mr2,2); |
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spi_xfer(TDC_stream,delval2,19); |
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spi_xfer(TDC_stream,delval2,19); |
179 |
output_high(TDC_ENABLE); |
179 |
output_high(TDC_ENABLE); |
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|
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|
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// update reg4 |
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// update reg4 |
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output_low(TDC_ENABLE); |
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output_low(TDC_ENABLE); |
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spi_xfer(TDC_stream,0x84); |
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spi_xfer(TDC_stream,0x84); |
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spi_xfer(TDC_stream,0b00100,5); |
184 |
spi_xfer(TDC_stream,0b00100,5); |
185 |
spi_xfer(TDC_stream,delval3,19); |
185 |
spi_xfer(TDC_stream,delval3,19); |
186 |
output_high(TDC_ENABLE); |
186 |
output_high(TDC_ENABLE); |
187 |
|
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|
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// update reg5 |
188 |
// update reg5 |
189 |
output_low(TDC_ENABLE); |
189 |
output_low(TDC_ENABLE); |
190 |
spi_xfer(TDC_stream,0x85); |
190 |
spi_xfer(TDC_stream,0x85); |
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spi_xfer(TDC_stream,conf_fire,3); |
191 |
spi_xfer(TDC_stream,conf_fire,3); |
192 |
spi_xfer(TDC_stream,en_startnoise,1); |
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spi_xfer(TDC_stream,en_startnoise,1); |
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spi_xfer(TDC_stream,dis_phasenoise,1); |
193 |
spi_xfer(TDC_stream,dis_phasenoise,1); |
194 |
spi_xfer(TDC_stream,repeat_fire,3); |
194 |
spi_xfer(TDC_stream,repeat_fire,3); |
195 |
spi_xfer(TDC_stream,phase_fire,16); |
195 |
spi_xfer(TDC_stream,phase_fire,16); |
196 |
output_high(TDC_ENABLE); |
196 |
output_high(TDC_ENABLE); |
197 |
} |
197 |
} |
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|
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