Rev 1756 Rev 1757
-   1  
-   2 //struct {
-   3 unsigned int8 firenum;
-   4 unsigned int8 div_fire;
-   5 unsigned int8 calresnum :2;
-   6 unsigned int8 clkhsdiv ;
-   7 unsigned int8 start_clkhs:1;
-   8 unsigned int8 portnum :1;
-   9 unsigned int8 Tcycle :1;
-   10 unsigned int8 fakenum :1;
-   11 unsigned int8 selclkT :1;
-   12 unsigned int8 calibrate :1;
-   13 unsigned int8 disautocal :1;
-   14 unsigned int8 MRange :1;
-   15 unsigned int8 neg_stop2 :1;
-   16 unsigned int8 neg_stop1 :1;
-   17 unsigned int8 neg_start :1;
-   18 //}reg0;
-   19  
-   20 //struct {
-   21 unsigned int hit2 :4;
-   22 unsigned int hit1 :4;
-   23 unsigned int fast_init :1;
-   24 unsigned int sc :1;
-   25 unsigned int hitin2 :3;
-   26 unsigned int hitin1 :3;
-   27 //}reg1;
-   28  
-   29 //struct {
-   30 unsigned int en_int :3;
-   31 unsigned int rfedge2 :1;
-   32 unsigned int rfedge1 :1;
-   33 unsigned int delval1 :3;
-   34 //}reg2;
-   35  
-   36 //struct {
-   37 unsigned int en_err_val :1;
-   38 unsigned int tim0_mr2 :2;
-   39 unsigned int32 delval :7;
-   40 //}reg3;
-   41  
-   42 //}TDC_registers;
-   43  
-   44  
1 void TDC_init() 45 void TDC_init()
2 { 46 {
3 output_low(TDC_ENABLE); 47 output_low(TDC_ENABLE);
4 spi_xfer(TDC_stream,0x70); 48 spi_xfer(TDC_stream,0x70);
5 output_high(TDC_ENABLE); 49 output_high(TDC_ENABLE);
6 } 50 }
7   51  
8 void TDC_reset() 52 void TDC_reset()
9 { 53 {
10 output_low(TDC_ENABLE); 54 output_low(TDC_ENABLE);
11 spi_xfer(TDC_stream,0x50); 55 spi_xfer(TDC_stream,0x50);
12 output_high(TDC_ENABLE); 56 output_high(TDC_ENABLE);
13 } 57 }
14   58  
15 void TDC_start_cycle() 59 void TDC_start_cycle()
16 { 60 {
17 output_low(TDC_ENABLE); 61 output_low(TDC_ENABLE);
18 spi_xfer(TDC_stream,0x01); 62 spi_xfer(TDC_stream,0x01);
19 output_high(TDC_ENABLE); 63 output_high(TDC_ENABLE);
20 } 64 }
21   65  
22 void TDC_start_temp() 66 void TDC_start_temp()
23 { 67 {
24 output_low(TDC_ENABLE); 68 output_low(TDC_ENABLE);
25 spi_xfer(TDC_stream,0x02); 69 spi_xfer(TDC_stream,0x02);
26 output_high(TDC_ENABLE); 70 output_high(TDC_ENABLE);
27 } 71 }
28   72  
29 void TDC_start_cal_resonator() 73 void TDC_start_cal_resonator()
30 { 74 {
31 output_low(TDC_ENABLE); 75 output_low(TDC_ENABLE);
32 spi_xfer(TDC_stream,0x03); 76 spi_xfer(TDC_stream,0x03);
33 output_high(TDC_ENABLE); 77 output_high(TDC_ENABLE);
34 } 78 }
35   79  
36 void TDC_start_cal() 80 void TDC_start_cal()
37 { 81 {
38 output_low(TDC_ENABLE); 82 output_low(TDC_ENABLE);
39 spi_xfer(TDC_stream,0x04); 83 spi_xfer(TDC_stream,0x04);
40 output_high(TDC_ENABLE); 84 output_high(TDC_ENABLE);
41 } 85 }
42   86  
43 unsigned int32 TDC_get_measurement(int num) 87 unsigned int32 TDC_get_measurement(int num)
44 { 88 {
45 unsigned int32 ret; 89 unsigned int32 ret;
46   90  
47 output_low(TDC_ENABLE); 91 output_low(TDC_ENABLE);
48 spi_xfer(TDC_stream,0xB0 + num - 1); 92 spi_xfer(TDC_stream,0xB0 + num - 1);
49 ret=spi_xfer(TDC_stream,0,32); 93 ret=spi_xfer(TDC_stream,0,32);
50 output_high(TDC_ENABLE); 94 output_high(TDC_ENABLE);
51 return ret; 95 return ret;
52 } 96 }
53   97  
54 unsigned int16 TDC_get_status() 98 unsigned int16 TDC_get_status()
55 { 99 {
56 unsigned int16 ret; 100 unsigned int16 ret;
57   101  
58 output_low(TDC_ENABLE); 102 output_low(TDC_ENABLE);
59 spi_xfer(TDC_stream,0xB4,8); 103 spi_xfer(TDC_stream,0xB4,8);
60 ret=spi_xfer(TDC_stream,0,16); 104 ret=spi_xfer(TDC_stream,0,16);
61 output_high(TDC_ENABLE); 105 output_high(TDC_ENABLE);
62 return ret; 106 return ret;
63 } 107 }
64   108  
65 unsigned int8 TDC_get_reg1() 109 unsigned int8 TDC_get_reg1()
66 { 110 {
67 unsigned int8 ret; 111 unsigned int8 ret;
68   112  
69 output_low(TDC_ENABLE); 113 output_low(TDC_ENABLE);
70 spi_xfer(TDC_stream,0xB5,8); 114 spi_xfer(TDC_stream,0xB5,8);
71 ret=spi_xfer(TDC_stream,0,8); 115 ret=spi_xfer(TDC_stream,0,8);
72 output_high(TDC_ENABLE); 116 output_high(TDC_ENABLE);
73 return ret; 117 return ret;
74 } 118 }
75   119  
76 void TDC_setup_reg1() 120 void TDC_update_registers()
77 { 121 {
78 output_low(TDC_ENABLE); 122 output_low(TDC_ENABLE);
79 spi_xfer(TDC_stream,0x81,8); 123 spi_xfer(TDC_stream,0x81,8);
80 spi_xfer(TDC_stream,0x224000,24); 124 spi_xfer(TDC_stream,reg1.*,24);
81 output_high(TDC_ENABLE); 125 output_high(TDC_ENABLE);
82   126  
83 output_low(TDC_ENABLE); 127 /* output_low(TDC_ENABLE);
84 spi_xfer(TDC_stream,0xB1); 128 spi_xfer(TDC_stream,0xB1);
85 output_high(TDC_ENABLE); 129 output_high(TDC_ENABLE);
86   130  
87 output_low(TDC_ENABLE); 131 output_low(TDC_ENABLE);
88 spi_xfer(TDC_stream,0xB2); 132 spi_xfer(TDC_stream,0xB2);
89 output_high(TDC_ENABLE); 133 output_high(TDC_ENABLE);
90   134  
91 output_low(TDC_ENABLE); 135 output_low(TDC_ENABLE);
92 spi_xfer(TDC_stream,0xB3); 136 spi_xfer(TDC_stream,0xB3);
93 output_high(TDC_ENABLE); 137 output_high(TDC_ENABLE);
94   138  
95 output_low(TDC_ENABLE); 139 output_low(TDC_ENABLE);
96 spi_xfer(TDC_stream,0xB4); 140 spi_xfer(TDC_stream,0xB4);
97 output_high(TDC_ENABLE); 141 output_high(TDC_ENABLE); */
-   142 }
-   143  
-   144 void TDC_set_firenum()
-   145 {
-   146 reg0.Tcycle=TDC_TCYCLE_SHORT;
98 } 147 }