1 |
/* mija 2008 |
1 |
/* mija 2008 |
2 |
demo for RFM02 - TX 868MHz |
2 |
demo for RFM02 - TX 868MHz |
3 |
|
3 |
|
4 |
CPU ATMEGA16 |
4 |
CPU ATMEGA16 |
5 |
fcpu = 1MHz |
5 |
fcpu = 1MHz |
6 |
|
6 |
|
7 |
!! define PIN,PORT,DDR for IOpin !! |
7 |
!! define PIN,PORT,DDR for IOpin !! |
8 |
|
8 |
|
9 |
tested with module RFM12B RX 9600 BW 134kHz |
9 |
tested with module RFM12B RX 9600 BW 134kHz |
10 |
*/ |
10 |
*/ |
11 |
|
11 |
|
12 |
#include <avr/io.h> |
12 |
#include <avr/io.h> |
13 |
#include <util/delay.h> |
13 |
#include <util/delay.h> |
14 |
#include "RFM02.h" |
14 |
#include "RFM02.h" |
15 |
|
15 |
|
16 |
#define F_CPU 1000000UL |
16 |
#define F_CPU 1000000UL |
17 |
|
17 |
|
18 |
//************************************************************************ |
18 |
//************************************************************************ |
19 |
|
19 |
|
20 |
#define SDI PB3 |
20 |
#define SDI PB3 |
21 |
#define SDI_PORT PORTB |
21 |
#define SDI_PORT PORTB |
22 |
#define SDI_DDR DDRB |
22 |
#define SDI_DDR DDRB |
23 |
|
23 |
|
24 |
#define FSK PC1 |
24 |
#define FSK PC1 |
25 |
#define FSK_PORT PORTC |
25 |
#define FSK_PORT PORTC |
26 |
#define FSK_DDR DDRC |
26 |
#define FSK_DDR DDRC |
27 |
|
27 |
|
28 |
#define SDO PB4 // input for mega |
28 |
#define SDO PB4 // input for mega |
29 |
#define SDO_PORT PORTB |
29 |
#define SDO_PORT PORTB |
30 |
#define SDO_DDR DDRB |
30 |
#define SDO_DDR DDRB |
31 |
#define SDO_PIN PINB |
31 |
#define SDO_PIN PINB |
32 |
|
32 |
|
33 |
#define SCK PB5 |
33 |
#define SCK PB5 |
34 |
#define SCK_PORT PORTB |
34 |
#define SCK_PORT PORTB |
35 |
#define SCK_DDR DDRB |
35 |
#define SCK_DDR DDRB |
36 |
|
36 |
|
37 |
#define nIRQ PD2 // input for mega |
37 |
#define nIRQ PD2 // input for mega |
38 |
#define nIRQ_PORT PORTD |
38 |
#define nIRQ_PORT PORTD |
39 |
#define nIRQ_DDR DDRD |
39 |
#define nIRQ_DDR DDRD |
40 |
#define nIRQ_PIN PIND |
40 |
#define nIRQ_PIN PIND |
41 |
|
41 |
|
42 |
#define nSEL PB2 |
42 |
#define nSEL PB2 |
43 |
#define nSEL_PORT PORTB |
43 |
#define nSEL_PORT PORTB |
44 |
#define nSEL_DDR DDRB |
44 |
#define nSEL_DDR DDRB |
45 |
|
45 |
|
46 |
#define LED PC3 |
46 |
#define LED PC3 |
47 |
#define LED_PORT PORTC |
47 |
#define LED_PORT PORTC |
48 |
#define LED_DDR DDRC |
48 |
#define LED_DDR DDRC |
49 |
|
49 |
|
50 |
// interni |
50 |
// interni |
51 |
#define SDI_H SDI_PORT |= _BV(SDI) |
51 |
#define SDI_H SDI_PORT |= _BV(SDI) |
52 |
#define SDI_L SDI_PORT &= (~(_BV(SDI))) |
52 |
#define SDI_L SDI_PORT &= (~(_BV(SDI))) |
53 |
#define SDI_INIT SDI_DDR |= _BV(SDI) |
53 |
#define SDI_INIT SDI_DDR |= _BV(SDI) |
54 |
|
54 |
|
55 |
#define FSK_H FSK_PORT |= _BV(FSK) |
55 |
#define FSK_H FSK_PORT |= _BV(FSK) |
56 |
#define FSK_L FSK_PORT &= (~(_BV(FSK))) |
56 |
#define FSK_L FSK_PORT &= (~(_BV(FSK))) |
57 |
#define FSK_INIT FSK_DDR |= _BV(FSK) |
57 |
#define FSK_INIT FSK_DDR |= _BV(FSK) |
58 |
|
58 |
|
59 |
#define SDO_INPUT (SDO_PIN & _BV(SDO)) |
59 |
#define SDO_INPUT (SDO_PIN & _BV(SDO)) |
60 |
#define SDO_INIT SDO_DDR &= (~(_BV(SDO))) |
60 |
#define SDO_INIT SDO_DDR &= (~(_BV(SDO))) |
61 |
|
61 |
|
62 |
#define SCK_H SCK_PORT |= _BV(SCK) |
62 |
#define SCK_H SCK_PORT |= _BV(SCK) |
63 |
#define SCK_L SCK_PORT &= (~(_BV(SCK))) |
63 |
#define SCK_L SCK_PORT &= (~(_BV(SCK))) |
64 |
#define SCK_INIT SCK_DDR |= _BV(SCK) |
64 |
#define SCK_INIT SCK_DDR |= _BV(SCK) |
65 |
|
65 |
|
66 |
#define nIRQ_INPUT (nIRQ_PIN & _BV(nIRQ)) |
66 |
#define nIRQ_INPUT (nIRQ_PIN & _BV(nIRQ)) |
67 |
#define nIRQ_INIT nIRQ_DDR &= (~(_BV(nIRQ))) |
67 |
#define nIRQ_INIT nIRQ_DDR &= (~(_BV(nIRQ))) |
68 |
|
68 |
|
69 |
#define nSEL_H nSEL_PORT |= _BV(nSEL) |
69 |
#define nSEL_H nSEL_PORT |= _BV(nSEL) |
70 |
#define nSEL_L nSEL_PORT &= (~(_BV(nSEL))) |
70 |
#define nSEL_L nSEL_PORT &= (~(_BV(nSEL))) |
71 |
#define nSEL_INIT nSEL_DDR |= _BV(nSEL) |
71 |
#define nSEL_INIT nSEL_DDR |= _BV(nSEL) |
72 |
|
72 |
|
73 |
#define LED_H LED_PORT |= _BV(LED) |
73 |
#define LED_H LED_PORT |= _BV(LED) |
74 |
#define LED_L LED_PORT &= (~(_BV(LED))) |
74 |
#define LED_L LED_PORT &= (~(_BV(LED))) |
75 |
#define LED_INIT LED_DDR |= _BV(LED) |
75 |
#define LED_INIT LED_DDR |= _BV(LED) |
76 |
|
76 |
|
77 |
#define START_TX RF_WRITE_CMD(CMD_POWER|POWER_EX|POWER_ES|POWER_EA|POWER_DC) |
77 |
#define START_TX RF_WRITE_CMD(CMD_POWER|POWER_EX|POWER_ES|POWER_EA|POWER_DC) |
78 |
#define STOP_TX RF_WRITE_CMD(CMD_POWER|POWER_DC) |
78 |
#define STOP_TX RF_WRITE_CMD(CMD_POWER|POWER_DC) |
79 |
|
79 |
|
80 |
//************************************************************************ |
80 |
//************************************************************************ |
81 |
|
81 |
|
82 |
//uint8_t test[16]={0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x03b,0x3c,0x3d,0x3e,0x3f}; |
82 |
//uint8_t test[16]={0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x03b,0x3c,0x3d,0x3e,0x3f}; |
83 |
uint8_t test[17]="\n\rATmega16\n\r ---"; |
83 |
uint8_t test[17]="\n\rATmega16\n\r ---"; |
84 |
//uint8_t test[16]="0123456789abcdef"; |
84 |
//uint8_t test[16]="0123456789abcdef"; |
85 |
|
85 |
|
86 |
|
86 |
|
87 |
//************************************************************************ |
87 |
//************************************************************************ |
88 |
|
88 |
|
89 |
void delay_ms(uint16_t time) |
89 |
void delay_ms(uint16_t time) |
90 |
{ |
90 |
{ |
91 |
while(time--) _delay_ms(1); |
91 |
while(time--) _delay_ms(1); |
92 |
} |
92 |
} |
93 |
|
93 |
|
94 |
void IO_INIT(void) |
94 |
void IO_INIT(void) |
95 |
{ |
95 |
{ |
96 |
SDI_INIT; |
96 |
SDI_INIT; |
97 |
SDO_INIT; |
97 |
SDO_INIT; |
98 |
SCK_INIT; |
98 |
SCK_INIT; |
99 |
nIRQ_INIT; |
99 |
nIRQ_INIT; |
100 |
nSEL_INIT; |
100 |
nSEL_INIT; |
101 |
FSK_INIT; |
101 |
FSK_INIT; |
102 |
LED_INIT; |
102 |
LED_INIT; |
103 |
} |
103 |
} |
104 |
|
104 |
|
105 |
void RF_INIT(void) |
105 |
void RF_INIT(void) |
106 |
{ |
106 |
{ |
107 |
nSEL_H; |
107 |
nSEL_H; |
108 |
SDI_H; |
108 |
SDI_H; |
109 |
SCK_L; |
109 |
SCK_L; |
110 |
nIRQ_INPUT; |
110 |
nIRQ_INPUT; |
111 |
SDO_INPUT; |
111 |
SDO_INPUT; |
112 |
FSK_H; |
112 |
FSK_H; |
113 |
} |
113 |
} |
114 |
|
114 |
|
115 |
void RF_WRITE_CMD(uint16_t cmd) |
115 |
void RF_WRITE_CMD(uint16_t cmd) |
116 |
{ |
116 |
{ |
117 |
uint8_t i; |
117 |
uint8_t i; |
118 |
|
118 |
|
119 |
SCK_L; |
119 |
SCK_L; |
120 |
nSEL_L; |
120 |
nSEL_L; |
121 |
for (i=0;i<16;i++) |
121 |
for (i=0;i<16;i++) |
122 |
{ |
122 |
{ |
123 |
SCK_L; |
123 |
SCK_L; |
124 |
SCK_L; |
124 |
SCK_L; |
125 |
if (cmd & 0x8000) SDI_H; |
125 |
if (cmd & 0x8000) SDI_H; |
126 |
else SDI_L; |
126 |
else SDI_L; |
127 |
SCK_H; |
127 |
SCK_H; |
128 |
SCK_H; |
128 |
SCK_H; |
129 |
cmd <<= 1; |
129 |
cmd <<= 1; |
130 |
} |
130 |
} |
131 |
SCK_L; |
131 |
SCK_L; |
132 |
nSEL_H; |
132 |
nSEL_H; |
133 |
} |
133 |
} |
134 |
|
134 |
|
135 |
void RF_WRITE_DATA(uint8_t data) |
135 |
void RF_WRITE_DATA(uint8_t data) |
136 |
{ |
136 |
{ |
137 |
uint8_t i; |
137 |
uint8_t i; |
138 |
|
138 |
|
139 |
for (i=0;i<8;i++) |
139 |
for (i=0;i<8;i++) |
140 |
{ |
140 |
{ |
141 |
while (nIRQ_INPUT); |
141 |
while (nIRQ_INPUT); |
142 |
while (!nIRQ_INPUT); |
142 |
while (!nIRQ_INPUT); |
143 |
if (data & 0x80)FSK_H; |
143 |
if (data & 0x80)FSK_H; |
144 |
else FSK_L; |
144 |
else FSK_L; |
145 |
data <<= 1; |
145 |
data <<= 1; |
146 |
} |
146 |
} |
147 |
} |
147 |
} |
148 |
|
148 |
|
149 |
int main() |
149 |
int main() |
150 |
{ |
150 |
{ |
151 |
uint8_t i,j,ChkSum; |
151 |
uint8_t i,j,ChkSum; |
152 |
|
152 |
|
153 |
IO_INIT(); |
153 |
IO_INIT(); |
154 |
RF_INIT(); |
154 |
RF_INIT(); |
155 |
LED_H; |
155 |
LED_H; |
156 |
delay_ms(100); |
156 |
delay_ms(100); |
157 |
|
157 |
|
158 |
RF_WRITE_CMD(CMD_STATUS); |
158 |
RF_WRITE_CMD(CMD_STATUS); |
159 |
RF_WRITE_CMD(CMD_SETTING |BAND_868 |C_12pF |TX_DEV_90); |
159 |
RF_WRITE_CMD(CMD_SETTING |BAND_868 |C_12pF |TX_DEV_90); |
160 |
RF_WRITE_CMD(CMD_FREQUENCY |FREQUENCY_868); |
160 |
RF_WRITE_CMD(CMD_FREQUENCY |FREQUENCY_868); |
161 |
RF_WRITE_CMD(0xD040); |
161 |
RF_WRITE_CMD(0xD040); |
162 |
RF_WRITE_CMD(CMD_RATE |RATE_19200); |
162 |
RF_WRITE_CMD(CMD_RATE |RATE_19200); |
163 |
RF_WRITE_CMD(CMD_BATTERY |TX_EBS); |
163 |
RF_WRITE_CMD(CMD_BATTERY |TX_EBS); |
164 |
RF_WRITE_CMD(CMD_POWER |POWER_DC); |
164 |
RF_WRITE_CMD(CMD_POWER |POWER_DC); |
165 |
RF_WRITE_CMD(POWER_OUT_0); |
165 |
RF_WRITE_CMD(POWER_OUT_0); |
166 |
|
166 |
|
167 |
j= 0; |
167 |
j= 0; |
168 |
while (1) |
168 |
while (1) |
169 |
{ |
169 |
{ |
170 |
LED_H; |
170 |
LED_H; |
171 |
|
171 |
|
172 |
START_TX; |
172 |
START_TX; |
173 |
ChkSum = 0; |
173 |
ChkSum = 0; |
174 |
for (i=0;i<3;i++) RF_WRITE_DATA(0xAA); |
174 |
for (i=0;i<3;i++) RF_WRITE_DATA(0xAA); |
175 |
RF_WRITE_DATA(0x2D); |
175 |
RF_WRITE_DATA(0x2D); |
176 |
RF_WRITE_DATA(0xD4); |
176 |
RF_WRITE_DATA(0xD4); |
177 |
|
177 |
|
178 |
for (i=0;i<16;i++) |
178 |
for (i=0;i<16;i++) |
179 |
{ |
179 |
{ |
180 |
RF_WRITE_DATA(test[i]); |
180 |
RF_WRITE_DATA(test[i]); |
181 |
ChkSum += test[i]; |
181 |
ChkSum += test[i]; |
182 |
} |
182 |
} |
183 |
RF_WRITE_DATA(ChkSum); |
183 |
RF_WRITE_DATA(ChkSum); |
184 |
RF_WRITE_DATA(0xAA); |
184 |
RF_WRITE_DATA(0xAA); |
185 |
RF_WRITE_DATA(0xAA); |
185 |
RF_WRITE_DATA(0xAA); |
186 |
STOP_TX; |
186 |
STOP_TX; |
187 |
|
187 |
|
188 |
LED_L; |
188 |
LED_L; |
189 |
delay_ms(500); |
189 |
delay_ms(500); |
190 |
j++; |
190 |
j++; |
191 |
test[13]=(j/100)+0x30; |
191 |
test[13]=(j/100)+0x30; |
192 |
test[14]=((j%100)/10)+0x30; |
192 |
test[14]=((j%100)/10)+0x30; |
193 |
test[15]=((j%100)%10)+0x30; |
193 |
test[15]=((j%100)%10)+0x30; |
194 |
} |
194 |
} |
195 |
return 0; |
195 |
return 0; |
196 |
} |
196 |
} |
197 |
|
197 |
|
198 |
|
198 |
|
199 |
|
199 |
|