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/*! \file timer.c \brief System Timer function library. */ |
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/*! \file timer.c \brief System Timer function library. */ |
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//***************************************************************************** |
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//***************************************************************************** |
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// |
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// |
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// File Name : 'timer.c' |
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// File Name : 'timer.c' |
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// Title : System Timer function library |
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// Title : System Timer function library |
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// Author : Pascal Stang - Copyright (C) 2000-2002 |
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// Author : Pascal Stang - Copyright (C) 2000-2002 |
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// Created : 11/22/2000 |
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// Created : 11/22/2000 |
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// Revised : 07/09/2003 |
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// Revised : 07/09/2003 |
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// Version : 1.1 |
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// Version : 1.1 |
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// Target MCU : Atmel AVR Series |
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// Target MCU : Atmel AVR Series |
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// Editor Tabs : 4 |
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// Editor Tabs : 4 |
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// |
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// |
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// This code is distributed under the GNU Public License |
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// This code is distributed under the GNU Public License |
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// which can be found at http://www.gnu.org/licenses/gpl.txt |
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// which can be found at http://www.gnu.org/licenses/gpl.txt |
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// |
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// |
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//***************************************************************************** |
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//***************************************************************************** |
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|
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|
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#include <avr/io.h> |
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#include <avr/io.h> |
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#include <avr/interrupt.h> |
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#include <avr/interrupt.h> |
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#include <avr/pgmspace.h> |
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#include <avr/pgmspace.h> |
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#include <avr/sleep.h> |
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#include <avr/sleep.h> |
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|
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|
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#include "global.h" |
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#include "global.h" |
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#include "timer.h" |
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#include "timer.h" |
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|
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|
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#include "rprintf.h" |
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#include "rprintf.h" |
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|
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|
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// Program ROM constants |
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// Program ROM constants |
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// the prescale division values stored in order of timer control register index |
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// the prescale division values stored in order of timer control register index |
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// STOP, CLK, CLK/8, CLK/64, CLK/256, CLK/1024 |
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// STOP, CLK, CLK/8, CLK/64, CLK/256, CLK/1024 |
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unsigned short __attribute__ ((progmem)) TimerPrescaleFactor[] = {0,1,8,64,256,1024}; |
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unsigned short __attribute__ ((progmem)) TimerPrescaleFactor[] = {0,1,8,64,256,1024}; |
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// the prescale division values stored in order of timer control register index |
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// the prescale division values stored in order of timer control register index |
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// STOP, CLK, CLK/8, CLK/32, CLK/64, CLK/128, CLK/256, CLK/1024 |
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// STOP, CLK, CLK/8, CLK/32, CLK/64, CLK/128, CLK/256, CLK/1024 |
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unsigned short __attribute__ ((progmem)) TimerRTCPrescaleFactor[] = {0,1,8,32,64,128,256,1024}; |
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unsigned short __attribute__ ((progmem)) TimerRTCPrescaleFactor[] = {0,1,8,32,64,128,256,1024}; |
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|
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|
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// Global variables |
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// Global variables |
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// time registers |
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// time registers |
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volatile unsigned long TimerPauseReg; |
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volatile unsigned long TimerPauseReg; |
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volatile unsigned long Timer0Reg0; |
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volatile unsigned long Timer0Reg0; |
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volatile unsigned long Timer2Reg0; |
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volatile unsigned long Timer2Reg0; |
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|
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|
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typedef void (*voidFuncPtr)(void); |
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typedef void (*voidFuncPtr)(void); |
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volatile static voidFuncPtr TimerIntFunc[TIMER_NUM_INTERRUPTS]; |
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volatile static voidFuncPtr TimerIntFunc[TIMER_NUM_INTERRUPTS]; |
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|
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|
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// delay for a minimum of <us> microseconds |
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// delay for a minimum of <us> microseconds |
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// the time resolution is dependent on the time the loop takes |
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// the time resolution is dependent on the time the loop takes |
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// e.g. with 4Mhz and 5 cycles per loop, the resolution is 1.25 us |
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// e.g. with 4Mhz and 5 cycles per loop, the resolution is 1.25 us |
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void delay_us(unsigned short time_us) |
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void delay_us(unsigned short time_us) |
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{ |
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{ |
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unsigned short delay_loops; |
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unsigned short delay_loops; |
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register unsigned short i; |
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register unsigned short i; |
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|
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|
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delay_loops = (time_us+3)/5*CYCLES_PER_US; // +3 for rounding up (dirty) |
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delay_loops = (time_us+3)/5*CYCLES_PER_US; // +3 for rounding up (dirty) |
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|
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|
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// one loop takes 5 cpu cycles |
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// one loop takes 5 cpu cycles |
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for (i=0; i < delay_loops; i++) {}; |
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for (i=0; i < delay_loops; i++) {}; |
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} |
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} |
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/* |
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/* |
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void delay_ms(unsigned char time_ms) |
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void delay_ms(unsigned char time_ms) |
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{ |
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{ |
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unsigned short delay_count = F_CPU / 4000; |
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unsigned short delay_count = F_CPU / 4000; |
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|
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|
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unsigned short cnt; |
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unsigned short cnt; |
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asm volatile ("\n" |
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asm volatile ("\n" |
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"L_dl1%=:\n\t" |
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"L_dl1%=:\n\t" |
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"mov %A0, %A2\n\t" |
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"mov %A0, %A2\n\t" |
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"mov %B0, %B2\n" |
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"mov %B0, %B2\n" |
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"L_dl2%=:\n\t" |
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"L_dl2%=:\n\t" |
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"sbiw %A0, 1\n\t" |
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"sbiw %A0, 1\n\t" |
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"brne L_dl2%=\n\t" |
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"brne L_dl2%=\n\t" |
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"dec %1\n\t" "brne L_dl1%=\n\t":"=&w" (cnt) |
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"dec %1\n\t" "brne L_dl1%=\n\t":"=&w" (cnt) |
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:"r"(time_ms), "r"((unsigned short) (delay_count)) |
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:"r"(time_ms), "r"((unsigned short) (delay_count)) |
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); |
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); |
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} |
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} |
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*/ |
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*/ |
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void timerInit(void) |
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void timerInit(void) |
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{ |
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{ |
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u08 intNum; |
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u08 intNum; |
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// detach all user functions from interrupts |
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// detach all user functions from interrupts |
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for(intNum=0; intNum<TIMER_NUM_INTERRUPTS; intNum++) |
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for(intNum=0; intNum<TIMER_NUM_INTERRUPTS; intNum++) |
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timerDetach(intNum); |
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timerDetach(intNum); |
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|
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|
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// initialize all timers |
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// initialize all timers |
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timer0Init(); |
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timer0Init(); |
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timer1Init(); |
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timer1Init(); |
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#ifdef TCNT2 // support timer2 only if it exists |
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#ifdef TCNT2 // support timer2 only if it exists |
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timer2Init(); |
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timer2Init(); |
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#endif |
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#endif |
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// enable interrupts |
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// enable interrupts |
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sei(); |
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sei(); |
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} |
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} |
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|
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|
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void timer0Init() |
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void timer0Init() |
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{ |
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{ |
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// initialize timer 0 |
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// initialize timer 0 |
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timer0SetPrescaler( TIMER0PRESCALE ); // set prescaler |
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timer0SetPrescaler( TIMER0PRESCALE ); // set prescaler |
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outb(TCNT0, 0); // reset TCNT0 |
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outb(TCNT0, 0); // reset TCNT0 |
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sbi(TIMSK, TOIE0); // enable TCNT0 overflow interrupt |
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sbi(TIMSK, TOIE0); // enable TCNT0 overflow interrupt |
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|
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|
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timer0ClearOverflowCount(); // initialize time registers |
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timer0ClearOverflowCount(); // initialize time registers |
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} |
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} |
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|
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|
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void timer1Init(void) |
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void timer1Init(void) |
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{ |
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{ |
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// initialize timer 1 |
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// initialize timer 1 |
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timer1SetPrescaler( TIMER1PRESCALE ); // set prescaler |
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timer1SetPrescaler( TIMER1PRESCALE ); // set prescaler |
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outb(TCNT1H, 0); // reset TCNT1 |
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outb(TCNT1H, 0); // reset TCNT1 |
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outb(TCNT1L, 0); |
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outb(TCNT1L, 0); |
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sbi(TIMSK, TOIE1); // enable TCNT1 overflow |
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sbi(TIMSK, TOIE1); // enable TCNT1 overflow |
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} |
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} |
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|
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|
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#ifdef TCNT2 // support timer2 only if it exists |
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#ifdef TCNT2 // support timer2 only if it exists |
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void timer2Init(void) |
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void timer2Init(void) |
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{ |
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{ |
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// initialize timer 2 |
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// initialize timer 2 |
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timer2SetPrescaler( TIMER2PRESCALE ); // set prescaler |
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timer2SetPrescaler( TIMER2PRESCALE ); // set prescaler |
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outb(TCNT2, 0); // reset TCNT2 |
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outb(TCNT2, 0); // reset TCNT2 |
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sbi(TIMSK, TOIE2); // enable TCNT2 overflow |
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sbi(TIMSK, TOIE2); // enable TCNT2 overflow |
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|
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|
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timer2ClearOverflowCount(); // initialize time registers |
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timer2ClearOverflowCount(); // initialize time registers |
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} |
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} |
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#endif |
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#endif |
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|
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|
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void timer0SetPrescaler(u08 prescale) |
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void timer0SetPrescaler(u08 prescale) |
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{ |
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{ |
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// set prescaler on timer 0 |
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// set prescaler on timer 0 |
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outb(TCCR0, (inb(TCCR0) & ~TIMER_PRESCALE_MASK) | prescale); |
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outb(TCCR0, (inb(TCCR0) & ~TIMER_PRESCALE_MASK) | prescale); |
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} |
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} |
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|
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|
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void timer1SetPrescaler(u08 prescale) |
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void timer1SetPrescaler(u08 prescale) |
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{ |
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{ |
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// set prescaler on timer 1 |
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// set prescaler on timer 1 |
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outb(TCCR1B, (inb(TCCR1B) & ~TIMER_PRESCALE_MASK) | prescale); |
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outb(TCCR1B, (inb(TCCR1B) & ~TIMER_PRESCALE_MASK) | prescale); |
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} |
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} |
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|
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|
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#ifdef TCNT2 // support timer2 only if it exists |
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#ifdef TCNT2 // support timer2 only if it exists |
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void timer2SetPrescaler(u08 prescale) |
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void timer2SetPrescaler(u08 prescale) |
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{ |
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{ |
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// set prescaler on timer 2 |
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// set prescaler on timer 2 |
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outb(TCCR2, (inb(TCCR2) & ~TIMER_PRESCALE_MASK) | prescale); |
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outb(TCCR2, (inb(TCCR2) & ~TIMER_PRESCALE_MASK) | prescale); |
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} |
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} |
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#endif |
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#endif |
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|
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|
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u16 timer0GetPrescaler(void) |
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u16 timer0GetPrescaler(void) |
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{ |
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{ |
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// get the current prescaler setting |
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// get the current prescaler setting |
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return (pgm_read_word(TimerPrescaleFactor+(inb(TCCR0) & TIMER_PRESCALE_MASK))); |
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return (pgm_read_word(TimerPrescaleFactor+(inb(TCCR0) & TIMER_PRESCALE_MASK))); |
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} |
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} |
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|
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|
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u16 timer1GetPrescaler(void) |
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u16 timer1GetPrescaler(void) |
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{ |
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{ |
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// get the current prescaler setting |
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// get the current prescaler setting |
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return (pgm_read_word(TimerPrescaleFactor+(inb(TCCR1B) & TIMER_PRESCALE_MASK))); |
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return (pgm_read_word(TimerPrescaleFactor+(inb(TCCR1B) & TIMER_PRESCALE_MASK))); |
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} |
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} |
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|
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|
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#ifdef TCNT2 // support timer2 only if it exists |
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#ifdef TCNT2 // support timer2 only if it exists |
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u16 timer2GetPrescaler(void) |
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u16 timer2GetPrescaler(void) |
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{ |
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{ |
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//TODO: can we assume for all 3-timer AVR processors, |
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//TODO: can we assume for all 3-timer AVR processors, |
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// that timer2 is the RTC timer? |
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// that timer2 is the RTC timer? |
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|
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|
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// get the current prescaler setting |
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// get the current prescaler setting |
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return (pgm_read_word(TimerRTCPrescaleFactor+(inb(TCCR2) & TIMER_PRESCALE_MASK))); |
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return (pgm_read_word(TimerRTCPrescaleFactor+(inb(TCCR2) & TIMER_PRESCALE_MASK))); |
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} |
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} |
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#endif |
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#endif |
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|
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|
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void timerAttach(u08 interruptNum, void (*userFunc)(void) ) |
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void timerAttach(u08 interruptNum, void (*userFunc)(void) ) |
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{ |
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{ |
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// make sure the interrupt number is within bounds |
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// make sure the interrupt number is within bounds |
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if(interruptNum < TIMER_NUM_INTERRUPTS) |
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if(interruptNum < TIMER_NUM_INTERRUPTS) |
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{ |
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{ |
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// set the interrupt function to run |
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// set the interrupt function to run |
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// the supplied user's function |
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// the supplied user's function |
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TimerIntFunc[interruptNum] = userFunc; |
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TimerIntFunc[interruptNum] = userFunc; |
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} |
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} |
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} |
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} |
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|
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|
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void timerDetach(u08 interruptNum) |
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void timerDetach(u08 interruptNum) |
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{ |
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{ |
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// make sure the interrupt number is within bounds |
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// make sure the interrupt number is within bounds |
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if(interruptNum < TIMER_NUM_INTERRUPTS) |
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if(interruptNum < TIMER_NUM_INTERRUPTS) |
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{ |
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{ |
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// set the interrupt function to run nothing |
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// set the interrupt function to run nothing |
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TimerIntFunc[interruptNum] = 0; |
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TimerIntFunc[interruptNum] = 0; |
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} |
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} |
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} |
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} |
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/* |
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/* |
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u32 timerMsToTics(u16 ms) |
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u32 timerMsToTics(u16 ms) |
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{ |
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{ |
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// calculate the prescaler division rate |
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// calculate the prescaler division rate |
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u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
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u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
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// calculate the number of timer tics in x milliseconds |
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// calculate the number of timer tics in x milliseconds |
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return (ms*(F_CPU/(prescaleDiv*256)))/1000; |
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return (ms*(F_CPU/(prescaleDiv*256)))/1000; |
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} |
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} |
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|
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|
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u16 timerTicsToMs(u32 tics) |
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u16 timerTicsToMs(u32 tics) |
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{ |
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{ |
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// calculate the prescaler division rate |
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// calculate the prescaler division rate |
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u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
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u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
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// calculate the number of milliseconds in x timer tics |
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// calculate the number of milliseconds in x timer tics |
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return (tics*1000*(prescaleDiv*256))/F_CPU; |
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return (tics*1000*(prescaleDiv*256))/F_CPU; |
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} |
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} |
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*/ |
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*/ |
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void timerPause(unsigned short pause_ms) |
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void timerPause(unsigned short pause_ms) |
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{ |
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{ |
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// pauses for exactly <pause_ms> number of milliseconds |
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// pauses for exactly <pause_ms> number of milliseconds |
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u08 timerThres; |
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u08 timerThres; |
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u32 ticRateHz; |
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u32 ticRateHz; |
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u32 pause; |
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u32 pause; |
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|
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|
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// capture current pause timer value |
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// capture current pause timer value |
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timerThres = inb(TCNT0); |
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timerThres = inb(TCNT0); |
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// reset pause timer overflow count |
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// reset pause timer overflow count |
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TimerPauseReg = 0; |
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TimerPauseReg = 0; |
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// calculate delay for [pause_ms] milliseconds |
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// calculate delay for [pause_ms] milliseconds |
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// prescaler division = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))) |
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// prescaler division = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))) |
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ticRateHz = F_CPU/timer0GetPrescaler(); |
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ticRateHz = F_CPU/timer0GetPrescaler(); |
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// precision management |
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// precision management |
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// prevent overflow and precision underflow |
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// prevent overflow and precision underflow |
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// -could add more conditions to improve accuracy |
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// -could add more conditions to improve accuracy |
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if( ((ticRateHz < 429497) && (pause_ms <= 10000)) ) |
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if( ((ticRateHz < 429497) && (pause_ms <= 10000)) ) |
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pause = (pause_ms*ticRateHz)/1000; |
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pause = (pause_ms*ticRateHz)/1000; |
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else |
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else |
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pause = pause_ms*(ticRateHz/1000); |
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pause = pause_ms*(ticRateHz/1000); |
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|
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|
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// loop until time expires |
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// loop until time expires |
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while( ((TimerPauseReg<<8) | inb(TCNT0)) < (pause+timerThres) ) |
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while( ((TimerPauseReg<<8) | inb(TCNT0)) < (pause+timerThres) ) |
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{ |
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{ |
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if( TimerPauseReg < (pause>>8)); |
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if( TimerPauseReg < (pause>>8)); |
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{ |
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{ |
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// save power by idling the processor |
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// save power by idling the processor |
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set_sleep_mode(SLEEP_MODE_IDLE); |
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set_sleep_mode(SLEEP_MODE_IDLE); |
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sleep_mode(); |
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sleep_mode(); |
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} |
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} |
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} |
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} |
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|
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|
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/* old inaccurate code, for reference |
237 |
/* old inaccurate code, for reference |
238 |
|
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|
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// calculate delay for [pause_ms] milliseconds |
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// calculate delay for [pause_ms] milliseconds |
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u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
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u16 prescaleDiv = 1<<(pgm_read_byte(TimerPrescaleFactor+inb(TCCR0))); |
241 |
u32 pause = (pause_ms*(F_CPU/(prescaleDiv*256)))/1000; |
241 |
u32 pause = (pause_ms*(F_CPU/(prescaleDiv*256)))/1000; |
242 |
|
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|
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TimerPauseReg = 0; |
243 |
TimerPauseReg = 0; |
244 |
while(TimerPauseReg < pause); |
244 |
while(TimerPauseReg < pause); |
245 |
|
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|
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*/ |
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*/ |
247 |
} |
247 |
} |
248 |
|
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|
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void timer0ClearOverflowCount(void) |
249 |
void timer0ClearOverflowCount(void) |
250 |
{ |
250 |
{ |
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// clear the timer overflow counter registers |
251 |
// clear the timer overflow counter registers |
252 |
Timer0Reg0 = 0; // initialize time registers |
252 |
Timer0Reg0 = 0; // initialize time registers |
253 |
} |
253 |
} |
254 |
|
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|
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long timer0GetOverflowCount(void) |
255 |
long timer0GetOverflowCount(void) |
256 |
{ |
256 |
{ |
257 |
// return the current timer overflow count |
257 |
// return the current timer overflow count |
258 |
// (this is since the last timer0ClearOverflowCount() command was called) |
258 |
// (this is since the last timer0ClearOverflowCount() command was called) |
259 |
return Timer0Reg0; |
259 |
return Timer0Reg0; |
260 |
} |
260 |
} |
261 |
|
261 |
|
262 |
#ifdef TCNT2 // support timer2 only if it exists |
262 |
#ifdef TCNT2 // support timer2 only if it exists |
263 |
void timer2ClearOverflowCount(void) |
263 |
void timer2ClearOverflowCount(void) |
264 |
{ |
264 |
{ |
265 |
// clear the timer overflow counter registers |
265 |
// clear the timer overflow counter registers |
266 |
Timer2Reg0 = 0; // initialize time registers |
266 |
Timer2Reg0 = 0; // initialize time registers |
267 |
} |
267 |
} |
268 |
|
268 |
|
269 |
long timer2GetOverflowCount(void) |
269 |
long timer2GetOverflowCount(void) |
270 |
{ |
270 |
{ |
271 |
// return the current timer overflow count |
271 |
// return the current timer overflow count |
272 |
// (this is since the last timer2ClearOverflowCount() command was called) |
272 |
// (this is since the last timer2ClearOverflowCount() command was called) |
273 |
return Timer2Reg0; |
273 |
return Timer2Reg0; |
274 |
} |
274 |
} |
275 |
#endif |
275 |
#endif |
276 |
|
276 |
|
277 |
void timer1PWMInit(u08 bitRes) |
277 |
void timer1PWMInit(u08 bitRes) |
278 |
{ |
278 |
{ |
279 |
// configures timer1 for use with PWM output |
279 |
// configures timer1 for use with PWM output |
280 |
// on OC1A and OC1B pins |
280 |
// on OC1A and OC1B pins |
281 |
|
281 |
|
282 |
// enable timer1 as 8,9,10bit PWM |
282 |
// enable timer1 as 8,9,10bit PWM |
283 |
if(bitRes == 9) |
283 |
if(bitRes == 9) |
284 |
{ // 9bit mode |
284 |
{ // 9bit mode |
285 |
sbi(TCCR1A,PWM11); |
285 |
sbi(TCCR1A,PWM11); |
286 |
cbi(TCCR1A,PWM10); |
286 |
cbi(TCCR1A,PWM10); |
287 |
} |
287 |
} |
288 |
else if( bitRes == 10 ) |
288 |
else if( bitRes == 10 ) |
289 |
{ // 10bit mode |
289 |
{ // 10bit mode |
290 |
sbi(TCCR1A,PWM11); |
290 |
sbi(TCCR1A,PWM11); |
291 |
sbi(TCCR1A,PWM10); |
291 |
sbi(TCCR1A,PWM10); |
292 |
} |
292 |
} |
293 |
else |
293 |
else |
294 |
{ // default 8bit mode |
294 |
{ // default 8bit mode |
295 |
cbi(TCCR1A,PWM11); |
295 |
cbi(TCCR1A,PWM11); |
296 |
sbi(TCCR1A,PWM10); |
296 |
sbi(TCCR1A,PWM10); |
297 |
} |
297 |
} |
298 |
|
298 |
|
299 |
// clear output compare value A |
299 |
// clear output compare value A |
300 |
outb(OCR1AH, 0); |
300 |
outb(OCR1AH, 0); |
301 |
outb(OCR1AL, 0); |
301 |
outb(OCR1AL, 0); |
302 |
// clear output compare value B |
302 |
// clear output compare value B |
303 |
outb(OCR1BH, 0); |
303 |
outb(OCR1BH, 0); |
304 |
outb(OCR1BL, 0); |
304 |
outb(OCR1BL, 0); |
305 |
} |
305 |
} |
306 |
|
306 |
|
307 |
#ifdef WGM10 |
307 |
#ifdef WGM10 |
308 |
// include support for arbitrary top-count PWM |
308 |
// include support for arbitrary top-count PWM |
309 |
// on new AVR processors that support it |
309 |
// on new AVR processors that support it |
310 |
void timer1PWMInitICR(u16 topcount) |
310 |
void timer1PWMInitICR(u16 topcount) |
311 |
{ |
311 |
{ |
312 |
// set PWM mode with ICR top-count |
312 |
// set PWM mode with ICR top-count |
313 |
cbi(TCCR1A,WGM10); |
313 |
cbi(TCCR1A,WGM10); |
314 |
sbi(TCCR1A,WGM11); |
314 |
sbi(TCCR1A,WGM11); |
315 |
sbi(TCCR1B,WGM12); |
315 |
sbi(TCCR1B,WGM12); |
316 |
sbi(TCCR1B,WGM13); |
316 |
sbi(TCCR1B,WGM13); |
317 |
|
317 |
|
318 |
// set top count value |
318 |
// set top count value |
319 |
ICR1 = topcount; |
319 |
ICR1 = topcount; |
320 |
|
320 |
|
321 |
// clear output compare value A |
321 |
// clear output compare value A |
322 |
OCR1A = 0; |
322 |
OCR1A = 0; |
323 |
// clear output compare value B |
323 |
// clear output compare value B |
324 |
OCR1B = 0; |
324 |
OCR1B = 0; |
325 |
|
325 |
|
326 |
} |
326 |
} |
327 |
#endif |
327 |
#endif |
328 |
|
328 |
|
329 |
void timer1PWMOff(void) |
329 |
void timer1PWMOff(void) |
330 |
{ |
330 |
{ |
331 |
// turn off timer1 PWM mode |
331 |
// turn off timer1 PWM mode |
332 |
cbi(TCCR1A,PWM11); |
332 |
cbi(TCCR1A,PWM11); |
333 |
cbi(TCCR1A,PWM10); |
333 |
cbi(TCCR1A,PWM10); |
334 |
// set PWM1A/B (OutputCompare action) to none |
334 |
// set PWM1A/B (OutputCompare action) to none |
335 |
timer1PWMAOff(); |
335 |
timer1PWMAOff(); |
336 |
timer1PWMBOff(); |
336 |
timer1PWMBOff(); |
337 |
} |
337 |
} |
338 |
|
338 |
|
339 |
void timer1PWMAOn(void) |
339 |
void timer1PWMAOn(void) |
340 |
{ |
340 |
{ |
341 |
// turn on channel A (OC1A) PWM output |
341 |
// turn on channel A (OC1A) PWM output |
342 |
// set OC1A as non-inverted PWM |
342 |
// set OC1A as non-inverted PWM |
343 |
sbi(TCCR1A,COM1A1); |
343 |
sbi(TCCR1A,COM1A1); |
344 |
cbi(TCCR1A,COM1A0); |
344 |
cbi(TCCR1A,COM1A0); |
345 |
} |
345 |
} |
346 |
|
346 |
|
347 |
void timer1PWMBOn(void) |
347 |
void timer1PWMBOn(void) |
348 |
{ |
348 |
{ |
349 |
// turn on channel B (OC1B) PWM output |
349 |
// turn on channel B (OC1B) PWM output |
350 |
// set OC1B as non-inverted PWM |
350 |
// set OC1B as non-inverted PWM |
351 |
sbi(TCCR1A,COM1B1); |
351 |
sbi(TCCR1A,COM1B1); |
352 |
cbi(TCCR1A,COM1B0); |
352 |
cbi(TCCR1A,COM1B0); |
353 |
} |
353 |
} |
354 |
|
354 |
|
355 |
void timer1PWMAOff(void) |
355 |
void timer1PWMAOff(void) |
356 |
{ |
356 |
{ |
357 |
// turn off channel A (OC1A) PWM output |
357 |
// turn off channel A (OC1A) PWM output |
358 |
// set OC1A (OutputCompare action) to none |
358 |
// set OC1A (OutputCompare action) to none |
359 |
cbi(TCCR1A,COM1A1); |
359 |
cbi(TCCR1A,COM1A1); |
360 |
cbi(TCCR1A,COM1A0); |
360 |
cbi(TCCR1A,COM1A0); |
361 |
} |
361 |
} |
362 |
|
362 |
|
363 |
void timer1PWMBOff(void) |
363 |
void timer1PWMBOff(void) |
364 |
{ |
364 |
{ |
365 |
// turn off channel B (OC1B) PWM output |
365 |
// turn off channel B (OC1B) PWM output |
366 |
// set OC1B (OutputCompare action) to none |
366 |
// set OC1B (OutputCompare action) to none |
367 |
cbi(TCCR1A,COM1B1); |
367 |
cbi(TCCR1A,COM1B1); |
368 |
cbi(TCCR1A,COM1B0); |
368 |
cbi(TCCR1A,COM1B0); |
369 |
} |
369 |
} |
370 |
|
370 |
|
371 |
void timer1PWMASet(u16 pwmDuty) |
371 |
void timer1PWMASet(u16 pwmDuty) |
372 |
{ |
372 |
{ |
373 |
// set PWM (output compare) duty for channel A |
373 |
// set PWM (output compare) duty for channel A |
374 |
// this PWM output is generated on OC1A pin |
374 |
// this PWM output is generated on OC1A pin |
375 |
// NOTE: pwmDuty should be in the range 0-255 for 8bit PWM |
375 |
// NOTE: pwmDuty should be in the range 0-255 for 8bit PWM |
376 |
// pwmDuty should be in the range 0-511 for 9bit PWM |
376 |
// pwmDuty should be in the range 0-511 for 9bit PWM |
377 |
// pwmDuty should be in the range 0-1023 for 10bit PWM |
377 |
// pwmDuty should be in the range 0-1023 for 10bit PWM |
378 |
//outp( (pwmDuty>>8), OCR1AH); // set the high 8bits of OCR1A |
378 |
//outp( (pwmDuty>>8), OCR1AH); // set the high 8bits of OCR1A |
379 |
//outp( (pwmDuty&0x00FF), OCR1AL); // set the low 8bits of OCR1A |
379 |
//outp( (pwmDuty&0x00FF), OCR1AL); // set the low 8bits of OCR1A |
380 |
OCR1A = pwmDuty; |
380 |
OCR1A = pwmDuty; |
381 |
} |
381 |
} |
382 |
|
382 |
|
383 |
void timer1PWMBSet(u16 pwmDuty) |
383 |
void timer1PWMBSet(u16 pwmDuty) |
384 |
{ |
384 |
{ |
385 |
// set PWM (output compare) duty for channel B |
385 |
// set PWM (output compare) duty for channel B |
386 |
// this PWM output is generated on OC1B pin |
386 |
// this PWM output is generated on OC1B pin |
387 |
// NOTE: pwmDuty should be in the range 0-255 for 8bit PWM |
387 |
// NOTE: pwmDuty should be in the range 0-255 for 8bit PWM |
388 |
// pwmDuty should be in the range 0-511 for 9bit PWM |
388 |
// pwmDuty should be in the range 0-511 for 9bit PWM |
389 |
// pwmDuty should be in the range 0-1023 for 10bit PWM |
389 |
// pwmDuty should be in the range 0-1023 for 10bit PWM |
390 |
//outp( (pwmDuty>>8), OCR1BH); // set the high 8bits of OCR1B |
390 |
//outp( (pwmDuty>>8), OCR1BH); // set the high 8bits of OCR1B |
391 |
//outp( (pwmDuty&0x00FF), OCR1BL); // set the low 8bits of OCR1B |
391 |
//outp( (pwmDuty&0x00FF), OCR1BL); // set the low 8bits of OCR1B |
392 |
OCR1B = pwmDuty; |
392 |
OCR1B = pwmDuty; |
393 |
} |
393 |
} |
394 |
|
394 |
|
395 |
//! Interrupt handler for tcnt0 overflow interrupt |
395 |
//! Interrupt handler for tcnt0 overflow interrupt |
396 |
TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW0) |
396 |
TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW0) |
397 |
{ |
397 |
{ |
398 |
Timer0Reg0++; // increment low-order counter |
398 |
Timer0Reg0++; // increment low-order counter |
399 |
|
399 |
|
400 |
// increment pause counter |
400 |
// increment pause counter |
401 |
TimerPauseReg++; |
401 |
TimerPauseReg++; |
402 |
|
402 |
|
403 |
// if a user function is defined, execute it too |
403 |
// if a user function is defined, execute it too |
404 |
if(TimerIntFunc[TIMER0OVERFLOW_INT]) |
404 |
if(TimerIntFunc[TIMER0OVERFLOW_INT]) |
405 |
TimerIntFunc[TIMER0OVERFLOW_INT](); |
405 |
TimerIntFunc[TIMER0OVERFLOW_INT](); |
406 |
} |
406 |
} |
407 |
|
407 |
|
408 |
//! Interrupt handler for tcnt1 overflow interrupt |
408 |
//! Interrupt handler for tcnt1 overflow interrupt |
409 |
TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW1) |
409 |
TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW1) |
410 |
{ |
410 |
{ |
411 |
// if a user function is defined, execute it |
411 |
// if a user function is defined, execute it |
412 |
if(TimerIntFunc[TIMER1OVERFLOW_INT]) |
412 |
if(TimerIntFunc[TIMER1OVERFLOW_INT]) |
413 |
TimerIntFunc[TIMER1OVERFLOW_INT](); |
413 |
TimerIntFunc[TIMER1OVERFLOW_INT](); |
414 |
} |
414 |
} |
415 |
|
415 |
|
416 |
#ifdef TCNT2 // support timer2 only if it exists |
416 |
#ifdef TCNT2 // support timer2 only if it exists |
417 |
//! Interrupt handler for tcnt2 overflow interrupt |
417 |
//! Interrupt handler for tcnt2 overflow interrupt |
418 |
TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW2) |
418 |
TIMER_INTERRUPT_HANDLER(SIG_OVERFLOW2) |
419 |
{ |
419 |
{ |
420 |
Timer2Reg0++; // increment low-order counter |
420 |
Timer2Reg0++; // increment low-order counter |
421 |
|
421 |
|
422 |
// if a user function is defined, execute it |
422 |
// if a user function is defined, execute it |
423 |
if(TimerIntFunc[TIMER2OVERFLOW_INT]) |
423 |
if(TimerIntFunc[TIMER2OVERFLOW_INT]) |
424 |
TimerIntFunc[TIMER2OVERFLOW_INT](); |
424 |
TimerIntFunc[TIMER2OVERFLOW_INT](); |
425 |
} |
425 |
} |
426 |
#endif |
426 |
#endif |
427 |
|
427 |
|
428 |
#ifdef OCR0 |
428 |
#ifdef OCR0 |
429 |
// include support for Output Compare 0 for new AVR processors that support it |
429 |
// include support for Output Compare 0 for new AVR processors that support it |
430 |
//! Interrupt handler for OutputCompare0 match (OC0) interrupt |
430 |
//! Interrupt handler for OutputCompare0 match (OC0) interrupt |
431 |
TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE0) |
431 |
TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE0) |
432 |
{ |
432 |
{ |
433 |
// if a user function is defined, execute it |
433 |
// if a user function is defined, execute it |
434 |
if(TimerIntFunc[TIMER0OUTCOMPARE_INT]) |
434 |
if(TimerIntFunc[TIMER0OUTCOMPARE_INT]) |
435 |
TimerIntFunc[TIMER0OUTCOMPARE_INT](); |
435 |
TimerIntFunc[TIMER0OUTCOMPARE_INT](); |
436 |
} |
436 |
} |
437 |
#endif |
437 |
#endif |
438 |
|
438 |
|
439 |
//! Interrupt handler for CutputCompare1A match (OC1A) interrupt |
439 |
//! Interrupt handler for CutputCompare1A match (OC1A) interrupt |
440 |
TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE1A) |
440 |
TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE1A) |
441 |
{ |
441 |
{ |
442 |
// if a user function is defined, execute it |
442 |
// if a user function is defined, execute it |
443 |
if(TimerIntFunc[TIMER1OUTCOMPAREA_INT]) |
443 |
if(TimerIntFunc[TIMER1OUTCOMPAREA_INT]) |
444 |
TimerIntFunc[TIMER1OUTCOMPAREA_INT](); |
444 |
TimerIntFunc[TIMER1OUTCOMPAREA_INT](); |
445 |
} |
445 |
} |
446 |
|
446 |
|
447 |
//! Interrupt handler for OutputCompare1B match (OC1B) interrupt |
447 |
//! Interrupt handler for OutputCompare1B match (OC1B) interrupt |
448 |
TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE1B) |
448 |
TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE1B) |
449 |
{ |
449 |
{ |
450 |
// if a user function is defined, execute it |
450 |
// if a user function is defined, execute it |
451 |
if(TimerIntFunc[TIMER1OUTCOMPAREB_INT]) |
451 |
if(TimerIntFunc[TIMER1OUTCOMPAREB_INT]) |
452 |
TimerIntFunc[TIMER1OUTCOMPAREB_INT](); |
452 |
TimerIntFunc[TIMER1OUTCOMPAREB_INT](); |
453 |
} |
453 |
} |
454 |
|
454 |
|
455 |
//! Interrupt handler for InputCapture1 (IC1) interrupt |
455 |
//! Interrupt handler for InputCapture1 (IC1) interrupt |
456 |
TIMER_INTERRUPT_HANDLER(SIG_INPUT_CAPTURE1) |
456 |
TIMER_INTERRUPT_HANDLER(SIG_INPUT_CAPTURE1) |
457 |
{ |
457 |
{ |
458 |
// if a user function is defined, execute it |
458 |
// if a user function is defined, execute it |
459 |
if(TimerIntFunc[TIMER1INPUTCAPTURE_INT]) |
459 |
if(TimerIntFunc[TIMER1INPUTCAPTURE_INT]) |
460 |
TimerIntFunc[TIMER1INPUTCAPTURE_INT](); |
460 |
TimerIntFunc[TIMER1INPUTCAPTURE_INT](); |
461 |
} |
461 |
} |
462 |
|
462 |
|
463 |
//! Interrupt handler for OutputCompare2 match (OC2) interrupt |
463 |
//! Interrupt handler for OutputCompare2 match (OC2) interrupt |
464 |
TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE2) |
464 |
TIMER_INTERRUPT_HANDLER(SIG_OUTPUT_COMPARE2) |
465 |
{ |
465 |
{ |
466 |
// if a user function is defined, execute it |
466 |
// if a user function is defined, execute it |
467 |
if(TimerIntFunc[TIMER2OUTCOMPARE_INT]) |
467 |
if(TimerIntFunc[TIMER2OUTCOMPARE_INT]) |
468 |
TimerIntFunc[TIMER2OUTCOMPARE_INT](); |
468 |
TimerIntFunc[TIMER2OUTCOMPARE_INT](); |
469 |
} |
469 |
} |