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############################################################## |
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############################################################## |
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# |
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# |
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# Xilinx Core Generator version 14.3 |
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# Xilinx Core Generator version 14.3 |
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# Date: Tue May 6 10:43:16 2014 |
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# Date: Tue May 6 10:43:16 2014 |
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# |
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############################################################## |
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############################################################## |
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# |
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# |
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# This file contains the customisation parameters for a |
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# This file contains the customisation parameters for a |
9 |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
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# Xilinx CORE Generator IP GUI. It is strongly recommended |
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# that you do not manually alter this file as it may cause |
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# that you do not manually alter this file as it may cause |
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# unexpected and unsupported behavior. |
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# unexpected and unsupported behavior. |
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# |
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# |
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############################################################## |
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############################################################## |
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# |
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# |
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# Generated from component: xilinx.com:ip:clk_wiz:3.6 |
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# Generated from component: xilinx.com:ip:clk_wiz:3.6 |
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# |
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# |
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############################################################## |
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############################################################## |
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# |
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# |
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# BEGIN Project Options |
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# BEGIN Project Options |
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SET addpads = false |
20 |
SET addpads = false |
21 |
SET asysymbol = true |
21 |
SET asysymbol = true |
22 |
SET busformat = BusFormatAngleBracketNotRipped |
22 |
SET busformat = BusFormatAngleBracketNotRipped |
23 |
SET createndf = false |
23 |
SET createndf = false |
24 |
SET designentry = VHDL |
24 |
SET designentry = VHDL |
25 |
SET device = xc6vlx240t |
25 |
SET device = xc6vlx240t |
26 |
SET devicefamily = virtex6 |
26 |
SET devicefamily = virtex6 |
27 |
SET flowvendor = Other |
27 |
SET flowvendor = Other |
28 |
SET formalverification = false |
28 |
SET formalverification = false |
29 |
SET foundationsym = false |
29 |
SET foundationsym = false |
30 |
SET implementationfiletype = Ngc |
30 |
SET implementationfiletype = Ngc |
31 |
SET package = ff1156 |
31 |
SET package = ff1156 |
32 |
SET removerpms = false |
32 |
SET removerpms = false |
33 |
SET simulationfiles = Behavioral |
33 |
SET simulationfiles = Behavioral |
34 |
SET speedgrade = -1 |
34 |
SET speedgrade = -1 |
35 |
SET verilogsim = false |
35 |
SET verilogsim = false |
36 |
SET vhdlsim = true |
36 |
SET vhdlsim = true |
37 |
# END Project Options |
37 |
# END Project Options |
38 |
# BEGIN Select |
38 |
# BEGIN Select |
39 |
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 |
39 |
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 |
40 |
# END Select |
40 |
# END Select |
41 |
# BEGIN Parameters |
41 |
# BEGIN Parameters |
42 |
CSET calc_done=DONE |
42 |
CSET calc_done=DONE |
43 |
CSET clk_in_sel_port=CLK_IN_SEL |
43 |
CSET clk_in_sel_port=CLK_IN_SEL |
44 |
CSET clk_out1_port=CLK_OUT_6 |
44 |
CSET clk_out1_port=CLK_OUT_6 |
45 |
CSET clk_out1_use_fine_ps_gui=false |
45 |
CSET clk_out1_use_fine_ps_gui=false |
46 |
CSET clk_out2_port=CLK_OUT2 |
46 |
CSET clk_out2_port=CLK_OUT2 |
47 |
CSET clk_out2_use_fine_ps_gui=false |
47 |
CSET clk_out2_use_fine_ps_gui=false |
48 |
CSET clk_out3_port=CLK_OUT3 |
48 |
CSET clk_out3_port=CLK_OUT3 |
49 |
CSET clk_out3_use_fine_ps_gui=false |
49 |
CSET clk_out3_use_fine_ps_gui=false |
50 |
CSET clk_out4_port=CLK_OUT4 |
50 |
CSET clk_out4_port=CLK_OUT4 |
51 |
CSET clk_out4_use_fine_ps_gui=false |
51 |
CSET clk_out4_use_fine_ps_gui=false |
52 |
CSET clk_out5_port=CLK_OUT5 |
52 |
CSET clk_out5_port=CLK_OUT5 |
53 |
CSET clk_out5_use_fine_ps_gui=false |
53 |
CSET clk_out5_use_fine_ps_gui=false |
54 |
CSET clk_out6_port=CLK_OUT6 |
54 |
CSET clk_out6_port=CLK_OUT6 |
55 |
CSET clk_out6_use_fine_ps_gui=false |
55 |
CSET clk_out6_use_fine_ps_gui=false |
56 |
CSET clk_out7_port=CLK_OUT7 |
56 |
CSET clk_out7_port=CLK_OUT7 |
57 |
CSET clk_out7_use_fine_ps_gui=false |
57 |
CSET clk_out7_use_fine_ps_gui=false |
58 |
CSET clk_valid_port=CLK_VALID |
58 |
CSET clk_valid_port=CLK_VALID |
59 |
CSET clkfb_in_n_port=CLKFB_IN_N |
59 |
CSET clkfb_in_n_port=CLKFB_IN_N |
60 |
CSET clkfb_in_p_port=CLKFB_IN_P |
60 |
CSET clkfb_in_p_port=CLKFB_IN_P |
61 |
CSET clkfb_in_port=CLKFB_IN |
61 |
CSET clkfb_in_port=CLKFB_IN |
62 |
CSET clkfb_in_signaling=SINGLE |
62 |
CSET clkfb_in_signaling=SINGLE |
63 |
CSET clkfb_out_n_port=CLKFB_OUT_N |
63 |
CSET clkfb_out_n_port=CLKFB_OUT_N |
64 |
CSET clkfb_out_p_port=CLKFB_OUT_P |
64 |
CSET clkfb_out_p_port=CLKFB_OUT_P |
65 |
CSET clkfb_out_port=CLKFB_OUT |
65 |
CSET clkfb_out_port=CLKFB_OUT |
66 |
CSET clkfb_stopped_port=CLKFB_STOPPED |
66 |
CSET clkfb_stopped_port=CLKFB_STOPPED |
67 |
CSET clkin1_jitter_ps=80.0 |
67 |
CSET clkin1_jitter_ps=80.0 |
68 |
CSET clkin1_ui_jitter=0.010 |
68 |
CSET clkin1_ui_jitter=0.010 |
69 |
CSET clkin2_jitter_ps=100.0 |
69 |
CSET clkin2_jitter_ps=100.0 |
70 |
CSET clkin2_ui_jitter=0.010 |
70 |
CSET clkin2_ui_jitter=0.010 |
71 |
CSET clkout1_drives=BUFG |
71 |
CSET clkout1_drives=BUFG |
72 |
CSET clkout1_requested_duty_cycle=50.000 |
72 |
CSET clkout1_requested_duty_cycle=50.000 |
73 |
CSET clkout1_requested_out_freq=100.000 |
73 |
CSET clkout1_requested_out_freq=100.000 |
74 |
CSET clkout1_requested_phase=0.000 |
74 |
CSET clkout1_requested_phase=0.000 |
75 |
CSET clkout2_drives=BUFG |
75 |
CSET clkout2_drives=BUFG |
76 |
CSET clkout2_requested_duty_cycle=50.000 |
76 |
CSET clkout2_requested_duty_cycle=50.000 |
77 |
CSET clkout2_requested_out_freq=100.000 |
77 |
CSET clkout2_requested_out_freq=100.000 |
78 |
CSET clkout2_requested_phase=0.000 |
78 |
CSET clkout2_requested_phase=0.000 |
79 |
CSET clkout2_used=false |
79 |
CSET clkout2_used=false |
80 |
CSET clkout3_drives=BUFG |
80 |
CSET clkout3_drives=BUFG |
81 |
CSET clkout3_requested_duty_cycle=50.000 |
81 |
CSET clkout3_requested_duty_cycle=50.000 |
82 |
CSET clkout3_requested_out_freq=100.000 |
82 |
CSET clkout3_requested_out_freq=100.000 |
83 |
CSET clkout3_requested_phase=0.000 |
83 |
CSET clkout3_requested_phase=0.000 |
84 |
CSET clkout3_used=false |
84 |
CSET clkout3_used=false |
85 |
CSET clkout4_drives=BUFG |
85 |
CSET clkout4_drives=BUFG |
86 |
CSET clkout4_requested_duty_cycle=50.000 |
86 |
CSET clkout4_requested_duty_cycle=50.000 |
87 |
CSET clkout4_requested_out_freq=100.000 |
87 |
CSET clkout4_requested_out_freq=100.000 |
88 |
CSET clkout4_requested_phase=0.000 |
88 |
CSET clkout4_requested_phase=0.000 |
89 |
CSET clkout4_used=false |
89 |
CSET clkout4_used=false |
90 |
CSET clkout5_drives=BUFG |
90 |
CSET clkout5_drives=BUFG |
91 |
CSET clkout5_requested_duty_cycle=50.000 |
91 |
CSET clkout5_requested_duty_cycle=50.000 |
92 |
CSET clkout5_requested_out_freq=100.000 |
92 |
CSET clkout5_requested_out_freq=100.000 |
93 |
CSET clkout5_requested_phase=0.000 |
93 |
CSET clkout5_requested_phase=0.000 |
94 |
CSET clkout5_used=false |
94 |
CSET clkout5_used=false |
95 |
CSET clkout6_drives=BUFG |
95 |
CSET clkout6_drives=BUFG |
96 |
CSET clkout6_requested_duty_cycle=50.000 |
96 |
CSET clkout6_requested_duty_cycle=50.000 |
97 |
CSET clkout6_requested_out_freq=100.000 |
97 |
CSET clkout6_requested_out_freq=100.000 |
98 |
CSET clkout6_requested_phase=0.000 |
98 |
CSET clkout6_requested_phase=0.000 |
99 |
CSET clkout6_used=false |
99 |
CSET clkout6_used=false |
100 |
CSET clkout7_drives=BUFG |
100 |
CSET clkout7_drives=BUFG |
101 |
CSET clkout7_requested_duty_cycle=50.000 |
101 |
CSET clkout7_requested_duty_cycle=50.000 |
102 |
CSET clkout7_requested_out_freq=100.000 |
102 |
CSET clkout7_requested_out_freq=100.000 |
103 |
CSET clkout7_requested_phase=0.000 |
103 |
CSET clkout7_requested_phase=0.000 |
104 |
CSET clkout7_used=false |
104 |
CSET clkout7_used=false |
105 |
CSET clock_mgr_type=MANUAL |
105 |
CSET clock_mgr_type=MANUAL |
106 |
CSET component_name=clk_125MHz_to_6MHz |
106 |
CSET component_name=clk_125MHz_to_6MHz |
107 |
CSET daddr_port=DADDR |
107 |
CSET daddr_port=DADDR |
108 |
CSET dclk_port=DCLK |
108 |
CSET dclk_port=DCLK |
109 |
CSET dcm_clk_feedback=1X |
109 |
CSET dcm_clk_feedback=1X |
110 |
CSET dcm_clk_out1_port=CLK0 |
110 |
CSET dcm_clk_out1_port=CLK0 |
111 |
CSET dcm_clk_out2_port=CLK0 |
111 |
CSET dcm_clk_out2_port=CLK0 |
112 |
CSET dcm_clk_out3_port=CLK0 |
112 |
CSET dcm_clk_out3_port=CLK0 |
113 |
CSET dcm_clk_out4_port=CLK0 |
113 |
CSET dcm_clk_out4_port=CLK0 |
114 |
CSET dcm_clk_out5_port=CLK0 |
114 |
CSET dcm_clk_out5_port=CLK0 |
115 |
CSET dcm_clk_out6_port=CLK0 |
115 |
CSET dcm_clk_out6_port=CLK0 |
116 |
CSET dcm_clkdv_divide=2.0 |
116 |
CSET dcm_clkdv_divide=2.0 |
117 |
CSET dcm_clkfx_divide=1 |
117 |
CSET dcm_clkfx_divide=1 |
118 |
CSET dcm_clkfx_multiply=4 |
118 |
CSET dcm_clkfx_multiply=4 |
119 |
CSET dcm_clkgen_clk_out1_port=CLKFX |
119 |
CSET dcm_clkgen_clk_out1_port=CLKFX |
120 |
CSET dcm_clkgen_clk_out2_port=CLKFX |
120 |
CSET dcm_clkgen_clk_out2_port=CLKFX |
121 |
CSET dcm_clkgen_clk_out3_port=CLKFX |
121 |
CSET dcm_clkgen_clk_out3_port=CLKFX |
122 |
CSET dcm_clkgen_clkfx_divide=1 |
122 |
CSET dcm_clkgen_clkfx_divide=1 |
123 |
CSET dcm_clkgen_clkfx_md_max=0.000 |
123 |
CSET dcm_clkgen_clkfx_md_max=0.000 |
124 |
CSET dcm_clkgen_clkfx_multiply=4 |
124 |
CSET dcm_clkgen_clkfx_multiply=4 |
125 |
CSET dcm_clkgen_clkfxdv_divide=2 |
125 |
CSET dcm_clkgen_clkfxdv_divide=2 |
126 |
CSET dcm_clkgen_clkin_period=10.000 |
126 |
CSET dcm_clkgen_clkin_period=10.000 |
127 |
CSET dcm_clkgen_notes=None |
127 |
CSET dcm_clkgen_notes=None |
128 |
CSET dcm_clkgen_spread_spectrum=NONE |
128 |
CSET dcm_clkgen_spread_spectrum=NONE |
129 |
CSET dcm_clkgen_startup_wait=false |
129 |
CSET dcm_clkgen_startup_wait=false |
130 |
CSET dcm_clkin_divide_by_2=false |
130 |
CSET dcm_clkin_divide_by_2=false |
131 |
CSET dcm_clkin_period=10.000 |
131 |
CSET dcm_clkin_period=10.000 |
132 |
CSET dcm_clkout_phase_shift=NONE |
132 |
CSET dcm_clkout_phase_shift=NONE |
133 |
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS |
133 |
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS |
134 |
CSET dcm_notes=None |
134 |
CSET dcm_notes=None |
135 |
CSET dcm_phase_shift=0 |
135 |
CSET dcm_phase_shift=0 |
136 |
CSET dcm_pll_cascade=NONE |
136 |
CSET dcm_pll_cascade=NONE |
137 |
CSET dcm_startup_wait=false |
137 |
CSET dcm_startup_wait=false |
138 |
CSET den_port=DEN |
138 |
CSET den_port=DEN |
139 |
CSET din_port=DIN |
139 |
CSET din_port=DIN |
140 |
CSET dout_port=DOUT |
140 |
CSET dout_port=DOUT |
141 |
CSET drdy_port=DRDY |
141 |
CSET drdy_port=DRDY |
142 |
CSET dwe_port=DWE |
142 |
CSET dwe_port=DWE |
143 |
CSET feedback_source=FDBK_AUTO |
143 |
CSET feedback_source=FDBK_AUTO |
144 |
CSET in_freq_units=Units_MHz |
144 |
CSET in_freq_units=Units_MHz |
145 |
CSET in_jitter_units=Units_UI |
145 |
CSET in_jitter_units=Units_UI |
146 |
CSET input_clk_stopped_port=INPUT_CLK_STOPPED |
146 |
CSET input_clk_stopped_port=INPUT_CLK_STOPPED |
147 |
CSET jitter_options=UI |
147 |
CSET jitter_options=UI |
148 |
CSET jitter_sel=No_Jitter |
148 |
CSET jitter_sel=No_Jitter |
149 |
CSET locked_port=LOCKED |
149 |
CSET locked_port=LOCKED |
150 |
CSET mmcm_bandwidth=OPTIMIZED |
150 |
CSET mmcm_bandwidth=OPTIMIZED |
151 |
CSET mmcm_clkfbout_mult_f=6.000 |
151 |
CSET mmcm_clkfbout_mult_f=6.000 |
152 |
CSET mmcm_clkfbout_phase=0.000 |
152 |
CSET mmcm_clkfbout_phase=0.000 |
153 |
CSET mmcm_clkfbout_use_fine_ps=false |
153 |
CSET mmcm_clkfbout_use_fine_ps=false |
154 |
CSET mmcm_clkin1_period=8.000 |
154 |
CSET mmcm_clkin1_period=8.000 |
155 |
CSET mmcm_clkin2_period=10.0 |
155 |
CSET mmcm_clkin2_period=10.0 |
156 |
CSET mmcm_clkout0_divide_f=125.000 |
156 |
CSET mmcm_clkout0_divide_f=125.000 |
157 |
CSET mmcm_clkout0_duty_cycle=0.500 |
157 |
CSET mmcm_clkout0_duty_cycle=0.500 |
158 |
CSET mmcm_clkout0_phase=0.000 |
158 |
CSET mmcm_clkout0_phase=0.000 |
159 |
CSET mmcm_clkout0_use_fine_ps=false |
159 |
CSET mmcm_clkout0_use_fine_ps=false |
160 |
CSET mmcm_clkout1_divide=1 |
160 |
CSET mmcm_clkout1_divide=1 |
161 |
CSET mmcm_clkout1_duty_cycle=0.500 |
161 |
CSET mmcm_clkout1_duty_cycle=0.500 |
162 |
CSET mmcm_clkout1_phase=0.000 |
162 |
CSET mmcm_clkout1_phase=0.000 |
163 |
CSET mmcm_clkout1_use_fine_ps=false |
163 |
CSET mmcm_clkout1_use_fine_ps=false |
164 |
CSET mmcm_clkout2_divide=1 |
164 |
CSET mmcm_clkout2_divide=1 |
165 |
CSET mmcm_clkout2_duty_cycle=0.500 |
165 |
CSET mmcm_clkout2_duty_cycle=0.500 |
166 |
CSET mmcm_clkout2_phase=0.000 |
166 |
CSET mmcm_clkout2_phase=0.000 |
167 |
CSET mmcm_clkout2_use_fine_ps=false |
167 |
CSET mmcm_clkout2_use_fine_ps=false |
168 |
CSET mmcm_clkout3_divide=1 |
168 |
CSET mmcm_clkout3_divide=1 |
169 |
CSET mmcm_clkout3_duty_cycle=0.500 |
169 |
CSET mmcm_clkout3_duty_cycle=0.500 |
170 |
CSET mmcm_clkout3_phase=0.000 |
170 |
CSET mmcm_clkout3_phase=0.000 |
171 |
CSET mmcm_clkout3_use_fine_ps=false |
171 |
CSET mmcm_clkout3_use_fine_ps=false |
172 |
CSET mmcm_clkout4_cascade=false |
172 |
CSET mmcm_clkout4_cascade=false |
173 |
CSET mmcm_clkout4_divide=1 |
173 |
CSET mmcm_clkout4_divide=1 |
174 |
CSET mmcm_clkout4_duty_cycle=0.500 |
174 |
CSET mmcm_clkout4_duty_cycle=0.500 |
175 |
CSET mmcm_clkout4_phase=0.000 |
175 |
CSET mmcm_clkout4_phase=0.000 |
176 |
CSET mmcm_clkout4_use_fine_ps=false |
176 |
CSET mmcm_clkout4_use_fine_ps=false |
177 |
CSET mmcm_clkout5_divide=1 |
177 |
CSET mmcm_clkout5_divide=1 |
178 |
CSET mmcm_clkout5_duty_cycle=0.500 |
178 |
CSET mmcm_clkout5_duty_cycle=0.500 |
179 |
CSET mmcm_clkout5_phase=0.000 |
179 |
CSET mmcm_clkout5_phase=0.000 |
180 |
CSET mmcm_clkout5_use_fine_ps=false |
180 |
CSET mmcm_clkout5_use_fine_ps=false |
181 |
CSET mmcm_clkout6_divide=1 |
181 |
CSET mmcm_clkout6_divide=1 |
182 |
CSET mmcm_clkout6_duty_cycle=0.500 |
182 |
CSET mmcm_clkout6_duty_cycle=0.500 |
183 |
CSET mmcm_clkout6_phase=0.000 |
183 |
CSET mmcm_clkout6_phase=0.000 |
184 |
CSET mmcm_clkout6_use_fine_ps=false |
184 |
CSET mmcm_clkout6_use_fine_ps=false |
185 |
CSET mmcm_clock_hold=false |
185 |
CSET mmcm_clock_hold=false |
186 |
CSET mmcm_compensation=ZHOLD |
186 |
CSET mmcm_compensation=ZHOLD |
187 |
CSET mmcm_divclk_divide=1 |
187 |
CSET mmcm_divclk_divide=1 |
188 |
CSET mmcm_notes=None |
188 |
CSET mmcm_notes=None |
189 |
CSET mmcm_ref_jitter1=0.010 |
189 |
CSET mmcm_ref_jitter1=0.010 |
190 |
CSET mmcm_ref_jitter2=0.010 |
190 |
CSET mmcm_ref_jitter2=0.010 |
191 |
CSET mmcm_startup_wait=false |
191 |
CSET mmcm_startup_wait=false |
192 |
CSET num_out_clks=1 |
192 |
CSET num_out_clks=1 |
193 |
CSET override_dcm=false |
193 |
CSET override_dcm=false |
194 |
CSET override_dcm_clkgen=false |
194 |
CSET override_dcm_clkgen=false |
195 |
CSET override_mmcm=false |
195 |
CSET override_mmcm=false |
196 |
CSET override_pll=false |
196 |
CSET override_pll=false |
197 |
CSET platform=lin64 |
197 |
CSET platform=lin64 |
198 |
CSET pll_bandwidth=OPTIMIZED |
198 |
CSET pll_bandwidth=OPTIMIZED |
199 |
CSET pll_clk_feedback=CLKFBOUT |
199 |
CSET pll_clk_feedback=CLKFBOUT |
200 |
CSET pll_clkfbout_mult=4 |
200 |
CSET pll_clkfbout_mult=4 |
201 |
CSET pll_clkfbout_phase=0.000 |
201 |
CSET pll_clkfbout_phase=0.000 |
202 |
CSET pll_clkin_period=10.000 |
202 |
CSET pll_clkin_period=10.000 |
203 |
CSET pll_clkout0_divide=1 |
203 |
CSET pll_clkout0_divide=1 |
204 |
CSET pll_clkout0_duty_cycle=0.500 |
204 |
CSET pll_clkout0_duty_cycle=0.500 |
205 |
CSET pll_clkout0_phase=0.000 |
205 |
CSET pll_clkout0_phase=0.000 |
206 |
CSET pll_clkout1_divide=1 |
206 |
CSET pll_clkout1_divide=1 |
207 |
CSET pll_clkout1_duty_cycle=0.500 |
207 |
CSET pll_clkout1_duty_cycle=0.500 |
208 |
CSET pll_clkout1_phase=0.000 |
208 |
CSET pll_clkout1_phase=0.000 |
209 |
CSET pll_clkout2_divide=1 |
209 |
CSET pll_clkout2_divide=1 |
210 |
CSET pll_clkout2_duty_cycle=0.500 |
210 |
CSET pll_clkout2_duty_cycle=0.500 |
211 |
CSET pll_clkout2_phase=0.000 |
211 |
CSET pll_clkout2_phase=0.000 |
212 |
CSET pll_clkout3_divide=1 |
212 |
CSET pll_clkout3_divide=1 |
213 |
CSET pll_clkout3_duty_cycle=0.500 |
213 |
CSET pll_clkout3_duty_cycle=0.500 |
214 |
CSET pll_clkout3_phase=0.000 |
214 |
CSET pll_clkout3_phase=0.000 |
215 |
CSET pll_clkout4_divide=1 |
215 |
CSET pll_clkout4_divide=1 |
216 |
CSET pll_clkout4_duty_cycle=0.500 |
216 |
CSET pll_clkout4_duty_cycle=0.500 |
217 |
CSET pll_clkout4_phase=0.000 |
217 |
CSET pll_clkout4_phase=0.000 |
218 |
CSET pll_clkout5_divide=1 |
218 |
CSET pll_clkout5_divide=1 |
219 |
CSET pll_clkout5_duty_cycle=0.500 |
219 |
CSET pll_clkout5_duty_cycle=0.500 |
220 |
CSET pll_clkout5_phase=0.000 |
220 |
CSET pll_clkout5_phase=0.000 |
221 |
CSET pll_compensation=SYSTEM_SYNCHRONOUS |
221 |
CSET pll_compensation=SYSTEM_SYNCHRONOUS |
222 |
CSET pll_divclk_divide=1 |
222 |
CSET pll_divclk_divide=1 |
223 |
CSET pll_notes=None |
223 |
CSET pll_notes=None |
224 |
CSET pll_ref_jitter=0.010 |
224 |
CSET pll_ref_jitter=0.010 |
225 |
CSET power_down_port=POWER_DOWN |
225 |
CSET power_down_port=POWER_DOWN |
226 |
CSET prim_in_freq=125 |
226 |
CSET prim_in_freq=125 |
227 |
CSET prim_in_jitter=0.010 |
227 |
CSET prim_in_jitter=0.010 |
228 |
CSET prim_source=Global_buffer |
228 |
CSET prim_source=Global_buffer |
229 |
CSET primary_port=CLK_IN_125 |
229 |
CSET primary_port=CLK_IN_125 |
230 |
CSET primitive=MMCM |
230 |
CSET primitive=MMCM |
231 |
CSET primtype_sel=MMCM_ADV |
231 |
CSET primtype_sel=MMCM_ADV |
232 |
CSET psclk_port=PSCLK |
232 |
CSET psclk_port=PSCLK |
233 |
CSET psdone_port=PSDONE |
233 |
CSET psdone_port=PSDONE |
234 |
CSET psen_port=PSEN |
234 |
CSET psen_port=PSEN |
235 |
CSET psincdec_port=PSINCDEC |
235 |
CSET psincdec_port=PSINCDEC |
236 |
CSET relative_inclk=REL_PRIMARY |
236 |
CSET relative_inclk=REL_PRIMARY |
237 |
CSET reset_port=RESET |
237 |
CSET reset_port=RESET |
238 |
CSET secondary_in_freq=100.000 |
238 |
CSET secondary_in_freq=100.000 |
239 |
CSET secondary_in_jitter=0.010 |
239 |
CSET secondary_in_jitter=0.010 |
240 |
CSET secondary_port=CLK_IN2 |
240 |
CSET secondary_port=CLK_IN2 |
241 |
CSET secondary_source=Single_ended_clock_capable_pin |
241 |
CSET secondary_source=Single_ended_clock_capable_pin |
242 |
CSET ss_mod_freq=250 |
242 |
CSET ss_mod_freq=250 |
243 |
CSET ss_mode=CENTER_HIGH |
243 |
CSET ss_mode=CENTER_HIGH |
244 |
CSET status_port=STATUS |
244 |
CSET status_port=STATUS |
245 |
CSET summary_strings=empty |
245 |
CSET summary_strings=empty |
246 |
CSET use_clk_valid=false |
246 |
CSET use_clk_valid=false |
247 |
CSET use_clkfb_stopped=false |
247 |
CSET use_clkfb_stopped=false |
248 |
CSET use_dyn_phase_shift=false |
248 |
CSET use_dyn_phase_shift=false |
249 |
CSET use_dyn_reconfig=false |
249 |
CSET use_dyn_reconfig=false |
250 |
CSET use_freeze=false |
250 |
CSET use_freeze=false |
251 |
CSET use_freq_synth=true |
251 |
CSET use_freq_synth=true |
252 |
CSET use_inclk_stopped=false |
252 |
CSET use_inclk_stopped=false |
253 |
CSET use_inclk_switchover=false |
253 |
CSET use_inclk_switchover=false |
254 |
CSET use_locked=false |
254 |
CSET use_locked=false |
255 |
CSET use_max_i_jitter=false |
255 |
CSET use_max_i_jitter=false |
256 |
CSET use_min_o_jitter=false |
256 |
CSET use_min_o_jitter=false |
257 |
CSET use_min_power=false |
257 |
CSET use_min_power=false |
258 |
CSET use_phase_alignment=true |
258 |
CSET use_phase_alignment=true |
259 |
CSET use_power_down=false |
259 |
CSET use_power_down=false |
260 |
CSET use_reset=false |
260 |
CSET use_reset=false |
261 |
CSET use_spread_spectrum=false |
261 |
CSET use_spread_spectrum=false |
262 |
CSET use_spread_spectrum_1=false |
262 |
CSET use_spread_spectrum_1=false |
263 |
CSET use_status=false |
263 |
CSET use_status=false |
264 |
# END Parameters |
264 |
# END Parameters |
265 |
# BEGIN Extra information |
265 |
# BEGIN Extra information |
266 |
MISC pkg_timestamp=2012-05-10T12:44:55Z |
266 |
MISC pkg_timestamp=2012-05-10T12:44:55Z |
267 |
# END Extra information |
267 |
# END Extra information |
268 |
GENERATE |
268 |
GENERATE |
269 |
# CRC: 255c3699 |
269 |
# CRC: 255c3699 |