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-- wrapper for the SPI master transmitter logic |
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-- wrapper for the SPI master transmitter logic |
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-- |
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-- |
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library ieee; |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.std_logic_1164.all; |
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|
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|
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library UNISIM; |
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library UNISIM; |
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use UNISIM.vcomponents.all; |
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use UNISIM.vcomponents.all; |
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|
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|
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library comm; |
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library comm; |
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|
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|
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entity spi_transmitter_wrapper is |
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entity spi_transmitter_wrapper is |
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generic ( |
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generic ( |
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G_DATA1 : std_logic_vector; |
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G_DATA1 : std_logic_vector; |
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G_DATA2 : std_logic_vector; |
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G_DATA2 : std_logic_vector; |
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G_NUM_BITS_PACKET : integer; |
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G_NUM_BITS_PACKET : integer; |
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G_NUM_PACKETS : integer; |
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G_NUM_PACKETS : integer; |
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G_NUM_BITS_PAUSE : integer |
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G_NUM_BITS_PAUSE : integer |
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); |
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); |
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port ( |
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port ( |
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|
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|
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-- input clock: |
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-- input clock: |
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i_clk125 : in std_logic; |
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i_clk125 : in std_logic; |
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|
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|
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i_reset : in std_logic; |
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i_reset : in std_logic; |
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|
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|
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i_data_selector : in std_logic; |
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i_data_selector : in std_logic; |
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|
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|
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o_done : out std_logic; |
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o_done : out std_logic; |
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|
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|
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-- SPI output: |
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-- SPI output: |
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OUT_SPI_N_CE : OUT std_logic_vector; |
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OUT_SPI_N_CE : OUT std_logic_vector; |
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OUT_SPI_DOUT : OUT std_logic; |
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OUT_SPI_DOUT : OUT std_logic; |
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OUT_SPI_CLK : OUT std_logic |
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OUT_SPI_CLK : OUT std_logic |
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|
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|
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); |
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); |
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|
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|
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end spi_transmitter_wrapper; |
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end spi_transmitter_wrapper; |
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|
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|
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architecture behavioral of spi_transmitter_wrapper is |
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architecture behavioral of spi_transmitter_wrapper is |
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|
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|
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component clk_125MHz_to_6MHz |
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component clk_125MHz_to_6MHz |
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port |
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port |
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(-- Clock in ports |
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(-- Clock in ports |
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CLK_IN_125 : in std_logic; |
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CLK_IN_125 : in std_logic; |
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-- Clock out ports |
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-- Clock out ports |
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CLK_OUT_6 : out std_logic |
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CLK_OUT_6 : out std_logic |
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); |
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); |
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end component; |
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end component; |
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|
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|
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-- divided clock: |
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-- divided clock: |
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signal s_spi_input_clk : std_logic; |
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signal s_spi_input_clk : std_logic; |
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signal s_clk_6MHz : std_logic; |
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signal s_clk_6MHz : std_logic; |
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signal s_clk_125kHz_tmp : std_logic; |
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signal s_clk_125kHz_tmp : std_logic; |
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attribute clock_signal : string; |
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attribute clock_signal : string; |
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attribute clock_signal of s_spi_input_clk : signal is "yes"; |
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attribute clock_signal of s_spi_input_clk : signal is "yes"; |
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|
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|
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-- SPI output pins registers: |
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-- SPI output pins registers: |
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signal s_out_spi_n_ce_d : std_logic_vector( OUT_SPI_N_CE'range ); |
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signal s_out_spi_n_ce_d : std_logic_vector( OUT_SPI_N_CE'range ); |
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signal s_out_spi_dout_d : std_logic; |
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signal s_out_spi_dout_d : std_logic; |
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signal s_out_spi_clk_d : std_logic; |
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signal s_out_spi_clk_d : std_logic; |
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|
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|
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-- pack the OUT registers to IOB so that the timing is better: |
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-- pack the OUT registers to IOB so that the timing is better: |
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attribute iob : string; |
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attribute iob : string; |
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attribute iob of OUT_SPI_N_CE : signal is "FORCE"; |
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attribute iob of OUT_SPI_N_CE : signal is "FORCE"; |
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attribute iob of OUT_SPI_DOUT : signal is "FORCE"; |
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attribute iob of OUT_SPI_DOUT : signal is "FORCE"; |
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attribute iob of OUT_SPI_CLK : signal is "FORCE"; |
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attribute iob of OUT_SPI_CLK : signal is "FORCE"; |
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|
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|
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begin |
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begin |
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|
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|
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-- IP Core clock wizard: |
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-- IP Core clock wizard: |
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clk_125MHz_to_6MHz_inst : clk_125MHz_to_6MHz |
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clk_125MHz_to_6MHz_inst : clk_125MHz_to_6MHz |
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port map ( CLK_IN_125 => i_clk125, CLK_OUT_6 => s_clk_6MHz ); |
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port map ( CLK_IN_125 => i_clk125, CLK_OUT_6 => s_clk_6MHz ); |
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|
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|
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-- ~1MHz clock: |
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-- ~1MHz clock: |
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BUFR_inst : BUFR |
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BUFR_inst : BUFR |
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generic map ( |
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generic map ( |
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BUFR_DIVIDE => "6", SIM_DEVICE => "VIRTEX6" ) |
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BUFR_DIVIDE => "6", SIM_DEVICE => "VIRTEX6" ) |
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port map ( |
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port map ( |
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O => s_clk_125kHz_tmp, -- s_spi_input_clk |
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O => s_clk_125kHz_tmp, -- s_spi_input_clk |
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CE => '1', |
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CE => '1', |
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CLR => '0', |
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CLR => '0', |
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I => s_clk_6MHz |
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I => s_clk_6MHz |
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); |
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); |
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|
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|
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BUFR2_inst : BUFR |
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BUFR2_inst : BUFR |
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generic map ( |
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generic map ( |
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BUFR_DIVIDE => "8", SIM_DEVICE => "VIRTEX6" ) |
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BUFR_DIVIDE => "8", SIM_DEVICE => "VIRTEX6" ) |
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port map ( |
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port map ( |
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O => s_spi_input_clk, |
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O => s_spi_input_clk, |
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CE => '1', |
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CE => '1', |
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CLR => '0', |
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CLR => '0', |
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I => s_clk_125kHz_tmp |
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I => s_clk_125kHz_tmp |
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); |
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); |
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|
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|
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-- SPI master transmitter: |
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-- SPI master transmitter: |
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spi_transmit_inst : entity comm.spi_master_transmit |
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spi_transmit_inst : entity comm.spi_master_transmit |
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generic map( |
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generic map( |
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G_DATA1 => G_DATA1, |
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G_DATA1 => G_DATA1, |
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G_DATA2 => G_DATA2, |
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G_DATA2 => G_DATA2, |
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G_NUM_BITS_PACKET => G_NUM_BITS_PACKET, |
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G_NUM_BITS_PACKET => G_NUM_BITS_PACKET, |
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G_NUM_PACKETS => G_NUM_PACKETS, |
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G_NUM_PACKETS => G_NUM_PACKETS, |
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G_NUM_BITS_PAUSE => G_NUM_BITS_PAUSE ) |
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G_NUM_BITS_PAUSE => G_NUM_BITS_PAUSE ) |
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port map( |
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port map( |
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i_clk => s_spi_input_clk, i_rst => i_reset, i_data_selector => i_data_selector, |
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i_clk => s_spi_input_clk, i_rst => i_reset, i_data_selector => i_data_selector, |
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o_done => o_done, |
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o_done => o_done, |
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o_n_ce => s_out_spi_n_ce_d, |
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o_n_ce => s_out_spi_n_ce_d, |
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o_dout => s_out_spi_dout_d, |
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o_dout => s_out_spi_dout_d, |
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o_clk => s_out_spi_clk_d |
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o_clk => s_out_spi_clk_d |
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); |
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); |
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|
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|
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-- registers: |
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-- registers: |
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registered_spi_output : process( s_clk_6MHz ) |
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registered_spi_output : process( s_clk_6MHz ) |
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begin |
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begin |
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if( rising_edge( s_clk_6MHz ) ) then |
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if( rising_edge( s_clk_6MHz ) ) then |
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OUT_SPI_N_CE <= s_out_spi_n_ce_d; |
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OUT_SPI_N_CE <= s_out_spi_n_ce_d; |
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OUT_SPI_DOUT <= s_out_spi_dout_d; |
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OUT_SPI_DOUT <= s_out_spi_dout_d; |
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OUT_SPI_CLK <= s_out_spi_clk_d; |
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OUT_SPI_CLK <= s_out_spi_clk_d; |
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end if; |
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end if; |
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end process; |
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end process; |
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|
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|
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end architecture; |
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end architecture; |
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