Rev 4918 Rev 4962
1 ----------------------------------------------- 1 -----------------------------------------------
2 -- wrapper for the SPI master transmitter logic 2 -- wrapper for the SPI master transmitter logic
3 -- 3 --
4 library ieee; 4 library ieee;
5 use ieee.std_logic_1164.all; 5 use ieee.std_logic_1164.all;
6   6  
7 library UNISIM; 7 library UNISIM;
8 use UNISIM.vcomponents.all; 8 use UNISIM.vcomponents.all;
9   9  
10 library comm; 10 library comm;
11   11  
12 entity spi_transmitter_wrapper is 12 entity spi_transmitter_wrapper is
13 generic ( 13 generic (
14 G_DATA1 : std_logic_vector; 14 G_DATA1 : std_logic_vector;
15 G_DATA2 : std_logic_vector; 15 G_DATA2 : std_logic_vector;
16 G_NUM_BITS_PACKET : integer; 16 G_NUM_BITS_PACKET : integer;
17 G_NUM_PACKETS : integer; 17 G_NUM_PACKETS : integer;
18 G_NUM_BITS_PAUSE : integer 18 G_NUM_BITS_PAUSE : integer
19 ); 19 );
20 port ( 20 port (
21 21
22 -- input clock: 22 -- input clock:
23 i_clk125 : in std_logic; 23 i_clk125 : in std_logic;
24 24
25 i_reset : in std_logic; 25 i_reset : in std_logic;
26 26
27 i_data_selector : in std_logic; 27 i_data_selector : in std_logic;
28 28
29 o_done : out std_logic; 29 o_done : out std_logic;
30 30
31 -- SPI output: 31 -- SPI output:
32 OUT_SPI_N_CE : OUT std_logic_vector; 32 OUT_SPI_N_CE : OUT std_logic_vector;
33 OUT_SPI_DOUT : OUT std_logic; 33 OUT_SPI_DOUT : OUT std_logic;
34 OUT_SPI_CLK : OUT std_logic 34 OUT_SPI_CLK : OUT std_logic
35 35
36 ); 36 );
37 37
38 end spi_transmitter_wrapper; 38 end spi_transmitter_wrapper;
39   39  
40 architecture behavioral of spi_transmitter_wrapper is 40 architecture behavioral of spi_transmitter_wrapper is
41   41  
42 component clk_125MHz_to_6MHz 42 component clk_125MHz_to_6MHz
43 port 43 port
44 (-- Clock in ports 44 (-- Clock in ports
45 CLK_IN_125 : in std_logic; 45 CLK_IN_125 : in std_logic;
46 -- Clock out ports 46 -- Clock out ports
47 CLK_OUT_6 : out std_logic 47 CLK_OUT_6 : out std_logic
48 ); 48 );
49 end component; 49 end component;
50   50  
51 -- divided clock: 51 -- divided clock:
52 signal s_spi_input_clk : std_logic; 52 signal s_spi_input_clk : std_logic;
53 signal s_clk_6MHz : std_logic; 53 signal s_clk_6MHz : std_logic;
54 signal s_clk_125kHz_tmp : std_logic; 54 signal s_clk_125kHz_tmp : std_logic;
55 attribute clock_signal : string; 55 attribute clock_signal : string;
56 attribute clock_signal of s_spi_input_clk : signal is "yes"; 56 attribute clock_signal of s_spi_input_clk : signal is "yes";
57 57
58 -- SPI output pins registers: 58 -- SPI output pins registers:
59 signal s_out_spi_n_ce_d : std_logic_vector( OUT_SPI_N_CE'range ); 59 signal s_out_spi_n_ce_d : std_logic_vector( OUT_SPI_N_CE'range );
60 signal s_out_spi_dout_d : std_logic; 60 signal s_out_spi_dout_d : std_logic;
61 signal s_out_spi_clk_d : std_logic; 61 signal s_out_spi_clk_d : std_logic;
62 62
63 -- pack the OUT registers to IOB so that the timing is better: 63 -- pack the OUT registers to IOB so that the timing is better:
64 attribute iob : string; 64 attribute iob : string;
65 attribute iob of OUT_SPI_N_CE : signal is "FORCE"; 65 attribute iob of OUT_SPI_N_CE : signal is "FORCE";
66 attribute iob of OUT_SPI_DOUT : signal is "FORCE"; 66 attribute iob of OUT_SPI_DOUT : signal is "FORCE";
67 attribute iob of OUT_SPI_CLK : signal is "FORCE"; 67 attribute iob of OUT_SPI_CLK : signal is "FORCE";
68   68  
69 begin 69 begin
70   70  
71 -- IP Core clock wizard: 71 -- IP Core clock wizard:
72 clk_125MHz_to_6MHz_inst : clk_125MHz_to_6MHz 72 clk_125MHz_to_6MHz_inst : clk_125MHz_to_6MHz
73 port map ( CLK_IN_125 => i_clk125, CLK_OUT_6 => s_clk_6MHz ); 73 port map ( CLK_IN_125 => i_clk125, CLK_OUT_6 => s_clk_6MHz );
74   74  
75 -- ~1MHz clock: 75 -- ~1MHz clock:
76 BUFR_inst : BUFR 76 BUFR_inst : BUFR
77 generic map ( 77 generic map (
78 BUFR_DIVIDE => "6", SIM_DEVICE => "VIRTEX6" ) 78 BUFR_DIVIDE => "6", SIM_DEVICE => "VIRTEX6" )
79 port map ( 79 port map (
80 O => s_clk_125kHz_tmp, -- s_spi_input_clk 80 O => s_clk_125kHz_tmp, -- s_spi_input_clk
81 CE => '1', 81 CE => '1',
82 CLR => '0', 82 CLR => '0',
83 I => s_clk_6MHz 83 I => s_clk_6MHz
84 ); 84 );
85 85
86 BUFR2_inst : BUFR 86 BUFR2_inst : BUFR
87 generic map ( 87 generic map (
88 BUFR_DIVIDE => "8", SIM_DEVICE => "VIRTEX6" ) 88 BUFR_DIVIDE => "8", SIM_DEVICE => "VIRTEX6" )
89 port map ( 89 port map (
90 O => s_spi_input_clk, 90 O => s_spi_input_clk,
91 CE => '1', 91 CE => '1',
92 CLR => '0', 92 CLR => '0',
93 I => s_clk_125kHz_tmp 93 I => s_clk_125kHz_tmp
94 ); 94 );
95   95  
96 -- SPI master transmitter: 96 -- SPI master transmitter:
97 spi_transmit_inst : entity comm.spi_master_transmit 97 spi_transmit_inst : entity comm.spi_master_transmit
98 generic map( 98 generic map(
99 G_DATA1 => G_DATA1, 99 G_DATA1 => G_DATA1,
100 G_DATA2 => G_DATA2, 100 G_DATA2 => G_DATA2,
101 G_NUM_BITS_PACKET => G_NUM_BITS_PACKET, 101 G_NUM_BITS_PACKET => G_NUM_BITS_PACKET,
102 G_NUM_PACKETS => G_NUM_PACKETS, 102 G_NUM_PACKETS => G_NUM_PACKETS,
103 G_NUM_BITS_PAUSE => G_NUM_BITS_PAUSE ) 103 G_NUM_BITS_PAUSE => G_NUM_BITS_PAUSE )
104 port map( 104 port map(
105 i_clk => s_spi_input_clk, i_rst => i_reset, i_data_selector => i_data_selector, 105 i_clk => s_spi_input_clk, i_rst => i_reset, i_data_selector => i_data_selector,
106 o_done => o_done, 106 o_done => o_done,
107 o_n_ce => s_out_spi_n_ce_d, 107 o_n_ce => s_out_spi_n_ce_d,
108 o_dout => s_out_spi_dout_d, 108 o_dout => s_out_spi_dout_d,
109 o_clk => s_out_spi_clk_d 109 o_clk => s_out_spi_clk_d
110 ); 110 );
111 111
112 -- registers: 112 -- registers:
113 registered_spi_output : process( s_clk_6MHz ) 113 registered_spi_output : process( s_clk_6MHz )
114 begin 114 begin
115 if( rising_edge( s_clk_6MHz ) ) then 115 if( rising_edge( s_clk_6MHz ) ) then
116 OUT_SPI_N_CE <= s_out_spi_n_ce_d; 116 OUT_SPI_N_CE <= s_out_spi_n_ce_d;
117 OUT_SPI_DOUT <= s_out_spi_dout_d; 117 OUT_SPI_DOUT <= s_out_spi_dout_d;
118 OUT_SPI_CLK <= s_out_spi_clk_d; 118 OUT_SPI_CLK <= s_out_spi_clk_d;
119 end if; 119 end if;
120 end process; 120 end process;
121 121
122 end architecture; 122 end architecture;
123   123