Rev 4918 Rev 4962
1 -- Dummy user_logic_cmp_winfo 1 -- Dummy user_logic_cmp_winfo
2 -- 2 --
3 -- 3 --
4 -- Uses only data1 stream and simply adds to each byte a given number 4 -- Uses only data1 stream and simply adds to each byte a given number
5 -- 5 --
6 -- uses the information_block entity for version/type control 6 -- uses the information_block entity for version/type control
7   7  
8 library ieee; 8 library ieee;
9 use ieee.std_logic_1164.all; 9 use ieee.std_logic_1164.all;
10 use ieee.numeric_std.all; 10 use ieee.numeric_std.all;
11   11  
12 entity user_logic_cmp is 12 entity user_logic_cmp is
13 port ( 13 port (
14 i_clk : in std_logic; 14 i_clk : in std_logic;
15 i_rst : in std_logic; 15 i_rst : in std_logic;
16 16
17 -- data1 interface: 17 -- data1 interface:
18 i_data1in_data : in std_logic_vector( 31 downto 0 ); 18 i_data1in_data : in std_logic_vector( 31 downto 0 );
19 i_data1in_valid : in std_logic; 19 i_data1in_valid : in std_logic;
20 o_data1in_enable : out std_logic; 20 o_data1in_enable : out std_logic;
21 o_data1out_data : out std_logic_vector( 31 downto 0 ); 21 o_data1out_data : out std_logic_vector( 31 downto 0 );
22 o_data1out_valid : out std_logic; 22 o_data1out_valid : out std_logic;
23 i_data1out_enable : in std_logic; 23 i_data1out_enable : in std_logic;
24 24
25 -- data2 interface: 25 -- data2 interface:
26 i_data2in_data : in std_logic_vector( 31 downto 0 ); 26 i_data2in_data : in std_logic_vector( 31 downto 0 );
27 i_data2in_valid : in std_logic; 27 i_data2in_valid : in std_logic;
28 o_data2in_enable : out std_logic; 28 o_data2in_enable : out std_logic;
29 o_data2out_data : out std_logic_vector( 31 downto 0 ); 29 o_data2out_data : out std_logic_vector( 31 downto 0 );
30 o_data2out_valid : out std_logic; 30 o_data2out_valid : out std_logic;
31 i_data2out_enable : in std_logic; 31 i_data2out_enable : in std_logic;
32 32
33 -- control interface: 33 -- control interface:
34 i_controlin_data : in std_logic_vector( 31 downto 0 ); 34 i_controlin_data : in std_logic_vector( 31 downto 0 );
35 i_controlin_valid : in std_logic; 35 i_controlin_valid : in std_logic;
36 o_controlin_enable : out std_logic; 36 o_controlin_enable : out std_logic;
37 o_controlout_data : out std_logic_vector( 31 downto 0 ); 37 o_controlout_data : out std_logic_vector( 31 downto 0 );
38 o_controlout_valid : out std_logic; 38 o_controlout_valid : out std_logic;
39 i_controlout_enable : in std_logic 39 i_controlout_enable : in std_logic
40 40
41 ); 41 );
42 end entity; 42 end entity;
43   43  
44 architecture behavioral of user_logic_cmp is 44 architecture behavioral of user_logic_cmp is
45   45  
46 component information_block is 46 component information_block is
47 port ( 47 port (
48 clk : in std_logic; rst : in std_logic; 48 clk : in std_logic; rst : in std_logic;
49 -- Input side: 49 -- Input side:
50 i_data : in std_logic_vector( 31 downto 0 ); i_valid : in std_logic; o_enable : out std_logic; 50 i_data : in std_logic_vector( 31 downto 0 ); i_valid : in std_logic; o_enable : out std_logic;
51 -- Output side: 51 -- Output side:
52 o_data : out std_logic_vector( 31 downto 0 ); o_valid : out std_logic; i_enable : in std_logic ); 52 o_data : out std_logic_vector( 31 downto 0 ); o_valid : out std_logic; i_enable : in std_logic );
53 end component; 53 end component;
54   54  
55 begin 55 begin
56   56  
57 -- Example how to read and transmit data: 57 -- Example how to read and transmit data:
58 sum_process : process( i_clk ) 58 sum_process : process( i_clk )
59 begin 59 begin
60 if( rising_edge( i_clk ) ) then 60 if( rising_edge( i_clk ) ) then
61 if( i_rst = '1' ) then 61 if( i_rst = '1' ) then
62 o_data1out_data <= ( others => '0' ); 62 o_data1out_data <= ( others => '0' );
63 o_data1out_valid <= '0'; 63 o_data1out_valid <= '0';
64 else 64 else
65 o_data1out_data( 31 downto 24 ) <= std_logic_vector( unsigned(i_data1in_data( 31 downto 24 )) + to_unsigned(1,8) ); 65 o_data1out_data( 31 downto 24 ) <= std_logic_vector( unsigned(i_data1in_data( 31 downto 24 )) + to_unsigned(1,8) );
66 o_data1out_data( 23 downto 16 ) <= std_logic_vector( unsigned(i_data1in_data( 23 downto 16 )) + to_unsigned(2,8) ); 66 o_data1out_data( 23 downto 16 ) <= std_logic_vector( unsigned(i_data1in_data( 23 downto 16 )) + to_unsigned(2,8) );
67 o_data1out_data( 15 downto 8 ) <= std_logic_vector( unsigned(i_data1in_data( 15 downto 8 )) + to_unsigned(3,8) ); 67 o_data1out_data( 15 downto 8 ) <= std_logic_vector( unsigned(i_data1in_data( 15 downto 8 )) + to_unsigned(3,8) );
68 o_data1out_data( 7 downto 0 ) <= std_logic_vector( unsigned(i_data1in_data( 7 downto 0 )) + to_unsigned(4,8) ); 68 o_data1out_data( 7 downto 0 ) <= std_logic_vector( unsigned(i_data1in_data( 7 downto 0 )) + to_unsigned(4,8) );
69 o_data1out_valid <= i_data1in_valid; 69 o_data1out_valid <= i_data1in_valid;
70 end if; 70 end if;
71 end if; 71 end if;
72 end process; 72 end process;
73 o_data1in_enable <= i_data1out_enable; 73 o_data1in_enable <= i_data1out_enable;
74 74
75 -- information_block: 75 -- information_block:
76 info_block_inst : information_block 76 info_block_inst : information_block
77 port map ( 77 port map (
78 clk => i_clk, rst => i_rst, 78 clk => i_clk, rst => i_rst,
79 i_data => i_controlin_data, i_valid => i_controlin_valid, o_enable => o_controlin_enable, 79 i_data => i_controlin_data, i_valid => i_controlin_valid, o_enable => o_controlin_enable,
80 o_data => o_controlout_data, o_valid => o_controlout_valid, i_enable => i_controlout_enable ); 80 o_data => o_controlout_data, o_valid => o_controlout_valid, i_enable => i_controlout_enable );
81 81
82 end architecture; 82 end architecture;