Rev 3641 Rev 4962
1 ############################################################## 1 ##############################################################
2 # 2 #
3 # Xilinx Core Generator version 14.3 3 # Xilinx Core Generator version 14.3
4 # Date: Tue Apr 29 09:14:51 2014 4 # Date: Tue Apr 29 09:14:51 2014
5 # 5 #
6 ############################################################## 6 ##############################################################
7 # 7 #
8 # This file contains the customisation parameters for a 8 # This file contains the customisation parameters for a
9 # Xilinx CORE Generator IP GUI. It is strongly recommended 9 # Xilinx CORE Generator IP GUI. It is strongly recommended
10 # that you do not manually alter this file as it may cause 10 # that you do not manually alter this file as it may cause
11 # unexpected and unsupported behavior. 11 # unexpected and unsupported behavior.
12 # 12 #
13 ############################################################## 13 ##############################################################
14 # 14 #
15 # Generated from component: xilinx.com:ip:fifo_generator:9.2 15 # Generated from component: xilinx.com:ip:fifo_generator:9.2
16 # 16 #
17 ############################################################## 17 ##############################################################
18 # 18 #
19 # BEGIN Project Options 19 # BEGIN Project Options
20 SET addpads = false 20 SET addpads = false
21 SET asysymbol = true 21 SET asysymbol = true
22 SET busformat = BusFormatAngleBracketNotRipped 22 SET busformat = BusFormatAngleBracketNotRipped
23 SET createndf = false 23 SET createndf = false
24 SET designentry = VHDL 24 SET designentry = VHDL
25 SET device = xc6vlx240t 25 SET device = xc6vlx240t
26 SET devicefamily = virtex6 26 SET devicefamily = virtex6
27 SET flowvendor = Other 27 SET flowvendor = Other
28 SET formalverification = false 28 SET formalverification = false
29 SET foundationsym = false 29 SET foundationsym = false
30 SET implementationfiletype = Ngc 30 SET implementationfiletype = Ngc
31 SET package = ff1156 31 SET package = ff1156
32 SET removerpms = false 32 SET removerpms = false
33 SET simulationfiles = Behavioral 33 SET simulationfiles = Behavioral
34 SET speedgrade = -1 34 SET speedgrade = -1
35 SET verilogsim = false 35 SET verilogsim = false
36 SET vhdlsim = true 36 SET vhdlsim = true
37 # END Project Options 37 # END Project Options
38 # BEGIN Select 38 # BEGIN Select
39 SELECT Fifo_Generator xilinx.com:ip:fifo_generator:9.2 39 SELECT Fifo_Generator xilinx.com:ip:fifo_generator:9.2
40 # END Select 40 # END Select
41 # BEGIN Parameters 41 # BEGIN Parameters
42 CSET add_ngc_constraint_axi=false 42 CSET add_ngc_constraint_axi=false
43 CSET almost_empty_flag=false 43 CSET almost_empty_flag=false
44 CSET almost_full_flag=false 44 CSET almost_full_flag=false
45 CSET aruser_width=1 45 CSET aruser_width=1
46 CSET awuser_width=1 46 CSET awuser_width=1
47 CSET axi_address_width=32 47 CSET axi_address_width=32
48 CSET axi_data_width=64 48 CSET axi_data_width=64
49 CSET axi_type=AXI4_Stream 49 CSET axi_type=AXI4_Stream
50 CSET axis_type=FIFO 50 CSET axis_type=FIFO
51 CSET buser_width=1 51 CSET buser_width=1
52 CSET clock_enable_type=Slave_Interface_Clock_Enable 52 CSET clock_enable_type=Slave_Interface_Clock_Enable
53 CSET clock_type_axi=Common_Clock 53 CSET clock_type_axi=Common_Clock
54 CSET component_name=fifo_32x512 54 CSET component_name=fifo_32x512
55 CSET data_count=false 55 CSET data_count=false
56 CSET data_count_width=9 56 CSET data_count_width=9
57 CSET disable_timing_violations=false 57 CSET disable_timing_violations=false
58 CSET disable_timing_violations_axi=false 58 CSET disable_timing_violations_axi=false
59 CSET dout_reset_value=0 59 CSET dout_reset_value=0
60 CSET empty_threshold_assert_value=2 60 CSET empty_threshold_assert_value=2
61 CSET empty_threshold_assert_value_axis=1022 61 CSET empty_threshold_assert_value_axis=1022
62 CSET empty_threshold_assert_value_rach=1022 62 CSET empty_threshold_assert_value_rach=1022
63 CSET empty_threshold_assert_value_rdch=1022 63 CSET empty_threshold_assert_value_rdch=1022
64 CSET empty_threshold_assert_value_wach=1022 64 CSET empty_threshold_assert_value_wach=1022
65 CSET empty_threshold_assert_value_wdch=1022 65 CSET empty_threshold_assert_value_wdch=1022
66 CSET empty_threshold_assert_value_wrch=1022 66 CSET empty_threshold_assert_value_wrch=1022
67 CSET empty_threshold_negate_value=3 67 CSET empty_threshold_negate_value=3
68 CSET enable_aruser=false 68 CSET enable_aruser=false
69 CSET enable_awuser=false 69 CSET enable_awuser=false
70 CSET enable_buser=false 70 CSET enable_buser=false
71 CSET enable_common_overflow=false 71 CSET enable_common_overflow=false
72 CSET enable_common_underflow=false 72 CSET enable_common_underflow=false
73 CSET enable_data_counts_axis=false 73 CSET enable_data_counts_axis=false
74 CSET enable_data_counts_rach=false 74 CSET enable_data_counts_rach=false
75 CSET enable_data_counts_rdch=false 75 CSET enable_data_counts_rdch=false
76 CSET enable_data_counts_wach=false 76 CSET enable_data_counts_wach=false
77 CSET enable_data_counts_wdch=false 77 CSET enable_data_counts_wdch=false
78 CSET enable_data_counts_wrch=false 78 CSET enable_data_counts_wrch=false
79 CSET enable_ecc=false 79 CSET enable_ecc=false
80 CSET enable_ecc_axis=false 80 CSET enable_ecc_axis=false
81 CSET enable_ecc_rach=false 81 CSET enable_ecc_rach=false
82 CSET enable_ecc_rdch=false 82 CSET enable_ecc_rdch=false
83 CSET enable_ecc_wach=false 83 CSET enable_ecc_wach=false
84 CSET enable_ecc_wdch=false 84 CSET enable_ecc_wdch=false
85 CSET enable_ecc_wrch=false 85 CSET enable_ecc_wrch=false
86 CSET enable_read_channel=false 86 CSET enable_read_channel=false
87 CSET enable_read_pointer_increment_by2=false 87 CSET enable_read_pointer_increment_by2=false
88 CSET enable_reset_synchronization=true 88 CSET enable_reset_synchronization=true
89 CSET enable_ruser=false 89 CSET enable_ruser=false
90 CSET enable_tdata=false 90 CSET enable_tdata=false
91 CSET enable_tdest=false 91 CSET enable_tdest=false
92 CSET enable_tid=false 92 CSET enable_tid=false
93 CSET enable_tkeep=false 93 CSET enable_tkeep=false
94 CSET enable_tlast=false 94 CSET enable_tlast=false
95 CSET enable_tready=true 95 CSET enable_tready=true
96 CSET enable_tstrobe=false 96 CSET enable_tstrobe=false
97 CSET enable_tuser=false 97 CSET enable_tuser=false
98 CSET enable_write_channel=false 98 CSET enable_write_channel=false
99 CSET enable_wuser=false 99 CSET enable_wuser=false
100 CSET fifo_application_type_axis=Data_FIFO 100 CSET fifo_application_type_axis=Data_FIFO
101 CSET fifo_application_type_rach=Data_FIFO 101 CSET fifo_application_type_rach=Data_FIFO
102 CSET fifo_application_type_rdch=Data_FIFO 102 CSET fifo_application_type_rdch=Data_FIFO
103 CSET fifo_application_type_wach=Data_FIFO 103 CSET fifo_application_type_wach=Data_FIFO
104 CSET fifo_application_type_wdch=Data_FIFO 104 CSET fifo_application_type_wdch=Data_FIFO
105 CSET fifo_application_type_wrch=Data_FIFO 105 CSET fifo_application_type_wrch=Data_FIFO
106 CSET fifo_implementation=Common_Clock_Block_RAM 106 CSET fifo_implementation=Common_Clock_Block_RAM
107 CSET fifo_implementation_axis=Common_Clock_Block_RAM 107 CSET fifo_implementation_axis=Common_Clock_Block_RAM
108 CSET fifo_implementation_rach=Common_Clock_Block_RAM 108 CSET fifo_implementation_rach=Common_Clock_Block_RAM
109 CSET fifo_implementation_rdch=Common_Clock_Block_RAM 109 CSET fifo_implementation_rdch=Common_Clock_Block_RAM
110 CSET fifo_implementation_wach=Common_Clock_Block_RAM 110 CSET fifo_implementation_wach=Common_Clock_Block_RAM
111 CSET fifo_implementation_wdch=Common_Clock_Block_RAM 111 CSET fifo_implementation_wdch=Common_Clock_Block_RAM
112 CSET fifo_implementation_wrch=Common_Clock_Block_RAM 112 CSET fifo_implementation_wrch=Common_Clock_Block_RAM
113 CSET full_flags_reset_value=0 113 CSET full_flags_reset_value=0
114 CSET full_threshold_assert_value=510 114 CSET full_threshold_assert_value=510
115 CSET full_threshold_assert_value_axis=1023 115 CSET full_threshold_assert_value_axis=1023
116 CSET full_threshold_assert_value_rach=1023 116 CSET full_threshold_assert_value_rach=1023
117 CSET full_threshold_assert_value_rdch=1023 117 CSET full_threshold_assert_value_rdch=1023
118 CSET full_threshold_assert_value_wach=1023 118 CSET full_threshold_assert_value_wach=1023
119 CSET full_threshold_assert_value_wdch=1023 119 CSET full_threshold_assert_value_wdch=1023
120 CSET full_threshold_assert_value_wrch=1023 120 CSET full_threshold_assert_value_wrch=1023
121 CSET full_threshold_negate_value=509 121 CSET full_threshold_negate_value=509
122 CSET id_width=4 122 CSET id_width=4
123 CSET inject_dbit_error=false 123 CSET inject_dbit_error=false
124 CSET inject_dbit_error_axis=false 124 CSET inject_dbit_error_axis=false
125 CSET inject_dbit_error_rach=false 125 CSET inject_dbit_error_rach=false
126 CSET inject_dbit_error_rdch=false 126 CSET inject_dbit_error_rdch=false
127 CSET inject_dbit_error_wach=false 127 CSET inject_dbit_error_wach=false
128 CSET inject_dbit_error_wdch=false 128 CSET inject_dbit_error_wdch=false
129 CSET inject_dbit_error_wrch=false 129 CSET inject_dbit_error_wrch=false
130 CSET inject_sbit_error=false 130 CSET inject_sbit_error=false
131 CSET inject_sbit_error_axis=false 131 CSET inject_sbit_error_axis=false
132 CSET inject_sbit_error_rach=false 132 CSET inject_sbit_error_rach=false
133 CSET inject_sbit_error_rdch=false 133 CSET inject_sbit_error_rdch=false
134 CSET inject_sbit_error_wach=false 134 CSET inject_sbit_error_wach=false
135 CSET inject_sbit_error_wdch=false 135 CSET inject_sbit_error_wdch=false
136 CSET inject_sbit_error_wrch=false 136 CSET inject_sbit_error_wrch=false
137 CSET input_data_width=32 137 CSET input_data_width=32
138 CSET input_depth=512 138 CSET input_depth=512
139 CSET input_depth_axis=1024 139 CSET input_depth_axis=1024
140 CSET input_depth_rach=16 140 CSET input_depth_rach=16
141 CSET input_depth_rdch=1024 141 CSET input_depth_rdch=1024
142 CSET input_depth_wach=16 142 CSET input_depth_wach=16
143 CSET input_depth_wdch=1024 143 CSET input_depth_wdch=1024
144 CSET input_depth_wrch=16 144 CSET input_depth_wrch=16
145 CSET interface_type=Native 145 CSET interface_type=Native
146 CSET output_data_width=32 146 CSET output_data_width=32
147 CSET output_depth=512 147 CSET output_depth=512
148 CSET overflow_flag=false 148 CSET overflow_flag=false
149 CSET overflow_flag_axi=false 149 CSET overflow_flag_axi=false
150 CSET overflow_sense=Active_High 150 CSET overflow_sense=Active_High
151 CSET overflow_sense_axi=Active_High 151 CSET overflow_sense_axi=Active_High
152 CSET performance_options=Standard_FIFO 152 CSET performance_options=Standard_FIFO
153 CSET programmable_empty_type=No_Programmable_Empty_Threshold 153 CSET programmable_empty_type=No_Programmable_Empty_Threshold
154 CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold 154 CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
155 CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold 155 CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
156 CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold 156 CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
157 CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold 157 CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
158 CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold 158 CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
159 CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold 159 CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
160 CSET programmable_full_type=No_Programmable_Full_Threshold 160 CSET programmable_full_type=No_Programmable_Full_Threshold
161 CSET programmable_full_type_axis=No_Programmable_Full_Threshold 161 CSET programmable_full_type_axis=No_Programmable_Full_Threshold
162 CSET programmable_full_type_rach=No_Programmable_Full_Threshold 162 CSET programmable_full_type_rach=No_Programmable_Full_Threshold
163 CSET programmable_full_type_rdch=No_Programmable_Full_Threshold 163 CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
164 CSET programmable_full_type_wach=No_Programmable_Full_Threshold 164 CSET programmable_full_type_wach=No_Programmable_Full_Threshold
165 CSET programmable_full_type_wdch=No_Programmable_Full_Threshold 165 CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
166 CSET programmable_full_type_wrch=No_Programmable_Full_Threshold 166 CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
167 CSET rach_type=FIFO 167 CSET rach_type=FIFO
168 CSET rdch_type=FIFO 168 CSET rdch_type=FIFO
169 CSET read_clock_frequency=1 169 CSET read_clock_frequency=1
170 CSET read_data_count=false 170 CSET read_data_count=false
171 CSET read_data_count_width=9 171 CSET read_data_count_width=9
172 CSET register_slice_mode_axis=Fully_Registered 172 CSET register_slice_mode_axis=Fully_Registered
173 CSET register_slice_mode_rach=Fully_Registered 173 CSET register_slice_mode_rach=Fully_Registered
174 CSET register_slice_mode_rdch=Fully_Registered 174 CSET register_slice_mode_rdch=Fully_Registered
175 CSET register_slice_mode_wach=Fully_Registered 175 CSET register_slice_mode_wach=Fully_Registered
176 CSET register_slice_mode_wdch=Fully_Registered 176 CSET register_slice_mode_wdch=Fully_Registered
177 CSET register_slice_mode_wrch=Fully_Registered 177 CSET register_slice_mode_wrch=Fully_Registered
178 CSET reset_pin=true 178 CSET reset_pin=true
179 CSET reset_type=Synchronous_Reset 179 CSET reset_type=Synchronous_Reset
180 CSET ruser_width=1 180 CSET ruser_width=1
181 CSET synchronization_stages=2 181 CSET synchronization_stages=2
182 CSET synchronization_stages_axi=2 182 CSET synchronization_stages_axi=2
183 CSET tdata_width=64 183 CSET tdata_width=64
184 CSET tdest_width=4 184 CSET tdest_width=4
185 CSET tid_width=8 185 CSET tid_width=8
186 CSET tkeep_width=4 186 CSET tkeep_width=4
187 CSET tstrb_width=4 187 CSET tstrb_width=4
188 CSET tuser_width=4 188 CSET tuser_width=4
189 CSET underflow_flag=false 189 CSET underflow_flag=false
190 CSET underflow_flag_axi=false 190 CSET underflow_flag_axi=false
191 CSET underflow_sense=Active_High 191 CSET underflow_sense=Active_High
192 CSET underflow_sense_axi=Active_High 192 CSET underflow_sense_axi=Active_High
193 CSET use_clock_enable=false 193 CSET use_clock_enable=false
194 CSET use_dout_reset=true 194 CSET use_dout_reset=true
195 CSET use_embedded_registers=false 195 CSET use_embedded_registers=false
196 CSET use_extra_logic=false 196 CSET use_extra_logic=false
197 CSET valid_flag=true 197 CSET valid_flag=true
198 CSET valid_sense=Active_High 198 CSET valid_sense=Active_High
199 CSET wach_type=FIFO 199 CSET wach_type=FIFO
200 CSET wdch_type=FIFO 200 CSET wdch_type=FIFO
201 CSET wrch_type=FIFO 201 CSET wrch_type=FIFO
202 CSET write_acknowledge_flag=false 202 CSET write_acknowledge_flag=false
203 CSET write_acknowledge_sense=Active_High 203 CSET write_acknowledge_sense=Active_High
204 CSET write_clock_frequency=1 204 CSET write_clock_frequency=1
205 CSET write_data_count=false 205 CSET write_data_count=false
206 CSET write_data_count_width=9 206 CSET write_data_count_width=9
207 CSET wuser_width=1 207 CSET wuser_width=1
208 # END Parameters 208 # END Parameters
209 # BEGIN Extra information 209 # BEGIN Extra information
210 MISC pkg_timestamp=2012-06-23T13:35:37Z 210 MISC pkg_timestamp=2012-06-23T13:35:37Z
211 # END Extra information 211 # END Extra information
212 GENERATE 212 GENERATE
213 # CRC: e2c6d431 213 # CRC: e2c6d431