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library ieee; |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.std_logic_1164.all; |
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|
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library UNISIM; |
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library UNISIM; |
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use UNISIM.vcomponents.all; |
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use UNISIM.vcomponents.all; |
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|
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library utilities; |
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library utilities; |
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|
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entity processing_block is |
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entity processing_block is |
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port ( |
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port ( |
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|
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|
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-- clock: |
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-- clock: |
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clk_iserdes_in : in std_logic; |
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clk_iserdes_in : in std_logic; |
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clk_iserdes_in_div : in std_logic; |
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clk_iserdes_in_div : in std_logic; |
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clk_global : in std_logic; |
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clk_global : in std_logic; |
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|
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|
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-- reset: |
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-- reset: |
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rst : in std_logic; |
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rst : in std_logic; |
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|
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|
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-- bitslip: |
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-- bitslip: |
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bitslip : in std_logic; |
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bitslip : in std_logic; |
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bitslip_done : in std_logic; -- todo: use this |
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bitslip_done : in std_logic; -- todo: use this |
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bitslip_drop_byte : in std_logic; |
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bitslip_drop_byte : in std_logic; |
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|
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|
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-- input signal: |
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-- input signal: |
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in_data_p : in std_logic; |
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in_data_p : in std_logic; |
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in_data_n : in std_logic; |
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in_data_n : in std_logic; |
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in_data_swap_pn : in std_logic; |
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in_data_swap_pn : in std_logic; |
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|
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|
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-- input switch for counter output: |
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-- input switch for counter output: |
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in_output_counting : in std_logic; |
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in_output_counting : in std_logic; |
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|
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|
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-- output after iserdes and pack16 for bitslip: |
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-- output after iserdes and pack16 for bitslip: |
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o_iserdes_output : out std_logic_vector( 15 downto 0 ); |
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o_iserdes_output : out std_logic_vector( 15 downto 0 ); |
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o_iserdes_output_valid : out std_logic; |
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o_iserdes_output_valid : out std_logic; |
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|
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|
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-- output fwft FIFO: |
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-- output fwft FIFO: |
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o_data : out std_logic_vector( 31 downto 0 ); |
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o_data : out std_logic_vector( 31 downto 0 ); |
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o_valid : out std_logic; |
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o_valid : out std_logic; |
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i_rden : in std_logic |
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i_rden : in std_logic |
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); |
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); |
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|
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|
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end processing_block; |
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end processing_block; |
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|
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|
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architecture behavioral of processing_block is |
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architecture behavioral of processing_block is |
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|
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|
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component swap_endianness |
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component swap_endianness |
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port ( |
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port ( |
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i_data : in std_logic_vector; |
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i_data : in std_logic_vector; |
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o_data : out std_logic_vector |
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o_data : out std_logic_vector |
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); |
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); |
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end component; |
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end component; |
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|
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|
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component fifo_32x512_dualclk_fwft |
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component fifo_32x512_dualclk_fwft |
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port ( |
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port ( |
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rst : in std_logic; |
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rst : in std_logic; |
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wr_clk : in std_logic; |
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wr_clk : in std_logic; |
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rd_clk : in std_logic; |
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rd_clk : in std_logic; |
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din : in std_logic_vector(31 downto 0); |
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din : in std_logic_vector(31 downto 0); |
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wr_en : in std_logic; |
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wr_en : in std_logic; |
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rd_en : in std_logic; |
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rd_en : in std_logic; |
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dout : out std_logic_vector(31 downto 0); |
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dout : out std_logic_vector(31 downto 0); |
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full : out std_logic; |
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full : out std_logic; |
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empty : out std_logic; |
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empty : out std_logic; |
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valid : out std_logic |
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valid : out std_logic |
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); |
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); |
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end component; |
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end component; |
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|
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|
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component myserdes_ddr_wrapper |
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component myserdes_ddr_wrapper |
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generic |
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generic |
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( sys_w : integer := 1; |
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( sys_w : integer := 1; |
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dev_w : integer := 8); |
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dev_w : integer := 8); |
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port ( |
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port ( |
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-- CLOCK: |
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-- CLOCK: |
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clk_in : in std_logic; |
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clk_in : in std_logic; |
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clk_in_div : in std_logic; |
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clk_in_div : in std_logic; |
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-- PADS IN: |
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-- PADS IN: |
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data_in_from_pins_p : in std_logic; |
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data_in_from_pins_p : in std_logic; |
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data_in_from_pins_n : in std_logic; |
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data_in_from_pins_n : in std_logic; |
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-- DATA OUT: |
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-- DATA OUT: |
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data_in_to_device : out std_logic_vector( dev_w - 1 downto 0 ); |
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data_in_to_device : out std_logic_vector( dev_w - 1 downto 0 ); |
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|
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|
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bitslip : in std_logic; |
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bitslip : in std_logic; |
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rst_in : in std_logic ); |
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rst_in : in std_logic ); |
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end component; |
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end component; |
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|
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|
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component saw_generator_wrapper |
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component saw_generator_wrapper |
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generic ( |
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generic ( |
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G_INCREASE_EVERY_NTH : positive := 4 |
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G_INCREASE_EVERY_NTH : positive := 4 |
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); |
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); |
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port ( |
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port ( |
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|
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|
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i_clk : in std_logic; |
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i_clk : in std_logic; |
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i_rst : in std_logic; |
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i_rst : in std_logic; |
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|
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|
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o_valid : out std_logic; |
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o_valid : out std_logic; |
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o_data : out std_logic_vector |
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o_data : out std_logic_vector |
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|
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|
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); |
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); |
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end component; |
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end component; |
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|
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|
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-- Frame signal |
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-- Frame signal |
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signal s_in_frame_for_data : std_logic_vector( 7 downto 0 ); |
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signal s_in_frame_for_data : std_logic_vector( 7 downto 0 ); |
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signal s_in_frame_for_data_precorrect : std_logic_vector( 7 downto 0 ); |
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signal s_in_frame_for_data_precorrect : std_logic_vector( 7 downto 0 ); |
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|
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|
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signal s_in_frame_for_data_packed16 : std_logic_vector( 15 downto 0 ); |
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signal s_in_frame_for_data_packed16 : std_logic_vector( 15 downto 0 ); |
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signal s_in_frame_for_data_packed16_le : std_logic_vector( 15 downto 0 ); |
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signal s_in_frame_for_data_packed16_le : std_logic_vector( 15 downto 0 ); |
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signal s_in_frame_for_data_packed16_swapped : std_logic_vector( 15 downto 0 ); |
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signal s_in_frame_for_data_packed16_swapped : std_logic_vector( 15 downto 0 ); |
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signal s_in_frame_for_data_packed16_valid : std_logic; |
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signal s_in_frame_for_data_packed16_valid : std_logic; |
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signal s_in_frame_for_data_packed16_valid_wbitslip_done : std_logic; |
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signal s_in_frame_for_data_packed16_valid_wbitslip_done : std_logic; |
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signal s_in_frame_for_data_packed32 : std_logic_vector( 31 downto 0 ); |
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signal s_in_frame_for_data_packed32 : std_logic_vector( 31 downto 0 ); |
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signal s_in_frame_for_data_packed32_valid : std_logic; |
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signal s_in_frame_for_data_packed32_valid : std_logic; |
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|
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|
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signal s_rst_n : std_logic; |
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signal s_rst_n : std_logic; |
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|
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-- counter: |
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-- counter: |
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signal s_counter_valid : std_logic; |
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signal s_counter_valid : std_logic; |
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signal s_counter_data : std_logic_vector( 31 downto 0 ); |
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signal s_counter_data : std_logic_vector( 31 downto 0 ); |
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|
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|
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-- selection signals for the final FIFO: |
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-- selection signals for the final FIFO: |
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signal s_selected_source_valid : std_logic; |
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signal s_selected_source_valid : std_logic; |
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signal s_selected_source_data : std_logic_vector( 31 downto 0 ); |
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signal s_selected_source_data : std_logic_vector( 31 downto 0 ); |
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|
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|
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-- byte drop request |
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-- byte drop request |
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signal s_bitslip_drop_byte_n : std_logic; |
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signal s_bitslip_drop_byte_n : std_logic; |
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|
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|
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begin |
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begin |
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s_rst_n <= not rst; |
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s_rst_n <= not rst; |
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s_bitslip_drop_byte_n <= not bitslip_drop_byte; |
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s_bitslip_drop_byte_n <= not bitslip_drop_byte; |
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|
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-- iserdes wrapper: |
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-- iserdes wrapper: |
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myserdes_ddr_wrapper_inst : myserdes_ddr_wrapper |
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myserdes_ddr_wrapper_inst : myserdes_ddr_wrapper |
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port map ( |
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port map ( |
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clk_in => clk_iserdes_in, clk_in_div => clk_iserdes_in_div, |
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clk_in => clk_iserdes_in, clk_in_div => clk_iserdes_in_div, |
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data_in_from_pins_p => in_data_p, data_in_from_pins_n => in_data_n, data_in_to_device => s_in_frame_for_data_precorrect, |
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data_in_from_pins_p => in_data_p, data_in_from_pins_n => in_data_n, data_in_to_device => s_in_frame_for_data_precorrect, |
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bitslip => bitslip, rst_in => rst ); |
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bitslip => bitslip, rst_in => rst ); |
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|
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|
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-- correct hardware swapping of P&N wires: |
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-- correct hardware swapping of P&N wires: |
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s_in_frame_for_data <= s_in_frame_for_data_precorrect when in_data_swap_pn = '0' else |
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s_in_frame_for_data <= s_in_frame_for_data_precorrect when in_data_swap_pn = '0' else |
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not s_in_frame_for_data_precorrect; |
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not s_in_frame_for_data_precorrect; |
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|
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|
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-- glue two parts to 16-bit full data: |
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-- glue two parts to 16-bit full data: |
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glue_data_inst : entity work.glue_data |
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glue_data_inst : entity work.glue_data |
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port map ( |
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port map ( |
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i_clk => clk_iserdes_in_div, i_reset_n => s_rst_n, |
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i_clk => clk_iserdes_in_div, i_reset_n => s_rst_n, |
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i_data => s_in_frame_for_data, i_valid => s_bitslip_drop_byte_n, o_enable => open, |
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i_data => s_in_frame_for_data, i_valid => s_bitslip_drop_byte_n, o_enable => open, |
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o_data => s_in_frame_for_data_packed16, o_valid => s_in_frame_for_data_packed16_valid, i_enable => '1' ); |
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o_data => s_in_frame_for_data_packed16, o_valid => s_in_frame_for_data_packed16_valid, i_enable => '1' ); |
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|
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|
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-- output the 16-bit to manage bitslip: |
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-- output the 16-bit to manage bitslip: |
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o_iserdes_output <= s_in_frame_for_data_packed16; |
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o_iserdes_output <= s_in_frame_for_data_packed16; |
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o_iserdes_output_valid <= s_in_frame_for_data_packed16_valid; |
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o_iserdes_output_valid <= s_in_frame_for_data_packed16_valid; |
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|
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|
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-- these data go further after bitslip has been set: |
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-- these data go further after bitslip has been set: |
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s_in_frame_for_data_packed16_le <= s_in_frame_for_data_packed16; |
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s_in_frame_for_data_packed16_le <= s_in_frame_for_data_packed16; |
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s_in_frame_for_data_packed16_valid_wbitslip_done <= bitslip_done and s_in_frame_for_data_packed16_valid; |
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s_in_frame_for_data_packed16_valid_wbitslip_done <= bitslip_done and s_in_frame_for_data_packed16_valid; |
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|
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|
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-- insert the pack block to 32 bits: |
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-- insert the pack block to 32 bits: |
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pack_data32_inst : entity utilities.pack_data |
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pack_data32_inst : entity utilities.pack_data |
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generic map ( |
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generic map ( |
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G_OUTPUT_WIDTH => 32 ) |
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G_OUTPUT_WIDTH => 32 ) |
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port map ( |
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port map ( |
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i_clk => clk_iserdes_in_div, i_reset_n => s_rst_n, |
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i_clk => clk_iserdes_in_div, i_reset_n => s_rst_n, |
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i_data => s_in_frame_for_data_packed16_le, i_valid => s_in_frame_for_data_packed16_valid_wbitslip_done, o_enable => open, |
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i_data => s_in_frame_for_data_packed16_le, i_valid => s_in_frame_for_data_packed16_valid_wbitslip_done, o_enable => open, |
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o_data => s_in_frame_for_data_packed32, o_valid => s_in_frame_for_data_packed32_valid, i_enable => '1' ); |
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o_data => s_in_frame_for_data_packed32, o_valid => s_in_frame_for_data_packed32_valid, i_enable => '1' ); |
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|
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|
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-- counter: |
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-- counter: |
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counter_inst : saw_generator_wrapper |
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counter_inst : saw_generator_wrapper |
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generic map( G_INCREASE_EVERY_NTH => 4 ) |
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generic map( G_INCREASE_EVERY_NTH => 4 ) |
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port map( |
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port map( |
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i_clk => clk_iserdes_in_div, i_rst => rst, o_valid => s_counter_valid, o_data => s_counter_data ); |
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i_clk => clk_iserdes_in_div, i_rst => rst, o_valid => s_counter_valid, o_data => s_counter_data ); |
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|
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|
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-- output either the grabbed data or the counter, based on request: |
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-- output either the grabbed data or the counter, based on request: |
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s_selected_source_valid <= s_counter_valid when in_output_counting = '1' else s_in_frame_for_data_packed32_valid; |
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s_selected_source_valid <= s_counter_valid when in_output_counting = '1' else s_in_frame_for_data_packed32_valid; |
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s_selected_source_data <= s_counter_data when in_output_counting = '1' else s_in_frame_for_data_packed32; |
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s_selected_source_data <= s_counter_data when in_output_counting = '1' else s_in_frame_for_data_packed32; |
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|
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|
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-- insert the cross-domain FIFO: |
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-- insert the cross-domain FIFO: |
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cross_domain_fifo_inst : fifo_32x512_dualclk_fwft |
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cross_domain_fifo_inst : fifo_32x512_dualclk_fwft |
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port map ( |
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port map ( |
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rst => rst, wr_clk => clk_iserdes_in_div, rd_clk => clk_global, |
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rst => rst, wr_clk => clk_iserdes_in_div, rd_clk => clk_global, |
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din => s_selected_source_data, wr_en => s_selected_source_valid, full => open, |
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din => s_selected_source_data, wr_en => s_selected_source_valid, full => open, |
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dout => o_data, valid => o_valid, rd_en => i_rden, empty => open ); |
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dout => o_data, valid => o_valid, rd_en => i_rden, empty => open ); |
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|
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|
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end architecture; |
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end architecture; |
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