| 1 |
library ieee; |
1 |
library ieee; |
| 2 |
use ieee.std_logic_1164.all; |
2 |
use ieee.std_logic_1164.all; |
| 3 |
|
3 |
|
| 4 |
entity swap_endianness is |
4 |
entity swap_endianness is |
| 5 |
port ( |
5 |
port ( |
| 6 |
i_data : in std_logic_vector; |
6 |
i_data : in std_logic_vector; |
| 7 |
o_data : out std_logic_vector |
7 |
o_data : out std_logic_vector |
| 8 |
); |
8 |
); |
| 9 |
|
9 |
|
| 10 |
end swap_endianness; |
10 |
end swap_endianness; |
| 11 |
|
11 |
|
| 12 |
architecture behavioral of swap_endianness is |
12 |
architecture behavioral of swap_endianness is |
| 13 |
|
13 |
|
| 14 |
begin |
14 |
begin |
| 15 |
|
15 |
|
| 16 |
assert ( i_data'length = o_data'length ) report "The input and output data lengths have to match." severity failure; |
16 |
assert ( i_data'length = o_data'length ) report "The input and output data lengths have to match." severity failure; |
| 17 |
assert ( i_data'length mod 8 = 0 ) report "The data length has to be divisible by 8. (Whole bytes)." severity failure; |
17 |
assert ( i_data'length mod 8 = 0 ) report "The data length has to be divisible by 8. (Whole bytes)." severity failure; |
| 18 |
|
18 |
|
| 19 |
swap_gen : for i in 0 to ((i_data'length / 8) - 1) generate |
19 |
swap_gen : for i in 0 to ((i_data'length / 8) - 1) generate |
| 20 |
o_data( 8*(i+1) - 1 downto 8*i ) <= i_data( i_data'length - 8*i - 1 downto i_data'length - 8*(i+1) ); |
20 |
o_data( 8*(i+1) - 1 downto 8*i ) <= i_data( i_data'length - 8*i - 1 downto i_data'length - 8*(i+1) ); |
| 21 |
end generate; |
21 |
end generate; |
| 22 |
|
22 |
|
| 23 |
end architecture; |
23 |
end architecture; |
| 24 |
|
24 |
|