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library ieee; |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.std_logic_1164.all; |
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|
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|
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library UNISIM; |
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library UNISIM; |
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use UNISIM.vcomponents.all; |
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use UNISIM.vcomponents.all; |
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|
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|
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library sychro1; |
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library sychro1; |
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library utilities; |
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library utilities; |
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library comm; |
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library comm; |
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|
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|
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library kakona; |
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library kakona; |
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use kakona.kakona_package.all; |
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use kakona.kakona_package.all; |
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|
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|
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entity xilly_toplevel is |
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entity xilly_toplevel is |
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|
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|
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port ( |
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port ( |
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-- FMC & other ports: |
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-- FMC & other ports: |
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|
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|
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-- local oscillator to be divided |
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-- local oscillator to be divided |
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IN_CLK_LO_N : IN std_logic; |
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IN_CLK_LO_N : IN std_logic; |
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IN_CLK_LO_P : IN std_logic; |
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IN_CLK_LO_P : IN std_logic; |
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-- divided clock |
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-- divided clock |
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OUT_CLK_LO_DIVIDED_N : OUT std_logic; |
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OUT_CLK_LO_DIVIDED_N : OUT std_logic; |
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OUT_CLK_LO_DIVIDED_P : OUT std_logic; |
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OUT_CLK_LO_DIVIDED_P : OUT std_logic; |
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|
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|
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-- input data: |
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-- input data: |
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-- clock: |
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-- clock: |
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IN_CLK_FOR_DATA_P : IN std_logic; |
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IN_CLK_FOR_DATA_P : IN std_logic; |
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IN_CLK_FOR_DATA_N : IN std_logic; |
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IN_CLK_FOR_DATA_N : IN std_logic; |
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-- frame signal: |
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-- frame signal: |
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IN_FRAME_FOR_DATA_N : IN std_logic; |
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IN_FRAME_FOR_DATA_N : IN std_logic; |
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IN_FRAME_FOR_DATA_P : IN std_logic; |
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IN_FRAME_FOR_DATA_P : IN std_logic; |
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|
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|
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-- data from ADCs: |
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-- data from ADCs: |
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IN_DATA_ADC_P : IN std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS - 1 downto 0 ); |
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IN_DATA_ADC_P : IN std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS - 1 downto 0 ); |
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IN_DATA_ADC_N : IN std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS - 1 downto 0 ); |
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IN_DATA_ADC_N : IN std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS - 1 downto 0 ); |
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|
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|
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-- our LEDs: |
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-- our LEDs: |
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GPIO_LED2 : OUT std_logic_vector(3 DOWNTO 0); |
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GPIO_LED2 : OUT std_logic_vector(3 DOWNTO 0); |
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|
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|
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-- SPI communication block: |
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-- SPI communication block: |
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OUT_SPI_N_CE : OUT std_logic_vector( C_NUM_INPUT_ADC_MODULES-1 downto 0 ); |
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OUT_SPI_N_CE : OUT std_logic_vector( C_NUM_INPUT_ADC_MODULES-1 downto 0 ); |
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OUT_SPI_DOUT : OUT std_logic; |
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OUT_SPI_DOUT : OUT std_logic; |
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OUT_SPI_CLK : OUT std_logic; |
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OUT_SPI_CLK : OUT std_logic; |
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|
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|
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-- test: |
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-- test: |
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--OUT_TEST1 : OUT std_logic; |
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--OUT_TEST1 : OUT std_logic; |
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|
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|
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-- dummy inputs due to incorrect soldering -- pins are hardconnected to ground. |
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-- dummy inputs due to incorrect soldering -- pins are hardconnected to ground. |
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IN_DUMMY : IN std_logic_vector( 1 downto 0 ); |
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IN_DUMMY : IN std_logic_vector( 1 downto 0 ); |
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|
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|
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-- GPIO_DIP_SWITCH: |
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-- GPIO_DIP_SWITCH: |
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GPIO_DIP_SW : IN std_logic_vector( 7 downto 0 ); |
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GPIO_DIP_SW : IN std_logic_vector( 7 downto 0 ); |
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|
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|
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-- original xillybus-only ports: |
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-- original xillybus-only ports: |
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PCIE_PERST_B_LS : IN std_logic; |
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PCIE_PERST_B_LS : IN std_logic; |
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PCIE_REFCLK_N : IN std_logic; |
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PCIE_REFCLK_N : IN std_logic; |
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PCIE_REFCLK_P : IN std_logic; |
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PCIE_REFCLK_P : IN std_logic; |
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PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0); |
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PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0); |
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PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0); |
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PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0); |
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GPIO_LED : OUT std_logic_vector(3 DOWNTO 0); |
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GPIO_LED : OUT std_logic_vector(3 DOWNTO 0); |
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PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0); |
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PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0); |
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PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0)); |
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PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0)); |
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end xilly_toplevel; |
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end xilly_toplevel; |
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|
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|
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architecture behavioral of xilly_toplevel is |
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architecture behavioral of xilly_toplevel is |
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|
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|
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component multiplexer_from_fifos |
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component multiplexer_from_fifos |
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generic |
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generic |
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( G_NUM_CHANNELS : natural := 2; -- number of channels |
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( G_NUM_CHANNELS : natural := 2; -- number of channels |
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G_DATA_WIDTH : natural := 32 -- data width of individual packets |
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G_DATA_WIDTH : natural := 32 -- data width of individual packets |
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); |
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); |
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port ( |
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port ( |
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|
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|
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clk : in std_logic; |
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clk : in std_logic; |
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rst : in std_logic; |
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rst : in std_logic; |
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|
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|
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-- input side |
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-- input side |
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i_data : in std_logic_vector( G_DATA_WIDTH*G_NUM_CHANNELS - 1 downto 0 ); |
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i_data : in std_logic_vector( G_DATA_WIDTH*G_NUM_CHANNELS - 1 downto 0 ); |
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i_valid : in std_logic_vector( G_NUM_CHANNELS - 1 downto 0 ); |
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i_valid : in std_logic_vector( G_NUM_CHANNELS - 1 downto 0 ); |
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o_rden : out std_logic_vector( G_NUM_CHANNELS - 1 downto 0 ); |
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o_rden : out std_logic_vector( G_NUM_CHANNELS - 1 downto 0 ); |
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|
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|
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-- output side |
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-- output side |
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o_data : out std_logic_vector( G_DATA_WIDTH - 1 downto 0 ); |
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o_data : out std_logic_vector( G_DATA_WIDTH - 1 downto 0 ); |
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o_valid : out std_logic; |
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o_valid : out std_logic; |
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i_full : in std_logic |
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i_full : in std_logic |
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|
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|
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); |
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); |
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end component; |
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end component; |
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|
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|
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COMPONENT fifo_32x512_walmostfull |
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COMPONENT fifo_32x512_walmostfull |
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PORT ( |
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PORT ( |
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clk : IN STD_LOGIC; |
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clk : IN STD_LOGIC; |
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srst : IN STD_LOGIC; |
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srst : IN STD_LOGIC; |
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din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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wr_en : IN STD_LOGIC; |
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wr_en : IN STD_LOGIC; |
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rd_en : IN STD_LOGIC; |
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rd_en : IN STD_LOGIC; |
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dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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full : OUT STD_LOGIC; |
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full : OUT STD_LOGIC; |
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empty : OUT STD_LOGIC; |
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empty : OUT STD_LOGIC; |
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valid : OUT STD_LOGIC; |
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valid : OUT STD_LOGIC; |
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prog_full : OUT STD_LOGIC |
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prog_full : OUT STD_LOGIC |
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); |
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); |
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END COMPONENT; |
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END COMPONENT; |
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|
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|
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component bitslip_compensation |
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component bitslip_compensation |
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port ( |
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port ( |
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|
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|
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clk : in std_logic; |
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clk : in std_logic; |
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rst : in std_logic; |
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rst : in std_logic; |
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|
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|
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i_data : in std_logic_vector( 15 downto 0 ); |
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i_data : in std_logic_vector( 15 downto 0 ); |
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i_valid : in std_logic; |
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i_valid : in std_logic; |
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|
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|
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o_bitslip : out std_logic; |
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o_bitslip : out std_logic; |
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o_bitslip_done : out std_logic; |
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o_bitslip_done : out std_logic; |
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o_bitslip_drop_byte : out std_logic; |
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o_bitslip_drop_byte : out std_logic; |
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o_bitslip_failed : out std_logic |
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o_bitslip_failed : out std_logic |
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|
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|
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); |
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); |
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end component; |
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end component; |
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|
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|
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component iserdes_clock_generator |
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component iserdes_clock_generator |
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port |
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port |
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( |
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( |
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-- Clock and reset signals |
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-- Clock and reset signals |
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CLK_IN_P : in std_logic; -- Differential fast clock from IOB |
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CLK_IN_P : in std_logic; -- Differential fast clock from IOB |
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CLK_IN_N : in std_logic; |
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CLK_IN_N : in std_logic; |
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CLK_OUT : out std_logic; -- Fast clock output (synchronous to data) |
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CLK_OUT : out std_logic; -- Fast clock output (synchronous to data) |
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CLK_DIV_OUT : out std_logic; -- Slow clock output |
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CLK_DIV_OUT : out std_logic; -- Slow clock output |
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|
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|
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CLK_RESET : in std_logic); -- Reset signal for Clock circuit |
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CLK_RESET : in std_logic); -- Reset signal for Clock circuit |
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|
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|
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end component; |
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end component; |
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|
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|
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|
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|
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component xillybus |
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component xillybus |
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port ( |
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port ( |
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PCIE_PERST_B_LS : IN std_logic; |
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PCIE_PERST_B_LS : IN std_logic; |
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PCIE_REFCLK_N : IN std_logic; |
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PCIE_REFCLK_N : IN std_logic; |
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PCIE_REFCLK_P : IN std_logic; |
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PCIE_REFCLK_P : IN std_logic; |
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PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0); |
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PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0); |
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PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0); |
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PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0); |
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GPIO_LED : OUT std_logic_vector(3 DOWNTO 0); |
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GPIO_LED : OUT std_logic_vector(3 DOWNTO 0); |
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PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0); |
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PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0); |
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PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0); |
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PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0); |
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bus_clk : OUT std_logic; |
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bus_clk : OUT std_logic; |
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quiesce : OUT std_logic; |
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quiesce : OUT std_logic; |
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user_r_control_r_rden : OUT std_logic; |
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user_r_control_r_rden : OUT std_logic; |
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user_r_control_r_empty : IN std_logic := '0'; |
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user_r_control_r_empty : IN std_logic := '0'; |
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user_r_control_r_data : IN std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
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user_r_control_r_data : IN std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
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user_r_control_r_eof : IN std_logic := '0'; |
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user_r_control_r_eof : IN std_logic := '0'; |
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user_r_control_r_open : OUT std_logic; |
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user_r_control_r_open : OUT std_logic; |
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user_w_control_w_wren : OUT std_logic; |
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user_w_control_w_wren : OUT std_logic; |
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user_w_control_w_full : IN std_logic := '0'; |
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user_w_control_w_full : IN std_logic := '0'; |
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user_w_control_w_data : OUT std_logic_vector(31 DOWNTO 0); |
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user_w_control_w_data : OUT std_logic_vector(31 DOWNTO 0); |
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user_w_control_w_open : OUT std_logic; |
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user_w_control_w_open : OUT std_logic; |
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user_r_data1_r_rden : OUT std_logic; |
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user_r_data1_r_rden : OUT std_logic; |
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user_r_data1_r_empty : IN std_logic; |
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user_r_data1_r_empty : IN std_logic; |
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user_r_data1_r_data : IN std_logic_vector(31 DOWNTO 0); |
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user_r_data1_r_data : IN std_logic_vector(31 DOWNTO 0); |
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user_r_data1_r_eof : IN std_logic; |
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user_r_data1_r_eof : IN std_logic; |
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user_r_data1_r_open : OUT std_logic; |
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user_r_data1_r_open : OUT std_logic; |
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user_w_data1_w_wren : OUT std_logic; |
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user_w_data1_w_wren : OUT std_logic; |
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user_w_data1_w_full : IN std_logic; |
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user_w_data1_w_full : IN std_logic; |
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user_w_data1_w_data : OUT std_logic_vector(31 DOWNTO 0); |
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user_w_data1_w_data : OUT std_logic_vector(31 DOWNTO 0); |
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user_w_data1_w_open : OUT std_logic; |
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user_w_data1_w_open : OUT std_logic; |
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user_r_data2_r_rden : OUT std_logic; |
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user_r_data2_r_rden : OUT std_logic; |
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user_r_data2_r_empty : IN std_logic := '0'; |
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user_r_data2_r_empty : IN std_logic := '0'; |
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user_r_data2_r_data : IN std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
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user_r_data2_r_data : IN std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
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user_r_data2_r_eof : IN std_logic := '0'; |
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user_r_data2_r_eof : IN std_logic := '0'; |
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user_r_data2_r_open : OUT std_logic; |
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user_r_data2_r_open : OUT std_logic; |
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user_w_data2_w_wren : OUT std_logic; |
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user_w_data2_w_wren : OUT std_logic; |
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user_w_data2_w_full : IN std_logic := '0'; |
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user_w_data2_w_full : IN std_logic := '0'; |
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user_w_data2_w_data : OUT std_logic_vector(31 DOWNTO 0); |
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user_w_data2_w_data : OUT std_logic_vector(31 DOWNTO 0); |
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user_w_data2_w_open : OUT std_logic); |
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user_w_data2_w_open : OUT std_logic); |
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end component; |
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end component; |
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|
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|
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component xilly_userlogiccmp_wrapper |
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component xilly_userlogiccmp_wrapper |
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port ( |
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port ( |
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i_clk : in std_logic; |
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i_clk : in std_logic; |
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i_rst : in std_logic; |
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i_rst : in std_logic; |
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|
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|
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user_r_control_r_rden : in std_logic := '0'; |
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user_r_control_r_rden : in std_logic := '0'; |
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user_r_control_r_empty : out std_logic := '1'; |
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user_r_control_r_empty : out std_logic := '1'; |
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user_r_control_r_data : out std_logic_vector(31 DOWNTO 0); |
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user_r_control_r_data : out std_logic_vector(31 DOWNTO 0); |
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|
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|
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user_w_control_w_wren : in std_logic := '0'; |
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user_w_control_w_wren : in std_logic := '0'; |
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user_w_control_w_full : out std_logic := '0'; |
188 |
user_w_control_w_full : out std_logic := '0'; |
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user_w_control_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
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user_w_control_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
190 |
|
190 |
|
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user_r_data1_r_rden : in std_logic := '0'; |
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user_r_data1_r_rden : in std_logic := '0'; |
192 |
user_r_data1_r_empty : out std_logic := '1'; |
192 |
user_r_data1_r_empty : out std_logic := '1'; |
193 |
user_r_data1_r_data : out std_logic_vector(31 DOWNTO 0); |
193 |
user_r_data1_r_data : out std_logic_vector(31 DOWNTO 0); |
194 |
|
194 |
|
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user_w_data1_w_wren : in std_logic := '0'; |
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user_w_data1_w_wren : in std_logic := '0'; |
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user_w_data1_w_full : out std_logic := '0'; |
196 |
user_w_data1_w_full : out std_logic := '0'; |
197 |
user_w_data1_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
197 |
user_w_data1_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' ); |
198 |
|
198 |
|
199 |
user_r_data2_r_rden : in std_logic := '0'; |
199 |
user_r_data2_r_rden : in std_logic := '0'; |
200 |
user_r_data2_r_empty : out std_logic := '1'; |
200 |
user_r_data2_r_empty : out std_logic := '1'; |
201 |
user_r_data2_r_data : out std_logic_vector(31 DOWNTO 0); |
201 |
user_r_data2_r_data : out std_logic_vector(31 DOWNTO 0); |
202 |
|
202 |
|
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user_w_data2_w_wren : in std_logic := '0'; |
203 |
user_w_data2_w_wren : in std_logic := '0'; |
204 |
user_w_data2_w_full : out std_logic := '0'; |
204 |
user_w_data2_w_full : out std_logic := '0'; |
205 |
user_w_data2_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' ) |
205 |
user_w_data2_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' ) |
206 |
); |
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); |
207 |
end component; |
207 |
end component; |
208 |
|
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|
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signal bus_clk : std_logic; |
209 |
signal bus_clk : std_logic; |
210 |
signal quiesce : std_logic; |
210 |
signal quiesce : std_logic; |
211 |
|
211 |
|
212 |
signal user_r_control_r_rden : std_logic; |
212 |
signal user_r_control_r_rden : std_logic; |
213 |
signal user_r_control_r_empty : std_logic; |
213 |
signal user_r_control_r_empty : std_logic; |
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signal user_r_control_r_data : std_logic_vector(31 DOWNTO 0); |
214 |
signal user_r_control_r_data : std_logic_vector(31 DOWNTO 0); |
215 |
--signal user_r_control_r_eof : std_logic; |
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--signal user_r_control_r_eof : std_logic; |
216 |
signal user_r_control_r_open : std_logic; |
216 |
signal user_r_control_r_open : std_logic; |
217 |
signal user_w_control_w_wren : std_logic; |
217 |
signal user_w_control_w_wren : std_logic; |
218 |
signal user_w_control_w_full : std_logic; |
218 |
signal user_w_control_w_full : std_logic; |
219 |
signal user_w_control_w_data : std_logic_vector(31 DOWNTO 0); |
219 |
signal user_w_control_w_data : std_logic_vector(31 DOWNTO 0); |
220 |
signal user_w_control_w_open : std_logic; |
220 |
signal user_w_control_w_open : std_logic; |
221 |
|
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|
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signal user_r_data1_r_rden : std_logic; |
222 |
signal user_r_data1_r_rden : std_logic; |
223 |
signal user_r_data1_r_empty : std_logic; |
223 |
signal user_r_data1_r_empty : std_logic; |
224 |
signal user_r_data1_r_data : std_logic_vector(31 DOWNTO 0); |
224 |
signal user_r_data1_r_data : std_logic_vector(31 DOWNTO 0); |
225 |
--signal user_r_data1_r_eof : std_logic; |
225 |
--signal user_r_data1_r_eof : std_logic; |
226 |
signal user_r_data1_r_open : std_logic; |
226 |
signal user_r_data1_r_open : std_logic; |
227 |
signal user_w_data1_w_wren : std_logic; |
227 |
signal user_w_data1_w_wren : std_logic; |
228 |
signal user_w_data1_w_full : std_logic; |
228 |
signal user_w_data1_w_full : std_logic; |
229 |
signal user_w_data1_w_data : std_logic_vector(31 DOWNTO 0); |
229 |
signal user_w_data1_w_data : std_logic_vector(31 DOWNTO 0); |
230 |
signal user_w_data1_w_open : std_logic; |
230 |
signal user_w_data1_w_open : std_logic; |
231 |
|
231 |
|
232 |
signal user_r_data2_r_rden : std_logic; |
232 |
signal user_r_data2_r_rden : std_logic; |
233 |
signal user_r_data2_r_empty : std_logic; |
233 |
signal user_r_data2_r_empty : std_logic; |
234 |
signal user_r_data2_r_data : std_logic_vector(31 DOWNTO 0); |
234 |
signal user_r_data2_r_data : std_logic_vector(31 DOWNTO 0); |
235 |
--signal user_r_data2_r_eof : std_logic; |
235 |
--signal user_r_data2_r_eof : std_logic; |
236 |
signal user_r_data2_r_open : std_logic; |
236 |
signal user_r_data2_r_open : std_logic; |
237 |
signal user_w_data2_w_wren : std_logic; |
237 |
signal user_w_data2_w_wren : std_logic; |
238 |
signal user_w_data2_w_full : std_logic; |
238 |
signal user_w_data2_w_full : std_logic; |
239 |
signal user_w_data2_w_data : std_logic_vector(31 DOWNTO 0); |
239 |
signal user_w_data2_w_data : std_logic_vector(31 DOWNTO 0); |
240 |
signal user_w_data2_w_open : std_logic; |
240 |
signal user_w_data2_w_open : std_logic; |
241 |
|
241 |
|
242 |
-- reset signal from xillybus. '1' when no device is open |
242 |
-- reset signal from xillybus. '1' when no device is open |
243 |
signal s_reset : std_logic; |
243 |
signal s_reset : std_logic; |
244 |
|
244 |
|
245 |
|
245 |
|
246 |
-- generated clock from ADC by iserdes_clock_generator: |
246 |
-- generated clock from ADC by iserdes_clock_generator: |
247 |
signal s_iserdes_clk : std_logic; |
247 |
signal s_iserdes_clk : std_logic; |
248 |
signal s_iserdes_clk_div : std_logic; |
248 |
signal s_iserdes_clk_div : std_logic; |
249 |
|
249 |
|
250 |
-- Frame signal |
250 |
-- Frame signal |
251 |
signal s_data16_to_bitslip : std_logic_vector( 15 downto 0 ); |
251 |
signal s_data16_to_bitslip : std_logic_vector( 15 downto 0 ); |
252 |
signal s_data16_to_bitslip_valid : std_logic; |
252 |
signal s_data16_to_bitslip_valid : std_logic; |
253 |
signal s_bitslip : std_logic; |
253 |
signal s_bitslip : std_logic; |
254 |
signal s_bitslip_done : std_logic; |
254 |
signal s_bitslip_done : std_logic; |
255 |
signal s_bitslip_drop_byte : std_logic; |
255 |
signal s_bitslip_drop_byte : std_logic; |
256 |
signal s_bitslip_failed : std_logic; |
256 |
signal s_bitslip_failed : std_logic; |
257 |
|
257 |
|
258 |
signal s_bitslip_regged : std_logic; |
258 |
signal s_bitslip_regged : std_logic; |
259 |
signal s_bitslip_drop_byte_regged : std_logic; |
259 |
signal s_bitslip_drop_byte_regged : std_logic; |
260 |
|
260 |
|
261 |
-- from all ADC processing blocks: |
261 |
-- from all ADC processing blocks: |
262 |
signal s_from_processing_blocks_data : std_logic_vector( (C_NUM_INPUT_ADC_DATA_PORTS+1)*32 - 1 downto 0 ); -- +1 is space for output from frame |
262 |
signal s_from_processing_blocks_data : std_logic_vector( (C_NUM_INPUT_ADC_DATA_PORTS+1)*32 - 1 downto 0 ); -- +1 is space for output from frame |
263 |
signal s_from_processing_blocks_valid : std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS+1 - 1 downto 0 ); |
263 |
signal s_from_processing_blocks_valid : std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS+1 - 1 downto 0 ); |
264 |
signal s_from_processing_blocks_rden : std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS+1 - 1 downto 0 ); |
264 |
signal s_from_processing_blocks_rden : std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS+1 - 1 downto 0 ); |
265 |
|
265 |
|
266 |
-- from multiplexer: |
266 |
-- from multiplexer: |
267 |
signal s_from_multiplexer_data : std_logic_vector( 31 downto 0 ); |
267 |
signal s_from_multiplexer_data : std_logic_vector( 31 downto 0 ); |
268 |
signal s_from_multiplexer_valid : std_logic; |
268 |
signal s_from_multiplexer_valid : std_logic; |
269 |
signal s_from_multiplexer_full : std_logic; |
269 |
signal s_from_multiplexer_full : std_logic; |
270 |
|
270 |
|
271 |
-- SPI communication module: |
271 |
-- SPI communication module: |
272 |
signal s_spi_done : std_logic; |
272 |
signal s_spi_done : std_logic; |
273 |
|
273 |
|
274 |
-- GPIO_DIP_SW register |
274 |
-- GPIO_DIP_SW register |
275 |
signal s_gpio_dip_sw : std_logic_vector( 7 downto 0 ); |
275 |
signal s_gpio_dip_sw : std_logic_vector( 7 downto 0 ); |
276 |
|
276 |
|
277 |
signal s_valid_for_bitslip_processing : std_logic; |
277 |
signal s_valid_for_bitslip_processing : std_logic; |
278 |
|
278 |
|
279 |
begin |
279 |
begin |
280 |
|
280 |
|
281 |
-- Xillybus instantiation: |
281 |
-- Xillybus instantiation: |
282 |
xillybus_ins : xillybus |
282 |
xillybus_ins : xillybus |
283 |
port map ( |
283 |
port map ( |
284 |
-- Ports related to /dev/xillybus_control_r |
284 |
-- Ports related to /dev/xillybus_control_r |
285 |
-- FPGA to CPU signals: |
285 |
-- FPGA to CPU signals: |
286 |
user_r_control_r_rden => user_r_control_r_rden, |
286 |
user_r_control_r_rden => user_r_control_r_rden, |
287 |
user_r_control_r_empty => user_r_control_r_empty, |
287 |
user_r_control_r_empty => user_r_control_r_empty, |
288 |
user_r_control_r_data => user_r_control_r_data, |
288 |
user_r_control_r_data => user_r_control_r_data, |
289 |
user_r_control_r_eof => '0', |
289 |
user_r_control_r_eof => '0', |
290 |
user_r_control_r_open => user_r_control_r_open, |
290 |
user_r_control_r_open => user_r_control_r_open, |
291 |
|
291 |
|
292 |
-- Ports related to /dev/xillybus_control_w |
292 |
-- Ports related to /dev/xillybus_control_w |
293 |
-- CPU to FPGA signals: |
293 |
-- CPU to FPGA signals: |
294 |
user_w_control_w_wren => user_w_control_w_wren, |
294 |
user_w_control_w_wren => user_w_control_w_wren, |
295 |
user_w_control_w_full => user_w_control_w_full, |
295 |
user_w_control_w_full => user_w_control_w_full, |
296 |
user_w_control_w_data => user_w_control_w_data, |
296 |
user_w_control_w_data => user_w_control_w_data, |
297 |
user_w_control_w_open => user_w_control_w_open, |
297 |
user_w_control_w_open => user_w_control_w_open, |
298 |
|
298 |
|
299 |
-- Ports related to /dev/xillybus_data1_r |
299 |
-- Ports related to /dev/xillybus_data1_r |
300 |
-- FPGA to CPU signals: |
300 |
-- FPGA to CPU signals: |
301 |
user_r_data1_r_rden => user_r_data1_r_rden, |
301 |
user_r_data1_r_rden => user_r_data1_r_rden, |
302 |
user_r_data1_r_empty => user_r_data1_r_empty, |
302 |
user_r_data1_r_empty => user_r_data1_r_empty, |
303 |
user_r_data1_r_data => user_r_data1_r_data, |
303 |
user_r_data1_r_data => user_r_data1_r_data, |
304 |
user_r_data1_r_eof => '0', |
304 |
user_r_data1_r_eof => '0', |
305 |
user_r_data1_r_open => user_r_data1_r_open, |
305 |
user_r_data1_r_open => user_r_data1_r_open, |
306 |
|
306 |
|
307 |
-- Ports related to /dev/xillybus_data1_w |
307 |
-- Ports related to /dev/xillybus_data1_w |
308 |
-- CPU to FPGA signals: |
308 |
-- CPU to FPGA signals: |
309 |
user_w_data1_w_wren => user_w_data1_w_wren, |
309 |
user_w_data1_w_wren => user_w_data1_w_wren, |
310 |
user_w_data1_w_full => user_w_data1_w_full, |
310 |
user_w_data1_w_full => user_w_data1_w_full, |
311 |
user_w_data1_w_data => user_w_data1_w_data, |
311 |
user_w_data1_w_data => user_w_data1_w_data, |
312 |
user_w_data1_w_open => user_w_data1_w_open, |
312 |
user_w_data1_w_open => user_w_data1_w_open, |
313 |
|
313 |
|
314 |
-- Ports related to /dev/xillybus_data2_r |
314 |
-- Ports related to /dev/xillybus_data2_r |
315 |
-- FPGA to CPU signals: |
315 |
-- FPGA to CPU signals: |
316 |
user_r_data2_r_rden => user_r_data2_r_rden, |
316 |
user_r_data2_r_rden => user_r_data2_r_rden, |
317 |
user_r_data2_r_empty => user_r_data2_r_empty, |
317 |
user_r_data2_r_empty => user_r_data2_r_empty, |
318 |
user_r_data2_r_data => user_r_data2_r_data, |
318 |
user_r_data2_r_data => user_r_data2_r_data, |
319 |
user_r_data2_r_eof => '0', |
319 |
user_r_data2_r_eof => '0', |
320 |
user_r_data2_r_open => user_r_data2_r_open, |
320 |
user_r_data2_r_open => user_r_data2_r_open, |
321 |
|
321 |
|
322 |
-- Ports related to /dev/xillybus_data2_w |
322 |
-- Ports related to /dev/xillybus_data2_w |
323 |
-- CPU to FPGA signals: |
323 |
-- CPU to FPGA signals: |
324 |
user_w_data2_w_wren => user_w_data2_w_wren, |
324 |
user_w_data2_w_wren => user_w_data2_w_wren, |
325 |
user_w_data2_w_full => user_w_data2_w_full, |
325 |
user_w_data2_w_full => user_w_data2_w_full, |
326 |
user_w_data2_w_data => user_w_data2_w_data, |
326 |
user_w_data2_w_data => user_w_data2_w_data, |
327 |
user_w_data2_w_open => user_w_data2_w_open, |
327 |
user_w_data2_w_open => user_w_data2_w_open, |
328 |
|
328 |
|
329 |
-- General signals |
329 |
-- General signals |
330 |
PCIE_PERST_B_LS => PCIE_PERST_B_LS, |
330 |
PCIE_PERST_B_LS => PCIE_PERST_B_LS, |
331 |
PCIE_REFCLK_N => PCIE_REFCLK_N, |
331 |
PCIE_REFCLK_N => PCIE_REFCLK_N, |
332 |
PCIE_REFCLK_P => PCIE_REFCLK_P, |
332 |
PCIE_REFCLK_P => PCIE_REFCLK_P, |
333 |
PCIE_RX_N => PCIE_RX_N, |
333 |
PCIE_RX_N => PCIE_RX_N, |
334 |
PCIE_RX_P => PCIE_RX_P, |
334 |
PCIE_RX_P => PCIE_RX_P, |
335 |
GPIO_LED => GPIO_LED, |
335 |
GPIO_LED => GPIO_LED, |
336 |
PCIE_TX_N => PCIE_TX_N, |
336 |
PCIE_TX_N => PCIE_TX_N, |
337 |
PCIE_TX_P => PCIE_TX_P, |
337 |
PCIE_TX_P => PCIE_TX_P, |
338 |
bus_clk => bus_clk, |
338 |
bus_clk => bus_clk, |
339 |
quiesce => quiesce |
339 |
quiesce => quiesce |
340 |
); |
340 |
); |
341 |
|
341 |
|
342 |
s_reset <= '0' when user_r_control_r_open = '1' or |
342 |
s_reset <= '0' when user_r_control_r_open = '1' or |
343 |
user_w_control_w_open = '1' or |
343 |
user_w_control_w_open = '1' or |
344 |
user_r_data1_r_open = '1' or |
344 |
user_r_data1_r_open = '1' or |
345 |
user_w_data1_w_open = '1' or |
345 |
user_w_data1_w_open = '1' or |
346 |
user_r_data2_r_open = '1' or |
346 |
user_r_data2_r_open = '1' or |
347 |
user_w_data2_w_open = '1' or |
347 |
user_w_data2_w_open = '1' or |
348 |
s_gpio_dip_sw(0) = '0' else |
348 |
s_gpio_dip_sw(0) = '0' else |
349 |
'1'; |
349 |
'1'; |
350 |
|
350 |
|
351 |
-- register the gpio_dip_sw(0) with the 125MHz clock: |
351 |
-- register the gpio_dip_sw(0) with the 125MHz clock: |
352 |
registers_for_gpio0 : process( bus_clk ) |
352 |
registers_for_gpio0 : process( bus_clk ) |
353 |
begin |
353 |
begin |
354 |
if( rising_edge( bus_clk ) ) then |
354 |
if( rising_edge( bus_clk ) ) then |
355 |
s_gpio_dip_sw(0) <= gpio_dip_sw(0); |
355 |
s_gpio_dip_sw(0) <= gpio_dip_sw(0); |
356 |
s_gpio_dip_sw(2) <= gpio_dip_sw(2); -- used for SPI confifuration block that is clocked with bus_clk |
356 |
s_gpio_dip_sw(2) <= gpio_dip_sw(2); -- used for SPI confifuration block that is clocked with bus_clk |
357 |
end if; |
357 |
end if; |
358 |
end process; |
358 |
end process; |
359 |
|
359 |
|
360 |
-- register the gpio_dip_sw(1) with the clk_div clock: |
360 |
-- register the gpio_dip_sw(1) with the clk_div clock: |
361 |
registers_for_gpio1 : process( s_iserdes_clk_div ) |
361 |
registers_for_gpio1 : process( s_iserdes_clk_div ) |
362 |
begin |
362 |
begin |
363 |
if( rising_edge( s_iserdes_clk_div ) ) then |
363 |
if( rising_edge( s_iserdes_clk_div ) ) then |
364 |
s_gpio_dip_sw(1) <= gpio_dip_sw(1); |
364 |
s_gpio_dip_sw(1) <= gpio_dip_sw(1); |
365 |
end if; |
365 |
end if; |
366 |
end process; |
366 |
end process; |
367 |
|
367 |
|
368 |
|
368 |
|
369 |
-- xilly_userlogiccmp_wrapper instantiation: |
369 |
-- xilly_userlogiccmp_wrapper instantiation: |
370 |
xilly_userlogiccmp_wrapper_inst : xilly_userlogiccmp_wrapper |
370 |
xilly_userlogiccmp_wrapper_inst : xilly_userlogiccmp_wrapper |
371 |
port map ( |
371 |
port map ( |
372 |
i_clk => bus_clk, |
372 |
i_clk => bus_clk, |
373 |
i_rst => s_reset, |
373 |
i_rst => s_reset, |
374 |
|
374 |
|
375 |
user_r_control_r_rden => user_r_control_r_rden, |
375 |
user_r_control_r_rden => user_r_control_r_rden, |
376 |
user_r_control_r_empty => user_r_control_r_empty, |
376 |
user_r_control_r_empty => user_r_control_r_empty, |
377 |
user_r_control_r_data => user_r_control_r_data, |
377 |
user_r_control_r_data => user_r_control_r_data, |
378 |
|
378 |
|
379 |
user_w_control_w_wren => user_w_control_w_wren, |
379 |
user_w_control_w_wren => user_w_control_w_wren, |
380 |
user_w_control_w_full => user_w_control_w_full, |
380 |
user_w_control_w_full => user_w_control_w_full, |
381 |
user_w_control_w_data => user_w_control_w_data, |
381 |
user_w_control_w_data => user_w_control_w_data, |
382 |
|
382 |
|
383 |
user_r_data1_r_rden => user_r_data1_r_rden, |
383 |
user_r_data1_r_rden => user_r_data1_r_rden, |
384 |
user_r_data1_r_empty => user_r_data1_r_empty, |
384 |
user_r_data1_r_empty => user_r_data1_r_empty, |
385 |
user_r_data1_r_data => user_r_data1_r_data, |
385 |
user_r_data1_r_data => user_r_data1_r_data, |
386 |
|
386 |
|
387 |
user_w_data1_w_wren => user_w_data1_w_wren, |
387 |
user_w_data1_w_wren => user_w_data1_w_wren, |
388 |
user_w_data1_w_full => user_w_data1_w_full, |
388 |
user_w_data1_w_full => user_w_data1_w_full, |
389 |
user_w_data1_w_data => user_w_data1_w_data, |
389 |
user_w_data1_w_data => user_w_data1_w_data, |
390 |
|
390 |
|
391 |
-- user_r_data2_r_rden => user_r_data2_r_rden, |
391 |
-- user_r_data2_r_rden => user_r_data2_r_rden, |
392 |
-- user_r_data2_r_empty => user_r_data2_r_empty, |
392 |
-- user_r_data2_r_empty => user_r_data2_r_empty, |
393 |
-- user_r_data2_r_data => user_r_data2_r_data, |
393 |
-- user_r_data2_r_data => user_r_data2_r_data, |
394 |
|
394 |
|
395 |
-- user_w_data2_w_wren => user_w_data2_w_wren, |
395 |
-- user_w_data2_w_wren => user_w_data2_w_wren, |
396 |
-- user_w_data2_w_full => user_w_data2_w_full, |
396 |
-- user_w_data2_w_full => user_w_data2_w_full, |
397 |
-- user_w_data2_w_data => user_w_data2_w_data |
397 |
-- user_w_data2_w_data => user_w_data2_w_data |
398 |
|
398 |
|
399 |
user_r_data2_r_rden => open, |
399 |
user_r_data2_r_rden => open, |
400 |
user_r_data2_r_empty => open, |
400 |
user_r_data2_r_empty => open, |
401 |
user_r_data2_r_data => open, |
401 |
user_r_data2_r_data => open, |
402 |
|
402 |
|
403 |
user_w_data2_w_wren => open, |
403 |
user_w_data2_w_wren => open, |
404 |
user_w_data2_w_full => open, |
404 |
user_w_data2_w_full => open, |
405 |
user_w_data2_w_data => open |
405 |
user_w_data2_w_data => open |
406 |
|
406 |
|
407 |
); |
407 |
); |
408 |
|
408 |
|
409 |
|
409 |
|
410 |
|
410 |
|
411 |
|
411 |
|
412 |
|
412 |
|
413 |
|
413 |
|
414 |
|
414 |
|
415 |
-- tie outputs: |
415 |
-- tie outputs: |
416 |
|
416 |
|
417 |
--OUT_TEST1 <= '0'; |
417 |
--OUT_TEST1 <= '0'; |
418 |
|
418 |
|
419 |
|
419 |
|
420 |
|
420 |
|
421 |
|
421 |
|
422 |
GPIO_LED2(0) <= s_bitslip_done; |
422 |
GPIO_LED2(0) <= s_bitslip_done; |
423 |
GPIO_LED2(1) <= s_bitslip_failed; |
423 |
GPIO_LED2(1) <= s_bitslip_failed; |
424 |
GPIO_LED2(2) <= s_bitslip_drop_byte_regged; |
424 |
GPIO_LED2(2) <= s_bitslip_drop_byte_regged; |
425 |
GPIO_LED2(3) <= s_bitslip_regged; |
425 |
GPIO_LED2(3) <= s_bitslip_regged; |
426 |
|
426 |
|
427 |
ddd : process( s_iserdes_clk_div ) |
427 |
ddd : process( s_iserdes_clk_div ) |
428 |
begin |
428 |
begin |
429 |
if( rising_edge( s_iserdes_clk_div ) ) then |
429 |
if( rising_edge( s_iserdes_clk_div ) ) then |
430 |
if( s_reset = '1' ) then |
430 |
if( s_reset = '1' ) then |
431 |
s_bitslip_regged <= '0'; |
431 |
s_bitslip_regged <= '0'; |
432 |
s_bitslip_drop_byte_regged <= '0'; |
432 |
s_bitslip_drop_byte_regged <= '0'; |
433 |
else |
433 |
else |
434 |
s_bitslip_regged <= s_bitslip_regged or s_bitslip; |
434 |
s_bitslip_regged <= s_bitslip_regged or s_bitslip; |
435 |
s_bitslip_drop_byte_regged <= s_bitslip_drop_byte_regged or s_bitslip_drop_byte; |
435 |
s_bitslip_drop_byte_regged <= s_bitslip_drop_byte_regged or s_bitslip_drop_byte; |
436 |
end if; |
436 |
end if; |
437 |
end if; |
437 |
end if; |
438 |
end process; |
438 |
end process; |
439 |
|
439 |
|
440 |
----------------------------------------------------------------------------------------------- |
440 |
----------------------------------------------------------------------------------------------- |
441 |
-- DATA PROCESSING: |
441 |
-- DATA PROCESSING: |
442 |
|
442 |
|
443 |
-- Clock generator: |
443 |
-- Clock generator: |
444 |
iserdes_clock_generator_inst : iserdes_clock_generator |
444 |
iserdes_clock_generator_inst : iserdes_clock_generator |
445 |
port map ( |
445 |
port map ( |
446 |
CLK_IN_P => IN_CLK_FOR_DATA_P, CLK_IN_N => IN_CLK_FOR_DATA_N, |
446 |
CLK_IN_P => IN_CLK_FOR_DATA_P, CLK_IN_N => IN_CLK_FOR_DATA_N, |
447 |
CLK_OUT => s_iserdes_clk, CLK_DIV_OUT => s_iserdes_clk_div, CLK_RESET => '0' ); |
447 |
CLK_OUT => s_iserdes_clk, CLK_DIV_OUT => s_iserdes_clk_div, CLK_RESET => '0' ); |
448 |
|
448 |
|
449 |
-- FRAME signal processing block: |
449 |
-- FRAME signal processing block: |
450 |
frame_processing_block_inst : entity work.processing_block |
450 |
frame_processing_block_inst : entity work.processing_block |
451 |
port map ( |
451 |
port map ( |
452 |
clk_iserdes_in => s_iserdes_clk, clk_iserdes_in_div => s_iserdes_clk_div, clk_global => bus_clk, |
452 |
clk_iserdes_in => s_iserdes_clk, clk_iserdes_in_div => s_iserdes_clk_div, clk_global => bus_clk, |
453 |
rst => s_reset, |
453 |
rst => s_reset, |
454 |
bitslip => s_bitslip, bitslip_done => s_bitslip_done, bitslip_drop_byte => s_bitslip_drop_byte, |
454 |
bitslip => s_bitslip, bitslip_done => s_bitslip_done, bitslip_drop_byte => s_bitslip_drop_byte, |
455 |
in_data_p => IN_FRAME_FOR_DATA_P, in_data_n => IN_FRAME_FOR_DATA_N, |
455 |
in_data_p => IN_FRAME_FOR_DATA_P, in_data_n => IN_FRAME_FOR_DATA_N, |
456 |
in_data_swap_pn => C_FRAME_WIRES_SWAPPED_PN, |
456 |
in_data_swap_pn => C_FRAME_WIRES_SWAPPED_PN, |
457 |
in_output_counting => s_gpio_dip_sw(1), |
457 |
in_output_counting => s_gpio_dip_sw(1), |
458 |
|
458 |
|
459 |
o_iserdes_output => s_data16_to_bitslip, |
459 |
o_iserdes_output => s_data16_to_bitslip, |
460 |
o_iserdes_output_valid => s_data16_to_bitslip_valid, |
460 |
o_iserdes_output_valid => s_data16_to_bitslip_valid, |
461 |
|
461 |
|
462 |
o_data => s_from_processing_blocks_data( 31 downto 0 ), |
462 |
o_data => s_from_processing_blocks_data( 31 downto 0 ), |
463 |
o_valid => s_from_processing_blocks_valid( 0 ), |
463 |
o_valid => s_from_processing_blocks_valid( 0 ), |
464 |
i_rden => s_from_processing_blocks_rden( 0 ) |
464 |
i_rden => s_from_processing_blocks_rden( 0 ) |
465 |
); |
465 |
); |
466 |
|
466 |
|
467 |
-- bitslip processing: |
467 |
-- bitslip processing: |
468 |
s_valid_for_bitslip_processing <= s_data16_to_bitslip_valid and s_spi_done; |
468 |
s_valid_for_bitslip_processing <= s_data16_to_bitslip_valid and s_spi_done; |
469 |
|
469 |
|
470 |
bitslip_compensation_inst : bitslip_compensation |
470 |
bitslip_compensation_inst : bitslip_compensation |
471 |
port map ( |
471 |
port map ( |
472 |
clk => s_iserdes_clk_div, rst => s_reset, |
472 |
clk => s_iserdes_clk_div, rst => s_reset, |
473 |
i_data => s_data16_to_bitslip, i_valid => s_valid_for_bitslip_processing, |
473 |
i_data => s_data16_to_bitslip, i_valid => s_valid_for_bitslip_processing, |
474 |
o_bitslip => s_bitslip, o_bitslip_done => s_bitslip_done, o_bitslip_drop_byte => s_bitslip_drop_byte, o_bitslip_failed => s_bitslip_failed ); |
474 |
o_bitslip => s_bitslip, o_bitslip_done => s_bitslip_done, o_bitslip_drop_byte => s_bitslip_drop_byte, o_bitslip_failed => s_bitslip_failed ); |
475 |
|
475 |
|
476 |
-- ADCs signal processing blocks: |
476 |
-- ADCs signal processing blocks: |
477 |
adc_proc_block_gen : for i in 0 to C_NUM_INPUT_ADC_DATA_PORTS - 1 generate |
477 |
adc_proc_block_gen : for i in 0 to C_NUM_INPUT_ADC_DATA_PORTS - 1 generate |
478 |
adc_processing_block_inst : entity work.processing_block |
478 |
adc_processing_block_inst : entity work.processing_block |
479 |
port map ( |
479 |
port map ( |
480 |
clk_iserdes_in => s_iserdes_clk, clk_iserdes_in_div => s_iserdes_clk_div, clk_global => bus_clk, |
480 |
clk_iserdes_in => s_iserdes_clk, clk_iserdes_in_div => s_iserdes_clk_div, clk_global => bus_clk, |
481 |
rst => s_reset, |
481 |
rst => s_reset, |
482 |
bitslip => s_bitslip, bitslip_done => s_bitslip_done, bitslip_drop_byte => s_bitslip_drop_byte, |
482 |
bitslip => s_bitslip, bitslip_done => s_bitslip_done, bitslip_drop_byte => s_bitslip_drop_byte, |
483 |
in_data_p => IN_DATA_ADC_P(i), in_data_n => IN_DATA_ADC_N(i), |
483 |
in_data_p => IN_DATA_ADC_P(i), in_data_n => IN_DATA_ADC_N(i), |
484 |
in_data_swap_pn => C_DATA_WIRES_SWAPPED_PN(i), |
484 |
in_data_swap_pn => C_DATA_WIRES_SWAPPED_PN(i), |
485 |
in_output_counting => '0', |
485 |
in_output_counting => '0', |
486 |
|
486 |
|
487 |
o_iserdes_output => open, o_iserdes_output_valid => open, |
487 |
o_iserdes_output => open, o_iserdes_output_valid => open, |
488 |
|
488 |
|
489 |
o_data => s_from_processing_blocks_data( 32*(i+1+1) - 1 downto 32*(i+1) ), -- i+1, because 31 downto 0 is used by the FRAME result |
489 |
o_data => s_from_processing_blocks_data( 32*(i+1+1) - 1 downto 32*(i+1) ), -- i+1, because 31 downto 0 is used by the FRAME result |
490 |
o_valid => s_from_processing_blocks_valid( i + 1 ), |
490 |
o_valid => s_from_processing_blocks_valid( i + 1 ), |
491 |
i_rden => s_from_processing_blocks_rden( i + 1 ) |
491 |
i_rden => s_from_processing_blocks_rden( i + 1 ) |
492 |
); |
492 |
); |
493 |
end generate; |
493 |
end generate; |
494 |
|
494 |
|
495 |
-- multiplexer: |
495 |
-- multiplexer: |
496 |
multiplexer_from_fifos_inst : multiplexer_from_fifos |
496 |
multiplexer_from_fifos_inst : multiplexer_from_fifos |
497 |
generic map ( |
497 |
generic map ( |
498 |
G_NUM_CHANNELS => C_NUM_INPUT_ADC_DATA_PORTS + 1, |
498 |
G_NUM_CHANNELS => C_NUM_INPUT_ADC_DATA_PORTS + 1, |
499 |
G_DATA_WIDTH => 32 ) |
499 |
G_DATA_WIDTH => 32 ) |
500 |
port map ( |
500 |
port map ( |
501 |
clk => bus_clk, rst => s_reset, |
501 |
clk => bus_clk, rst => s_reset, |
502 |
|
502 |
|
503 |
i_data => s_from_processing_blocks_data, i_valid => s_from_processing_blocks_valid, |
503 |
i_data => s_from_processing_blocks_data, i_valid => s_from_processing_blocks_valid, |
504 |
o_rden => s_from_processing_blocks_rden, |
504 |
o_rden => s_from_processing_blocks_rden, |
505 |
|
505 |
|
506 |
o_data => s_from_multiplexer_data, o_valid => s_from_multiplexer_valid, i_full => s_from_multiplexer_full |
506 |
o_data => s_from_multiplexer_data, o_valid => s_from_multiplexer_valid, i_full => s_from_multiplexer_full |
507 |
); |
507 |
); |
508 |
|
508 |
|
509 |
-- interface to xillybus: |
509 |
-- interface to xillybus: |
510 |
-- FIFO_OUT instantiation: |
510 |
-- FIFO_OUT instantiation: |
511 |
data2_frame_fifo_out_inst : fifo_32x512_walmostfull |
511 |
data2_frame_fifo_out_inst : fifo_32x512_walmostfull |
512 |
port map ( |
512 |
port map ( |
513 |
clk => bus_clk, srst => s_reset, |
513 |
clk => bus_clk, srst => s_reset, |
514 |
din => s_from_multiplexer_data, wr_en => s_from_multiplexer_valid, full => open, prog_full => s_from_multiplexer_full, |
514 |
din => s_from_multiplexer_data, wr_en => s_from_multiplexer_valid, full => open, prog_full => s_from_multiplexer_full, |
515 |
dout => user_r_data2_r_data, rd_en => user_r_data2_r_rden, empty => user_r_data2_r_empty, valid => open ); |
515 |
dout => user_r_data2_r_data, rd_en => user_r_data2_r_rden, empty => user_r_data2_r_empty, valid => open ); |
516 |
|
516 |
|
517 |
----------------------------------------------------------------------------------------------- |
517 |
----------------------------------------------------------------------------------------------- |
518 |
-- LO - Local Oscillator division module: |
518 |
-- LO - Local Oscillator division module: |
519 |
|
519 |
|
520 |
-- TODO: not tested: addition of the CE input. Will the ADCs configure themselves without CLOCK? |
520 |
-- TODO: not tested: addition of the CE input. Will the ADCs configure themselves without CLOCK? |
521 |
lo_divider_wrapper_inst : entity work.lo_divider_wrapper |
521 |
lo_divider_wrapper_inst : entity work.lo_divider_wrapper |
522 |
generic map ( G_DIVISOR => 30 ) |
522 |
generic map ( G_DIVISOR => 30 ) |
523 |
port map ( |
523 |
port map ( |
524 |
IN_CLK_LO_N => IN_CLK_LO_N, IN_CLK_LO_P => IN_CLK_LO_P, in_clk_enable => '1', |
524 |
IN_CLK_LO_N => IN_CLK_LO_N, IN_CLK_LO_P => IN_CLK_LO_P, in_clk_enable => '1', |
525 |
OUT_CLK_LO_DIVIDED_N => OUT_CLK_LO_DIVIDED_N, OUT_CLK_LO_DIVIDED_P => OUT_CLK_LO_DIVIDED_P ); |
525 |
OUT_CLK_LO_DIVIDED_N => OUT_CLK_LO_DIVIDED_N, OUT_CLK_LO_DIVIDED_P => OUT_CLK_LO_DIVIDED_P ); |
526 |
|
526 |
|
527 |
----------------------------------------------------------------------------------------------- |
527 |
----------------------------------------------------------------------------------------------- |
528 |
-- SPI MASTER COMMUNICATION MODULE |
528 |
-- SPI MASTER COMMUNICATION MODULE |
529 |
|
529 |
|
530 |
spi_transmitter_wrapper_inst : entity work.spi_transmitter_wrapper |
530 |
spi_transmitter_wrapper_inst : entity work.spi_transmitter_wrapper |
531 |
generic map( |
531 |
generic map( |
532 |
G_DATA1 => C_SPI_ADC_DATA1, |
532 |
G_DATA1 => C_SPI_ADC_DATA1, |
533 |
G_DATA2 => C_SPI_ADC_DATA2, |
533 |
G_DATA2 => C_SPI_ADC_DATA2, |
534 |
G_NUM_BITS_PACKET => C_SPI_ADC_LENGTH, |
534 |
G_NUM_BITS_PACKET => C_SPI_ADC_LENGTH, |
535 |
G_NUM_PACKETS => C_SPI_ADC_PACKETS, |
535 |
G_NUM_PACKETS => C_SPI_ADC_PACKETS, |
536 |
G_NUM_BITS_PAUSE => C_SPI_ADC_PAUSE ) |
536 |
G_NUM_BITS_PAUSE => C_SPI_ADC_PAUSE ) |
537 |
port map( |
537 |
port map( |
538 |
i_clk125 => bus_clk, i_reset => s_reset, i_data_selector => s_gpio_dip_sw(2), |
538 |
i_clk125 => bus_clk, i_reset => s_reset, i_data_selector => s_gpio_dip_sw(2), |
539 |
o_done => s_spi_done, |
539 |
o_done => s_spi_done, |
540 |
OUT_SPI_N_CE => OUT_SPI_N_CE, OUT_SPI_DOUT => OUT_SPI_DOUT, OUT_SPI_CLK => OUT_SPI_CLK ); |
540 |
OUT_SPI_N_CE => OUT_SPI_N_CE, OUT_SPI_DOUT => OUT_SPI_DOUT, OUT_SPI_CLK => OUT_SPI_CLK ); |
541 |
|
541 |
|
542 |
end architecture; |
542 |
end architecture; |
543 |
|
543 |
|