Rev 3205 Rev 3206
1 ---------------------------------------------------------------------------------- 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz 2 -- Company: www.mlab.cz
3 -- Based on code written by MIHO. 3 -- Based on code written by MIHO.
4 -- 4 --
5 -- HW Design Name: S3AN01A 5 -- HW Design Name: S3AN01A
6 -- Project Name: Atomic Counter 6 -- Project Name: Atomic Counter
7 -- Target Devices: XC3S50AN-4 7 -- Target Devices: XC3S50AN-4
8 -- Tool versions: ISE 13.3 8 -- Tool versions: ISE 13.3
9 -- Description: Counter up to 640 MHz synchonised by GPS. 9 -- Description: Counter up to 640 MHz synchonised by GPS.
10 -- Output frequency is displayed on the 7seg. LED display. 10 -- Output frequency is displayed on the 7seg. LED display.
11 -- You can choice half or full frequency by DIPSW7. 11 -- You can choice half or full frequency by DIPSW7.
12 -- 12 --
13 -- Dependencies: TTLPECL01A, GPS01A 13 -- Dependencies: TTLPECL01A, GPS01A
14 -- 14 --
15 -- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $ 15 -- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $
16 -- 16 --
17 ---------------------------------------------------------------------------------- 17 ----------------------------------------------------------------------------------
18   18  
19 library IEEE; 19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL; 20 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.numeric_std.ALL; 21 use IEEE.numeric_std.ALL;
22   22  
23 library UNISIM; 23 library UNISIM;
24 use UNISIM.vcomponents.all; 24 use UNISIM.vcomponents.all;
25   25  
26 entity AtomicCounter is 26 entity AtomicCounter is
27 generic ( 27 generic (
28 -- Top Value for 100MHz Clock Counter 28 -- Top Value for 100MHz Clock Counter
29 MAXCOUNT: integer := 10_000; -- Maximum for the first counter 29 MAXCOUNT: integer := 10_000; -- Maximum for the first counter
30 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider 30 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
31 ); 31 );
32 port ( 32 port (
33 -- Clock on PCB 33 -- Clock on PCB
34 CLK100MHz: in std_logic; 34 CLK100MHz: in std_logic;
35   35  
36 -- Mode Signals (usualy not used) 36 -- Mode Signals (usualy not used)
37 M: in std_logic_vector(2 downto 0); 37 M: in std_logic_vector(2 downto 0);
38 VS: in std_logic_vector(2 downto 0); 38 VS: in std_logic_vector(2 downto 0);
39   39  
40 -- Dipswitch Inputs 40 -- Dipswitch Inputs
41 DIPSW: in std_logic_vector(7 downto 0); 41 DIPSW: in std_logic_vector(7 downto 0);
42   42  
43 -- Push Buttons 43 -- Push Buttons
44 PB: in std_logic_vector(3 downto 0); 44 PB: in std_logic_vector(3 downto 0);
45   45  
46 -- LED Bar Outputs 46 -- LED Bar Outputs
47 LED: out std_logic_vector(7 downto 0); 47 LED: out std_logic_vector(7 downto 0);
48   48  
49 -- LED Display (8 digit with 7 segments and ddecimal point) 49 -- LED Display (8 digit with 7 segments and ddecimal point)
50 LD_A_n: out std_logic; 50 LD_A_n: out std_logic;
51 LD_B_n: out std_logic; 51 LD_B_n: out std_logic;
52 LD_C_n: out std_logic; 52 LD_C_n: out std_logic;
53 LD_D_n: out std_logic; 53 LD_D_n: out std_logic;
54 LD_E_n: out std_logic; 54 LD_E_n: out std_logic;
55 LD_F_n: out std_logic; 55 LD_F_n: out std_logic;
56 LD_G_n: out std_logic; 56 LD_G_n: out std_logic;
57 LD_DP_n: out std_logic; 57 LD_DP_n: out std_logic;
58 LD_0_n: out std_logic; 58 LD_0_n: out std_logic;
59 LD_1_n: out std_logic; 59 LD_1_n: out std_logic;
60 LD_2_n: out std_logic; 60 LD_2_n: out std_logic;
61 LD_3_n: out std_logic; 61 LD_3_n: out std_logic;
62 LD_4_n: out std_logic; 62 LD_4_n: out std_logic;
63 LD_5_n: out std_logic; 63 LD_5_n: out std_logic;
64 LD_6_n: out std_logic; 64 LD_6_n: out std_logic;
65 LD_7_n: out std_logic; 65 LD_7_n: out std_logic;
66   66  
67 -- VGA Video Out Port 67 -- VGA Video Out Port
68 VGA_R: out std_logic_vector(1 downto 0); 68 VGA_R: out std_logic_vector(1 downto 0);
69 VGA_G: out std_logic_vector(1 downto 0); 69 VGA_G: out std_logic_vector(1 downto 0);
70 VGA_B: out std_logic_vector(1 downto 0); 70 VGA_B: out std_logic_vector(1 downto 0);
71 VGA_VS: out std_logic; 71 VGA_VS: out std_logic;
72 VGA_HS: out std_logic; 72 VGA_HS: out std_logic;
73   73  
74 -- Bank 1 Pins - Inputs for this Test 74 -- Bank 1 Pins - Inputs for this Test
75 B: inout std_logic_vector(24 downto 0); 75 B: inout std_logic_vector(24 downto 0);
76 76
77 -- PS/2 Bidirectional Port (open collector, J31 and J32) 77 -- PS/2 Bidirectional Port (open collector, J31 and J32)
78 PS2_CLK1: inout std_logic; 78 PS2_CLK1: inout std_logic;
79 PS2_DATA1: inout std_logic; 79 PS2_DATA1: inout std_logic;
80 PS2_CLK2: inout std_logic; 80 PS2_CLK2: inout std_logic;
81 PS2_DATA2: inout std_logic; 81 PS2_DATA2: inout std_logic;
82   82  
83 -- Diferencial Signals on 4 pin header (J7) 83 -- Diferencial Signals on 4 pin header (J7)
84 DIF1P: inout std_logic; 84 DIF1P: inout std_logic;
85 DIF1N: inout std_logic; 85 DIF1N: inout std_logic;
86 DIF2P: inout std_logic; 86 DIF2P: inout std_logic;
87 DIF2N: inout std_logic; 87 DIF2N: inout std_logic;
88 88
89   89  
90 -- I2C Signals (on connector J30) 90 -- I2C Signals (on connector J30)
91 I2C_SCL: inout std_logic; 91 I2C_SCL: inout std_logic;
92 I2C_SDA: inout std_logic; 92 I2C_SDA: inout std_logic;
93   93  
94 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) 94 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
95 SD1AP: inout std_logic; 95 SD1AP: inout std_logic;
96 SD1AN: inout std_logic; 96 SD1AN: inout std_logic;
97 SD1BP: inout std_logic; 97 SD1BP: inout std_logic;
98 SD1BN: inout std_logic; 98 SD1BN: inout std_logic;
99 SD2AP: inout std_logic; 99 SD2AP: inout std_logic;
100 SD2AN: inout std_logic; 100 SD2AN: inout std_logic;
101 SD2BP: inout std_logic; 101 SD2BP: inout std_logic;
102 SD2BN: inout std_logic; 102 SD2BN: inout std_logic;
103   103  
104 -- Analog In Out 104 -- Analog In Out
105 ANA_OUTD: out std_logic; 105 ANA_OUTD: out std_logic;
106 ANA_REFD: out std_logic; 106 ANA_REFD: out std_logic;
107 ANA_IND: in std_logic; 107 ANA_IND: in std_logic;
108   108  
109 -- SPI Memory Interface 109 -- SPI Memory Interface
110 SPI_CS_n: inout std_logic; 110 SPI_CS_n: inout std_logic;
111 SPI_DO: inout std_logic; 111 SPI_DO: inout std_logic;
112 SPI_DI: inout std_logic; 112 SPI_DI: inout std_logic;
113 SPI_CLK: inout std_logic; 113 SPI_CLK: inout std_logic;
114 SPI_WP_n: inout std_logic 114 SPI_WP_n: inout std_logic
115 ); 115 );
116 end entity AtomicCounter; 116 end entity AtomicCounter;
117   117  
118   118  
119 architecture AtomicCounter_a of AtomicCounter is 119 architecture AtomicCounter_a of AtomicCounter is
120   120  
121 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is 121 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is
122 variable i : integer:=0; 122 variable i : integer:=0;
123 variable mybcd : std_logic_vector(19 downto 0) := (others => '0'); 123 variable mybcd : std_logic_vector(19 downto 0) := (others => '0');
124 variable bint : std_logic_vector(15 downto 0) := bin; 124 variable bint : std_logic_vector(15 downto 0) := bin;
125 begin 125 begin
126 for i in 0 to 15 loop -- repeating 16 times. 126 for i in 0 to 15 loop -- repeating 16 times.
127 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits. 127 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits.
128 mybcd(0) := bint(15); 128 mybcd(0) := bint(15);
129 bint(15 downto 1) := bint(14 downto 0); 129 bint(15 downto 1) := bint(14 downto 0);
130 bint(0) :='0'; 130 bint(0) :='0';
131   131  
132   132  
133 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. 133 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
134 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); 134 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
135 end if; 135 end if;
136   136  
137 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. 137 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
138 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); 138 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
139 end if; 139 end if;
140   140  
141 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. 141 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
142 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); 142 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
143 end if; 143 end if;
144   144  
145 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4. 145 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
146 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3); 146 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
147 end if; 147 end if;
148   148  
149 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4. 149 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
150 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3); 150 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
151 end if; 151 end if;
152   152  
153 end loop; 153 end loop;
154 154
155 return mybcd; 155 return mybcd;
156 end to_bcd; 156 end to_bcd;
157   157  
158   158  
159 -- Counters 159 -- Counters
160 -- ---------------- 160 -- ----------------
161   161  
162 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary) 162 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
163 signal CounterMaxcount: unsigned(15 downto 0) := "0000000000000000"; -- Main Counter 10 kHz, max. 655.35 MHz (binary) 163 signal CounterMaxcount: unsigned(15 downto 0) := "0000000000000000"; -- Main Counter 10 kHz, max. 655.35 MHz (binary)
164   164  
165   165  
166 -- LED Display 166 -- LED Display
167 -- ----------- 167 -- -----------
168   168  
169 signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- Variable for bin/BCD conversion 169 signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- Variable for bin/BCD conversion
170 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input 170 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
171 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency 171 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
172 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider 172 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
173 signal Enable: std_logic; 173 signal Enable: std_logic;
174 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output 174 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
175 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output 175 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
176 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output 176 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
177   177  
178 178
179 signal LO_CLOCK: std_logic; -- Frequency divided by 2 179 signal LO_CLOCK: std_logic; -- Frequency divided by 2
180 signal EXT_CLOCK: std_logic; -- Input Frequency 180 signal EXT_CLOCK: std_logic; -- Input Frequency
181   181  
182 signal Decko: std_logic; -- D flip-flop 182 signal Decko: std_logic; -- D flip-flop
183 signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata 183 signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata
184 184
185 begin 185 begin
186   186  
187 -- Input divider by 2 187 -- Input divider by 2
188 process (EXT_CLOCK) 188 process (EXT_CLOCK)
189 begin 189 begin
190 if rising_edge(EXT_CLOCK) then 190 if rising_edge(EXT_CLOCK) then
191 LO_CLOCK <= not LO_CLOCK; 191 LO_CLOCK <= not LO_CLOCK;
192 end if; 192 end if;
193 end process; 193 end process;
194   194  
195   195  
196 -- Counter 196 -- Counter
197 process (LO_CLOCK) 197 process (LO_CLOCK)
198 begin 198 begin
199 199
200 if rising_edge(LO_CLOCK) then 200 if rising_edge(LO_CLOCK) then
201 201
202 if (State = 3) or (State = 0) then 202 if (State = 3) or (State = 0) then
203 if Counter < MAXCOUNT-1 then 203 if Counter < MAXCOUNT-1 then
204 Counter <= Counter + 1; 204 Counter <= Counter + 1;
205 else 205 else
206 Counter <= (others => '0'); 206 Counter <= (others => '0');
207 CounterMaxcount <= CounterMaxcount + 1; 207 CounterMaxcount <= CounterMaxcount + 1;
208 end if; 208 end if;
209 end if; 209 end if;
210 if (State = 1) then 210 if (State = 1) then
211 Freq(15 downto 0) <= std_logic_vector("00"&Counter); 211 Freq(15 downto 0) <= std_logic_vector("00"&Counter);
212 Freq(31 downto 16) <= std_logic_vector(CounterMaxcount); 212 Freq(31 downto 16) <= std_logic_vector(CounterMaxcount);
213 end if; 213 end if;
214 if (State = 2) then 214 if (State = 2) then
215 CounterMaxcount <= (others => '0'); 215 CounterMaxcount <= (others => '0');
216 Counter <= (others => '0'); 216 Counter <= (others => '0');
217 end if; 217 end if;
218 end if; 218 end if;
219   219  
220 end process; 220 end process;
221   221  
222   222  
223 -- Sampling 1PPS signal 223 -- Sampling 1PPS signal
224 process (LO_CLOCK) 224 process (LO_CLOCK)
225 begin 225 begin
226 if rising_edge(LO_CLOCK) then 226 if rising_edge(LO_CLOCK) then
227 Decko <= B(22); 227 Decko <= B(22);
228 end if; 228 end if;
229 end process; 229 end process;
230   230  
231 -- Automata for controlling the Counter 231 -- Automata for controlling the Counter
232 process (LO_CLOCK) 232 process (LO_CLOCK)
233 begin 233 begin
234 if rising_edge(LO_CLOCK) then 234 if rising_edge(LO_CLOCK) then
235 if (Decko = '1') then 235 if (Decko = '1') then
236 if (State < 3) then 236 if (State < 3) then
237 State <= State + 1; 237 State <= State + 1;
238 end if; 238 end if;
239 else 239 else
240 State <= (others => '0'); 240 State <= (others => '0');
241 end if; 241 end if;
242 end if; 242 end if;
243 end process; 243 end process;
244   244  
245 -- Coding to BCD for LED Display 245 -- Coding to BCD for LED Display
246   246  
247 process (Decko) 247 process (Decko)
248 begin 248 begin
249 if falling_edge(Decko) then 249 if falling_edge(Decko) then
250 if DIPSW(7) = '0' then 250 if DIPSW(7) = '0' then
251 NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0); -- Half frequency 251 NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0); -- Half frequency
252 NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0); 252 NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0);
253 else 253 else
254 NumberPom(15 downto 0) <= to_bcd(Freq(14 downto 1)&"0")(15 downto 0); -- Full frequency 254 NumberPom(15 downto 0) <= to_bcd(Freq(14 downto 1)&"0")(15 downto 0); -- Full frequency
255 NumberPom(35 downto 16) <= to_bcd(Freq(30 downto 15))(19 downto 0); 255 NumberPom(35 downto 16) <= to_bcd(Freq(30 downto 15))(19 downto 0);
256 end if; 256 end if;
257 end if; 257 end if;
258 end process; 258 end process;
259   259  
260 Number(35 downto 0) <= NumberPom(35 downto 0); 260 Number(35 downto 0) <= NumberPom(35 downto 0);
261 261
262 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar 262 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
263 LED(6 downto 4) <= (others => '0'); 263 LED(6 downto 4) <= (others => '0');
264 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar 264 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
265   265  
266 -- LED Display (multiplexed) 266 -- LED Display (multiplexed)
267 -- ========================= 267 -- =========================
268   268  
269 -- Connect LED Display Output Ports (negative outputs) 269 -- Connect LED Display Output Ports (negative outputs)
270 LD_A_n <= not (Segments(0) and Enable); 270 LD_A_n <= not (Segments(0) and Enable);
271 LD_B_n <= not (Segments(1) and Enable); 271 LD_B_n <= not (Segments(1) and Enable);
272 LD_C_n <= not (Segments(2) and Enable); 272 LD_C_n <= not (Segments(2) and Enable);
273 LD_D_n <= not (Segments(3) and Enable); 273 LD_D_n <= not (Segments(3) and Enable);
274 LD_E_n <= not (Segments(4) and Enable); 274 LD_E_n <= not (Segments(4) and Enable);
275 LD_F_n <= not (Segments(5) and Enable); 275 LD_F_n <= not (Segments(5) and Enable);
276 LD_G_n <= not (Segments(6) and Enable); 276 LD_G_n <= not (Segments(6) and Enable);
277 LD_DP_n <= not (Segments(7) and Enable); 277 LD_DP_n <= not (Segments(7) and Enable);
278   278  
279 LD_0_n <= not Digits(0); 279 LD_0_n <= not Digits(0);
280 LD_1_n <= not Digits(1); 280 LD_1_n <= not Digits(1);
281 LD_2_n <= not Digits(2); 281 LD_2_n <= not Digits(2);
282 LD_3_n <= not Digits(3); 282 LD_3_n <= not Digits(3);
283 LD_4_n <= not Digits(4); 283 LD_4_n <= not Digits(4);
284 LD_5_n <= not Digits(5); 284 LD_5_n <= not Digits(5);
285 LD_6_n <= not Digits(6); 285 LD_6_n <= not Digits(6);
286 LD_7_n <= not Digits(7); 286 LD_7_n <= not Digits(7);
287   287  
288 -- Time Multiplex 288 -- Time Multiplex
289 process (CLK100MHz) 289 process (CLK100MHz)
290 begin 290 begin
291 if rising_edge(CLK100MHz) then 291 if rising_edge(CLK100MHz) then
292 if MuxCounter < MUXCOUNT-1 then 292 if MuxCounter < MUXCOUNT-1 then
293 MuxCounter <= MuxCounter + 1; 293 MuxCounter <= MuxCounter + 1;
294 else 294 else
295 MuxCounter <= (others => '0'); 295 MuxCounter <= (others => '0');
296 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left 296 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
297 Enable <= '0'; 297 Enable <= '0';
298 end if; 298 end if;
299 if MuxCounter > (MUXCOUNT-4) then 299 if MuxCounter > (MUXCOUNT-4) then
300 Enable <= '1'; 300 Enable <= '1';
301 end if; 301 end if;
302 end if; 302 end if;
303 end process; 303 end process;
304   304  
305 -- HEX to 7 Segmet Decoder 305 -- HEX to 7 Segmet Decoder
306 -- -- A 306 -- -- A
307 -- | | F B 307 -- | | F B
308 -- -- G 308 -- -- G
309 -- | | E C 309 -- | | E C
310 -- -- D H 310 -- -- D H
311 -- ABCDEFGH 311 -- ABCDEFGH
312 Segments <= "11111100" when Code="0000" else -- Digit 0 312 Segments <= "11111100" when Code="0000" else -- Digit 0
313 "01100000" when Code="0001" else -- Digit 1 313 "01100000" when Code="0001" else -- Digit 1
314 "11011010" when Code="0010" else -- Digit 2 314 "11011010" when Code="0010" else -- Digit 2
315 "11110010" when Code="0011" else -- Digit 3 315 "11110010" when Code="0011" else -- Digit 3
316 "01100110" when Code="0100" else -- Digit 4 316 "01100110" when Code="0100" else -- Digit 4
317 "10110110" when Code="0101" else -- Digit 5 317 "10110110" when Code="0101" else -- Digit 5
318 "10111110" when Code="0110" else -- Digit 6 318 "10111110" when Code="0110" else -- Digit 6
319 "11100000" when Code="0111" else -- Digit 7 319 "11100000" when Code="0111" else -- Digit 7
320 "11111110" when Code="1000" else -- Digit 8 320 "11111110" when Code="1000" else -- Digit 8
321 "11110110" when Code="1001" else -- Digit 9 321 "11110110" when Code="1001" else -- Digit 9
322 "11101110" when Code="1010" else -- Digit A 322 "11101110" when Code="1010" else -- Digit A
323 "00111110" when Code="1011" else -- Digit b 323 "00111110" when Code="1011" else -- Digit b
324 "10011100" when Code="1100" else -- Digit C 324 "10011100" when Code="1100" else -- Digit C
325 "01111010" when Code="1101" else -- Digit d 325 "01111010" when Code="1101" else -- Digit d
326 "10011110" when Code="1110" else -- Digit E 326 "10011110" when Code="1110" else -- Digit E
327 "10001110" when Code="1111" else -- Digit F 327 "10001110" when Code="1111" else -- Digit F
328 "00000000"; 328 "00000000";
329   329  
330 Code <= Number( 3 downto 0) when Digits="00000001" else 330 Code <= Number( 3 downto 0) when Digits="00000001" else
331 Number( 7 downto 4) when Digits="00000010" else 331 Number( 7 downto 4) when Digits="00000010" else
332 Number(11 downto 8) when Digits="00000100" else 332 Number(11 downto 8) when Digits="00000100" else
333 Number(15 downto 12) when Digits="00001000" else 333 Number(15 downto 12) when Digits="00001000" else
334 Number(19 downto 16) when Digits="00010000" else 334 Number(19 downto 16) when Digits="00010000" else
335 Number(23 downto 20) when Digits="00100000" else 335 Number(23 downto 20) when Digits="00100000" else
336 Number(27 downto 24) when Digits="01000000" else 336 Number(27 downto 24) when Digits="01000000" else
337 Number(31 downto 28) when Digits="10000000" else 337 Number(31 downto 28) when Digits="10000000" else
338 "0000"; 338 "0000";
339   339  
340   340  
341   341  
342 -- Diferencial In/Outs 342 -- Diferencial In/Outs
343 -- ======================== 343 -- ========================
344 DIFbuffer1 : IBUFGDS 344 DIFbuffer1 : IBUFGDS
345 generic map ( 345 generic map (
346 DIFF_TERM => FALSE, -- Differential Termination 346 DIFF_TERM => FALSE, -- Differential Termination
347 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 347 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
348 -- "0"-"16" 348 -- "0"-"16"
349 IOSTANDARD => "LVPECL_33") 349 IOSTANDARD => "LVPECL_33")
350 port map ( 350 port map (
351 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) 351 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
352 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) 352 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
353 O => EXT_CLOCK -- Buffer output - Counter INPUT 353 O => EXT_CLOCK -- Buffer output - Counter INPUT
354 ); 354 );
355   355  
356 OBUFDS_inst : OBUFDS 356 OBUFDS_inst : OBUFDS
357 generic map ( 357 generic map (
358 IOSTANDARD => "LVDS_33") 358 IOSTANDARD => "LVDS_33")
359 port map ( 359 port map (
360 O => SD2AP, -- Diff_p output (connect directly to top-level port) 360 O => SD2AP, -- Diff_p output (connect directly to top-level port)
361 OB => SD2AN, -- Diff_n output (connect directly to top-level port) 361 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
362 I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS 362 I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS
363 ); 363 );
364 364
365 -- Output Signal on SATA Connector 365 -- Output Signal on SATA Connector
366 -- SD1AP <= 'Z'; -- Counter INPUT 366 -- SD1AP <= 'Z'; -- Counter INPUT
367 -- SD1AN <= 'Z'; 367 -- SD1AN <= 'Z';
368 SD1BP <= 'Z'; 368 SD1BP <= 'Z';
369 SD1BN <= 'Z'; 369 SD1BN <= 'Z';
370   370  
371 -- Input Here via SATA Cable 371 -- Input Here via SATA Cable
372 -- SD2AP <= 'Z'; -- Counter OUTPUT 372 -- SD2AP <= 'Z'; -- Counter OUTPUT
373 -- SD2AN <= 'Z'; 373 -- SD2AN <= 'Z';
374 SD2BP <= 'Z'; 374 SD2BP <= 'Z';
375 SD2BN <= 'Z'; 375 SD2BN <= 'Z';
376   376  
377   377  
378 -- Unused Signals 378 -- Unused Signals
379 -- ============== 379 -- ==============
380   380  
381 -- Differential inputs onn header 381 -- Differential inputs onn header
382 DIF1N <= 'Z'; 382 DIF1N <= 'Z';
383 DIF1P <= 'Z'; 383 DIF1P <= 'Z';
384 DIF2N <= 'Z'; 384 DIF2N <= 'Z';
385 DIF2P <= 'Z'; 385 DIF2P <= 'Z';
386   386  
387 -- I2C Signals (on connector J30) 387 -- I2C Signals (on connector J30)
388 I2C_SCL <= 'Z'; 388 I2C_SCL <= 'Z';
389 I2C_SDA <= 'Z'; 389 I2C_SDA <= 'Z';
390   390  
391 -- SPI Memory Interface 391 -- SPI Memory Interface
392 SPI_CS_n <= 'Z'; 392 SPI_CS_n <= 'Z';
393 SPI_DO <= 'Z'; 393 SPI_DO <= 'Z';
394 SPI_DI <= 'Z'; 394 SPI_DI <= 'Z';
395 SPI_CLK <= 'Z'; 395 SPI_CLK <= 'Z';
396 SPI_WP_n <= 'Z'; 396 SPI_WP_n <= 'Z';
397   397  
398 -- A/D 398 -- A/D
399 ANA_OUTD <= 'Z'; 399 ANA_OUTD <= 'Z';
400 ANA_REFD <= 'Z'; 400 ANA_REFD <= 'Z';
401   401  
402 -- VGA 402 -- VGA
403 VGA_R <= "ZZ"; 403 VGA_R <= "ZZ";
404 VGA_G <= "ZZ"; 404 VGA_G <= "ZZ";
405 VGA_B <= "ZZ"; 405 VGA_B <= "ZZ";
406 VGA_VS <= 'Z'; 406 VGA_VS <= 'Z';
407 VGA_HS <= 'Z'; 407 VGA_HS <= 'Z';
408   408  
409 -- PS2 409 -- PS2
410 PS2_DATA2 <= 'Z'; 410 PS2_DATA2 <= 'Z';
411 PS2_CLK2 <='Z'; 411 PS2_CLK2 <='Z';
412   412  
413 end architecture AtomicCounter_a; 413 end architecture AtomicCounter_a;