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---------------------------------------------------------------------------------- |
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---------------------------------------------------------------------------------- |
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-- Company: www.mlab.cz |
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-- Company: www.mlab.cz |
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-- Engineer: miho |
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-- Engineer: miho |
4 |
-- |
4 |
-- |
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-- Create Date: 19:31:10 02/20/2011 |
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-- Create Date: 19:31:10 02/20/2011 |
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-- Design Name: S3AN01A Test Design |
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-- Design Name: S3AN01A Test Design |
7 |
-- Module Name: PS2 |
7 |
-- Module Name: PS2 |
8 |
-- Project Name: S3AN01A Test Design |
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-- Project Name: S3AN01A Test Design |
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-- Target Devices: XILINX FPGA (Spartan3A/3AN) |
9 |
-- Target Devices: XILINX FPGA (Spartan3A/3AN) |
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-- Tool versions: ISE 12.4 / 13.1 / 13.3 |
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-- Tool versions: ISE 12.4 / 13.1 / 13.3 |
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-- Description: Test design for PCB verification |
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-- Description: Test design for PCB verification |
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-- |
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-- |
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-- Dependencies: None |
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-- Dependencies: None |
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-- |
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-- |
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-- Revision: 0.01 File Created |
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-- Revision: 0.01 File Created |
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-- |
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-- |
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---------------------------------------------------------------------------------- |
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---------------------------------------------------------------------------------- |
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-- |
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-- |
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-- PS/2 Keyboard Driver |
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-- PS/2 Keyboard Driver |
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-- ==================== |
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-- ==================== |
21 |
-- |
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-- |
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-- PS2_Code |
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-- PS2_Code |
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-- -------- |
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-- -------- |
24 |
-- |
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-- |
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-- Standard PS/2 Scan Code |
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-- Standard PS/2 Scan Code |
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-- |
26 |
-- |
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-- |
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-- |
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-- PS2_Attribs |
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-- PS2_Attribs |
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-- ----------- |
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-- ----------- |
30 |
-- |
30 |
-- |
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-- Bit 0 - Shift |
31 |
-- Bit 0 - Shift |
32 |
-- Bit 1 - Ctrl |
32 |
-- Bit 1 - Ctrl |
33 |
-- Bit 2 - Alt |
33 |
-- Bit 2 - Alt |
34 |
-- Bit 3 - Ext0 (arrows, ...) |
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-- Bit 3 - Ext0 (arrows, ...) |
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-- Bit 4 - Ext1 |
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-- Bit 4 - Ext1 |
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-- Bit 5 - Shift Num (arrows with NumLock) |
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-- Bit 5 - Shift Num (arrows with NumLock) |
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-- Bit 6 |
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-- Bit 6 |
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-- Bit 7 - Break (key release) |
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-- Bit 7 - Break (key release) |
39 |
-- |
39 |
-- |
40 |
-- |
40 |
-- |
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-- PS2_Shifts |
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-- PS2_Shifts |
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-- ---------- |
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-- ---------- |
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-- |
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-- |
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-- Bit 0 - Shift Left |
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-- Bit 0 - Shift Left |
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-- Bit 1 - Shift Right |
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-- Bit 1 - Shift Right |
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-- Bit 2 - Ctrl Left |
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-- Bit 2 - Ctrl Left |
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-- Bit 3 - Ctrl Right |
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-- Bit 3 - Ctrl Right |
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-- Bit 4 - Alt Left |
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-- Bit 4 - Alt Left |
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-- Bit 5 - Alt Right |
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-- Bit 5 - Alt Right |
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-- Bit 6 - Num Lock |
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-- Bit 6 - Num Lock |
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-- Bit 7 - Caps Lock |
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-- Bit 7 - Caps Lock |
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-- Bit 8 - Scroll Lock |
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-- Bit 8 - Scroll Lock |
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-- Bit 9 - Shift Num (virtual state) - Not to be used |
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-- Bit 9 - Shift Num (virtual state) - Not to be used |
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-- |
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-- |
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---------------------------------------------------------------------------------- |
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---------------------------------------------------------------------------------- |
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|
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|
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|
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|
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library IEEE; |
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library IEEE; |
59 |
use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.NUMERIC_STD.ALL; |
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use IEEE.NUMERIC_STD.ALL; |
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|
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|
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entity PS2 is |
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entity PS2 is |
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generic ( |
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generic ( |
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-- Top Value for 100MHz Clock Counter |
64 |
-- Top Value for 100MHz Clock Counter |
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CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000) |
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CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000) |
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); |
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); |
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port ( |
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port ( |
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-- Main Clock |
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-- Main Clock |
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Clk: in std_logic; |
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Clk: in std_logic; |
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|
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|
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-- PS/2 Port |
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-- PS/2 Port |
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PS2_Clk: inout std_logic; |
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PS2_Clk: inout std_logic; |
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PS2_Data: inout std_logic; |
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PS2_Data: inout std_logic; |
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|
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|
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-- Result - valid when PS2_Valid |
75 |
-- Result - valid when PS2_Valid |
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PS2_Valid: out boolean; -- Valid Data (synchronous with Clk) |
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PS2_Valid: out boolean; -- Valid Data (synchronous with Clk) |
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PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code |
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PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code |
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PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
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PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
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|
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|
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-- Immediate State of Shifts |
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-- Immediate State of Shifts |
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PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc. |
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PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc. |
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); |
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); |
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end entity PS2; |
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end entity PS2; |
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|
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|
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|
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|
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library IEEE; |
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library IEEE; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.STD_LOGIC_1164.ALL; |
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package PS2_pkg is |
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package PS2_pkg is |
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component PS2 |
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component PS2 |
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generic ( |
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generic ( |
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-- Top Value for 100MHz Clock Counter |
91 |
-- Top Value for 100MHz Clock Counter |
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CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000) |
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CLKFREQ: integer -- Frequency in Hz (minimum cca 50_000) |
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); |
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); |
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port ( |
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port ( |
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-- Main Clock |
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-- Main Clock |
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Clk: in std_logic; |
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Clk: in std_logic; |
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|
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|
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-- PS/2 Port |
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-- PS/2 Port |
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PS2_Clk: inout std_logic; |
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PS2_Clk: inout std_logic; |
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PS2_Data: inout std_logic; |
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PS2_Data: inout std_logic; |
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|
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|
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-- Result - valid when PS2_Valid |
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-- Result - valid when PS2_Valid |
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PS2_Valid: out boolean; -- Valid Data (synchronous with Main Clock) |
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PS2_Valid: out boolean; -- Valid Data (synchronous with Main Clock) |
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PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code |
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PS2_Code: out std_logic_vector(7 downto 0); -- Key Scan Code |
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PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
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PS2_Attribs: out std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
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|
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|
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-- Immediate State of Shifts |
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-- Immediate State of Shifts |
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PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc. |
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PS2_Shifts: out std_logic_vector(9 downto 0) -- Immediate (live) State of Shift/Alt/Ctrl etc. |
109 |
); |
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); |
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end component PS2; |
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end component PS2; |
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end package; |
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end package; |
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|
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|
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|
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|
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architecture PS2_a of PS2 is |
114 |
architecture PS2_a of PS2 is |
115 |
|
115 |
|
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function to_std_logic(State: boolean) return std_logic is |
116 |
function to_std_logic(State: boolean) return std_logic is |
117 |
begin |
117 |
begin |
118 |
if State then |
118 |
if State then |
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return '1'; |
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return '1'; |
120 |
else |
120 |
else |
121 |
return '0'; |
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return '0'; |
122 |
end if; |
122 |
end if; |
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end function to_std_logic; |
123 |
end function to_std_logic; |
124 |
|
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|
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-- Sampled PS/2 Clock and Data |
125 |
-- Sampled PS/2 Clock and Data |
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signal PS2_Clk_d: std_logic := '0'; -- For sync with systerm clock |
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signal PS2_Clk_d: std_logic := '0'; -- For sync with systerm clock |
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signal PS2_Clk_dd: std_logic := '0'; -- For falling edge detection |
127 |
signal PS2_Clk_dd: std_logic := '0'; -- For falling edge detection |
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signal PS2_Data_d: std_logic := '0'; -- For sync with systerm clock |
128 |
signal PS2_Data_d: std_logic := '0'; -- For sync with systerm clock |
129 |
|
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|
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-- Level 0 - Read Byte from PS/2 Interface |
130 |
-- Level 0 - Read Byte from PS/2 Interface |
131 |
type ReadByte_t is ( -- Read Byte FSM State Type |
131 |
type ReadByte_t is ( -- Read Byte FSM State Type |
132 |
Idle, -- Inactive State |
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Idle, -- Inactive State |
133 |
D0, D1, D2, D3, D4, D5, D6, D7, -- Receiving Bits |
133 |
D0, D1, D2, D3, D4, D5, D6, D7, -- Receiving Bits |
134 |
Parity, -- Receiving Parity |
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Parity, -- Receiving Parity |
135 |
Final -- Receiving Stop Bit and Sending ReadByte_rdy |
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Final -- Receiving Stop Bit and Sending ReadByte_rdy |
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); |
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); |
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signal ReadByteState: ReadByte_t := Idle; -- Read Byte FSM State |
137 |
signal ReadByteState: ReadByte_t := Idle; -- Read Byte FSM State |
138 |
signal ReadByte: std_logic_vector(7 downto 0) := (others => '0'); -- Read Byte (Raw Scan Code Byte) |
138 |
signal ReadByte: std_logic_vector(7 downto 0) := (others => '0'); -- Read Byte (Raw Scan Code Byte) |
139 |
signal ReadByte_rdy: boolean := false; -- Read Byte Ready (synchronous with Clk) |
139 |
signal ReadByte_rdy: boolean := false; -- Read Byte Ready (synchronous with Clk) |
140 |
|
140 |
|
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-- Level 1 - Process Raw Scan Codes E0,F1 and F0 - valid only when Level1_rdy |
141 |
-- Level 1 - Process Raw Scan Codes E0,F1 and F0 - valid only when Level1_rdy |
142 |
signal FlagE0: boolean := false; -- E0 - Ext0 Key |
142 |
signal FlagE0: boolean := false; -- E0 - Ext0 Key |
143 |
signal FlagE1: boolean := false; -- E1 - Ext1 Key |
143 |
signal FlagE1: boolean := false; -- E1 - Ext1 Key |
144 |
signal FlagF0: boolean := false; -- F0 - Break (release) Key |
144 |
signal FlagF0: boolean := false; -- F0 - Break (release) Key |
145 |
signal Level1_rdy: boolean := false; -- Send Data and Flags to the next level |
145 |
signal Level1_rdy: boolean := false; -- Send Data and Flags to the next level |
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|
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|
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-- Level 2 - Process Raw Scan Codes and Shift-Like Atributes E0, E1 and F0 - valid only when Level2_rdy |
147 |
-- Level 2 - Process Raw Scan Codes and Shift-Like Atributes E0, E1 and F0 - valid only when Level2_rdy |
148 |
signal FlagBreak: boolean := false; -- F0 - Break (depress) Key |
148 |
signal FlagBreak: boolean := false; -- F0 - Break (depress) Key |
149 |
signal FlagAltR: boolean := false; -- E0 11 - State of Right Alt Key |
149 |
signal FlagAltR: boolean := false; -- E0 11 - State of Right Alt Key |
150 |
signal FlagAltL: boolean := false; -- 11 - State of Left Alt Key |
150 |
signal FlagAltL: boolean := false; -- 11 - State of Left Alt Key |
151 |
signal FlagShiftNum: boolean := false; -- E0 12 - State of Ext Left Shift (pseudo key) |
151 |
signal FlagShiftNum: boolean := false; -- E0 12 - State of Ext Left Shift (pseudo key) |
152 |
signal FlagShiftL: boolean := false; -- 12 |
152 |
signal FlagShiftL: boolean := false; -- 12 |
153 |
signal FlagShiftR: boolean := false; -- 59 |
153 |
signal FlagShiftR: boolean := false; -- 59 |
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signal FlagCtrlR: boolean := false; -- E0 14 |
154 |
signal FlagCtrlR: boolean := false; -- E0 14 |
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signal FlagCtrlL: boolean := false; -- 14 |
155 |
signal FlagCtrlL: boolean := false; -- 14 |
156 |
signal FlagExt0: boolean := false; -- E0 Keys (extended keys) |
156 |
signal FlagExt0: boolean := false; -- E0 Keys (extended keys) |
157 |
signal FlagExt1: boolean := false; -- E1 Keys (extended keys - Prt_Scr and Pause_Brk) |
157 |
signal FlagExt1: boolean := false; -- E1 Keys (extended keys - Prt_Scr and Pause_Brk) |
158 |
signal FlagNumLock: boolean := false; -- 77 Num Lock State |
158 |
signal FlagNumLock: boolean := false; -- 77 Num Lock State |
159 |
signal FlagScrollLock: boolean := false; -- 7E Scroll Lock State |
159 |
signal FlagScrollLock: boolean := false; -- 7E Scroll Lock State |
160 |
signal FlagCapsLock: boolean := false; -- 58 Caps Lock State |
160 |
signal FlagCapsLock: boolean := false; -- 58 Caps Lock State |
161 |
signal Level2_rdy: boolean := false; -- Send Data and Flags to the next level |
161 |
signal Level2_rdy: boolean := false; -- Send Data and Flags to the next level |
162 |
signal Level2a_rdy: boolean := false; -- Send Read Ack for Write Byte |
162 |
signal Level2a_rdy: boolean := false; -- Send Read Ack for Write Byte |
163 |
|
163 |
|
164 |
-- Write Byte |
164 |
-- Write Byte |
165 |
type WriteByteState_t is ( -- Write Byte FSM State Type |
165 |
type WriteByteState_t is ( -- Write Byte FSM State Type |
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Idle, -- Idle State |
166 |
Idle, -- Idle State |
167 |
WriteStart, -- Start (pull PS2_Clk down) |
167 |
WriteStart, -- Start (pull PS2_Clk down) |
168 |
WaitStart, -- Wait |
168 |
WaitStart, -- Wait |
169 |
SendBits, -- Send Data Bits |
169 |
SendBits, -- Send Data Bits |
170 |
WriteParity, -- Send Parity |
170 |
WriteParity, -- Send Parity |
171 |
WriteStop, -- Send Stop Bit |
171 |
WriteStop, -- Send Stop Bit |
172 |
AckBit, -- Wait for Ack Bit from Keyboard |
172 |
AckBit, -- Wait for Ack Bit from Keyboard |
173 |
Final, -- Wait for Idle on PS2_Clk and PS2_Data |
173 |
Final, -- Wait for Idle on PS2_Clk and PS2_Data |
174 |
WaitAckByte -- Wait for Ack Byte from Keyboard |
174 |
WaitAckByte -- Wait for Ack Byte from Keyboard |
175 |
); |
175 |
); |
176 |
signal WriteByteState: WriteByteState_t := Idle; -- Write Byte FSM State |
176 |
signal WriteByteState: WriteByteState_t := Idle; -- Write Byte FSM State |
177 |
signal WriteCode: std_logic_vector(7 downto 0) := (others =>'0'); -- What to Write |
177 |
signal WriteCode: std_logic_vector(7 downto 0) := (others =>'0'); -- What to Write |
178 |
signal WriteByte: boolean := false; -- Init Write Byte Sequence |
178 |
signal WriteByte: boolean := false; -- Init Write Byte Sequence |
179 |
signal SendingData: boolean := false; -- Block Receiver when Sending Data |
179 |
signal SendingData: boolean := false; -- Block Receiver when Sending Data |
180 |
signal WriteByte_ack: boolean := false; -- Ack Writen Byte |
180 |
signal WriteByte_ack: boolean := false; -- Ack Writen Byte |
181 |
|
181 |
|
182 |
signal WriteReg: std_logic_vector(7 downto 0) := (others =>'0'); -- Transmit Shift Register |
182 |
signal WriteReg: std_logic_vector(7 downto 0) := (others =>'0'); -- Transmit Shift Register |
183 |
signal ParityBit: std_logic := '0'; -- Parity Bit |
183 |
signal ParityBit: std_logic := '0'; -- Parity Bit |
184 |
signal StartTime: unsigned(31 downto 0) := (others =>'0'); -- Timer for Start of Write (PS2_Clk low) |
184 |
signal StartTime: unsigned(31 downto 0) := (others =>'0'); -- Timer for Start of Write (PS2_Clk low) |
185 |
signal WriteBits: unsigned(3 downto 0) := (others =>'0'); -- Bit Counter |
185 |
signal WriteBits: unsigned(3 downto 0) := (others =>'0'); -- Bit Counter |
186 |
|
186 |
|
187 |
-- Update LED Indicators |
187 |
-- Update LED Indicators |
188 |
type UpdState_t is ( -- Update Led Indicators FSM State Type |
188 |
type UpdState_t is ( -- Update Led Indicators FSM State Type |
189 |
Idle, -- Inactive State |
189 |
Idle, -- Inactive State |
190 |
SendReset, -- For Debug - Reset Keyboard |
190 |
SendReset, -- For Debug - Reset Keyboard |
191 |
SendLed1, -- Send FD |
191 |
SendLed1, -- Send FD |
192 |
SendLed2, -- Send New LED State |
192 |
SendLed2, -- Send New LED State |
193 |
SendFinal -- |
193 |
SendFinal -- |
194 |
); |
194 |
); |
195 |
signal UpdState: UpdState_t := Idle; -- Update Led Indicators FSM State |
195 |
signal UpdState: UpdState_t := Idle; -- Update Led Indicators FSM State |
196 |
signal UpdateLed: boolean := false; -- Send new LED State to the Keyboard |
196 |
signal UpdateLed: boolean := false; -- Send new LED State to the Keyboard |
197 |
signal UpdateLed_ack: boolean := false; -- Ack (1 clock pulse) |
197 |
signal UpdateLed_ack: boolean := false; -- Ack (1 clock pulse) |
198 |
|
198 |
|
199 |
begin |
199 |
begin |
200 |
|
200 |
|
201 |
-- Sync External Signals with Clock |
201 |
-- Sync External Signals with Clock |
202 |
process (Clk) |
202 |
process (Clk) |
203 |
begin |
203 |
begin |
204 |
if rising_edge(Clk) then |
204 |
if rising_edge(Clk) then |
205 |
-- Sync |
205 |
-- Sync |
206 |
PS2_Clk_d <= PS2_Clk; |
206 |
PS2_Clk_d <= PS2_Clk; |
207 |
PS2_Data_d <= PS2_Data; |
207 |
PS2_Data_d <= PS2_Data; |
208 |
-- For Falling Edge Detection |
208 |
-- For Falling Edge Detection |
209 |
PS2_Clk_dd <= PS2_Clk_d; |
209 |
PS2_Clk_dd <= PS2_Clk_d; |
210 |
end if; |
210 |
end if; |
211 |
end process; |
211 |
end process; |
212 |
|
212 |
|
213 |
-- Level 0 - Read Byte from PS/2 Interface |
213 |
-- Level 0 - Read Byte from PS/2 Interface |
214 |
process (Clk) |
214 |
process (Clk) |
215 |
begin |
215 |
begin |
216 |
if rising_edge(Clk) then |
216 |
if rising_edge(Clk) then |
217 |
ReadByte_rdy <= false; |
217 |
ReadByte_rdy <= false; |
218 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' and not SendingData then |
218 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' and not SendingData then |
219 |
-- Falling Edge of PS2_Clk |
219 |
-- Falling Edge of PS2_Clk |
220 |
case ReadByteState is |
220 |
case ReadByteState is |
221 |
when Idle => |
221 |
when Idle => |
222 |
-- Test Start Bit |
222 |
-- Test Start Bit |
223 |
if PS2_Data='0' then |
223 |
if PS2_Data='0' then |
224 |
ReadByteState <= D0; |
224 |
ReadByteState <= D0; |
225 |
end if; |
225 |
end if; |
226 |
when D0 => |
226 |
when D0 => |
227 |
-- Bit 0 |
227 |
-- Bit 0 |
228 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
228 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
229 |
ReadByteState <= D1; |
229 |
ReadByteState <= D1; |
230 |
when D1 => |
230 |
when D1 => |
231 |
-- Bit 1 |
231 |
-- Bit 1 |
232 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
232 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
233 |
ReadByteState <= D2; |
233 |
ReadByteState <= D2; |
234 |
when D2 => |
234 |
when D2 => |
235 |
-- Bit 2 |
235 |
-- Bit 2 |
236 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
236 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
237 |
ReadByteState <= D3; |
237 |
ReadByteState <= D3; |
238 |
when D3 => |
238 |
when D3 => |
239 |
-- Bit 3 |
239 |
-- Bit 3 |
240 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
240 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
241 |
ReadByteState <= D4; |
241 |
ReadByteState <= D4; |
242 |
when D4 => |
242 |
when D4 => |
243 |
-- Bit 4 |
243 |
-- Bit 4 |
244 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
244 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
245 |
ReadByteState <= D5; |
245 |
ReadByteState <= D5; |
246 |
when D5 => |
246 |
when D5 => |
247 |
-- Bit 5 |
247 |
-- Bit 5 |
248 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
248 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
249 |
ReadByteState <= D6; |
249 |
ReadByteState <= D6; |
250 |
when D6 => |
250 |
when D6 => |
251 |
-- Bit 6 |
251 |
-- Bit 6 |
252 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
252 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
253 |
ReadByteState <= D7; |
253 |
ReadByteState <= D7; |
254 |
when D7 => |
254 |
when D7 => |
255 |
-- Bit 7 |
255 |
-- Bit 7 |
256 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
256 |
ReadByte <= PS2_Data & ReadByte(7 downto 1); |
257 |
ReadByteState <= Parity; |
257 |
ReadByteState <= Parity; |
258 |
when Parity => |
258 |
when Parity => |
259 |
-- Check Parity Here... |
259 |
-- Check Parity Here... |
260 |
ReadByteState <= Final; |
260 |
ReadByteState <= Final; |
261 |
when Final => |
261 |
when Final => |
262 |
-- End of Byte |
262 |
-- End of Byte |
263 |
ReadByteState <= Idle; |
263 |
ReadByteState <= Idle; |
264 |
ReadByte_rdy <= true; -- Scan Code Ready (8 bit word) |
264 |
ReadByte_rdy <= true; -- Scan Code Ready (8 bit word) |
265 |
end case; |
265 |
end case; |
266 |
end if; |
266 |
end if; |
267 |
end if; |
267 |
end if; |
268 |
end process; |
268 |
end process; |
269 |
|
269 |
|
270 |
-- Level 1 - Process Raw Scan Codes and ESC Atributes E0, E1 and F0 |
270 |
-- Level 1 - Process Raw Scan Codes and ESC Atributes E0, E1 and F0 |
271 |
process (Clk) |
271 |
process (Clk) |
272 |
begin |
272 |
begin |
273 |
if rising_edge(Clk) then |
273 |
if rising_edge(Clk) then |
274 |
if Level1_rdy then |
274 |
if Level1_rdy then |
275 |
-- Clean State when Sent Data from Level1 processing |
275 |
-- Clean State when Sent Data from Level1 processing |
276 |
Level1_rdy <= false; |
276 |
Level1_rdy <= false; |
277 |
FlagE0 <= false; |
277 |
FlagE0 <= false; |
278 |
FlagE1 <= false; |
278 |
FlagE1 <= false; |
279 |
FlagF0 <= false; |
279 |
FlagF0 <= false; |
280 |
else |
280 |
else |
281 |
if ReadByte_rdy then |
281 |
if ReadByte_rdy then |
282 |
-- Process Scan Code Byte from Level 0 |
282 |
-- Process Scan Code Byte from Level 0 |
283 |
if ReadByte=X"E0" then |
283 |
if ReadByte=X"E0" then |
284 |
-- Ext Code |
284 |
-- Ext Code |
285 |
FlagE0 <= true; |
285 |
FlagE0 <= true; |
286 |
elsif ReadByte=X"E1" then |
286 |
elsif ReadByte=X"E1" then |
287 |
-- Special Ext Code |
287 |
-- Special Ext Code |
288 |
FlagE1 <= true; |
288 |
FlagE1 <= true; |
289 |
elsif ReadByte=X"F0" then |
289 |
elsif ReadByte=X"F0" then |
290 |
-- Break Flag |
290 |
-- Break Flag |
291 |
FlagF0 <= true; |
291 |
FlagF0 <= true; |
292 |
else |
292 |
else |
293 |
-- Scan Code |
293 |
-- Scan Code |
294 |
Level1_rdy <= true; |
294 |
Level1_rdy <= true; |
295 |
end if; |
295 |
end if; |
296 |
end if; |
296 |
end if; |
297 |
end if; |
297 |
end if; |
298 |
end if; |
298 |
end if; |
299 |
end process; |
299 |
end process; |
300 |
|
300 |
|
301 |
-- Level 2 - Process Shift (left and right shift, alt and ctrl) and Num Lock (numeric virtual shift) |
301 |
-- Level 2 - Process Shift (left and right shift, alt and ctrl) and Num Lock (numeric virtual shift) |
302 |
process (Clk) |
302 |
process (Clk) |
303 |
begin |
303 |
begin |
304 |
if rising_edge(Clk) then |
304 |
if rising_edge(Clk) then |
305 |
-- Clear Comands to Higher Level |
305 |
-- Clear Comands to Higher Level |
306 |
UpdateLed <= false; |
306 |
UpdateLed <= false; |
307 |
Level2a_rdy <= false; |
307 |
Level2a_rdy <= false; |
308 |
Level2_rdy <= false; |
308 |
Level2_rdy <= false; |
309 |
-- Process Read Byte |
309 |
-- Process Read Byte |
310 |
if Level1_rdy then |
310 |
if Level1_rdy then |
311 |
if ReadByte=X"11" then |
311 |
if ReadByte=X"11" then |
312 |
-- Alt Key |
312 |
-- Alt Key |
313 |
if FlagE0 then |
313 |
if FlagE0 then |
314 |
FlagAltR <= not FlagF0; |
314 |
FlagAltR <= not FlagF0; |
315 |
else |
315 |
else |
316 |
FlagAltL <= not FlagF0; |
316 |
FlagAltL <= not FlagF0; |
317 |
end if; |
317 |
end if; |
318 |
elsif ReadByte=X"12" then |
318 |
elsif ReadByte=X"12" then |
319 |
-- Left Shift |
319 |
-- Left Shift |
320 |
if FlagE0 then |
320 |
if FlagE0 then |
321 |
FlagShiftNum <= not FlagF0; |
321 |
FlagShiftNum <= not FlagF0; |
322 |
else |
322 |
else |
323 |
FlagShiftL <= not FlagF0; |
323 |
FlagShiftL <= not FlagF0; |
324 |
end if; |
324 |
end if; |
325 |
elsif ReadByte=X"59" then |
325 |
elsif ReadByte=X"59" then |
326 |
-- Right Shift |
326 |
-- Right Shift |
327 |
FlagShiftR <= not FlagF0; |
327 |
FlagShiftR <= not FlagF0; |
328 |
elsif ReadByte=X"14" then |
328 |
elsif ReadByte=X"14" then |
329 |
-- Ctrl |
329 |
-- Ctrl |
330 |
if FlagE0 then |
330 |
if FlagE0 then |
331 |
FlagCtrlR <= not FlagF0; |
331 |
FlagCtrlR <= not FlagF0; |
332 |
else |
332 |
else |
333 |
FlagCtrlL <= not FlagF0; |
333 |
FlagCtrlL <= not FlagF0; |
334 |
end if; |
334 |
end if; |
335 |
elsif ReadByte=X"77" and not FlagCtrlL and not FlagCtrlR and not FlagAltL and not FlagAltR then |
335 |
elsif ReadByte=X"77" and not FlagCtrlL and not FlagCtrlR and not FlagAltL and not FlagAltR then |
336 |
-- Num Lock On/Off |
336 |
-- Num Lock On/Off |
337 |
if not FlagF0 then |
337 |
if not FlagF0 then |
338 |
FlagNumLock <= not FlagNumLock; |
338 |
FlagNumLock <= not FlagNumLock; |
339 |
UpdateLed <= true; -- Set UpdateLed Request |
339 |
UpdateLed <= true; -- Set UpdateLed Request |
340 |
end if; |
340 |
end if; |
341 |
elsif ReadByte=X"58" then |
341 |
elsif ReadByte=X"58" then |
342 |
-- Caps Lock |
342 |
-- Caps Lock |
343 |
if not FlagF0 then |
343 |
if not FlagF0 then |
344 |
FlagCapsLock <= not FlagCapsLock; |
344 |
FlagCapsLock <= not FlagCapsLock; |
345 |
UpdateLed <= true; -- Set UpdateLed Request |
345 |
UpdateLed <= true; -- Set UpdateLed Request |
346 |
end if; |
346 |
end if; |
347 |
elsif ReadByte=X"7E" then |
347 |
elsif ReadByte=X"7E" then |
348 |
if not FlagF0 then |
348 |
if not FlagF0 then |
349 |
FlagScrollLock <= not FlagScrollLock; |
349 |
FlagScrollLock <= not FlagScrollLock; |
350 |
UpdateLed <= true; -- Set UpdateLed Request |
350 |
UpdateLed <= true; -- Set UpdateLed Request |
351 |
end if; |
351 |
end if; |
352 |
else |
352 |
else |
353 |
-- Send Data to the next Level |
353 |
-- Send Data to the next Level |
354 |
FlagExt0 <= FlagE0; |
354 |
FlagExt0 <= FlagE0; |
355 |
FlagExt1 <= FlagE1; |
355 |
FlagExt1 <= FlagE1; |
356 |
FlagBreak <= FlagF0; |
356 |
FlagBreak <= FlagF0; |
357 |
if WriteByteState=WaitAckByte then |
357 |
if WriteByteState=WaitAckByte then |
358 |
-- Send Data (Ack Byte) to WriteByte |
358 |
-- Send Data (Ack Byte) to WriteByte |
359 |
Level2a_rdy <= true; |
359 |
Level2a_rdy <= true; |
360 |
else |
360 |
else |
361 |
-- Send Scan Code to the next Level |
361 |
-- Send Scan Code to the next Level |
362 |
Level2_rdy <= true; |
362 |
Level2_rdy <= true; |
363 |
end if; |
363 |
end if; |
364 |
end if; |
364 |
end if; |
365 |
end if; |
365 |
end if; |
366 |
end if; |
366 |
end if; |
367 |
end process; |
367 |
end process; |
368 |
|
368 |
|
369 |
-- Send Data |
369 |
-- Send Data |
370 |
PS2_Valid <= Level2_rdy; |
370 |
PS2_Valid <= Level2_rdy; |
371 |
|
371 |
|
372 |
-- Scan COde |
372 |
-- Scan COde |
373 |
PS2_Code(7 downto 0) <= ReadByte; |
373 |
PS2_Code(7 downto 0) <= ReadByte; |
374 |
|
374 |
|
375 |
-- Attribs |
375 |
-- Attribs |
376 |
PS2_Attribs(0) <= '1' when FlagShiftL or FlagShiftR else '0'; -- Bit 0 - Shift |
376 |
PS2_Attribs(0) <= '1' when FlagShiftL or FlagShiftR else '0'; -- Bit 0 - Shift |
377 |
PS2_Attribs(1) <= '1' when FlagCtrlL or FlagCtrlR else '0'; -- Bit 1 - Ctrl |
377 |
PS2_Attribs(1) <= '1' when FlagCtrlL or FlagCtrlR else '0'; -- Bit 1 - Ctrl |
378 |
PS2_Attribs(2) <= '1' when FlagAltL or FlagAltR else '0'; -- Bit 2 - Alt |
378 |
PS2_Attribs(2) <= '1' when FlagAltL or FlagAltR else '0'; -- Bit 2 - Alt |
379 |
PS2_Attribs(3) <= '1' when FlagExt0 else '0'; -- Bit 3 - Ext Code E0 |
379 |
PS2_Attribs(3) <= '1' when FlagExt0 else '0'; -- Bit 3 - Ext Code E0 |
380 |
PS2_Attribs(4) <= '1' when FlagExt1 else '0'; -- Bit 4 - Ext Code E1 |
380 |
PS2_Attribs(4) <= '1' when FlagExt1 else '0'; -- Bit 4 - Ext Code E1 |
381 |
PS2_Attribs(5) <= '1' when FlagShiftNum else '0'; -- Bit 5 - Shift Num (Arrows,...) - only if NumLock Led is Off |
381 |
PS2_Attribs(5) <= '1' when FlagShiftNum else '0'; -- Bit 5 - Shift Num (Arrows,...) - only if NumLock Led is Off |
382 |
PS2_Attribs(6) <= '0'; |
382 |
PS2_Attribs(6) <= '0'; |
383 |
PS2_Attribs(7) <= '1' when FlagBreak else '0'; -- Bit 7 - Break (release) Key |
383 |
PS2_Attribs(7) <= '1' when FlagBreak else '0'; -- Bit 7 - Break (release) Key |
384 |
|
384 |
|
385 |
-- Immediate State of Shift Like Keys |
385 |
-- Immediate State of Shift Like Keys |
386 |
PS2_Shifts(0) <= '1' when FlagShiftL else '0'; -- Bit 0 - Shift Left |
386 |
PS2_Shifts(0) <= '1' when FlagShiftL else '0'; -- Bit 0 - Shift Left |
387 |
PS2_Shifts(1) <= '1' when FlagShiftR else '0'; -- Bit 1 - Shift Right |
387 |
PS2_Shifts(1) <= '1' when FlagShiftR else '0'; -- Bit 1 - Shift Right |
388 |
PS2_Shifts(2) <= '1' when FlagCtrlL else '0'; -- Bit 2 - Ctrl Left |
388 |
PS2_Shifts(2) <= '1' when FlagCtrlL else '0'; -- Bit 2 - Ctrl Left |
389 |
PS2_Shifts(3) <= '1' when FlagCtrlR else '0'; -- Bit 3 - Ctrl Right |
389 |
PS2_Shifts(3) <= '1' when FlagCtrlR else '0'; -- Bit 3 - Ctrl Right |
390 |
PS2_Shifts(4) <= '1' when FlagAltL else '0'; -- Bit 4 - Alt Left |
390 |
PS2_Shifts(4) <= '1' when FlagAltL else '0'; -- Bit 4 - Alt Left |
391 |
PS2_Shifts(5) <= '1' when FlagAltR else '0'; -- Bit 5 - Alt Right |
391 |
PS2_Shifts(5) <= '1' when FlagAltR else '0'; -- Bit 5 - Alt Right |
392 |
PS2_Shifts(6) <= '1' when FlagNumLock else '0'; -- Bit 7 - Num Lock |
392 |
PS2_Shifts(6) <= '1' when FlagNumLock else '0'; -- Bit 7 - Num Lock |
393 |
PS2_Shifts(7) <= '1' when FlagCapsLock else '0'; -- Bit 8 - Caps Lock |
393 |
PS2_Shifts(7) <= '1' when FlagCapsLock else '0'; -- Bit 8 - Caps Lock |
394 |
PS2_Shifts(8) <= '1' when FlagScrollLock else '0'; -- Bit 9 - Scroll Lock |
394 |
PS2_Shifts(8) <= '1' when FlagScrollLock else '0'; -- Bit 9 - Scroll Lock |
395 |
PS2_Shifts(9) <= '1' when FlagShiftNum else '0'; -- Bit 6 - Shift Num (virtual state) - Not to be used |
395 |
PS2_Shifts(9) <= '1' when FlagShiftNum else '0'; -- Bit 6 - Shift Num (virtual state) - Not to be used |
396 |
|
396 |
|
397 |
-- Write Byte to PS/2 Interface |
397 |
-- Write Byte to PS/2 Interface |
398 |
-- Init By: WriteByte |
398 |
-- Init By: WriteByte |
399 |
-- Finish Indication: WriteByte_ack |
399 |
-- Finish Indication: WriteByte_ack |
400 |
process (Clk) |
400 |
process (Clk) |
401 |
begin |
401 |
begin |
402 |
if rising_edge(Clk) then |
402 |
if rising_edge(Clk) then |
403 |
WriteByte_ack <= false; |
403 |
WriteByte_ack <= false; |
404 |
case WriteByteState is |
404 |
case WriteByteState is |
405 |
when Idle => |
405 |
when Idle => |
406 |
PS2_Clk <= 'Z'; |
406 |
PS2_Clk <= 'Z'; |
407 |
PS2_Data <= 'Z'; |
407 |
PS2_Data <= 'Z'; |
408 |
if WriteByte then |
408 |
if WriteByte then |
409 |
WriteByteState <= WriteStart; |
409 |
WriteByteState <= WriteStart; |
410 |
WriteReg <= WriteCode; |
410 |
WriteReg <= WriteCode; |
411 |
end if; |
411 |
end if; |
412 |
when WriteStart => |
412 |
when WriteStart => |
413 |
if PS2_Data_d='1' and PS2_Clk_d='1' then |
413 |
if PS2_Data_d='1' and PS2_Clk_d='1' then |
414 |
-- PS2 Interface in Idle State |
414 |
-- PS2 Interface in Idle State |
415 |
PS2_Clk <= '0'; -- Start of Write (PS2_Clk=L) |
415 |
PS2_Clk <= '0'; -- Start of Write (PS2_Clk=L) |
416 |
StartTime <= to_unsigned(CLKFREQ/16000, StartTime'length); -- cca 60us Start |
416 |
StartTime <= to_unsigned(CLKFREQ/16000, StartTime'length); -- cca 60us Start |
417 |
WriteBits <= to_unsigned(7, WriteBits'length); -- 8 bits |
417 |
WriteBits <= to_unsigned(7, WriteBits'length); -- 8 bits |
418 |
WriteByteState <= WaitStart; |
418 |
WriteByteState <= WaitStart; |
419 |
SendingData <= true; |
419 |
SendingData <= true; |
420 |
end if; |
420 |
end if; |
421 |
when WaitStart => |
421 |
when WaitStart => |
422 |
if StartTime>0 then |
422 |
if StartTime>0 then |
423 |
StartTime <= StartTime - 1; |
423 |
StartTime <= StartTime - 1; |
424 |
else |
424 |
else |
425 |
PS2_Data <= '0'; -- Start Bit |
425 |
PS2_Data <= '0'; -- Start Bit |
426 |
PS2_Clk <= 'Z'; -- Release Clk |
426 |
PS2_Clk <= 'Z'; -- Release Clk |
427 |
ParityBit <= '1'; -- Init Parity Generator (code 1111_1111 has parity 1) |
427 |
ParityBit <= '1'; -- Init Parity Generator (code 1111_1111 has parity 1) |
428 |
WriteByteState <= SendBits; |
428 |
WriteByteState <= SendBits; |
429 |
end if; |
429 |
end if; |
430 |
when SendBits => |
430 |
when SendBits => |
431 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
431 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
432 |
PS2_Data <= WriteReg(0); |
432 |
PS2_Data <= WriteReg(0); |
433 |
ParityBit <= ParityBit xor WriteReg(0); |
433 |
ParityBit <= ParityBit xor WriteReg(0); |
434 |
WriteReg <= '1' & WriteReg(7 downto 1); |
434 |
WriteReg <= '1' & WriteReg(7 downto 1); |
435 |
if WriteBits>0 then |
435 |
if WriteBits>0 then |
436 |
WriteBits <= WriteBits - 1; |
436 |
WriteBits <= WriteBits - 1; |
437 |
else |
437 |
else |
438 |
WriteByteState <= WriteParity; |
438 |
WriteByteState <= WriteParity; |
439 |
end if; |
439 |
end if; |
440 |
end if; |
440 |
end if; |
441 |
when WriteParity => |
441 |
when WriteParity => |
442 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
442 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
443 |
PS2_Data <= ParityBit; |
443 |
PS2_Data <= ParityBit; |
444 |
WriteByteState <= WriteStop; |
444 |
WriteByteState <= WriteStop; |
445 |
end if; |
445 |
end if; |
446 |
when WriteStop => |
446 |
when WriteStop => |
447 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
447 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
448 |
PS2_Data <= '1'; |
448 |
PS2_Data <= '1'; |
449 |
WriteByteState <= AckBit; |
449 |
WriteByteState <= AckBit; |
450 |
end if; |
450 |
end if; |
451 |
when AckBit => |
451 |
when AckBit => |
452 |
PS2_Data <= 'Z'; |
452 |
PS2_Data <= 'Z'; |
453 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
453 |
if PS2_Clk_dd='1' and PS2_Clk_d='0' then |
454 |
WriteByteState <= Final; |
454 |
WriteByteState <= Final; |
455 |
end if; |
455 |
end if; |
456 |
when Final => |
456 |
when Final => |
457 |
if PS2_Clk_d='1' then |
457 |
if PS2_Clk_d='1' then |
458 |
WriteByteState <= WaitAckByte; |
458 |
WriteByteState <= WaitAckByte; |
459 |
SendingData <= false; |
459 |
SendingData <= false; |
460 |
end if; |
460 |
end if; |
461 |
when WaitAckByte => |
461 |
when WaitAckByte => |
462 |
if Level2a_rdy then |
462 |
if Level2a_rdy then |
463 |
WriteByteState <= Idle; |
463 |
WriteByteState <= Idle; |
464 |
WriteByte_ack <= true; |
464 |
WriteByte_ack <= true; |
465 |
end if; |
465 |
end if; |
466 |
end case; |
466 |
end case; |
467 |
end if; |
467 |
end if; |
468 |
end process; |
468 |
end process; |
469 |
|
469 |
|
470 |
-- Level 3 - Update LED Indicators |
470 |
-- Level 3 - Update LED Indicators |
471 |
-- Init By: UpdateLed or Level2_rdy(with scan code and attrib) |
471 |
-- Init By: UpdateLed or Level2_rdy(with scan code and attrib) |
472 |
-- Finish Indication: UpdateLed_ack (not used) |
472 |
-- Finish Indication: UpdateLed_ack (not used) |
473 |
process (Clk) |
473 |
process (Clk) |
474 |
begin |
474 |
begin |
475 |
if rising_edge(Clk) then |
475 |
if rising_edge(Clk) then |
476 |
UpdateLed_ack <= false; -- 1 Clock Pulse |
476 |
UpdateLed_ack <= false; -- 1 Clock Pulse |
477 |
WriteByte <= false; |
477 |
WriteByte <= false; |
478 |
case UpdState is |
478 |
case UpdState is |
479 |
when Idle => |
479 |
when Idle => |
480 |
-- Register the request |
480 |
-- Register the request |
481 |
if Level2_rdy and ReadByte=X"07" and not FlagBreak then |
481 |
if Level2_rdy and ReadByte=X"07" and not FlagBreak then |
482 |
WriteCode <= X"FF"; |
482 |
WriteCode <= X"FF"; |
483 |
WriteByte <= true; |
483 |
WriteByte <= true; |
484 |
elsif UpdateLed then |
484 |
elsif UpdateLed then |
485 |
UpdateLed_ack <= true; |
485 |
UpdateLed_ack <= true; |
486 |
UpdState <= SendLed1; |
486 |
UpdState <= SendLed1; |
487 |
end if; |
487 |
end if; |
488 |
when SendReset => |
488 |
when SendReset => |
489 |
if WriteByteState=Idle then |
489 |
if WriteByteState=Idle then |
490 |
-- Send Keyborad Reset |
490 |
-- Send Keyborad Reset |
491 |
WriteCode <= X"FF"; |
491 |
WriteCode <= X"FF"; |
492 |
WriteByte <= true; |
492 |
WriteByte <= true; |
493 |
UpdState <= SendFinal; |
493 |
UpdState <= SendFinal; |
494 |
end if; |
494 |
end if; |
495 |
when SendLed1 => |
495 |
when SendLed1 => |
496 |
if WriteByteState=Idle then |
496 |
if WriteByteState=Idle then |
497 |
-- Send LED Command |
497 |
-- Send LED Command |
498 |
WriteCode <= X"ED"; |
498 |
WriteCode <= X"ED"; |
499 |
WriteByte <= true; |
499 |
WriteByte <= true; |
500 |
UpdState <= SendLed2; |
500 |
UpdState <= SendLed2; |
501 |
end if; |
501 |
end if; |
502 |
when SendLed2 => |
502 |
when SendLed2 => |
503 |
if WriteByte_ack then |
503 |
if WriteByte_ack then |
504 |
-- Send LED State |
504 |
-- Send LED State |
505 |
WriteCode <= "00000" & to_std_logic(FlagCapsLock) |
505 |
WriteCode <= "00000" & to_std_logic(FlagCapsLock) |
506 |
& to_std_logic(FlagNumLock) |
506 |
& to_std_logic(FlagNumLock) |
507 |
& to_std_logic(FlagScrollLock); |
507 |
& to_std_logic(FlagScrollLock); |
508 |
WriteByte <= true; |
508 |
WriteByte <= true; |
509 |
UpdState <= SendFinal; |
509 |
UpdState <= SendFinal; |
510 |
end if; |
510 |
end if; |
511 |
when SendFinal => |
511 |
when SendFinal => |
512 |
if WriteByte_ack then ---WriteByteState=Idle then |
512 |
if WriteByte_ack then ---WriteByteState=Idle then |
513 |
-- Last Data has been Send |
513 |
-- Last Data has been Send |
514 |
UpdState <= Idle; |
514 |
UpdState <= Idle; |
515 |
end if; |
515 |
end if; |
516 |
end case; |
516 |
end case; |
517 |
end if; |
517 |
end if; |
518 |
end process; |
518 |
end process; |
519 |
|
519 |
|
520 |
end architecture PS2_a; |
520 |
end architecture PS2_a; |