| 1 |
Ø H¯< éÙ, ..\..\..\os\kernel\include\ch.h ¨Ö RÙ ..\chconf.h ¯ëí +Ù4 (..\..\..\os\ports\RVCT\ARMCMx\chtypes.h ¤¨Ö ¨ÙD 8C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stddef.h Àç SÙD 8C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stdint.h Àç 7ÙE 9C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stdbool.h Àç ÔÙ1 %..\..\..\os\kernel\include\chlists.h ¨Ö Ù3 '..\..\..\os\ports\RVCT\ARMCMx\chcore.h ¤¨Ö 6Ù? 3..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx\cmparams.h ¤¨Ö Ù7 +..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h ¤¨Ö µÙ3 '..\..\..\os\ports\common\ARMCMx\nvic.h ¨Ö ´Ù/ #..\..\..\os\kernel\include\chsys.h ¨Ö íÙ. "..\..\..\os\kernel\include\chvt.h ¨Ö dÙ0 $..\..\..\os\kernel\include\chschd.h ¨Ö ¨Ù/ #..\..\..\os\kernel\include\chsem.h ¨Ö Ù0 $..\..\..\os\kernel\include\chbsem.h ¨Ö £Ù/ #..\..\..\os\kernel\include\chmtx.h ¨Ö óÙ0 $..\..\..\os\kernel\include\chcond.h ¨Ö ¦Ù2 &..\..\..\os\kernel\include\chevents.h ¨Ö ±Ù/ #..\..\..\os\kernel\include\chmsg.h ¨Ö Ù2 &..\..\..\os\kernel\include\chmboxes.h ¨Ö ¸Ù3 '..\..\..\os\kernel\include\chmemcore.h ¨Ö \Ù0 $..\..\..\os\kernel\include\chheap.h ¨Ö ¬Ù4 (..\..\..\os\kernel\include\chmempools.h ¨Ö ÖÙ3 '..\..\..\os\kernel\include\chthreads.h ¨Ö YÙ3 '..\..\..\os\kernel\include\chdynamic.h ¨Ö _Ù4 (..\..\..\os\kernel\include\chregistry.h ¨Ö ÉÙ2 &..\..\..\os\kernel\include\chinline.h ¨Ö ÇÙ2 &..\..\..\os\kernel\include\chqueues.h ¨Ö ®Ù3 '..\..\..\os\kernel\include\chstreams.h ¨Ö EÙ1 %..\..\..\os\kernel\include\chfiles.h ¨Ö 5Ù1 %..\..\..\os\kernel\include\chdebug.h ¨Ö AÙ* ..\..\..\os\hal\include\hal.h ¨Ö 7Ù8 ,..\..\..\boards\ST_STM32L_DISCOVERY\board.h 嬅 6Ù
..\halconf.h Ù
..\mcuconf.h ~Ù: ...\..\..\os\hal\platforms\STM32L1xx\hal_lld.h ¨Ö dÙ4 (..\..\..\os\hal\platforms\STM32\stm32.h ¨Ö ïÙ< 0..\..\..\os\hal\platforms\STM32L1xx\stm32l1xx.h ¨Ö êÙE 9..\..\..\os\ports\common\ARMCMx\CMSIS\include\core_cm3.h ¨Ö ÙI =..\..\..\os\ports\common\ARMCMx\CMSIS\include\core_cmInstr.h ¨Ö 5ÙH <..\..\..\os\ports\common\ARMCMx\CMSIS\include\core_cmFunc.h ¨Ö »Ù< 0..\..\..\os\hal\platforms\STM32L1xx\stm32_isr.h ¨Ö ÊÙ< 0..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.h ¨Ö æÙ< 0..\..\..\os\hal\platforms\STM32L1xx\stm32_rcc.h ¨Ö àÙ1 %..\..\..\os\hal\include\io_channel.h ¨Ö NÙ/ #..\..\..\os\hal\include\io_block.h ¨Ö Ù, ..\..\..\os\hal\include\mmcsd.h ¨Ö TÙ) ..\..\..\os\hal\include\tm.h ¨Ö Ù* ..\..\..\os\hal\include\pal.h ¨Ö /Ù= 1..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h ¨Ö Ù* ..\..\..\os\hal\include\adc.h ¨Ö DÙ: ...\..\..\os\hal\platforms\STM32L1xx\adc_lld.h ¨Ö qÙ* ..\..\..\os\hal\include\can.h ¨Ö :Ù* ..\..\..\os\hal\include\ext.h ¨Ö Ù* ..\..\..\os\hal\include\gpt.h ¨Ö !Ù6 *..\..\..\os\hal\platforms\STM32\gpt_lld.h ñ ¶Ù* ..\..\..\os\hal\include\i2c.h ¨Ö nÙ* ..\..\..\os\hal\include\icu.h ¨Ö +Ù* ..\..\..\os\hal\include\mac.h ¨Ö ;Ù* ..\..\..\os\hal\include\pwm.h ¨Ö Ù6 *..\..\..\os\hal\platforms\STM32\pwm_lld.h ¨Ö µÙ* ..\..\..\os\hal\include\rtc.h ¨Ö #Ù- !..\..\..\os\hal\include\serial.h ¨Ö æÙA 5..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h ªã åÙ* ..\..\..\os\hal\include\sdc.h ¨Ö 2Ù* ..\..\..\os\hal\include\spi.h ¨Ö Ù+ ..\..\..\os\hal\include\uart.h ¨Ö ®Ù* ..\..\..\os\hal\include\usb.h ¨Ö "Ù. "..\..\..\os\hal\include\mmc_spi.h ¨Ö |Ù1 %..\..\..\os\hal\include\serial_usb.h ¨Ö 5Ù& ..\..\..\os\hal\src\hal.c ¨Ö ÙÚ P _CH_H_ ÏÚ P
_CHIBIOS_RT_ ïÚ P CH_KERNEL_VERSION yÚ P CH_KERNEL_MAJOR *Ú P CH_KERNEL_MINOR Ú P CH_KERNEL_PATCH 3Ú P FALSE VÚ
P TRUE Ú P CH_SUCCESS ´Ú P |
1 |
Ø F: Ù, ..\..\..\os\kernel\include\ch.h ¨Ö RÙ ..\chconf.h ¯ëí +Ù4 (..\..\..\os\ports\RVCT\ARMCMx\chtypes.h ¤¨Ö ¨ÙD 8C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stddef.h Àç SÙD 8C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stdint.h Àç 7ÙE 9C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stdbool.h Àç ÔÙ1 %..\..\..\os\kernel\include\chlists.h ¨Ö Ù3 '..\..\..\os\ports\RVCT\ARMCMx\chcore.h ¤¨Ö 6Ù? 3..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx\cmparams.h ¤¨Ö Ù7 +..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h ¤¨Ö µÙ3 '..\..\..\os\ports\common\ARMCMx\nvic.h ¨Ö ´Ù/ #..\..\..\os\kernel\include\chsys.h ¨Ö íÙ. "..\..\..\os\kernel\include\chvt.h ¨Ö dÙ0 $..\..\..\os\kernel\include\chschd.h ¨Ö ¨Ù/ #..\..\..\os\kernel\include\chsem.h ¨Ö Ù0 $..\..\..\os\kernel\include\chbsem.h ¨Ö £Ù/ #..\..\..\os\kernel\include\chmtx.h ¨Ö óÙ0 $..\..\..\os\kernel\include\chcond.h ¨Ö ¦Ù2 &..\..\..\os\kernel\include\chevents.h ¨Ö ±Ù/ #..\..\..\os\kernel\include\chmsg.h ¨Ö Ù2 &..\..\..\os\kernel\include\chmboxes.h ¨Ö ¸Ù3 '..\..\..\os\kernel\include\chmemcore.h ¨Ö \Ù0 $..\..\..\os\kernel\include\chheap.h ¨Ö ¬Ù4 (..\..\..\os\kernel\include\chmempools.h ¨Ö ÖÙ3 '..\..\..\os\kernel\include\chthreads.h ¨Ö YÙ3 '..\..\..\os\kernel\include\chdynamic.h ¨Ö _Ù4 (..\..\..\os\kernel\include\chregistry.h ¨Ö ÉÙ2 &..\..\..\os\kernel\include\chinline.h ¨Ö ÇÙ2 &..\..\..\os\kernel\include\chqueues.h ¨Ö ®Ù3 '..\..\..\os\kernel\include\chstreams.h ¨Ö EÙ1 %..\..\..\os\kernel\include\chfiles.h ¨Ö 5Ù1 %..\..\..\os\kernel\include\chdebug.h ¨Ö AÙ* ..\..\..\os\hal\include\hal.h ¨Ö 7Ù8 ,..\..\..\boards\ST_STM32L_DISCOVERY\board.h 嬅 6Ù
..\halconf.h Ŧ¥ 5Ù
..\mcuconf.h ॠ$Ù: ...\..\..\os\hal\platforms\STM32L1xx\hal_lld.h ¨Ö dÙ4 (..\..\..\os\hal\platforms\STM32\stm32.h ¨Ö ïÙ< 0..\..\..\os\hal\platforms\STM32L1xx\stm32l1xx.h ¨Ö êÙE 9..\..\..\os\ports\common\ARMCMx\CMSIS\include\core_cm3.h ¨Ö ÙI =..\..\..\os\ports\common\ARMCMx\CMSIS\include\core_cmInstr.h ¨Ö 5ÙH <..\..\..\os\ports\common\ARMCMx\CMSIS\include\core_cmFunc.h ¨Ö »Ù< 0..\..\..\os\hal\platforms\STM32L1xx\stm32_isr.h ¨Ö ÊÙ< 0..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.h ¨Ö æÙ< 0..\..\..\os\hal\platforms\STM32L1xx\stm32_rcc.h ¨Ö àÙ1 %..\..\..\os\hal\include\io_channel.h ¨Ö NÙ/ #..\..\..\os\hal\include\io_block.h ¨Ö Ù, ..\..\..\os\hal\include\mmcsd.h ¨Ö TÙ) ..\..\..\os\hal\include\tm.h ¨Ö Ù* ..\..\..\os\hal\include\pal.h ¨Ö /Ù= 1..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h ¨Ö Ù* ..\..\..\os\hal\include\adc.h ¨Ö DÙ* ..\..\..\os\hal\include\can.h ¨Ö :Ù* ..\..\..\os\hal\include\ext.h ¨Ö Ù* ..\..\..\os\hal\include\gpt.h ¨Ö !Ù6 *..\..\..\os\hal\platforms\STM32\gpt_lld.h ñ ¶Ù* ..\..\..\os\hal\include\i2c.h ¨Ö nÙ* ..\..\..\os\hal\include\icu.h ¨Ö +Ù* ..\..\..\os\hal\include\mac.h ¨Ö ;Ù* ..\..\..\os\hal\include\pwm.h ¨Ö Ù* ..\..\..\os\hal\include\rtc.h ¨Ö #Ù- !..\..\..\os\hal\include\serial.h Ѥ ñÙA 5..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h ªã åÙ* ..\..\..\os\hal\include\sdc.h ¨Ö 2Ù* ..\..\..\os\hal\include\spi.h ¨Ö Ù+ ..\..\..\os\hal\include\uart.h ¨Ö ®Ù* ..\..\..\os\hal\include\usb.h ¨Ö "Ù. "..\..\..\os\hal\include\mmc_spi.h ¨Ö |Ù1 %..\..\..\os\hal\include\serial_usb.h ¨Ö 5Ù& ..\..\..\os\hal\src\hal.c ¨Ö ÙÚ P _CH_H_ ÏÚ P
_CHIBIOS_RT_ ïÚ P CH_KERNEL_VERSION yÚ P CH_KERNEL_MAJOR *Ú P CH_KERNEL_MINOR Ú P CH_KERNEL_PATCH 3Ú P FALSE VÚ
P TRUE Ú P CH_SUCCESS ´Ú P |
| 2 |
CH_FAILED *Ú P _CHCONF_H_ ¡Ú P
CH_FREQUENCY Ú P CH_TIME_QUANTUM |
2 |
CH_FAILED *Ú P _CHCONF_H_ ¡Ú P
CH_FREQUENCY Ú P CH_TIME_QUANTUM |
| 3 |
Ú P CH_MEMCORE_SIZE !Ú P CH_NO_IDLE_THREAD Ú P CH_OPTIMIZE_SPEED ~Ú P CH_USE_REGISTRY þÚ P CH_USE_WAITEXIT Ú P CH_USE_SEMAPHORES |Ú# P CH_USE_SEMAPHORES_PRIORITY Ú P
CH_USE_SEMSW îÚ P CH_USE_MUTEXES NÚ P CH_USE_CONDVARS Ú P CH_USE_CONDVARS_TIMEOUT Ú P CH_USE_EVENTS ¦Ú P CH_USE_EVENTS_TIMEOUT Ú P CH_USE_MESSAGES Ú! P CH_USE_MESSAGES_PRIORITY ,Ú P CH_USE_MAILBOXES ÑÚ P CH_USE_QUEUES £Ú P CH_USE_MEMCORE qÚ P CH_USE_HEAP aÚ P CH_USE_MALLOC_HEAP <Ú P CH_USE_MEMPOOLS Ú P CH_USE_DYNAMIC tÚ" P CH_DBG_SYSTEM_STATE_CHECK Ú P CH_DBG_ENABLE_CHECKS ÖÚ P CH_DBG_ENABLE_ASSERTS `Ú P CH_DBG_ENABLE_TRACE Ú" P CH_DBG_ENABLE_STACK_CHECK JÚ P CH_DBG_FILL_THREADS þÚ! P CH_DBG_THREADS_PROFILING qÚ P THREAD_EXT_FIELDS Ú P THREAD_EXT_INIT_HOOK xÚ P THREAD_EXT_EXIT_HOOK rÚ# P THREAD_CONTEXT_SWITCH_HOOK Ú P IDLE_LOOP_HOOK hÚ P SYSTEM_TICK_EVENT_HOOK ¿Ú P SYSTEM_HALT_HOOK ®Ú P _CHTYPES_H_ 0Ú P __stddef_h ¸Ú P __ARMCLIB_VERSION lÚ P __STDDEF_DECLS mÚ P __CLIBNS BÚ P __cplusplus |
3 |
Ú P CH_MEMCORE_SIZE !Ú P CH_NO_IDLE_THREAD Ú P CH_OPTIMIZE_SPEED ~Ú P CH_USE_REGISTRY þÚ P CH_USE_WAITEXIT Ú P CH_USE_SEMAPHORES |Ú# P CH_USE_SEMAPHORES_PRIORITY Ú P
CH_USE_SEMSW îÚ P CH_USE_MUTEXES NÚ P CH_USE_CONDVARS Ú P CH_USE_CONDVARS_TIMEOUT Ú P CH_USE_EVENTS ¦Ú P CH_USE_EVENTS_TIMEOUT Ú P CH_USE_MESSAGES Ú! P CH_USE_MESSAGES_PRIORITY ,Ú P CH_USE_MAILBOXES ÑÚ P CH_USE_QUEUES £Ú P CH_USE_MEMCORE qÚ P CH_USE_HEAP aÚ P CH_USE_MALLOC_HEAP <Ú P CH_USE_MEMPOOLS Ú P CH_USE_DYNAMIC tÚ" P CH_DBG_SYSTEM_STATE_CHECK Ú P CH_DBG_ENABLE_CHECKS ÖÚ P CH_DBG_ENABLE_ASSERTS `Ú P CH_DBG_ENABLE_TRACE Ú" P CH_DBG_ENABLE_STACK_CHECK JÚ P CH_DBG_FILL_THREADS þÚ! P CH_DBG_THREADS_PROFILING qÚ P THREAD_EXT_FIELDS Ú P THREAD_EXT_INIT_HOOK xÚ P THREAD_EXT_EXIT_HOOK rÚ# P THREAD_CONTEXT_SWITCH_HOOK Ú P IDLE_LOOP_HOOK hÚ P SYSTEM_TICK_EVENT_HOOK ¿Ú P SYSTEM_HALT_HOOK ®Ú P _CHTYPES_H_ 0Ú P __stddef_h ¸Ú P __ARMCLIB_VERSION lÚ P __STDDEF_DECLS mÚ P __CLIBNS BÚ P __cplusplus |
| 4 |
Ú |
4 |
Ú |
| 5 |
ptrdiff_t -Ú size_t gÚ wchar_t Ú
P NULL Ú P offsetof _Ú P __stdint_h Ú P __STDINT_DECLS QÚ int8_t Ú int16_t nÚ int32_t pÚ int64_t kÚ uint8_t (Ú uint16_t ÷Ú uint32_t ùÚ uint64_t ôÚ
int_least8_t Ú int_least16_t êÚ int_least32_t ìÚ int_least64_t çÚ uint_least8_t ¤Ú uint_least16_t sÚ uint_least32_t uÚ uint_least64_t pÚ int_fast8_t Ú
int_fast16_t WÚ
int_fast32_t YÚ
int_fast64_t TÚ
uint_fast8_t Ú uint_fast16_t àÚ uint_fast32_t âÚ uint_fast64_t ÝÚ intptr_t }Ú |
5 |
ptrdiff_t -Ú size_t gÚ wchar_t Ú
P NULL Ú P offsetof _Ú P __stdint_h Ú P __STDINT_DECLS QÚ int8_t Ú int16_t nÚ int32_t pÚ int64_t kÚ uint8_t (Ú uint16_t ÷Ú uint32_t ùÚ uint64_t ôÚ
int_least8_t Ú int_least16_t êÚ int_least32_t ìÚ int_least64_t çÚ uint_least8_t ¤Ú uint_least16_t sÚ uint_least32_t uÚ uint_least64_t pÚ int_fast8_t Ú
int_fast16_t WÚ
int_fast32_t YÚ
int_fast64_t TÚ
uint_fast8_t Ú uint_fast16_t àÚ uint_fast32_t âÚ uint_fast64_t ÝÚ intptr_t }Ú |
| 6 |
uintptr_t Ú intmax_t Ú |
6 |
uintptr_t Ú intmax_t Ú |
| 7 |
uintmax_t Ú P INT8_MIN UÚ P |
7 |
uintmax_t Ú P INT8_MIN UÚ P |
| 8 |
INT16_MIN $Ú P |
8 |
INT16_MIN $Ú P |
| 9 |
INT32_MIN &Ú P |
9 |
INT32_MIN &Ú P |
| 10 |
INT64_MIN !Ú P INT8_MAX SÚ P |
10 |
INT64_MIN !Ú P INT8_MAX SÚ P |
| 11 |
INT16_MAX "Ú P |
11 |
INT16_MAX "Ú P |
| 12 |
INT32_MAX $Ú P |
12 |
INT32_MAX $Ú P |
| 13 |
INT64_MAX Ú P |
13 |
INT64_MAX Ú P |
| 14 |
UINT8_MAX üÚ P UINT16_MAX ËÚ P UINT32_MAX ÍÚ P UINT64_MAX ÈÚ P INT_LEAST8_MIN qÚ P INT_LEAST16_MIN @Ú P INT_LEAST32_MIN BÚ P INT_LEAST64_MIN =Ú P INT_LEAST8_MAX oÚ P INT_LEAST16_MAX >Ú P INT_LEAST32_MAX @Ú P INT_LEAST64_MAX ;Ú P UINT_LEAST8_MAX Ú P UINT_LEAST16_MAX çÚ P UINT_LEAST32_MAX éÚ P UINT_LEAST64_MAX äÚ P INT_FAST8_MIN ¾Ú P INT_FAST16_MIN Ú P INT_FAST32_MIN Ú P INT_FAST64_MIN Ú P INT_FAST8_MAX ¼Ú P INT_FAST16_MAX Ú P INT_FAST32_MAX Ú P INT_FAST64_MAX Ú P UINT_FAST8_MAX eÚ P UINT_FAST16_MAX 4Ú P UINT_FAST32_MAX 6Ú P UINT_FAST64_MAX 1Ú P INTPTR_MIN Ú P INTPTR_MAX Ú P UINTPTR_MAX :Ú P INTMAX_MIN £Ú P INTMAX_MAX ¡Ú P UINTMAX_MAX JÚ P PTRDIFF_MIN cÚ P PTRDIFF_MAX aÚ P SIG_ATOMIC_MIN mÚ P SIG_ATOMIC_MAX kÚ P SIZE_MAX ;Ú P |
14 |
UINT8_MAX üÚ P UINT16_MAX ËÚ P UINT32_MAX ÍÚ P UINT64_MAX ÈÚ P INT_LEAST8_MIN qÚ P INT_LEAST16_MIN @Ú P INT_LEAST32_MIN BÚ P INT_LEAST64_MIN =Ú P INT_LEAST8_MAX oÚ P INT_LEAST16_MAX >Ú P INT_LEAST32_MAX @Ú P INT_LEAST64_MAX ;Ú P UINT_LEAST8_MAX Ú P UINT_LEAST16_MAX çÚ P UINT_LEAST32_MAX éÚ P UINT_LEAST64_MAX äÚ P INT_FAST8_MIN ¾Ú P INT_FAST16_MIN Ú P INT_FAST32_MIN Ú P INT_FAST64_MIN Ú P INT_FAST8_MAX ¼Ú P INT_FAST16_MAX Ú P INT_FAST32_MAX Ú P INT_FAST64_MAX Ú P UINT_FAST8_MAX eÚ P UINT_FAST16_MAX 4Ú P UINT_FAST32_MAX 6Ú P UINT_FAST64_MAX 1Ú P INTPTR_MIN Ú P INTPTR_MAX Ú P UINTPTR_MAX :Ú P INTMAX_MIN £Ú P INTMAX_MAX ¡Ú P UINTMAX_MAX JÚ P PTRDIFF_MIN cÚ P PTRDIFF_MAX aÚ P SIG_ATOMIC_MIN mÚ P SIG_ATOMIC_MAX kÚ P SIZE_MAX ;Ú P |
| 15 |
WCHAR_MIN Ú P |
15 |
WCHAR_MIN Ú P |
| 16 |
WCHAR_MAX ÿÚ P WINT_MIN 6Ú P WINT_MAX 4Ú P INT8_C úÚ P INT16_C ÉÚ P INT32_C ËÚ P INT64_C ÆÚ P UINT8_C £Ú P UINT16_C rÚ P UINT32_C tÚ P UINT64_C oÚ P INTMAX_C HÚ P |
16 |
WCHAR_MAX ÿÚ P WINT_MIN 6Ú P WINT_MAX 4Ú P INT8_C úÚ P INT16_C ÉÚ P INT32_C ËÚ P INT64_C ÆÚ P UINT8_C £Ú P UINT16_C rÚ P UINT32_C tÚ P UINT64_C oÚ P INTMAX_C HÚ P |
| 17 |
UINTMAX_C ñÚ& P __bool_true_false_are_defined ÙÚ
P bool Ú
P true Ú P false ¶Ú bool_t vÚ tmode_t Ú tstate_t Ú trefs_t üÚ |
17 |
UINTMAX_C ñÚ& P __bool_true_false_are_defined ÙÚ
P bool Ú
P true Ú P false ¶Ú bool_t vÚ tmode_t Ú tstate_t Ú trefs_t üÚ |
| 18 |
tslices_t %Ú tprio_t òÚ msg_t ÝÚ |
18 |
tslices_t %Ú tprio_t òÚ msg_t ÝÚ |
| 19 |
eventid_t -Ú eventmask_t JÚ flagsmask_t _Ú |
19 |
eventid_t -Ú eventmask_t JÚ flagsmask_t _Ú |
| 20 |
systime_t Ú cnt_t ßÚ P INLINE Ú P ROMCONST FÚ P PACK_STRUCT_STRUCT Ú P PACK_STRUCT_BEGIN Ú P PACK_STRUCT_END Ú P _CHLISTS_H_ 6Ú 8 Thread aÚ Thread Ú P queue_init Ú P |
20 |
systime_t Ú cnt_t ßÚ P INLINE Ú P ROMCONST FÚ P PACK_STRUCT_STRUCT Ú P PACK_STRUCT_BEGIN Ú P PACK_STRUCT_END Ú P _CHLISTS_H_ 6Ú 8 Thread aÚ Thread Ú P queue_init Ú P |
| 21 |
list_init êÚ P isempty ²Ú P notempty ;Ú P _THREADSQUEUE_DATA ?Ú P THREADSQUEUE_DECL ¢Ú 8 |
21 |
list_init êÚ P isempty ²Ú P notempty ;Ú P _THREADSQUEUE_DATA ?Ú P THREADSQUEUE_DECL ¢Ú 8 |
| 22 |
<unnamed> QÚ " ¶p_next jÚ " ¶p_prev lÚ
ThreadsQueue Ú 8 |
22 |
<unnamed> QÚ " ¶p_next jÚ " ¶p_prev lÚ
ThreadsQueue Ú 8 |
| 23 |
<unnamed> QÚ " ºp_next fÚ ThreadsList Ú P _CHCORE_H_ Ú P |
23 |
<unnamed> QÚ " ºp_next fÚ ThreadsList Ú P _CHCORE_H_ Ú P |
| 24 |
CORTEX_M0 Ú P |
24 |
CORTEX_M0 Ú P |
| 25 |
CORTEX_M1 Ú P |
25 |
CORTEX_M1 Ú P |
| 26 |
CORTEX_M3 Ú P |
26 |
CORTEX_M3 Ú P |
| 27 |
CORTEX_M4 Ú P
_CMPARAMS_H_ úÚ P
CORTEX_MODEL Ú P CORTEX_HAS_ST Ú P CORTEX_HAS_MPU NÚ P CORTEX_HAS_FPU UÚ P CORTEX_PRIORITY_BITS \Ú P CORTEX_PRIORITY_LEVELS ¿Ú P CORTEX_MINIMUM_PRIORITY lÚ P CORTEX_MAXIMUM_PRIORITY jÚ! P CORTEX_IS_VALID_PRIORITY Ú( P CORTEX_IS_VALID_KERNEL_PRIORITY íÚ P CORTEX_PRIORITY_MASK bÚ P CH_ARCHITECTURE_ARM ùÚ P CH_COMPILER_NAME æÚ P _CHCORE_V7M_H_ ]Ú P CORTEX_BASEPRI_DISABLED ÌÚ$ P PORT_IDLE_THREAD_STACK_SIZE MÚ P PORT_INT_REQUIRED_STACK yÚ P CORTEX_ENABLE_WFI_IDLE Ú P CORTEX_PRIORITY_SYSTICK ^Ú P CORTEX_USE_FPU DÚ# P CORTEX_SIMPLIFIED_PRIORITY Ú P CORTEX_PRIORITY_SVCALL ÅÚ P CORTEX_VTOR_INIT Ú P CORTEX_PRIGROUP_INIT dÚ# P CORTEX_MAX_KERNEL_PRIORITY |Ú P CORTEX_BASEPRI_KERNEL GÚ P CORTEX_PRIORITY_PENDSV ºÚ P CH_ARCHITECTURE_ARM_v7M Ú P CH_ARCHITECTURE_NAME ¶Ú P CH_CORE_VARIANT_NAME Ú P
CH_PORT_INFO ùÚ regarm_t Ú stkalign_t ½Ú 8 extctx Ú
" är0 0Ú
" är1 /Ú
" är2 .Ú
" är3 -Ú " är12 ûÚ " älr_thd MÚ
" äpc ÿÚ " äxpsr Ú 8 intctx Ú
" ír4 #Ú
" ír5 "Ú
" ír6 !Ú
" ír7 Ú
" ír8 Ú
" ír9 Ú " ír10 ôÚ " ír11 óÚ
" ílr ëÚ 8 context ²Ú " ÷r13 çÚ P SETUP_CONTEXT Ú P STACK_ALIGN uÚ P THD_WA_SIZE DÚ P
WORKING_AREA Ú P PORT_IRQ_PROLOGUE MÚ P PORT_IRQ_EPILOGUE `Ú P PORT_IRQ_HANDLER ¾Ú P PORT_FAST_IRQ_HANDLER 'Ú P |
27 |
CORTEX_M4 Ú P
_CMPARAMS_H_ úÚ P
CORTEX_MODEL Ú P CORTEX_HAS_ST Ú P CORTEX_HAS_MPU NÚ P CORTEX_HAS_FPU UÚ P CORTEX_PRIORITY_BITS \Ú P CORTEX_PRIORITY_LEVELS ¿Ú P CORTEX_MINIMUM_PRIORITY lÚ P CORTEX_MAXIMUM_PRIORITY jÚ! P CORTEX_IS_VALID_PRIORITY Ú( P CORTEX_IS_VALID_KERNEL_PRIORITY íÚ P CORTEX_PRIORITY_MASK bÚ P CH_ARCHITECTURE_ARM ùÚ P CH_COMPILER_NAME æÚ P _CHCORE_V7M_H_ ]Ú P CORTEX_BASEPRI_DISABLED ÌÚ$ P PORT_IDLE_THREAD_STACK_SIZE MÚ P PORT_INT_REQUIRED_STACK yÚ P CORTEX_ENABLE_WFI_IDLE Ú P CORTEX_PRIORITY_SYSTICK ^Ú P CORTEX_USE_FPU DÚ# P CORTEX_SIMPLIFIED_PRIORITY Ú P CORTEX_PRIORITY_SVCALL ÅÚ P CORTEX_VTOR_INIT Ú P CORTEX_PRIGROUP_INIT dÚ# P CORTEX_MAX_KERNEL_PRIORITY |Ú P CORTEX_BASEPRI_KERNEL GÚ P CORTEX_PRIORITY_PENDSV ºÚ P CH_ARCHITECTURE_ARM_v7M Ú P CH_ARCHITECTURE_NAME ¶Ú P CH_CORE_VARIANT_NAME Ú P
CH_PORT_INFO ùÚ regarm_t Ú stkalign_t ½Ú 8 extctx Ú
" är0 0Ú
" är1 /Ú
" är2 .Ú
" är3 -Ú " är12 ûÚ " älr_thd MÚ
" äpc ÿÚ " äxpsr Ú 8 intctx Ú
" ír4 #Ú
" ír5 "Ú
" ír6 !Ú
" ír7 Ú
" ír8 Ú
" ír9 Ú " ír10 ôÚ " ír11 óÚ
" ílr ëÚ 8 context ²Ú " ÷r13 çÚ P SETUP_CONTEXT Ú P STACK_ALIGN uÚ P THD_WA_SIZE DÚ P
WORKING_AREA Ú P PORT_IRQ_PROLOGUE MÚ P PORT_IRQ_EPILOGUE `Ú P PORT_IRQ_HANDLER ¾Ú P PORT_FAST_IRQ_HANDLER 'Ú P |
| 28 |
port_init áÚ P |
28 |
port_init áÚ P |
| 29 |
port_lock ìÚ P port_unlock Ú P port_lock_from_isr Ú P port_unlock_from_isr 3Ú P
port_disable »Ú P
port_suspend Ú P port_enable *Ú P port_wait_for_interrupt ÒÚ P port_switch ÿÚ |
29 |
port_lock ìÚ P port_unlock Ú P port_lock_from_isr Ú P port_unlock_from_isr 3Ú P
port_disable »Ú P
port_suspend Ú P port_enable *Ú P port_wait_for_interrupt ÒÚ P port_switch ÿÚ |
| 30 |
port_halt Ú _port_init Ú _port_irq_epilogue <Ú _port_switch_from_isr éÚ _port_exit_from_isr ÅÚ , ntp yÚ , otp xÚ
_port_switch »Ú _port_thread_start <Ú P _NVIC_H_ &Ú P HANDLER_MEM_MANAGE cÚ P HANDLER_BUS_FAULT Ú P HANDLER_USAGE_FAULT øÚ P HANDLER_RESERVED_3 XÚ P HANDLER_RESERVED_4 WÚ P HANDLER_RESERVED_5 VÚ P HANDLER_RESERVED_6 UÚ P HANDLER_SVCALL Ú P HANDLER_DEBUG_MONITOR VÚ P HANDLER_RESERVED_9 RÚ P HANDLER_PENDSV Ú P HANDLER_SYSTICK &Ú IOREG8 GÚ IOREG32 Ú P |
30 |
port_halt Ú _port_init Ú _port_irq_epilogue <Ú _port_switch_from_isr éÚ _port_exit_from_isr ÅÚ , ntp yÚ , otp xÚ
_port_switch »Ú _port_thread_start <Ú P _NVIC_H_ &Ú P HANDLER_MEM_MANAGE cÚ P HANDLER_BUS_FAULT Ú P HANDLER_USAGE_FAULT øÚ P HANDLER_RESERVED_3 XÚ P HANDLER_RESERVED_4 WÚ P HANDLER_RESERVED_5 VÚ P HANDLER_RESERVED_6 UÚ P HANDLER_SVCALL Ú P HANDLER_DEBUG_MONITOR VÚ P HANDLER_RESERVED_9 RÚ P HANDLER_PENDSV Ú P HANDLER_SYSTICK &Ú IOREG8 GÚ IOREG32 Ú P |
| 31 |
NVIC_ITCR øÚ 8 |
31 |
NVIC_ITCR øÚ 8 |
| 32 |
<unnamed> QÚ |
32 |
<unnamed> QÚ |
| 33 |
" ¤CSR 5Ú |
33 |
" ¤CSR 5Ú |
| 34 |
" ¤RVR #Ú |
34 |
" ¤RVR #Ú |
| 35 |
" ¤CVR 2Ú |
35 |
" ¤CVR 2Ú |
| 36 |
" ¤CBVR îÚ CMx_ST çÚ P STBase Ú P ST_CSR ÑÚ P ST_RVR ¿Ú P ST_CVR ÎÚ P ST_CBVR Ú P CSR_ENABLE_MASK 4Ú P ENABLE_OFF_BITS ;Ú P ENABLE_ON_BITS {Ú P CSR_TICKINT_MASK ÃÚ P TICKINT_DISABLED_BITS cÚ P TICKINT_ENABLED_BITS ²Ú P CSR_CLKSOURCE_MASK *Ú P CLKSOURCE_EXT_BITS Ú P CLKSOURCE_CORE_BITS áÚ P CSR_COUNTFLAG_MASK 2Ú P RVR_RELOAD_MASK Ú P CVR_CURRENT_MASK ³Ú P CBVR_TENMS_MASK Ú P CBVR_SKEW_MASK ^Ú P CBVR_NOREF_MASK Ú 8 |
36 |
" ¤CBVR îÚ CMx_ST çÚ P STBase Ú P ST_CSR ÑÚ P ST_RVR ¿Ú P ST_CVR ÎÚ P ST_CBVR Ú P CSR_ENABLE_MASK 4Ú P ENABLE_OFF_BITS ;Ú P ENABLE_ON_BITS {Ú P CSR_TICKINT_MASK ÃÚ P TICKINT_DISABLED_BITS cÚ P TICKINT_ENABLED_BITS ²Ú P CSR_CLKSOURCE_MASK *Ú P CLKSOURCE_EXT_BITS Ú P CLKSOURCE_CORE_BITS áÚ P CSR_COUNTFLAG_MASK 2Ú P RVR_RELOAD_MASK Ú P CVR_CURRENT_MASK ³Ú P CBVR_TENMS_MASK Ú P CBVR_SKEW_MASK ^Ú P CBVR_NOREF_MASK Ú 8 |
| 37 |
<unnamed> QÚ <" ¾ISER Ú <" `¾unused1 ¨Ú <" ¾ICER Ú <" `¾unused2 §Ú <" ¾ISPR uÚ <" `¾unused3 ¦Ú <" ¾ICPR
Ú <" `¾unused4 ¥Ú <" ¾IABR Ú <" à¾unused5 "Ú <" ð¾IPR øÚ <" ¾unused6 ^Ú |
37 |
<unnamed> QÚ <" ¾ISER Ú <" `¾unused1 ¨Ú <" ¾ICER Ú <" `¾unused2 §Ú <" ¾ISPR uÚ <" `¾unused3 ¦Ú <" ¾ICPR
Ú <" `¾unused4 ¥Ú <" ¾IABR Ú <" à¾unused5 "Ú <" ð¾IPR øÚ <" ¾unused6 ^Ú |
| 38 |
" ¾STIR ¿Ú CMx_NVIC ZÚ P NVICBase Ú P |
38 |
" ¾STIR ¿Ú CMx_NVIC ZÚ P NVICBase Ú P |
| 39 |
NVIC_ISER ÷Ú P |
39 |
NVIC_ISER ÷Ú P |
| 40 |
NVIC_ICER Ú P |
40 |
NVIC_ICER Ú P |
| 41 |
NVIC_ISPR ìÚ P |
41 |
NVIC_ISPR ìÚ P |
| 42 |
NVIC_ICPR üÚ P |
42 |
NVIC_ICPR üÚ P |
| 43 |
NVIC_IABR Ú P NVIC_IPR AÚ P |
43 |
NVIC_IABR Ú P NVIC_IPR AÚ P |
| 44 |
NVIC_STIR èÚ 8 |
44 |
NVIC_STIR èÚ 8 |
| 45 |
<unnamed> QÚ |
45 |
<unnamed> QÚ |
| 46 |
" ÕCPUID sÚ |
46 |
" ÕCPUID sÚ |
| 47 |
" ÕICSR ¹Ú |
47 |
" ÕICSR ¹Ú |
| 48 |
" ÕVTOR Ú |
48 |
" ÕVTOR Ú |
| 49 |
" ÕAIRCR wÚ |
49 |
" ÕAIRCR wÚ |
| 50 |
" ÕSCR Ú |
50 |
" ÕSCR Ú |
| 51 |
" ÕCCR Ú <" ÕSHPR sÚ |
51 |
" ÕCCR Ú <" ÕSHPR sÚ |
| 52 |
" ÕSHCSR eÚ |
52 |
" ÕSHCSR eÚ |
| 53 |
" ÕCFSR ¼Ú |
53 |
" ÕCFSR ¼Ú |
| 54 |
" ÕHFSR ·Ú |
54 |
" ÕHFSR ·Ú |
| 55 |
" ÕDFSR »Ú |
55 |
" ÕDFSR »Ú |
| 56 |
" ÕMMFAR uÚ |
56 |
" ÕMMFAR uÚ |
| 57 |
" ÕBFAR ÏÚ |
57 |
" ÕBFAR ÏÚ |
| 58 |
" ÕAFSR ¾Ú <" ÕPFR ÎÚ |
58 |
" ÕAFSR ¾Ú <" ÕPFR ÎÚ |
| 59 |
" ÕDFR Ú |
59 |
" ÕDFR Ú |
| 60 |
" ÕADR Ú <" ÕMMFR zÚ <" ÕSAR ÄÚ <" Õunused1 ÝÚ |
60 |
" ÕADR Ú <" ÕMMFR zÚ <" ÕSAR ÄÚ <" Õunused1 ÝÚ |
| 61 |
" ÕCPACR Ú CMx_SCB ´Ú P SCBBase jÚ P |
61 |
" ÕCPACR Ú CMx_SCB ´Ú P SCBBase jÚ P |
| 62 |
SCB_CPUID
Ú P SCB_ICSR SÚ P SCB_VTOR 9Ú P |
62 |
SCB_CPUID
Ú P SCB_ICSR SÚ P SCB_VTOR 9Ú P |
| 63 |
SCB_AIRCR Ú P SCB_SCR Ú P SCB_CCR ®Ú P SCB_SHPR GÚ P |
63 |
SCB_AIRCR Ú P SCB_SCR Ú P SCB_CCR ®Ú P SCB_SHPR GÚ P |
| 64 |
SCB_SHCSR ÿÚ P SCB_CFSR VÚ P SCB_HFSR QÚ P SCB_DFSR UÚ P |
64 |
SCB_SHCSR ÿÚ P SCB_CFSR VÚ P SCB_HFSR QÚ P SCB_DFSR UÚ P |
| 65 |
SCB_MMFAR Ú P SCB_BFAR iÚ P SCB_AFSR XÚ P SCB_PFR Ú P SCB_DFR ªÚ P SCB_ADR ¯Ú P SCB_MMFR RÚ P SCB_SAR Ú P |
65 |
SCB_MMFAR Ú P SCB_BFAR iÚ P SCB_AFSR XÚ P SCB_PFR Ú P SCB_DFR ªÚ P SCB_ADR ¯Ú P SCB_MMFR RÚ P SCB_SAR Ú P |
| 66 |
SCB_CPACR Ú P ICSR_VECTACTIVE_MASK Ú P ICSR_RETTOBASE vÚ P ICSR_VECTPENDING_MASK OÚ P ICSR_ISRPENDING *Ú P ICSR_ISRPREEMPT Ú P ICSR_PENDSTCLR pÚ P ICSR_PENDSTSET eÚ P ICSR_PENDSVCLR nÚ P ICSR_PENDSVSET cÚ P ICSR_NMIPENDSET &Ú P AIRCR_VECTKEY ÆÚ P AIRCR_PRIGROUP_MASK ÒÚ P AIRCR_PRIGROUP gÚ 8 |
66 |
SCB_CPACR Ú P ICSR_VECTACTIVE_MASK Ú P ICSR_RETTOBASE vÚ P ICSR_VECTPENDING_MASK OÚ P ICSR_ISRPENDING *Ú P ICSR_ISRPREEMPT Ú P ICSR_PENDSTCLR pÚ P ICSR_PENDSTSET eÚ P ICSR_PENDSVCLR nÚ P ICSR_PENDSVSET cÚ P ICSR_NMIPENDSET &Ú P AIRCR_VECTKEY ÆÚ P AIRCR_PRIGROUP_MASK ÒÚ P AIRCR_PRIGROUP gÚ 8 |
| 67 |
<unnamed> QÚ <" unused1 3Ú |
67 |
<unnamed> QÚ <" unused1 3Ú |
| 68 |
" FPCCR ÀÚ |
68 |
" FPCCR ÀÚ |
| 69 |
" FPCAR ÂÚ |
69 |
" FPCAR ÂÚ |
| 70 |
" FPDSCR jÚ |
70 |
" FPDSCR jÚ |
| 71 |
" MVFR0 ÃÚ |
71 |
" MVFR0 ÃÚ |
| 72 |
" MVFR1 ÂÚ CMx_FPU ¡Ú P FPUBase WÚ P |
72 |
" MVFR1 ÂÚ CMx_FPU ¡Ú P FPUBase WÚ P |
| 73 |
SCB_FPCCR Ú P |
73 |
SCB_FPCCR Ú P |
| 74 |
SCB_FPCAR Ú P SCB_FPDSCR ¾Ú P |
74 |
SCB_FPCAR Ú P SCB_FPDSCR ¾Ú P |
| 75 |
SCB_MVFR0 Ú P |
75 |
SCB_MVFR0 Ú P |
| 76 |
SCB_MVFR1 Ú P FPCCR_ASPEN qÚ P FPCCR_LSPEN fÚ P
FPCCR_MONRDY
Ú P FPCCR_BFRDY qÚ P FPCCR_MMRDY _Ú P FPCCR_HFRDY kÚ P
FPCCR_THREAD .Ú P FPCCR_USER «Ú P
FPCCR_LSPACT Ú P FPDSCR_AHP ½Ú P |
76 |
SCB_MVFR1 Ú P FPCCR_ASPEN qÚ P FPCCR_LSPEN fÚ P
FPCCR_MONRDY
Ú P FPCCR_BFRDY qÚ P FPCCR_MMRDY _Ú P FPCCR_HFRDY kÚ P
FPCCR_THREAD .Ú P FPCCR_USER «Ú P
FPCCR_LSPACT Ú P FPDSCR_AHP ½Ú P |
| 77 |
FPDSCR_DN Ú P |
77 |
FPDSCR_DN Ú P |
| 78 |
FPDSCR_FZ øÚ P
FPDSCR_RMODE Ú 8 |
78 |
FPDSCR_FZ øÚ P
FPDSCR_RMODE Ú 8 |
| 79 |
<unnamed> QÚ |
79 |
<unnamed> QÚ |
| 80 |
" ©DHCSR Ú |
80 |
" ©DHCSR Ú |
| 81 |
" ©DCRSR Ú |
81 |
" ©DCRSR Ú |
| 82 |
" ©DCRDR ¤Ú |
82 |
" ©DCRDR ¤Ú |
| 83 |
" ©DEMCR ¨Ú CMx_SCS £Ú P SCSBase YÚ P |
83 |
" ©DEMCR ¨Ú CMx_SCS £Ú P SCSBase YÚ P |
| 84 |
SCS_DHCSR ýÚ P |
84 |
SCS_DHCSR ýÚ P |
| 85 |
SCS_DCRSR óÚ P |
85 |
SCS_DCRSR óÚ P |
| 86 |
SCS_DCRDR Ú P |
86 |
SCS_DCRDR Ú P |
| 87 |
SCS_DEMCR Ú P SCS_DEMCR_TRCENA ÜÚ 8 |
87 |
SCS_DEMCR Ú P SCS_DEMCR_TRCENA ÜÚ 8 |
| 88 |
<unnamed> QÚ |
88 |
<unnamed> QÚ |
| 89 |
" µCTRL ÔÚ |
89 |
" µCTRL ÔÚ |
| 90 |
" µCYCCNT AÚ |
90 |
" µCYCCNT AÚ |
| 91 |
" µCPICNT DÚ |
91 |
" µCPICNT DÚ |
| 92 |
" µEXCCNT @Ú |
92 |
" µEXCCNT @Ú |
| 93 |
" µ SLEEPCNT £Ú |
93 |
" µ SLEEPCNT £Ú |
| 94 |
" µLSUCNT ,Ú |
94 |
" µLSUCNT ,Ú |
| 95 |
" µFOLDCNT ùÚ |
95 |
" µFOLDCNT ùÚ |
| 96 |
" µPCSR ÑÚ CMx_DWT Ú P DWTBase SÚ P DWT_CTRL 8Ú P DWT_CYCCNT ¥Ú P DWT_CPICNT ¨Ú P DWT_EXCCNT ¤Ú P
DWT_SLEEPCNT Ú P DWT_LSUCNT Ú P DWT_FOLDCNT ]Ú P DWT_PCSR 5Ú P DWT_CTRL_CYCCNTENA -Ú |
96 |
" µPCSR ÑÚ CMx_DWT Ú P DWTBase SÚ P DWT_CTRL 8Ú P DWT_CYCCNT ¥Ú P DWT_CPICNT ¨Ú P DWT_EXCCNT ¤Ú P
DWT_SLEEPCNT Ú P DWT_LSUCNT Ú P DWT_FOLDCNT ]Ú P DWT_PCSR 5Ú P DWT_CTRL_CYCCNTENA -Ú |
| 97 |
, |
97 |
, |
| 98 |
n oÚ
, |
98 |
n oÚ
, |
| 99 |
prio Ú nvicEnableVector ^Ú |
99 |
prio Ú nvicEnableVector ^Ú |
| 100 |
, |
100 |
, |
| 101 |
n oÚ nvicDisableVector ïÚ , |
101 |
n oÚ nvicDisableVector ïÚ , |
| 102 |
handler óÚ
, |
102 |
handler óÚ
, |
| 103 |
prio Ú% nvicSetSystemHandlerPriority /Ú, P $PORT_OPTIMIZED_ISPREEMPTIONREQUIRED ÍÚ" P chSchIsPreemptionRequired Ú P |
103 |
prio Ú% nvicSetSystemHandlerPriority /Ú, P $PORT_OPTIMIZED_ISPREEMPTIONREQUIRED ÍÚ" P chSchIsPreemptionRequired Ú P |
| 104 |
_CHSYS_H_ ÊÚ P chSysGetIdleThread §Ú P |
104 |
_CHSYS_H_ ÊÚ P chSysGetIdleThread §Ú P |
| 105 |
chSysHalt &Ú P chSysSwitch 9Ú P
chSysDisable õÚ P
chSysSuspend ÇÚ P chSysEnable dÚ P |
105 |
chSysHalt &Ú P chSysSwitch 9Ú P
chSysDisable õÚ P
chSysSuspend ÇÚ P chSysEnable dÚ P |
| 106 |
chSysLock &Ú P chSysUnlock ?Ú P chSysLockFromIsr VÚ P chSysUnlockFromIsr oÚ P CH_IRQ_PROLOGUE Ú P CH_IRQ_EPILOGUE Ú P CH_IRQ_HANDLER |Ú P CH_FAST_IRQ_HANDLER åÚ |
106 |
chSysLock &Ú P chSysUnlock ?Ú P chSysLockFromIsr VÚ P chSysUnlockFromIsr oÚ P CH_IRQ_PROLOGUE Ú P CH_IRQ_EPILOGUE Ú P CH_IRQ_HANDLER |Ú P CH_FAST_IRQ_HANDLER åÚ |
| 107 |
chSysInit 8Ú chSysTimerHandlerI ²Ú P _CHVT_H_ !Ú
P S2ST Ú P MS2ST HÚ P US2ST @Ú vtfunc_t Ú 8
VirtualTimer ÅÚ
VirtualTimer Ú " évt_next ¹Ú " évt_prev »Ú |
107 |
chSysInit 8Ú chSysTimerHandlerI ²Ú P _CHVT_H_ !Ú
P S2ST Ú P MS2ST HÚ P US2ST @Ú vtfunc_t Ú 8
VirtualTimer ÅÚ
VirtualTimer Ú " évt_next ¹Ú " évt_prev »Ú |
| 108 |
" évt_time ×Ú " évt_func ÌÚ " évt_par 7Ú 8 |
108 |
" évt_time ×Ú " évt_func ÌÚ " évt_par 7Ú 8 |
| 109 |
<unnamed> QÚ " ðvt_next ²Ú " ðvt_prev ´Ú |
109 |
<unnamed> QÚ " ðvt_next ²Ú " ðvt_prev ´Ú |
| 110 |
" ðvt_time ÐÚ |
110 |
" ðvt_time ÐÚ |
| 111 |
" ð vt_systime kÚ VTList ¯Ú P chVTDoTickI ¹Ú P
chVTIsArmedI PÚ P chVTSet Ú P |
111 |
" ð vt_systime kÚ VTList ¯Ú P chVTDoTickI ¹Ú P
chVTIsArmedI PÚ P chVTSet Ú P |
| 112 |
chVTReset AÚ P |
112 |
chVTReset AÚ P |
| 113 |
chTimeNow +Ú vtlist +Ú _vt_init |Ú , vtp qÚ
, |
113 |
chTimeNow +Ú vtlist +Ú _vt_init |Ú , vtp qÚ
, |
| 114 |
time (Ú , vtfunc /Ú , par Ú chVTSetI îÚ , vtp qÚ chVTResetI Ú , |
114 |
time (Ú , vtfunc /Ú , par Ú chVTSetI îÚ , vtp qÚ chVTResetI Ú , |
| 115 |
start §Ú , |
115 |
start §Ú , |
| 116 |
end ¢Ú chTimeIsWithin CÚ P _CHSCHD_H_ ¥Ú P RDY_OK ×Ú P RDY_TIMEOUT @Ú P |
116 |
end ¢Ú chTimeIsWithin CÚ P _CHSCHD_H_ ¥Ú P RDY_OK ×Ú P RDY_TIMEOUT @Ú P |
| 117 |
RDY_RESET èÚ P NOPRIO èÚ P IDLEPRIO cÚ P LOWPRIO Ú P NORMALPRIO ´Ú P HIGHPRIO aÚ P ABSPRIO Ú P TIME_IMMEDIATE Ú P TIME_INFINITE ÍÚ P |
117 |
RDY_RESET èÚ P NOPRIO èÚ P IDLEPRIO cÚ P LOWPRIO Ú P NORMALPRIO ´Ú P HIGHPRIO aÚ P ABSPRIO Ú P TIME_IMMEDIATE Ú P TIME_INFINITE ÍÚ P |
| 118 |
firstprio ×Ú 8 |
118 |
firstprio ×Ú 8 |
| 119 |
<unnamed> QÚ " r_queue Ú |
119 |
<unnamed> QÚ " r_queue Ú |
| 120 |
" r_prio Ú " r_ctx õÚ " r_newer #Ú " r_older .Ú " |
120 |
" r_prio Ú " r_ctx õÚ " r_newer #Ú " r_older .Ú " |
| 121 |
r_current =Ú |
121 |
r_current =Ú |
| 122 |
ReadyList ^Ú rlist Ú P currp Ú P setcurrp CÚ _scheduler_init Ú , tp éÚ chSchReadyI «Ú , newstate kÚ chSchGoSleepS ãÚ , newstate kÚ
, |
122 |
ReadyList ^Ú rlist Ú P currp Ú P setcurrp CÚ _scheduler_init Ú , tp éÚ chSchReadyI «Ú , newstate kÚ chSchGoSleepS ãÚ , newstate kÚ
, |
| 123 |
time (Ú chSchGoSleepTimeoutS îÚ , tp éÚ , msg Ú
chSchWakeupS 'Ú chSchRescheduleS Ú chSchDoRescheduleBehind ÐÚ chSchDoRescheduleAhead IÚ chSchDoReschedule &Ú P chSchIsRescRequiredI çÚ P chSchCanYieldS jÚ P chSchDoYieldS ËÚ P chSchPreemption ¡Ú P |
123 |
time (Ú chSchGoSleepTimeoutS îÚ , tp éÚ , msg Ú
chSchWakeupS 'Ú chSchRescheduleS Ú chSchDoRescheduleBehind ÐÚ chSchDoRescheduleAhead IÚ chSchDoReschedule &Ú P chSchIsRescRequiredI çÚ P chSchCanYieldS jÚ P chSchDoYieldS ËÚ P chSchPreemption ¡Ú P |
| 124 |
_CHSEM_H_ äÚ 8 |
124 |
_CHSEM_H_ äÚ 8 |
| 125 |
Semaphore Ú " ³s_queue ÷Ú " ³s_cnt óÚ |
125 |
Semaphore Ú " ³s_queue ÷Ú " ³s_cnt óÚ |
| 126 |
Semaphore KÚ , sp êÚ |
126 |
Semaphore KÚ , sp êÚ |
| 127 |
, n qÚ |
127 |
, n qÚ |
| 128 |
chSemInit RÚ , sp êÚ |
128 |
chSemInit RÚ , sp êÚ |
| 129 |
, n qÚ chSemReset áÚ , sp êÚ |
129 |
, n qÚ chSemReset áÚ , sp êÚ |
| 130 |
, n qÚ chSemResetI Ú , sp êÚ |
130 |
, n qÚ chSemResetI Ú , sp êÚ |
| 131 |
chSemWait QÚ , sp êÚ chSemWaitS üÚ , sp êÚ
, |
131 |
chSemWait QÚ , sp êÚ chSemWaitS üÚ , sp êÚ
, |
| 132 |
time (Ú chSemWaitTimeout \Ú , sp êÚ
, |
132 |
time (Ú chSemWaitTimeout \Ú , sp êÚ
, |
| 133 |
time (Ú chSemWaitTimeoutS Ú , sp êÚ chSemSignal Ú , sp êÚ
chSemSignalI 9Ú , sp êÚ |
133 |
time (Ú chSemWaitTimeoutS Ú , sp êÚ chSemSignal Ú , sp êÚ
chSemSignalI 9Ú , sp êÚ |
| 134 |
, n qÚ chSemAddCounterI ¦Ú , sps uÚ , spw qÚ chSemSignalWait çÚ P _SEMAPHORE_DATA 1Ú P SEMAPHORE_DECL Ú P chSemFastWaitI SÚ P chSemFastSignalI Ú P chSemGetCounterI rÚ P _CHBSEM_H_ Ú 8 |
134 |
, n qÚ chSemAddCounterI ¦Ú , sps uÚ , spw qÚ chSemSignalWait çÚ P _SEMAPHORE_DATA 1Ú P SEMAPHORE_DECL Ú P chSemFastWaitI SÚ P chSemFastSignalI Ú P chSemGetCounterI rÚ P _CHBSEM_H_ Ú 8 |
| 135 |
<unnamed> QÚ " Úbs_sem LÚ BinarySemaphore ÚÚ P _BSEMAPHORE_DATA íÚ P BSEMAPHORE_DECL PÚ P chBSemInit ñÚ P chBSemWait ðÚ P chBSemWaitS Ú P chBSemWaitTimeout ûÚ P chBSemWaitTimeoutS ¦Ú P chBSemReset Ú P
chBSemResetI 5Ú P
chBSemSignal #Ú P chBSemSignalI ØÚ P chBSemGetStateI Ú P |
135 |
<unnamed> QÚ " Úbs_sem LÚ BinarySemaphore ÚÚ P _BSEMAPHORE_DATA íÚ P BSEMAPHORE_DECL PÚ P chBSemInit ñÚ P chBSemWait ðÚ P chBSemWaitS Ú P chBSemWaitTimeout ûÚ P chBSemWaitTimeoutS ¦Ú P chBSemReset Ú P
chBSemResetI 5Ú P
chBSemSignal #Ú P chBSemSignalI ØÚ P chBSemGetStateI Ú P |
| 136 |
_CHMTX_H_ ÐÚ 8 Mutex ¨Ú " êm_queue ÆÚ " êm_owner ÈÚ " êm_next 6Ú Mutex äÚ , mp ðÚ |
136 |
_CHMTX_H_ ÐÚ 8 Mutex ¨Ú " êm_queue ÆÚ " êm_owner ÈÚ " êm_next 6Ú Mutex äÚ , mp ðÚ |
| 137 |
chMtxInit >Ú , mp ðÚ |
137 |
chMtxInit >Ú , mp ðÚ |
| 138 |
chMtxLock IÚ , mp ðÚ chMtxLockS ôÚ , mp ðÚ
chMtxTryLock Ú , mp ðÚ chMtxTryLockS ¯Ú chMtxUnlock bÚ
chMtxUnlockS
Ú chMtxUnlockAll CÚ P _MUTEX_DATA JÚ P MUTEX_DECL Ú P chMtxQueueNotEmptyS Ú P _CHCOND_H_ £Ú 8 CondVar |
138 |
chMtxLock IÚ , mp ðÚ chMtxLockS ôÚ , mp ðÚ
chMtxTryLock Ú , mp ðÚ chMtxTryLockS ¯Ú chMtxUnlock bÚ
chMtxUnlockS
Ú chMtxUnlockAll CÚ P _MUTEX_DATA JÚ P MUTEX_DECL Ú P chMtxQueueNotEmptyS Ú P _CHCOND_H_ £Ú 8 CondVar |
| 139 |
Ú " c_queue 9Ú CondVar FÚ , cp úÚ chCondInit ñÚ , cp úÚ
chCondSignal #Ú , cp úÚ chCondSignalI ØÚ , cp úÚ chCondBroadcast èÚ , cp úÚ chCondBroadcastI Ú , cp úÚ chCondWait ðÚ , cp úÚ chCondWaitS Ú , cp úÚ
, |
139 |
Ú " c_queue 9Ú CondVar FÚ , cp úÚ chCondInit ñÚ , cp úÚ
chCondSignal #Ú , cp úÚ chCondSignalI ØÚ , cp úÚ chCondBroadcast èÚ , cp úÚ chCondBroadcastI Ú , cp úÚ chCondWait ðÚ , cp úÚ chCondWaitS Ú , cp úÚ
, |
| 140 |
time (Ú chCondWaitTimeout ûÚ , cp úÚ
, |
140 |
time (Ú chCondWaitTimeout ûÚ , cp úÚ
, |
| 141 |
time (Ú chCondWaitTimeoutS ¦Ú P _CONDVAR_DATA ÌÚ P
CONDVAR_DECL /Ú P
_CHEVENTS_H_ îÚ 8 EventListener cÚ EventListener Ú " el_next Ú " el_listener pÚ |
141 |
time (Ú chCondWaitTimeoutS ¦Ú P _CONDVAR_DATA ÌÚ P
CONDVAR_DECL /Ú P
_CHEVENTS_H_ îÚ 8 EventListener cÚ EventListener Ú " el_next Ú " el_listener pÚ |
| 142 |
" el_mask @Ú |
142 |
" el_mask @Ú |
| 143 |
" el_flags ÝÚ 8 EventSource <Ú " es_next Ú EventSource xÚ evhandler_t _Ú P _EVENTSOURCE_DATA ~Ú P EVENTSOURCE_DECL áÚ P ALL_EVENTS ªÚ P EVENT_MASK ªÚ P chEvtRegister rÚ P |
143 |
" el_flags ÝÚ 8 EventSource <Ú " es_next Ú EventSource xÚ evhandler_t _Ú P _EVENTSOURCE_DATA ~Ú P EVENTSOURCE_DECL áÚ P ALL_EVENTS ªÚ P EVENT_MASK ªÚ P chEvtRegister rÚ P |
| 144 |
chEvtInit +Ú P chEvtIsListeningI ýÚ P chEvtBroadcast "Ú P chEvtBroadcastI ×Ú , esp Ú , elp Ú
, |
144 |
chEvtInit +Ú P chEvtIsListeningI ýÚ P chEvtBroadcast "Ú P chEvtBroadcastI ×Ú , esp Ú , elp Ú
, |
| 145 |
mask +Ú chEvtRegisterMask ûÚ , esp Ú , elp Ú chEvtUnregister ¨Ú
, |
145 |
mask +Ú chEvtRegisterMask ûÚ , esp Ú , elp Ú chEvtUnregister ¨Ú
, |
| 146 |
mask +Ú chEvtGetAndClearEvents 3Ú
, |
146 |
mask +Ú chEvtGetAndClearEvents 3Ú
, |
| 147 |
mask +Ú chEvtAddEvents TÚ , elp Ú chEvtGetAndClearFlags ½Ú , elp Ú chEvtGetAndClearFlagsI rÚ , tp éÚ
, |
147 |
mask +Ú chEvtAddEvents TÚ , elp Ú chEvtGetAndClearFlags ½Ú , elp Ú chEvtGetAndClearFlagsI rÚ , tp éÚ
, |
| 148 |
mask +Ú chEvtSignal zÚ , tp éÚ
, |
148 |
mask +Ú chEvtSignal zÚ , tp éÚ
, |
| 149 |
mask +Ú
chEvtSignalI /Ú , esp Ú , |
149 |
mask +Ú
chEvtSignalI /Ú , esp Ú , |
| 150 |
flags ÈÚ chEvtBroadcastFlags HÚ , esp Ú , |
150 |
flags ÈÚ chEvtBroadcastFlags HÚ , esp Ú , |
| 151 |
flags ÈÚ chEvtBroadcastFlagsI ýÚ , handlers pÚ
, |
151 |
flags ÈÚ chEvtBroadcastFlagsI ýÚ , handlers pÚ
, |
| 152 |
mask +Ú chEvtDispatch ¤Ú
, |
152 |
mask +Ú chEvtDispatch ¤Ú
, |
| 153 |
mask +Ú
chEvtWaitOne Ú
, |
153 |
mask +Ú
chEvtWaitOne Ú
, |
| 154 |
mask +Ú
chEvtWaitAny Ú
, |
154 |
mask +Ú
chEvtWaitAny Ú
, |
| 155 |
mask +Ú
chEvtWaitAll (Ú
, |
155 |
mask +Ú
chEvtWaitAll (Ú
, |
| 156 |
mask +Ú
, |
156 |
mask +Ú
, |
| 157 |
time (Ú chEvtWaitOneTimeout *Ú
, |
157 |
time (Ú chEvtWaitOneTimeout *Ú
, |
| 158 |
mask +Ú
, |
158 |
mask +Ú
, |
| 159 |
time (Ú chEvtWaitAnyTimeout $Ú
, |
159 |
time (Ú chEvtWaitAnyTimeout $Ú
, |
| 160 |
mask +Ú
, |
160 |
mask +Ú
, |
| 161 |
time (Ú chEvtWaitAllTimeout 3Ú P |
161 |
time (Ú chEvtWaitAllTimeout 3Ú P |
| 162 |
_CHMSG_H_ âÚ P chMsgIsPendingI ñÚ P chMsgGet ©Ú P chMsgReleaseS «Ú , tp éÚ , msg Ú |
162 |
_CHMSG_H_ âÚ P chMsgIsPendingI ñÚ P chMsgGet ©Ú P chMsgReleaseS «Ú , tp éÚ , msg Ú |
| 163 |
chMsgSend ZÚ |
163 |
chMsgSend ZÚ |
| 164 |
chMsgWait OÚ , tp éÚ , msg Ú
chMsgRelease Ú P
_CHMBOXES_H_ õÚ 8 |
164 |
chMsgWait OÚ , tp éÚ , msg Ú
chMsgRelease Ú P
_CHMBOXES_H_ õÚ 8 |
| 165 |
<unnamed> QÚ " æ |
165 |
<unnamed> QÚ " æ |
| 166 |
mb_buffer Ú " æmb_top CÚ " æ mb_wrptr SÚ " æ mb_rdptr fÚ " æ mb_fullsem Ú " æ mb_emptysem Ú Mailbox 'Ú , mbp Ú , buf Ú |
166 |
mb_buffer Ú " æmb_top CÚ " æ mb_wrptr SÚ " æ mb_rdptr fÚ " æ mb_fullsem Ú " æ mb_emptysem Ú Mailbox 'Ú , mbp Ú , buf Ú |
| 167 |
, n qÚ chMBInit êÚ , mbp Ú |
167 |
, n qÚ chMBInit êÚ , mbp Ú |
| 168 |
chMBReset yÚ , mbp Ú , msg Ú , |
168 |
chMBReset yÚ , mbp Ú , msg Ú , |
| 169 |
timeout ÊÚ chMBPost ØÚ , mbp Ú , msg Ú , |
169 |
timeout ÊÚ chMBPost ØÚ , mbp Ú , msg Ú , |
| 170 |
timeout ÊÚ |
170 |
timeout ÊÚ |
| 171 |
chMBPostS Ú , mbp Ú , msg Ú |
171 |
chMBPostS Ú , mbp Ú , msg Ú |
| 172 |
chMBPostI Ú , mbp Ú , msg Ú , |
172 |
chMBPostI Ú , mbp Ú , msg Ú , |
| 173 |
timeout ÊÚ chMBPostAhead ûÚ , mbp Ú , msg Ú , |
173 |
timeout ÊÚ chMBPostAhead ûÚ , mbp Ú , msg Ú , |
| 174 |
timeout ÊÚ chMBPostAheadS ¦Ú , mbp Ú , msg Ú chMBPostAheadI °Ú , mbp Ú
, msgp Ú , |
174 |
timeout ÊÚ chMBPostAheadS ¦Ú , mbp Ú , msg Ú chMBPostAheadI °Ú , mbp Ú
, msgp Ú , |
| 175 |
timeout ÊÚ |
175 |
timeout ÊÚ |
| 176 |
chMBFetch Ú , mbp Ú
, msgp Ú , |
176 |
chMBFetch Ú , mbp Ú
, msgp Ú , |
| 177 |
timeout ÊÚ chMBFetchS =Ú , mbp Ú
, msgp Ú chMBFetchI GÚ P |
177 |
timeout ÊÚ chMBFetchS =Ú , mbp Ú
, msgp Ú chMBFetchI GÚ P |
| 178 |
chMBSizeI {Ú P chMBGetFreeCountI [Ú P chMBGetUsedCountI LÚ P |
178 |
chMBSizeI {Ú P chMBGetFreeCountI [Ú P chMBGetUsedCountI LÚ P |
| 179 |
chMBPeekI Ú P _MAILBOX_DATA ÍÚ P
MAILBOX_DECL 0Ú P _CHMEMCORE_H_ ¹Ú
memgetfunc_t ëÚ P MEM_ALIGN_SIZE lÚ P MEM_ALIGN_MASK {Ú P MEM_ALIGN_PREV jÚ P MEM_ALIGN_NEXT hÚ P MEM_IS_ALIGNED Ú _core_init ¹Ú
, |
179 |
chMBPeekI Ú P _MAILBOX_DATA ÍÚ P
MAILBOX_DECL 0Ú P _CHMEMCORE_H_ ¹Ú
memgetfunc_t ëÚ P MEM_ALIGN_SIZE lÚ P MEM_ALIGN_MASK {Ú P MEM_ALIGN_PREV jÚ P MEM_ALIGN_NEXT hÚ P MEM_IS_ALIGNED Ú _core_init ¹Ú
, |
| 180 |
size Ú chCoreAlloc Ú
, |
180 |
size Ú chCoreAlloc Ú
, |
| 181 |
size Ú
chCoreAllocI HÚ
chCoreStatus øÚ P _CHHEAP_H_ ©Ú 8 memory_heap Ú MemoryHeap öÚ 8 heap_header KÚ (" «align áÚ 8 |
181 |
size Ú
chCoreAllocI HÚ
chCoreStatus øÚ P _CHHEAP_H_ ©Ú 8 memory_heap Ú MemoryHeap öÚ 8 heap_header KÚ (" «align áÚ 8 |
| 182 |
<unnamed> QÚ 8 |
182 |
<unnamed> QÚ 8 |
| 183 |
<unnamed> SÚ " ®next @Ú " ®heap aÚ " u Ú |
183 |
<unnamed> SÚ " ®next @Ú " ®heap aÚ " u Ú |
| 184 |
" size SÚ " «h Ú " © h_provider ÆÚ " ©h_free Ú " ©h_mtx ÒÚ _heap_init ÄÚ , heapp ¹Ú , buf Ú
, |
184 |
" size SÚ " «h Ú " © h_provider ÆÚ " ©h_free Ú " ©h_mtx ÒÚ _heap_init ÄÚ , heapp ¹Ú , buf Ú
, |
| 185 |
size Ú chHeapInit ÷Ú , heapp ¹Ú
, |
185 |
size Ú chHeapInit ÷Ú , heapp ¹Ú
, |
| 186 |
size Ú chHeapAlloc Ú |
186 |
size Ú chHeapAlloc Ú |
| 187 |
, p _Ú chHeapFree Ú , heapp ¹Ú , sizep Ú
chHeapStatus Ú P _CHMEMPOOLS_H_ SÚ 8 pool_header -Ú " Åph_next ìÚ 8 |
187 |
, p _Ú chHeapFree Ú , heapp ¹Ú , sizep Ú
chHeapStatus Ú P _CHMEMPOOLS_H_ SÚ 8 pool_header -Ú " Åph_next ìÚ 8 |
| 188 |
<unnamed> QÚ " Çmp_next åÚ |
188 |
<unnamed> QÚ " Çmp_next åÚ |
| 189 |
" Çmp_object_size Ú " Ç mp_provider 1Ú MemoryPool ÚÚ P _MEMORYPOOL_DATA ÀÚ P MEMORYPOOL_DECL #Ú P |
189 |
" Çmp_object_size Ú " Ç mp_provider 1Ú MemoryPool ÚÚ P _MEMORYPOOL_DATA ÀÚ P MEMORYPOOL_DECL #Ú P |
| 190 |
chPoolAdd KÚ P chPoolAddI Ú , mp ðÚ
, |
190 |
chPoolAdd KÚ P chPoolAddI Ú , mp ðÚ
, |
| 191 |
size Ú , provider VÚ chPoolInit ÛÚ , mp ðÚ |
191 |
size Ú , provider VÚ chPoolInit ÛÚ , mp ðÚ |
| 192 |
, p _Ú |
192 |
, p _Ú |
| 193 |
, |
193 |
, |
| 194 |
n oÚ chPoolLoadArray æÚ , mp ðÚ
chPoolAllocI 7Ú , mp ðÚ chPoolAlloc Ú , mp ðÚ
, objp Ú chPoolFreeI ¢Ú , mp ðÚ
, objp Ú chPoolFree íÚ P _CHTHREADS_H_ ¶Ú P THD_STATE_READY Ú P THD_STATE_CURRENT gÚ P THD_STATE_SUSPENDED ÛÚ P THD_STATE_WTSEM þÚ P THD_STATE_WTMTX êÚ P THD_STATE_WTCOND ½Ú P THD_STATE_SLEEPING 1Ú P THD_STATE_WTEXIT §Ú P THD_STATE_WTOREVT OÚ P THD_STATE_WTANDEVT Ú P THD_STATE_SNDMSGQ mÚ P THD_STATE_SNDMSG ÀÚ P THD_STATE_WTMSG üÚ P THD_STATE_WTQUEUE ZÚ P THD_STATE_FINAL $Ú P THD_STATE_NAMES Ú P THD_MEM_MODE_MASK |Ú P THD_MEM_MODE_STATIC ÜÚ P THD_MEM_MODE_HEAP Ú P THD_MEM_MODE_MEMPOOL Ú P THD_TERMINATE ÉÚ " ®p_next rÚ " ®p_prev tÚ |
194 |
n oÚ chPoolLoadArray æÚ , mp ðÚ
chPoolAllocI 7Ú , mp ðÚ chPoolAlloc Ú , mp ðÚ
, objp Ú chPoolFreeI ¢Ú , mp ðÚ
, objp Ú chPoolFree íÚ P _CHTHREADS_H_ ¶Ú P THD_STATE_READY Ú P THD_STATE_CURRENT gÚ P THD_STATE_SUSPENDED ÛÚ P THD_STATE_WTSEM þÚ P THD_STATE_WTMTX êÚ P THD_STATE_WTCOND ½Ú P THD_STATE_SLEEPING 1Ú P THD_STATE_WTEXIT §Ú P THD_STATE_WTOREVT OÚ P THD_STATE_WTANDEVT Ú P THD_STATE_SNDMSGQ mÚ P THD_STATE_SNDMSG ÀÚ P THD_STATE_WTMSG üÚ P THD_STATE_WTQUEUE ZÚ P THD_STATE_FINAL $Ú P THD_STATE_NAMES Ú P THD_MEM_MODE_MASK |Ú P THD_MEM_MODE_STATIC ÜÚ P THD_MEM_MODE_HEAP Ú P THD_MEM_MODE_MEMPOOL Ú P THD_TERMINATE ÉÚ " ®p_next rÚ " ®p_prev tÚ |
| 195 |
" ®p_prio
Ú " ®p_ctx àÚ " ®p_newer Ú " ®p_older Ú " ®p_name Ú " ®p_state #Ú " ®p_flags 7Ú " ®p_refs Ú " ® |
195 |
" ®p_prio
Ú " ®p_ctx àÚ " ®p_newer Ú " ®p_older Ú " ®p_name Ú " ®p_state #Ú " ®p_flags 7Ú " ®p_refs Ú " ® |
| 196 |
p_preempt CÚ |
196 |
p_preempt CÚ |
| 197 |
" ®p_time Ú 8 |
197 |
" ®p_time Ú 8 |
| 198 |
<unnamed> SÚ " rdymsg Ú " exitcode ÛÚ " wtobjp Ú |
198 |
<unnamed> SÚ " rdymsg Ú " exitcode ÛÚ " wtobjp Ú |
| 199 |
" ewmask ªÚ " ®p_u ÀÚ " ® |
199 |
" ewmask ªÚ " ®p_u ÀÚ " ® |
| 200 |
p_waiting 4Ú " ® p_msgqueue µÚ " ®p_msg üÚ |
200 |
p_waiting 4Ú " ® p_msgqueue µÚ " ®p_msg üÚ |
| 201 |
" ® p_epending íÚ " ® |
201 |
" ® p_epending íÚ " ® |
| 202 |
p_mtxlist Ú |
202 |
p_mtxlist Ú |
| 203 |
" ® p_realprio ÙÚ " ®p_mpool Ú tfunc_t Ú P |
203 |
" ® p_realprio ÙÚ " ®p_mpool Ú tfunc_t Ú P |
| 204 |
chThdSelf DÚ P chThdGetPriority >Ú P chThdGetTicks ¨Ú P chThdLS 3Ú P chThdTerminated µÚ P chThdShouldTerminate Ú P
chThdResumeI Ú P chThdSleepS ~Ú P chThdSleepSeconds öÚ P chThdSleepMilliseconds ÕÚ P chThdSleepMicroseconds ÒÚ , tp éÚ
, |
204 |
chThdSelf DÚ P chThdGetPriority >Ú P chThdGetTicks ¨Ú P chThdLS 3Ú P chThdTerminated µÚ P chThdShouldTerminate Ú P
chThdResumeI Ú P chThdSleepS ~Ú P chThdSleepSeconds öÚ P chThdSleepMilliseconds ÕÚ P chThdSleepMicroseconds ÒÚ , tp éÚ
, |
| 205 |
prio Ú
_thread_init æÚ , wsp qÚ
, |
205 |
prio Ú
_thread_init æÚ , wsp qÚ
, |
| 206 |
size Ú
, |
206 |
size Ú
, |
| 207 |
prio Ú , pf ÷Ú , arg Ú
chThdCreateI HÚ , wsp qÚ
, |
207 |
prio Ú , pf ÷Ú , arg Ú
chThdCreateI HÚ , wsp qÚ
, |
| 208 |
size Ú
, |
208 |
size Ú
, |
| 209 |
prio Ú , pf ÷Ú , arg Ú chThdCreateStatic Ú , |
209 |
prio Ú , pf ÷Ú , arg Ú chThdCreateStatic Ú , |
| 210 |
newprio ÍÚ chThdSetPriority OÚ , tp éÚ chThdResume vÚ , tp éÚ chThdTerminate 8Ú
, |
210 |
newprio ÍÚ chThdSetPriority OÚ , tp éÚ chThdResume vÚ , tp éÚ chThdTerminate 8Ú
, |
| 211 |
time (Ú chThdSleep ðÚ
, |
211 |
time (Ú chThdSleep ðÚ
, |
| 212 |
time (Ú chThdSleepUntil ÚÚ chThdYield òÚ , msg Ú |
212 |
time (Ú chThdSleepUntil ÚÚ chThdYield òÚ , msg Ú |
| 213 |
chThdExit QÚ , msg Ú chThdExitS üÚ , tp éÚ |
213 |
chThdExit QÚ , msg Ú chThdExitS üÚ , tp éÚ |
| 214 |
chThdWait VÚ P _CHDYNAMIC_H_ ¼Ú , tp éÚ chThdAddRef ÁÚ , tp éÚ
chThdRelease $Ú , heapp ¹Ú
, |
214 |
chThdWait VÚ P _CHDYNAMIC_H_ ¼Ú , tp éÚ chThdAddRef ÁÚ , tp éÚ
chThdRelease $Ú , heapp ¹Ú
, |
| 215 |
size Ú
, |
215 |
size Ú
, |
| 216 |
prio Ú , pf ÷Ú , arg Ú chThdCreateFromHeap qÚ , mp ðÚ
, |
216 |
prio Ú , pf ÷Ú , arg Ú chThdCreateFromHeap qÚ , mp ðÚ
, |
| 217 |
prio Ú , pf ÷Ú , arg Ú" chThdCreateFromMemoryPool ÐÚ P _CHREGISTRY_H_ FÚ 8 |
217 |
prio Ú , pf ÷Ú , arg Ú" chThdCreateFromMemoryPool ÐÚ P _CHREGISTRY_H_ FÚ 8 |
| 218 |
<unnamed> QÚ <" Îch_identifier [Ú " Îch_zero Ú " Îch_size Ú " Î ch_version ®Ú " Î ch_ptrsize ¬Ú " Î ch_timesize QÚ " Îch_threadsize Ú " Î cf_off_prio iÚ " Î cf_off_ctx ÖÚ " Î
cf_off_newer Ú " Î
cf_off_older Ú " Î cf_off_name Ú " Îcf_off_stklimit ªÚ " Î
cf_off_state Ú " Î
cf_off_flags Ú " Î cf_off_refs sÚ " Îcf_off_preempt Ú " Î cf_off_time tÚ |
218 |
<unnamed> QÚ <" Îch_identifier [Ú " Îch_zero Ú " Îch_size Ú " Î ch_version ®Ú " Î ch_ptrsize ¬Ú " Î ch_timesize QÚ " Îch_threadsize Ú " Î cf_off_prio iÚ " Î cf_off_ctx ÖÚ " Î
cf_off_newer Ú " Î
cf_off_older Ú " Î cf_off_name Ú " Îcf_off_stklimit ªÚ " Î
cf_off_state Ú " Î
cf_off_flags Ú " Î cf_off_refs sÚ " Îcf_off_preempt Ú " Î cf_off_time tÚ |
| 219 |
chdebug_t JÚ P chRegSetThreadName ¹Ú P chRegGetThreadName ÅÚ P REG_REMOVE ¬Ú P REG_INSERT ¥Ú ch_debug Ú chRegFirstThread Ú , tp éÚ chRegNextThread êÚ P
_CHINLINE_H_ Ú prio_insert 0Ú
," ëtp ÕÚ ," ëtqp bÚ
" ëcp |
219 |
chdebug_t JÚ P chRegSetThreadName ¹Ú P chRegGetThreadName ÅÚ P REG_REMOVE ¬Ú P REG_INSERT ¥Ú ch_debug Ú chRegFirstThread Ú , tp éÚ chRegNextThread êÚ P
_CHINLINE_H_ Ú prio_insert 0Ú
," ëtp ÕÚ ," ëtqp bÚ
" ëcp |
| 220 |
Ú
queue_insert ÃÚ
," ïtp ÑÚ ," ïtqp ^Ú fifo_remove MÚ ," òtqp [Ú
" òtp òÚ lifo_remove GÚ ," õtqp XÚ
" õtp ïÚ dequeue øÚ
," øtp ÈÚ list_insert .Ú
," útp ÆÚ ," útlp XÚ list_remove 5Ú ," ýtlp UÚ
" ýtp çÚ P
_CHQUEUES_H_ ëÚ
P Q_OK yÚ P |
220 |
Ú
queue_insert ÃÚ
," ïtp ÑÚ ," ïtqp ^Ú fifo_remove MÚ ," òtqp [Ú
" òtp òÚ lifo_remove GÚ ," õtqp XÚ
" õtp ïÚ dequeue øÚ
," øtp ÈÚ list_insert .Ú
," útp ÆÚ ," útlp XÚ list_remove 5Ú ," ýtlp UÚ
" ýtp çÚ P
_CHQUEUES_H_ ëÚ
P Q_OK yÚ P |
| 221 |
Q_TIMEOUT âÚ P Q_RESET Ú P Q_EMPTY ~Ú P Q_FULL ÜÚ 8
GenericQueue ëÚ
GenericQueue 'Ú |
221 |
Q_TIMEOUT âÚ P Q_RESET Ú P Q_EMPTY ~Ú P Q_FULL ÜÚ 8
GenericQueue ëÚ
GenericQueue 'Ú |
| 222 |
qnotify_t Ú " |
222 |
qnotify_t Ú " |
| 223 |
q_waiting PÚ |
223 |
q_waiting PÚ |
| 224 |
" |
224 |
" |
| 225 |
q_counter YÚ " q_buffer ÓÚ " q_top Ú " q_wrptr Ú " q_rdptr #Ú " q_notify ´Ú " q_link £Ú P chQSizeI »Ú P |
225 |
q_counter YÚ " q_buffer ÓÚ " q_top Ú " q_wrptr Ú " q_rdptr #Ú " q_notify ´Ú " q_link £Ú P chQSizeI »Ú P |
| 226 |
chQSpaceI hÚ P chQGetLink íÚ InputQueue ØÚ P
chIQGetFullI RÚ P chIQGetEmptyI ÔÚ P
chIQIsEmptyI :Ú P chIQIsFullI ¸Ú P chIQGet 8Ú P _INPUTQUEUE_DATA ¾Ú P INPUTQUEUE_DECL !Ú OutputQueue UÚ P
chOQGetFullI LÚ P chOQGetEmptyI ÎÚ P
chOQIsEmptyI 4Ú P chOQIsFullI ²Ú P chOQPut Ú P _OUTPUTQUEUE_DATA [Ú P OUTPUTQUEUE_DECL ¾Ú , iqp Ú , bp ûÚ
, |
226 |
chQSpaceI hÚ P chQGetLink íÚ InputQueue ØÚ P
chIQGetFullI RÚ P chIQGetEmptyI ÔÚ P
chIQIsEmptyI :Ú P chIQIsFullI ¸Ú P chIQGet 8Ú P _INPUTQUEUE_DATA ¾Ú P INPUTQUEUE_DECL !Ú OutputQueue UÚ P
chOQGetFullI LÚ P chOQGetEmptyI ÎÚ P
chOQIsEmptyI 4Ú P chOQIsFullI ²Ú P chOQPut Ú P _OUTPUTQUEUE_DATA [Ú P OUTPUTQUEUE_DECL ¾Ú , iqp Ú , bp ûÚ
, |
| 227 |
size Ú
, infy Ú
, link Ú chIQInit ßÚ , iqp Ú chIQResetI #Ú , iqp Ú |
227 |
size Ú
, infy Ú
, link Ú chIQInit ßÚ , iqp Ú chIQResetI #Ú , iqp Ú |
| 228 |
, b Ú chIQPutI ñÚ , iqp Ú
, |
228 |
, b Ú chIQPutI ñÚ , iqp Ú
, |
| 229 |
time (Ú chIQGetTimeout `Ú , iqp Ú , bp ûÚ |
229 |
time (Ú chIQGetTimeout `Ú , iqp Ú , bp ûÚ |
| 230 |
, |
230 |
, |
| 231 |
n oÚ
, |
231 |
n oÚ
, |
| 232 |
time (Ú chIQReadTimeout Ú , oqp {Ú , bp ûÚ
, |
232 |
time (Ú chIQReadTimeout Ú , oqp {Ú , bp ûÚ
, |
| 233 |
size Ú
, onfy
Ú
, link Ú chOQInit ÙÚ , oqp {Ú chOQResetI Ú , oqp {Ú |
233 |
size Ú
, onfy
Ú
, link Ú chOQInit ÙÚ , oqp {Ú chOQResetI Ú , oqp {Ú |
| 234 |
, b Ú
, |
234 |
, b Ú
, |
| 235 |
time (Ú chOQPutTimeout AÚ , oqp {Ú chOQGetI Ú , oqp {Ú , bp ûÚ |
235 |
time (Ú chOQPutTimeout AÚ , oqp {Ú chOQGetI Ú , oqp {Ú , bp ûÚ |
| 236 |
, |
236 |
, |
| 237 |
n oÚ
, |
237 |
n oÚ
, |
| 238 |
time (Ú chOQWriteTimeout kÚ P _CHSTREAMS_H_ ¢Ú( P _base_sequential_stream_methods »Ú% P _base_sequential_stream_data Ú 8 BaseSequentialStreamVMT Ú " Íwrite ±Ú " Íread BÚ " Íput Ú " Íget Ú 8 |
238 |
time (Ú chOQWriteTimeout kÚ P _CHSTREAMS_H_ ¢Ú( P _base_sequential_stream_methods »Ú% P _base_sequential_stream_data Ú 8 BaseSequentialStreamVMT Ú " Íwrite ±Ú " Íread BÚ " Íput Ú " Íget Ú 8 |
| 239 |
<unnamed> QÚ " Òvmt Ú BaseSequentialStream ×Ú P chSequentialStreamWrite @Ú P chSequentialStreamRead ÑÚ P chSequentialStreamPut Ú P chSequentialStreamGet /Ú P _CHFILES_H_ RÚ P FILE_OK ¤Ú P FILE_ERROR ®Ú
fileoffset_t ïÚ" P _base_file_stream_methods bÚ P _base_file_stream_data ÂÚ 8 BaseFileStreamVMT EÚ " ßwrite Ú " ßread 0Ú " ßput uÚ " ßget Ú " ßclose ´Ú " ß geterror ZÚ " ßgetsize ËÚ " ß getposition Ú " ßlseek ¶Ú 8 |
239 |
<unnamed> QÚ " Òvmt Ú BaseSequentialStream ×Ú P chSequentialStreamWrite @Ú P chSequentialStreamRead ÑÚ P chSequentialStreamPut Ú P chSequentialStreamGet /Ú P _CHFILES_H_ RÚ P FILE_OK ¤Ú P FILE_ERROR ®Ú
fileoffset_t ïÚ" P _base_file_stream_methods bÚ P _base_file_stream_data ÂÚ 8 BaseFileStreamVMT EÚ " ßwrite Ú " ßread 0Ú " ßput uÚ " ßget Ú " ßclose ´Ú " ß geterror ZÚ " ßgetsize ËÚ " ß getposition Ú " ßlseek ¶Ú 8 |
| 240 |
<unnamed> QÚ " évmt mÚ BaseFileStream ~Ú P chFileStreamClose üÚ P chFileStreamGetError ÂÚ P chFileStreamGetSize 3Ú P chFileStreamGetPosition qÚ P chFileStreamSeek lÚ P _CHDEBUG_H_ ^Ú P CH_DBG_ENABLED ®Ú P
__QUOTE_THIS ÐÚ P CH_TRACE_BUFFER_SIZE Ú P CH_STACK_FILL_VALUE ãÚ P CH_THREAD_FILL_VALUE Ú P dbg_enter_lock ýÚ P dbg_leave_lock Ú P dbg_check_disable ìÚ P dbg_check_suspend ¾Ú P dbg_check_enable [Ú P dbg_check_lock Ú P dbg_check_unlock 6Ú P dbg_check_lock_from_isr KÚ" P dbg_check_unlock_from_isr dÚ P dbg_check_enter_isr ñÚ P dbg_check_leave_isr Ú P chDbgCheckClassI ¶Ú P chDbgCheckClassS ¬Ú P |
240 |
<unnamed> QÚ " évmt mÚ BaseFileStream ~Ú P chFileStreamClose üÚ P chFileStreamGetError ÂÚ P chFileStreamGetSize 3Ú P chFileStreamGetPosition qÚ P chFileStreamSeek lÚ P _CHDEBUG_H_ ^Ú P CH_DBG_ENABLED ®Ú P
__QUOTE_THIS ÐÚ P CH_TRACE_BUFFER_SIZE Ú P CH_STACK_FILL_VALUE ãÚ P CH_THREAD_FILL_VALUE Ú P dbg_enter_lock ýÚ P dbg_leave_lock Ú P dbg_check_disable ìÚ P dbg_check_suspend ¾Ú P dbg_check_enable [Ú P dbg_check_lock Ú P dbg_check_unlock 6Ú P dbg_check_lock_from_isr KÚ" P dbg_check_unlock_from_isr dÚ P dbg_check_enter_isr ñÚ P dbg_check_leave_isr Ú P chDbgCheckClassI ¶Ú P chDbgCheckClassS ¬Ú P |
| 241 |
dbg_trace Ú P chDbgCheck Ú P chDbgAssert kÚ P chDbgPanic ôÚ < À_idle_thread_wa âÚ |
241 |
dbg_trace Ú P chDbgCheck Ú P chDbgAssert kÚ P chDbgPanic ôÚ < À_idle_thread_wa âÚ |
| 242 |
, p _Ú
_idle_thread üÚ P _HAL_H_ Ú P |
242 |
, p _Ú
_idle_thread üÚ P _HAL_H_ Ú P |
| 243 |
_BOARD_H_ ìÚ" P BOARD_ST_STM32L_DISCOVERY Ú P BOARD_NAME ÏÚ P
STM32_LSECLK =Ú P
STM32_HSECLK AÚ P STM32_HSE_BYPASS âÚ P
STM32L1XX_MD =Ú P
GPIOA_BUTTON Ú P GPIOA_PIN1 ÐÚ P GPIOA_PIN2 ÏÚ P GPIOA_PIN3 ÎÚ P GPIOA_PIN4 ÍÚ P GPIOA_PIN5 ÌÚ P GPIOA_PIN6 ËÚ P GPIOA_PIN7 ÊÚ P GPIOA_PIN8 ÉÚ P GPIOA_PIN9 ÈÚ P GPIOA_PIN10 Ú P GPIOA_PIN11 Ú P GPIOA_PIN12 Ú P GPIOA_JTAG_TMS gÚ P GPIOA_JTAG_TCK yÚ P GPIOA_JTAG_TDI zÚ P GPIOB_PIN0 ÐÚ P GPIOB_PIN1 ÏÚ P GPIOB_BOOT1 Ú P GPIOB_JTAG_TDO sÚ P GPIOB_JTAG_TRST Ú P GPIOB_PIN5 ËÚ P GPIOB_LED4 ÞÚ P GPIOB_LED3 ßÚ P GPIOB_PIN8 ÈÚ P GPIOB_PIN9 ÇÚ P GPIOB_PIN10 Ú P GPIOB_PIN11 Ú P GPIOB_PIN12 Ú P GPIOB_PIN13 Ú P GPIOB_PIN14 Ú P GPIOB_PIN15 Ú P GPIOC_PIN0 ÏÚ P GPIOC_PIN1 ÎÚ P GPIOC_PIN2 ÍÚ P GPIOC_PIN3 ÌÚ P GPIOC_PIN4 ËÚ P GPIOC_PIN5 ÊÚ P GPIOC_PIN6 ÉÚ P GPIOC_PIN7 ÈÚ P GPIOC_PIN8 ÇÚ P GPIOC_PIN9 ÆÚ P GPIOC_PIN10 Ú P GPIOC_PIN11 Ú P GPIOC_PIN12 Ú P GPIOC_PIN13 Ú P GPIOC_OSC32_IN Ú P GPIOC_OSC32_OUT ;Ú P GPIOD_PIN0 ÎÚ P GPIOD_PIN1 ÍÚ P GPIOD_PIN2 ÌÚ P GPIOD_PIN3 ËÚ P GPIOD_PIN4 ÊÚ P GPIOD_PIN5 ÉÚ P GPIOD_PIN6 ÈÚ P GPIOD_PIN7 ÇÚ P GPIOD_PIN8 ÆÚ P GPIOD_PIN9 ÅÚ P GPIOD_PIN10 Ú P GPIOD_PIN11 Ú P GPIOD_PIN12 Ú P GPIOD_PIN13 Ú P GPIOD_PIN14 Ú P GPIOD_PIN15 Ú P GPIOE_PIN0 ÍÚ P GPIOE_PIN1 ÌÚ P GPIOE_PIN2 ËÚ P GPIOE_PIN3 ÊÚ P GPIOE_PIN4 ÉÚ P GPIOE_PIN5 ÈÚ P GPIOE_PIN6 ÇÚ P GPIOE_PIN7 ÆÚ P GPIOE_PIN8 ÅÚ P GPIOE_PIN9 ÄÚ P GPIOE_PIN10 Ú P GPIOE_PIN11 Ú P GPIOE_PIN12 Ú P GPIOE_PIN13 Ú P GPIOE_PIN14 Ú P GPIOE_PIN15 Ú P
GPIOH_OSC_IN Ú P GPIOH_OSC_OUT Ú P GPIOH_PIN2 ÈÚ P GPIOH_PIN3 ÇÚ P GPIOH_PIN4 ÆÚ P GPIOH_PIN5 ÅÚ P GPIOH_PIN6 ÄÚ P GPIOH_PIN7 ÃÚ P GPIOH_PIN8 ÂÚ P GPIOH_PIN9 ÁÚ P GPIOH_PIN10 Ú P GPIOH_PIN11 Ú P GPIOH_PIN12 Ú P GPIOH_PIN13 Ú P GPIOH_PIN14 Ú P GPIOH_PIN15 Ú P PIN_MODE_INPUT UÚ P PIN_MODE_OUTPUT òÚ P PIN_MODE_ALTERNATE =Ú P PIN_MODE_ANALOG 1Ú P PIN_ODR_LOW 9Ú P
PIN_ODR_HIGH Ú P PIN_OTYPE_PUSHPULL ôÚ P PIN_OTYPE_OPENDRAIN ÏÚ P PIN_OSPEED_400K iÚ P PIN_OSPEED_2M ÍÚ P PIN_OSPEED_10M Ú P PIN_OSPEED_40M Ú P PIN_PUPDR_FLOATING #Ú P PIN_PUPDR_PULLUP Ú P PIN_PUPDR_PULLDOWN Ú P PIN_AFIO_AF jÚ P VAL_GPIOA_MODER %Ú P VAL_GPIOA_OTYPER ·Ú P VAL_GPIOA_OSPEEDR Ú P VAL_GPIOA_PUPDR Ú P VAL_GPIOA_ODR »Ú P VAL_GPIOA_AFRL yÚ P VAL_GPIOA_AFRH }Ú P VAL_GPIOB_MODER $Ú P VAL_GPIOB_OTYPER ¶Ú P VAL_GPIOB_OSPEEDR
Ú P VAL_GPIOB_PUPDR Ú P VAL_GPIOB_ODR ºÚ P VAL_GPIOB_AFRL xÚ P VAL_GPIOB_AFRH |Ú P VAL_GPIOC_MODER #Ú P VAL_GPIOC_OTYPER µÚ P VAL_GPIOC_OSPEEDR Ú P VAL_GPIOC_PUPDR Ú P VAL_GPIOC_ODR ¹Ú P VAL_GPIOC_AFRL wÚ P VAL_GPIOC_AFRH {Ú P VAL_GPIOD_MODER "Ú P VAL_GPIOD_OTYPER ´Ú P VAL_GPIOD_OSPEEDR Ú P VAL_GPIOD_PUPDR Ú P VAL_GPIOD_ODR ¸Ú P VAL_GPIOD_AFRL vÚ P VAL_GPIOD_AFRH zÚ P VAL_GPIOE_MODER !Ú P VAL_GPIOE_OTYPER ³Ú P VAL_GPIOE_OSPEEDR Ú P VAL_GPIOE_PUPDR
Ú P VAL_GPIOE_ODR ·Ú P VAL_GPIOE_AFRL uÚ P VAL_GPIOE_AFRH yÚ P VAL_GPIOH_MODER Ú P VAL_GPIOH_OTYPER °Ú P VAL_GPIOH_OSPEEDR Ú P VAL_GPIOH_PUPDR |
243 |
_BOARD_H_ ìÚ" P BOARD_ST_STM32L_DISCOVERY Ú P BOARD_NAME ÏÚ P
STM32_LSECLK =Ú P
STM32_HSECLK AÚ P STM32_HSE_BYPASS âÚ P
STM32L1XX_MD =Ú P
GPIOA_BUTTON Ú P GPIOA_PIN1 ÐÚ P GPIOA_PIN2 ÏÚ P GPIOA_PIN3 ÎÚ P GPIOA_PIN4 ÍÚ P GPIOA_PIN5 ÌÚ P GPIOA_PIN6 ËÚ P GPIOA_PIN7 ÊÚ P GPIOA_PIN8 ÉÚ P GPIOA_PIN9 ÈÚ P GPIOA_PIN10 Ú P GPIOA_PIN11 Ú P GPIOA_PIN12 Ú P GPIOA_JTAG_TMS gÚ P GPIOA_JTAG_TCK yÚ P GPIOA_JTAG_TDI zÚ P GPIOB_PIN0 ÐÚ P GPIOB_PIN1 ÏÚ P GPIOB_BOOT1 Ú P GPIOB_JTAG_TDO sÚ P GPIOB_JTAG_TRST Ú P GPIOB_PIN5 ËÚ P GPIOB_LED4 ÞÚ P GPIOB_LED3 ßÚ P GPIOB_PIN8 ÈÚ P GPIOB_PIN9 ÇÚ P GPIOB_PIN10 Ú P GPIOB_PIN11 Ú P GPIOB_PIN12 Ú P GPIOB_PIN13 Ú P GPIOB_PIN14 Ú P GPIOB_PIN15 Ú P GPIOC_PIN0 ÏÚ P GPIOC_PIN1 ÎÚ P GPIOC_PIN2 ÍÚ P GPIOC_PIN3 ÌÚ P GPIOC_PIN4 ËÚ P GPIOC_PIN5 ÊÚ P GPIOC_PIN6 ÉÚ P GPIOC_PIN7 ÈÚ P GPIOC_PIN8 ÇÚ P GPIOC_PIN9 ÆÚ P GPIOC_PIN10 Ú P GPIOC_PIN11 Ú P GPIOC_PIN12 Ú P GPIOC_PIN13 Ú P GPIOC_OSC32_IN Ú P GPIOC_OSC32_OUT ;Ú P GPIOD_PIN0 ÎÚ P GPIOD_PIN1 ÍÚ P GPIOD_PIN2 ÌÚ P GPIOD_PIN3 ËÚ P GPIOD_PIN4 ÊÚ P GPIOD_PIN5 ÉÚ P GPIOD_PIN6 ÈÚ P GPIOD_PIN7 ÇÚ P GPIOD_PIN8 ÆÚ P GPIOD_PIN9 ÅÚ P GPIOD_PIN10 Ú P GPIOD_PIN11 Ú P GPIOD_PIN12 Ú P GPIOD_PIN13 Ú P GPIOD_PIN14 Ú P GPIOD_PIN15 Ú P GPIOE_PIN0 ÍÚ P GPIOE_PIN1 ÌÚ P GPIOE_PIN2 ËÚ P GPIOE_PIN3 ÊÚ P GPIOE_PIN4 ÉÚ P GPIOE_PIN5 ÈÚ P GPIOE_PIN6 ÇÚ P GPIOE_PIN7 ÆÚ P GPIOE_PIN8 ÅÚ P GPIOE_PIN9 ÄÚ P GPIOE_PIN10 Ú P GPIOE_PIN11 Ú P GPIOE_PIN12 Ú P GPIOE_PIN13 Ú P GPIOE_PIN14 Ú P GPIOE_PIN15 Ú P
GPIOH_OSC_IN Ú P GPIOH_OSC_OUT Ú P GPIOH_PIN2 ÈÚ P GPIOH_PIN3 ÇÚ P GPIOH_PIN4 ÆÚ P GPIOH_PIN5 ÅÚ P GPIOH_PIN6 ÄÚ P GPIOH_PIN7 ÃÚ P GPIOH_PIN8 ÂÚ P GPIOH_PIN9 ÁÚ P GPIOH_PIN10 Ú P GPIOH_PIN11 Ú P GPIOH_PIN12 Ú P GPIOH_PIN13 Ú P GPIOH_PIN14 Ú P GPIOH_PIN15 Ú P PIN_MODE_INPUT UÚ P PIN_MODE_OUTPUT òÚ P PIN_MODE_ALTERNATE =Ú P PIN_MODE_ANALOG 1Ú P PIN_ODR_LOW 9Ú P
PIN_ODR_HIGH Ú P PIN_OTYPE_PUSHPULL ôÚ P PIN_OTYPE_OPENDRAIN ÏÚ P PIN_OSPEED_400K iÚ P PIN_OSPEED_2M ÍÚ P PIN_OSPEED_10M Ú P PIN_OSPEED_40M Ú P PIN_PUPDR_FLOATING #Ú P PIN_PUPDR_PULLUP Ú P PIN_PUPDR_PULLDOWN Ú P PIN_AFIO_AF jÚ P VAL_GPIOA_MODER %Ú P VAL_GPIOA_OTYPER ·Ú P VAL_GPIOA_OSPEEDR Ú P VAL_GPIOA_PUPDR Ú P VAL_GPIOA_ODR »Ú P VAL_GPIOA_AFRL yÚ P VAL_GPIOA_AFRH }Ú P VAL_GPIOB_MODER $Ú P VAL_GPIOB_OTYPER ¶Ú P VAL_GPIOB_OSPEEDR
Ú P VAL_GPIOB_PUPDR Ú P VAL_GPIOB_ODR ºÚ P VAL_GPIOB_AFRL xÚ P VAL_GPIOB_AFRH |Ú P VAL_GPIOC_MODER #Ú P VAL_GPIOC_OTYPER µÚ P VAL_GPIOC_OSPEEDR Ú P VAL_GPIOC_PUPDR Ú P VAL_GPIOC_ODR ¹Ú P VAL_GPIOC_AFRL wÚ P VAL_GPIOC_AFRH {Ú P VAL_GPIOD_MODER "Ú P VAL_GPIOD_OTYPER ´Ú P VAL_GPIOD_OSPEEDR Ú P VAL_GPIOD_PUPDR Ú P VAL_GPIOD_ODR ¸Ú P VAL_GPIOD_AFRL vÚ P VAL_GPIOD_AFRH zÚ P VAL_GPIOE_MODER !Ú P VAL_GPIOE_OTYPER ³Ú P VAL_GPIOE_OSPEEDR Ú P VAL_GPIOE_PUPDR
Ú P VAL_GPIOE_ODR ·Ú P VAL_GPIOE_AFRL uÚ P VAL_GPIOE_AFRH yÚ P VAL_GPIOH_MODER Ú P VAL_GPIOH_OTYPER °Ú P VAL_GPIOH_OSPEEDR Ú P VAL_GPIOH_PUPDR |
| 244 |
Ú P VAL_GPIOH_ODR ´Ú P VAL_GPIOH_AFRL rÚ P VAL_GPIOH_AFRH vÚ |
244 |
Ú P VAL_GPIOH_ODR ´Ú P VAL_GPIOH_AFRL rÚ P VAL_GPIOH_AFRH vÚ |
| 245 |
boardInit :Ú P _HALCONF_H_ UÚ P STM32L1xx_MCUCONF yÚ P STM32_NO_INIT ÉÚ P STM32_HSI_ENABLED ÃÚ P STM32_LSI_ENABLED ¿Ú P STM32_HSE_ENABLED ÇÚ P STM32_LSE_ENABLED ÃÚ P STM32_ADC_CLOCK_ENABLED Ú P STM32_USB_CLOCK_ENABLED æÚ P STM32_MSIRANGE ¡Ú P STM32_SW YÚ P
STM32_PLLSRC +Ú P STM32_PLLMUL_VALUE =Ú P STM32_PLLDIV_VALUE HÚ P STM32_HPRE ÐÚ P STM32_PPRE1 Ú P STM32_PPRE2 Ú P
STM32_MCOSEL 8Ú P
STM32_MCOPRE 5Ú P
STM32_RTCSEL .Ú P
STM32_RTCPRE +Ú P |
245 |
boardInit :Ú P _HALCONF_H_ UÚ P STM32L1xx_MCUCONF yÚ P STM32_NO_INIT ÉÚ P STM32_HSI_ENABLED ÃÚ P STM32_LSI_ENABLED ¿Ú P STM32_HSE_ENABLED ÇÚ P STM32_LSE_ENABLED ÃÚ P STM32_ADC_CLOCK_ENABLED Ú P STM32_USB_CLOCK_ENABLED æÚ P STM32_MSIRANGE ¡Ú P STM32_SW YÚ P
STM32_PLLSRC +Ú P STM32_PLLMUL_VALUE =Ú P STM32_PLLDIV_VALUE HÚ P STM32_HPRE ÐÚ P STM32_PPRE1 Ú P STM32_PPRE2 Ú P
STM32_MCOSEL 8Ú P
STM32_MCOPRE 5Ú P
STM32_RTCSEL .Ú P
STM32_RTCPRE +Ú P |
| 246 |
STM32_VOS Ú P STM32_PVD_ENABLE Ú P |
246 |
STM32_VOS Ú P STM32_PVD_ENABLE Ú P |
| 247 |
STM32_PLS Ú P STM32_ADC_USE_ADC1 Ú$ P STM32_ADC_ADC1_DMA_PRIORITY «Ú P STM32_ADC_IRQ_PRIORITY óÚ( P STM32_ADC_ADC1_DMA_IRQ_PRIORITY XÚ% P STM32_EXT_EXTI0_IRQ_PRIORITY õÚ% P STM32_EXT_EXTI1_IRQ_PRIORITY ôÚ% P STM32_EXT_EXTI2_IRQ_PRIORITY óÚ% P STM32_EXT_EXTI3_IRQ_PRIORITY òÚ% P STM32_EXT_EXTI4_IRQ_PRIORITY ñÚ' P STM32_EXT_EXTI5_9_IRQ_PRIORITY TÚ) P !STM32_EXT_EXTI10_15_IRQ_PRIORITY ÷Ú& P STM32_EXT_EXTI16_IRQ_PRIORITY ¼Ú& P STM32_EXT_EXTI17_IRQ_PRIORITY »Ú& P STM32_EXT_EXTI18_IRQ_PRIORITY ºÚ& P STM32_EXT_EXTI19_IRQ_PRIORITY ¹Ú& P STM32_EXT_EXTI20_IRQ_PRIORITY ÁÚ) P !STM32_EXT_EXTI21_22_IRQ_PRIORITY ÷Ú P STM32_GPT_USE_TIM2 =Ú P STM32_GPT_USE_TIM3 <Ú P STM32_GPT_USE_TIM4 ;Ú$ P STM32_GPT_TIM2_IRQ_PRIORITY KÚ$ P STM32_GPT_TIM3_IRQ_PRIORITY JÚ$ P STM32_GPT_TIM4_IRQ_PRIORITY IÚ P STM32_I2C_USE_I2C1 Ú P STM32_I2C_USE_I2C2 Ú$ P STM32_I2C_I2C1_IRQ_PRIORITY ¥Ú$ P STM32_I2C_I2C2_IRQ_PRIORITY ¤Ú$ P STM32_I2C_I2C1_DMA_PRIORITY ¿Ú$ P STM32_I2C_I2C2_DMA_PRIORITY ¾Ú& P STM32_I2C_I2C1_DMA_ERROR_HOOK #Ú& P STM32_I2C_I2C2_DMA_ERROR_HOOK "Ú P STM32_ICU_USE_TIM2 GÚ P STM32_ICU_USE_TIM3 FÚ P STM32_ICU_USE_TIM4 EÚ$ P STM32_ICU_TIM2_IRQ_PRIORITY UÚ$ P STM32_ICU_TIM3_IRQ_PRIORITY TÚ$ P STM32_ICU_TIM4_IRQ_PRIORITY SÚ P STM32_PWM_USE_TIM2 4Ú P STM32_PWM_USE_TIM3 3Ú P STM32_PWM_USE_TIM4 2Ú$ P STM32_PWM_TIM2_IRQ_PRIORITY BÚ$ P STM32_PWM_TIM3_IRQ_PRIORITY AÚ$ P STM32_PWM_TIM4_IRQ_PRIORITY @Ú P STM32_SERIAL_USE_USART1 ºÚ P STM32_SERIAL_USE_USART2 ¹Ú P STM32_SERIAL_USE_USART3 ¸Ú% P STM32_SERIAL_USART1_PRIORITY Ú% P STM32_SERIAL_USART2_PRIORITY Ú% P STM32_SERIAL_USART3_PRIORITY Ú P STM32_SPI_USE_SPI1 ;Ú P STM32_SPI_USE_SPI2 :Ú$ P STM32_SPI_SPI1_DMA_PRIORITY cÚ$ P STM32_SPI_SPI2_DMA_PRIORITY bÚ$ P STM32_SPI_SPI1_IRQ_PRIORITY IÚ$ P STM32_SPI_SPI2_IRQ_PRIORITY HÚ! P STM32_SPI_DMA_ERROR_HOOK MÚ P STM32_UART_USE_USART1 BÚ P STM32_UART_USE_USART2 AÚ P STM32_UART_USE_USART3 @Ú' P STM32_UART_USART1_IRQ_PRIORITY PÚ' P STM32_UART_USART2_IRQ_PRIORITY OÚ' P STM32_UART_USART3_IRQ_PRIORITY NÚ' P STM32_UART_USART1_DMA_PRIORITY jÚ' P STM32_UART_USART2_DMA_PRIORITY iÚ' P STM32_UART_USART3_DMA_PRIORITY hÚ" P STM32_UART_DMA_ERROR_HOOK ûÚ P STM32_USB_USE_USB1 ?Ú' P STM32_USB_LOW_POWER_ON_SUSPEND 3Ú' P STM32_USB_USB1_HP_IRQ_PRIORITY PÚ' P STM32_USB_USB1_LP_IRQ_PRIORITY LÚ P HAL_USE_TM Ú P HAL_USE_PAL XÚ P HAL_USE_ADC mÚ P HAL_USE_CAN cÚ P HAL_USE_EXT DÚ P HAL_USE_GPT JÚ P HAL_USE_I2C wÚ P HAL_USE_ICU TÚ P HAL_USE_MAC dÚ P HAL_USE_MMC_SPI Ú P HAL_USE_PWM AÚ P HAL_USE_RTC LÚ P HAL_USE_SDC [Ú P HAL_USE_SERIAL oÚ P HAL_USE_SERIAL_USB Ú P HAL_USE_SPI IÚ P
HAL_USE_UART ÷Ú P HAL_USE_USB KÚ P
ADC_USE_WAIT Ú! P ADC_USE_MUTUAL_EXCLUSION 7Ú P CAN_USE_SLEEP_MODE -Ú! P I2C_USE_MUTUAL_EXCLUSION AÚ P MAC_USE_ZERO_COPY SÚ P MAC_USE_EVENTS ^Ú P MMC_NICE_WAITING ÞÚ P SDC_INIT_RETRY MÚ P SDC_MMC_SUPPORT ûÚ P SDC_NICE_WAITING áÚ P SERIAL_DEFAULT_BITRATE Ú P SERIAL_BUFFERS_SIZE ßÚ P
SPI_USE_WAIT çÚ! P SPI_USE_MUTUAL_EXCLUSION Ú P _HAL_LLD_H_ @Ú P |
247 |
STM32_PLS Ú P STM32_ADC_USE_ADC1 Ú$ P STM32_ADC_ADC1_DMA_PRIORITY «Ú P STM32_ADC_IRQ_PRIORITY óÚ( P STM32_ADC_ADC1_DMA_IRQ_PRIORITY XÚ% P STM32_EXT_EXTI0_IRQ_PRIORITY õÚ% P STM32_EXT_EXTI1_IRQ_PRIORITY ôÚ% P STM32_EXT_EXTI2_IRQ_PRIORITY óÚ% P STM32_EXT_EXTI3_IRQ_PRIORITY òÚ% P STM32_EXT_EXTI4_IRQ_PRIORITY ñÚ' P STM32_EXT_EXTI5_9_IRQ_PRIORITY TÚ) P !STM32_EXT_EXTI10_15_IRQ_PRIORITY ÷Ú& P STM32_EXT_EXTI16_IRQ_PRIORITY ¼Ú& P STM32_EXT_EXTI17_IRQ_PRIORITY »Ú& P STM32_EXT_EXTI18_IRQ_PRIORITY ºÚ& P STM32_EXT_EXTI19_IRQ_PRIORITY ¹Ú& P STM32_EXT_EXTI20_IRQ_PRIORITY ÁÚ) P !STM32_EXT_EXTI21_22_IRQ_PRIORITY ÷Ú P STM32_GPT_USE_TIM2 =Ú P STM32_GPT_USE_TIM3 <Ú P STM32_GPT_USE_TIM4 ;Ú$ P STM32_GPT_TIM2_IRQ_PRIORITY KÚ$ P STM32_GPT_TIM3_IRQ_PRIORITY JÚ$ P STM32_GPT_TIM4_IRQ_PRIORITY IÚ P STM32_I2C_USE_I2C1 Ú P STM32_I2C_USE_I2C2 Ú$ P STM32_I2C_I2C1_IRQ_PRIORITY ¥Ú$ P STM32_I2C_I2C2_IRQ_PRIORITY ¤Ú$ P STM32_I2C_I2C1_DMA_PRIORITY ¿Ú$ P STM32_I2C_I2C2_DMA_PRIORITY ¾Ú& P STM32_I2C_I2C1_DMA_ERROR_HOOK #Ú& P STM32_I2C_I2C2_DMA_ERROR_HOOK "Ú P STM32_ICU_USE_TIM2 GÚ P STM32_ICU_USE_TIM3 FÚ P STM32_ICU_USE_TIM4 EÚ$ P STM32_ICU_TIM2_IRQ_PRIORITY UÚ$ P STM32_ICU_TIM3_IRQ_PRIORITY TÚ$ P STM32_ICU_TIM4_IRQ_PRIORITY SÚ P STM32_PWM_USE_TIM2 4Ú P STM32_PWM_USE_TIM3 3Ú P STM32_PWM_USE_TIM4 2Ú$ P STM32_PWM_TIM2_IRQ_PRIORITY BÚ$ P STM32_PWM_TIM3_IRQ_PRIORITY AÚ$ P STM32_PWM_TIM4_IRQ_PRIORITY @Ú P STM32_SERIAL_USE_USART1 ºÚ P STM32_SERIAL_USE_USART2 ¹Ú P STM32_SERIAL_USE_USART3 ¸Ú% P STM32_SERIAL_USART1_PRIORITY Ú% P STM32_SERIAL_USART2_PRIORITY Ú% P STM32_SERIAL_USART3_PRIORITY Ú P STM32_SPI_USE_SPI1 ;Ú P STM32_SPI_USE_SPI2 :Ú$ P STM32_SPI_SPI1_DMA_PRIORITY cÚ$ P STM32_SPI_SPI2_DMA_PRIORITY bÚ$ P STM32_SPI_SPI1_IRQ_PRIORITY IÚ$ P STM32_SPI_SPI2_IRQ_PRIORITY HÚ! P STM32_SPI_DMA_ERROR_HOOK MÚ P STM32_UART_USE_USART1 BÚ P STM32_UART_USE_USART2 AÚ P STM32_UART_USE_USART3 @Ú' P STM32_UART_USART1_IRQ_PRIORITY PÚ' P STM32_UART_USART2_IRQ_PRIORITY OÚ' P STM32_UART_USART3_IRQ_PRIORITY NÚ' P STM32_UART_USART1_DMA_PRIORITY jÚ' P STM32_UART_USART2_DMA_PRIORITY iÚ' P STM32_UART_USART3_DMA_PRIORITY hÚ" P STM32_UART_DMA_ERROR_HOOK ûÚ P STM32_USB_USE_USB1 ?Ú' P STM32_USB_LOW_POWER_ON_SUSPEND 3Ú' P STM32_USB_USB1_HP_IRQ_PRIORITY PÚ' P STM32_USB_USB1_LP_IRQ_PRIORITY LÚ P HAL_USE_TM Ú P HAL_USE_PAL XÚ P HAL_USE_ADC mÚ P HAL_USE_CAN cÚ P HAL_USE_EXT DÚ P HAL_USE_GPT JÚ P HAL_USE_I2C wÚ P HAL_USE_ICU TÚ P HAL_USE_MAC dÚ P HAL_USE_MMC_SPI Ú P HAL_USE_PWM AÚ P HAL_USE_RTC LÚ P HAL_USE_SDC [Ú P HAL_USE_SERIAL oÚ P HAL_USE_SERIAL_USB Ú P HAL_USE_SPI IÚ P
HAL_USE_UART ÷Ú P HAL_USE_USB KÚ P
ADC_USE_WAIT Ú! P ADC_USE_MUTUAL_EXCLUSION 7Ú P CAN_USE_SLEEP_MODE -Ú! P I2C_USE_MUTUAL_EXCLUSION AÚ P MAC_USE_ZERO_COPY SÚ P MAC_USE_EVENTS ^Ú P MMC_NICE_WAITING ÞÚ P SDC_INIT_RETRY MÚ P SDC_MMC_SUPPORT ûÚ P SDC_NICE_WAITING áÚ P SERIAL_DEFAULT_BITRATE Ú P SERIAL_BUFFERS_SIZE ßÚ P
SPI_USE_WAIT çÚ! P SPI_USE_MUTUAL_EXCLUSION Ú P _HAL_LLD_H_ @Ú P |
| 248 |
_STM32_H_ ûÚ P __STM32L1XX_H ÆÚ P |
248 |
_STM32_H_ ûÚ P __STM32L1XX_H ÆÚ P |
| 249 |
HSE_VALUE ýÚ P HSE_STARTUP_TIMEOUT Ú P HSI_STARTUP_TIMEOUT ©Ú P |
249 |
HSE_VALUE ýÚ P HSE_STARTUP_TIMEOUT Ú P HSI_STARTUP_TIMEOUT ©Ú P |
| 250 |
HSI_VALUE ùÚ P |
250 |
HSI_VALUE ùÚ P |
| 251 |
LSI_VALUE õÚ P |
251 |
LSI_VALUE õÚ P |
| 252 |
LSE_VALUE ùÚ+ P #__STM32L1XX_STDPERIPH_VERSION_MAIN (Ú+ P #__STM32L1XX_STDPERIPH_VERSION_SUB1 2Ú+ P #__STM32L1XX_STDPERIPH_VERSION_SUB2 1Ú) P !__STM32L1XX_STDPERIPH_VERSION_RC ¼Ú& P __STM32L1XX_STDPERIPH_VERSION ¶Ú P |
252 |
LSE_VALUE ùÚ+ P #__STM32L1XX_STDPERIPH_VERSION_MAIN (Ú+ P #__STM32L1XX_STDPERIPH_VERSION_SUB1 2Ú+ P #__STM32L1XX_STDPERIPH_VERSION_SUB2 1Ú) P !__STM32L1XX_STDPERIPH_VERSION_RC ¼Ú& P __STM32L1XX_STDPERIPH_VERSION ¶Ú P |
| 253 |
__CM3_REV ìÚ P __MPU_PRESENT Ú P __NVIC_PRIO_BITS Ú P __Vendor_SysTickConfig ôÚ
8" IRQn ]Ú " ¾ NonMaskableInt_IRQn ½Ú " ¾ MemoryManagement_IRQn ¹Ú " ¾ BusFault_IRQn Ú " ¾ UsageFault_IRQn JÚ " ¾ SVC_IRQn ]Ú " ¾ DebugMonitor_IRQn hÚ " ¾ PendSV_IRQn Ú " ¾
SysTick_IRQn wÚ " ¾ |
253 |
__CM3_REV ìÚ P __MPU_PRESENT Ú P __NVIC_PRIO_BITS Ú P __Vendor_SysTickConfig ôÚ
8" IRQn ]Ú " ¾ NonMaskableInt_IRQn ½Ú " ¾ MemoryManagement_IRQn ¹Ú " ¾ BusFault_IRQn Ú " ¾ UsageFault_IRQn JÚ " ¾ SVC_IRQn ]Ú " ¾ DebugMonitor_IRQn hÚ " ¾ PendSV_IRQn Ú " ¾
SysTick_IRQn wÚ " ¾ |
| 254 |
WWDG_IRQn Ú " ¾ PVD_IRQn _Ú " ¾ TAMPER_STAMP_IRQn Ú " ¾ RTC_WKUP_IRQn °Ú " ¾ FLASH_IRQn ×Ú " ¾ RCC_IRQn qÚ " ¾ EXTI0_IRQn ÛÚ " ¾ EXTI1_IRQn ÚÚ " ¾ EXTI2_IRQn ÙÚ " ¾ EXTI3_IRQn ØÚ " ¾ EXTI4_IRQn ×Ú " ¾ DMA1_Channel1_IRQn éÚ " ¾ DMA1_Channel2_IRQn èÚ " ¾ DMA1_Channel3_IRQn çÚ " ¾ DMA1_Channel4_IRQn æÚ " ¾ DMA1_Channel5_IRQn åÚ " ¾ DMA1_Channel6_IRQn äÚ " ¾ DMA1_Channel7_IRQn ãÚ " ¾ |
254 |
WWDG_IRQn Ú " ¾ PVD_IRQn _Ú " ¾ TAMPER_STAMP_IRQn Ú " ¾ RTC_WKUP_IRQn °Ú " ¾ FLASH_IRQn ×Ú " ¾ RCC_IRQn qÚ " ¾ EXTI0_IRQn ÛÚ " ¾ EXTI1_IRQn ÚÚ " ¾ EXTI2_IRQn ÙÚ " ¾ EXTI3_IRQn ØÚ " ¾ EXTI4_IRQn ×Ú " ¾ DMA1_Channel1_IRQn éÚ " ¾ DMA1_Channel2_IRQn èÚ " ¾ DMA1_Channel3_IRQn çÚ " ¾ DMA1_Channel4_IRQn æÚ " ¾ DMA1_Channel5_IRQn åÚ " ¾ DMA1_Channel6_IRQn äÚ " ¾ DMA1_Channel7_IRQn ãÚ " ¾ |
| 255 |
ADC1_IRQn NÚ " ¾ USB_HP_IRQn bÚ " ¾ USB_LP_IRQn ^Ú " ¾ DAC_IRQn Ú " ¾ |
255 |
ADC1_IRQn NÚ " ¾ USB_HP_IRQn bÚ " ¾ USB_LP_IRQn ^Ú " ¾ DAC_IRQn Ú " ¾ |
| 256 |
COMP_IRQn Ú " ¾
EXTI9_5_IRQn :Ú " ¾ LCD_IRQn vÚ " ¾ |
256 |
COMP_IRQn Ú " ¾
EXTI9_5_IRQn :Ú " ¾ LCD_IRQn vÚ " ¾ |
| 257 |
TIM9_IRQn $Ú " ¾ TIM10_IRQn úÚ " ¾ TIM11_IRQn ùÚ " ¾ |
257 |
TIM9_IRQn $Ú " ¾ TIM10_IRQn úÚ " ¾ TIM11_IRQn ùÚ " ¾ |
| 258 |
TIM2_IRQn +Ú " ¾ |
258 |
TIM2_IRQn +Ú " ¾ |
| 259 |
TIM3_IRQn *Ú " ¾ |
259 |
TIM3_IRQn *Ú " ¾ |
| 260 |
TIM4_IRQn )Ú " ¾
I2C1_EV_IRQn XÚ " ¾
I2C1_ER_IRQn \Ú " ¾
I2C2_EV_IRQn WÚ " ¾
I2C2_ER_IRQn [Ú " ¾ |
260 |
TIM4_IRQn )Ú " ¾
I2C1_EV_IRQn XÚ " ¾
I2C1_ER_IRQn \Ú " ¾
I2C2_EV_IRQn WÚ " ¾
I2C2_ER_IRQn [Ú " ¾ |
| 261 |
SPI1_IRQn *Ú " ¾ |
261 |
SPI1_IRQn *Ú " ¾ |
| 262 |
SPI2_IRQn )Ú " ¾ USART1_IRQn Ú " ¾ USART2_IRQn Ú " ¾ USART3_IRQn Ú " ¾ EXTI15_10_IRQn ÝÚ " ¾ RTC_Alarm_IRQn Ú " ¾ USB_FS_WKUP_IRQn ±Ú " ¾ |
262 |
SPI2_IRQn )Ú " ¾ USART1_IRQn Ú " ¾ USART2_IRQn Ú " ¾ USART3_IRQn Ú " ¾ EXTI15_10_IRQn ÝÚ " ¾ RTC_Alarm_IRQn Ú " ¾ USB_FS_WKUP_IRQn ±Ú " ¾ |
| 263 |
TIM6_IRQn 'Ú P STM32L1XX_MDP éÚ P
STM32L1XX_HD @Ú " ¾ |
263 |
TIM6_IRQn 'Ú P STM32L1XX_MDP éÚ P
STM32L1XX_HD @Ú " ¾ |
| 264 |
TIM7_IRQn &Ú |
264 |
TIM7_IRQn &Ú |
| 265 |
IRQn_Type Ú P __CORE_CM3_H_GENERIC Ú! P __CM3_CMSIS_VERSION_MAIN 3Ú P __CM3_CMSIS_VERSION_SUB pÚ P __CM3_CMSIS_VERSION ÁÚ P __CORTEX_M xÚ P __CC_ARM 6Ú P __ASM "Ú P __INLINE >Ú P __STATIC_INLINE Ú P __FPU_USED ~Ú P __CORE_CMINSTR_H Ú P __ARMCC_VERSION Ú P __NOP Ú P __WFI Ú P __WFE !Ú P __SEV Ú P __ISB %Ú P __DSB *Ú P __DMB 0Ú P __REV Ú __REV16 ÔÚ , |
265 |
IRQn_Type Ú P __CORE_CM3_H_GENERIC Ú! P __CM3_CMSIS_VERSION_MAIN 3Ú P __CM3_CMSIS_VERSION_SUB pÚ P __CM3_CMSIS_VERSION ÁÚ P __CORTEX_M xÚ P __CC_ARM 6Ú P __ASM "Ú P __INLINE >Ú P __STATIC_INLINE Ú P __FPU_USED ~Ú P __CORE_CMINSTR_H Ú P __ARMCC_VERSION Ú P __NOP Ú P __WFI Ú P __WFE !Ú P __SEV Ú P __ISB %Ú P __DSB *Ú P __DMB 0Ú P __REV Ú __REV16 ÔÚ , |
| 266 |
" value ÿÚ __REVSH Ú ," value ÿÚ P __ROR Ú P __RBIT ÐÚ P __LDREXB <Ú P __LDREXH 6Ú P __LDREXW 'Ú P __STREXB %Ú P __STREXH Ú P __STREXW Ú P __CLREX Ú P __SSAT ÆÚ P __USAT ÄÚ P __CLZ Ú P __CORE_CMFUNC_H Ú __get_CONTROL \Ú |
266 |
" value ÿÚ __REVSH Ú ," value ÿÚ P __ROR Ú P __RBIT ÐÚ P __LDREXB <Ú P __LDREXH 6Ú P __LDREXW 'Ú P __STREXB %Ú P __STREXH Ú P __STREXW Ú P __CLREX Ú P __SSAT ÆÚ P __USAT ÄÚ P __CLZ Ú P __CORE_CMFUNC_H Ú __get_CONTROL \Ú |
| 267 |
"
__regControl @Ú __set_CONTROL PÚ , |
267 |
"
__regControl @Ú __set_CONTROL PÚ , |
| 268 |
" control Ú |
268 |
" control Ú |
| 269 |
"
__regControl >Ú __get_IPSR EÚ |
269 |
"
__regControl >Ú __get_IPSR EÚ |
| 270 |
" ¡ |
270 |
" ¡ |
| 271 |
__regIPSR äÚ __get_APSR MÚ |
271 |
__regIPSR äÚ __get_APSR MÚ |
| 272 |
" £ |
272 |
" £ |
| 273 |
__regAPSR êÚ __get_xPSR Ú |
273 |
__regAPSR êÚ __get_xPSR Ú |
| 274 |
" ¥ |
274 |
" ¥ |
| 275 |
__regXPSR ÑÚ |
275 |
__regXPSR ÑÚ |
| 276 |
__get_PSP Ú# |
276 |
__get_PSP Ú# |
| 277 |
" § __regProcessStackPointer HÚ |
277 |
" § __regProcessStackPointer HÚ |
| 278 |
__set_PSP Ú , |
278 |
__set_PSP Ú , |
| 279 |
" © topOfProcStack ZÚ# |
279 |
" © topOfProcStack ZÚ# |
| 280 |
" © __regProcessStackPointer FÚ |
280 |
" © __regProcessStackPointer FÚ |
| 281 |
__get_MSP Ú |
281 |
__get_MSP Ú |
| 282 |
" ¬ __regMainStackPointer £Ú |
282 |
" ¬ __regMainStackPointer £Ú |
| 283 |
__set_MSP Ú , |
283 |
__set_MSP Ú , |
| 284 |
" ® topOfMainStack dÚ |
284 |
" ® topOfMainStack dÚ |
| 285 |
" ® __regMainStackPointer ¡Ú __get_PRIMASK fÚ |
285 |
" ® __regMainStackPointer ¡Ú __get_PRIMASK fÚ |
| 286 |
" ±
__regPriMask UÚ __set_PRIMASK ZÚ , |
286 |
" ±
__regPriMask UÚ __set_PRIMASK ZÚ , |
| 287 |
" ³ priMask Ú |
287 |
" ³ priMask Ú |
| 288 |
" ³
__regPriMask SÚ P __enable_fault_irq \Ú P __disable_fault_irq íÚ __get_BASEPRI wÚ |
288 |
" ³
__regPriMask SÚ P __enable_fault_irq \Ú P __disable_fault_irq íÚ __get_BASEPRI wÚ |
| 289 |
" ¸
__regBasePri _Ú __set_BASEPRI kÚ , |
289 |
" ¸
__regBasePri _Ú __set_BASEPRI kÚ , |
| 290 |
" º basePri #Ú |
290 |
" º basePri #Ú |
| 291 |
" º
__regBasePri ]Ú __get_FAULTMASK ÑÚ |
291 |
" º
__regBasePri ]Ú __get_FAULTMASK ÑÚ |
| 292 |
" ½ __regFaultMask tÚ __set_FAULTMASK ÅÚ , |
292 |
" ½ __regFaultMask tÚ __set_FAULTMASK ÅÚ , |
| 293 |
" ¿ |
293 |
" ¿ |
| 294 |
faultMask 8Ú |
294 |
faultMask 8Ú |
| 295 |
" ¿ __regFaultMask rÚ P __CMSIS_GENERIC Ú P __CORE_CM3_H_DEPENDANT ýÚ P __I ¾Ú P __O ¸Ú
P __IO mÚ 8 |
295 |
" ¿ __regFaultMask rÚ P __CMSIS_GENERIC Ú P __CORE_CM3_H_DEPENDANT ýÚ P __I ¾Ú P __O ¸Ú
P __IO mÚ 8 |
| 296 |
<unnamed> SÚ 8 |
296 |
<unnamed> SÚ 8 |
| 297 |
<unnamed> QÚ |
297 |
<unnamed> QÚ |
| 298 |
" È _reserved0 òÚ |
298 |
" È _reserved0 òÚ |
| 299 |
" È Q ¢Ú |
299 |
" È Q ¢Ú |
| 300 |
" È V Ú |
300 |
" È V Ú |
| 301 |
" È C °Ú |
301 |
" È C °Ú |
| 302 |
" È Z Ú |
302 |
" È Z Ú |
| 303 |
" È N ¥Ú " Ç b Ú |
303 |
" È N ¥Ú " Ç b Ú |
| 304 |
" Ç w }Ú |
304 |
" Ç w }Ú |
| 305 |
APSR_Type ¸Ú 8 |
305 |
APSR_Type ¸Ú 8 |
| 306 |
<unnamed> SÚ 8 |
306 |
<unnamed> SÚ 8 |
| 307 |
<unnamed> QÚ |
307 |
<unnamed> QÚ |
| 308 |
" Ó ISR öÚ |
308 |
" Ó ISR öÚ |
| 309 |
" Ó _reserved0 çÚ " Ò b uÚ |
309 |
" Ó _reserved0 çÚ " Ò b uÚ |
| 310 |
" Ò w rÚ |
310 |
" Ò w rÚ |
| 311 |
IPSR_Type °Ú 8 |
311 |
IPSR_Type °Ú 8 |
| 312 |
<unnamed> SÚ 8 |
312 |
<unnamed> SÚ 8 |
| 313 |
<unnamed> QÚ |
313 |
<unnamed> QÚ |
| 314 |
" Ú ISR ïÚ |
314 |
" Ú ISR ïÚ |
| 315 |
" Ú _reserved0 àÚ |
315 |
" Ú _reserved0 àÚ |
| 316 |
" Ú T Ú
|
316 |
" Ú T Ú
|
| 317 |
" Ú IT BÚ |
317 |
" Ú IT BÚ |
| 318 |
" Ú Q Ú |
318 |
" Ú Q Ú |
| 319 |
" Ú V Ú |
319 |
" Ú V Ú |
| 320 |
" Ú C Ú |
320 |
" Ú C Ú |
| 321 |
" Ú Z Ú |
321 |
" Ú Z Ú |
| 322 |
" Ú N Ú " Ù b nÚ |
322 |
" Ú N Ú " Ù b nÚ |
| 323 |
" Ù w kÚ |
323 |
" Ù w kÚ |
| 324 |
xPSR_Type Ú 8 |
324 |
xPSR_Type Ú 8 |
| 325 |
<unnamed> SÚ 8 |
325 |
<unnamed> SÚ 8 |
| 326 |
<unnamed> QÚ |
326 |
<unnamed> QÚ |
| 327 |
" è nPRIV Ú |
327 |
" è nPRIV Ú |
| 328 |
" è SPSEL DÚ |
328 |
" è SPSEL DÚ |
| 329 |
" è FPCA ³Ú |
329 |
" è FPCA ³Ú |
| 330 |
" è _reserved0 ÒÚ " ç b `Ú |
330 |
" è _reserved0 ÒÚ " ç b `Ú |
| 331 |
" ç w ]Ú
CONTROL_Type ÇÚ 8 |
331 |
" ç w ]Ú
CONTROL_Type ÇÚ 8 |
| 332 |
<unnamed> QÚ <" ð ISER DÚ <" `ð |
332 |
<unnamed> QÚ <" ð ISER DÚ <" `ð |
| 333 |
RESERVED0 Ú <" ð ICER TÚ <" `ð RSERVED1 ãÚ <" ð ISPR 9Ú <" `ð |
333 |
RESERVED0 Ú <" ð ICER TÚ <" `ð RSERVED1 ãÚ <" ð ISPR 9Ú <" `ð |
| 334 |
RESERVED2 Ú <" ð ICPR IÚ <" `ð |
334 |
RESERVED2 Ú <" ð ICPR IÚ <" `ð |
| 335 |
RESERVED3 Ú <" ð IABR YÚ <" àð |
335 |
RESERVED3 Ú <" ð IABR YÚ <" àð |
| 336 |
RESERVED4 Ú <" ðð IP Ú <" ð |
336 |
RESERVED4 Ú <" ðð IP Ú <" ð |
| 337 |
RESERVED5 SÚ |
337 |
RESERVED5 SÚ |
| 338 |
" ð STIR Ú |
338 |
" ð STIR Ú |
| 339 |
NVIC_Type ¾Ú P NVIC_STIR_INTID_Pos lÚ P NVIC_STIR_INTID_Msk sÚ 8 |
339 |
NVIC_Type ¾Ú P NVIC_STIR_INTID_Pos lÚ P NVIC_STIR_INTID_Msk sÚ 8 |
| 340 |
<unnamed> QÚ |
340 |
<unnamed> QÚ |
| 341 |
"
CPUID ¼Ú |
341 |
"
CPUID ¼Ú |
| 342 |
"
ICSR Ú |
342 |
"
ICSR Ú |
| 343 |
"
VTOR èÚ |
343 |
"
VTOR èÚ |
| 344 |
"
AIRCR ÀÚ |
344 |
"
AIRCR ÀÚ |
| 345 |
"
SCR MÚ |
345 |
"
SCR MÚ |
| 346 |
"
CCR ]Ú <"
SHP Ú |
346 |
"
CCR ]Ú <"
SHP Ú |
| 347 |
"
SHCSR ®Ú |
347 |
"
SHCSR ®Ú |
| 348 |
"
CFSR Ú |
348 |
"
CFSR Ú |
| 349 |
"
HFSR Ú |
349 |
"
HFSR Ú |
| 350 |
"
DFSR Ú |
350 |
"
DFSR Ú |
| 351 |
"
MMFAR ¾Ú |
351 |
"
MMFAR ¾Ú |
| 352 |
"
BFAR Ú |
352 |
"
BFAR Ú |
| 353 |
"
AFSR Ú <"
PFR Ú |
353 |
"
AFSR Ú <"
PFR Ú |
| 354 |
"
DFR YÚ |
354 |
"
DFR YÚ |
| 355 |
"
ADR ^Ú <"
MMFR ÃÚ <"
ISAR ÂÚ <" |
355 |
"
ADR ^Ú <"
MMFR ÃÚ <"
ISAR ÂÚ <" |
| 356 |
RESERVED0 WÚ |
356 |
RESERVED0 WÚ |
| 357 |
"
CPACR ÈÚ SCB_Type Ú" P SCB_CPUID_IMPLEMENTER_Pos »Ú" P SCB_CPUID_IMPLEMENTER_Msk ÂÚ P SCB_CPUID_VARIANT_Pos ðÚ P SCB_CPUID_VARIANT_Msk ÷Ú# P SCB_CPUID_ARCHITECTURE_Pos xÚ# P SCB_CPUID_ARCHITECTURE_Msk Ú P SCB_CPUID_PARTNO_Pos 3Ú P SCB_CPUID_PARTNO_Msk :Ú P SCB_CPUID_REVISION_Pos Ú P SCB_CPUID_REVISION_Msk Ú P SCB_ICSR_NMIPENDSET_Pos NÚ P SCB_ICSR_NMIPENDSET_Msk UÚ P SCB_ICSR_PENDSVSET_Pos Ú P SCB_ICSR_PENDSVSET_Msk Ú P SCB_ICSR_PENDSVCLR_Pos Ú P SCB_ICSR_PENDSVCLR_Msk Ú P SCB_ICSR_PENDSTSET_Pos Ú P SCB_ICSR_PENDSTSET_Msk Ú P SCB_ICSR_PENDSTCLR_Pos Ú P SCB_ICSR_PENDSTCLR_Msk Ú P SCB_ICSR_ISRPREEMPT_Pos :Ú P SCB_ICSR_ISRPREEMPT_Msk AÚ P SCB_ICSR_ISRPENDING_Pos RÚ P SCB_ICSR_ISRPENDING_Msk YÚ! P SCB_ICSR_VECTPENDING_Pos Ú! P SCB_ICSR_VECTPENDING_Msk Ú P SCB_ICSR_RETTOBASE_Pos Ú P SCB_ICSR_RETTOBASE_Msk ¥Ú P SCB_ICSR_VECTACTIVE_Pos WÚ P SCB_ICSR_VECTACTIVE_Msk ^Ú P SCB_VTOR_TBLBASE_Pos 4Ú P SCB_VTOR_TBLBASE_Msk ;Ú P SCB_VTOR_TBLOFF_Pos vÚ P SCB_VTOR_TBLOFF_Msk }Ú P SCB_AIRCR_VECTKEY_Pos îÚ P SCB_AIRCR_VECTKEY_Msk õÚ" P SCB_AIRCR_VECTKEYSTAT_Pos ªÚ" P SCB_AIRCR_VECTKEYSTAT_Msk ±Ú P SCB_AIRCR_ENDIANESS_Pos kÚ P SCB_AIRCR_ENDIANESS_Msk rÚ P SCB_AIRCR_PRIGROUP_Pos Ú P SCB_AIRCR_PRIGROUP_Msk Ú" P SCB_AIRCR_SYSRESETREQ_Pos Ú" P SCB_AIRCR_SYSRESETREQ_Msk Ú$ P SCB_AIRCR_VECTCLRACTIVE_Pos .Ú$ P SCB_AIRCR_VECTCLRACTIVE_Msk 5Ú P SCB_AIRCR_VECTRESET_Pos PÚ P SCB_AIRCR_VECTRESET_Msk WÚ P SCB_SCR_SEVONPEND_Pos àÚ P SCB_SCR_SEVONPEND_Msk çÚ P SCB_SCR_SLEEPDEEP_Pos ûÚ P SCB_SCR_SLEEPDEEP_Msk Ú P SCB_SCR_SLEEPONEXIT_Pos >Ú P SCB_SCR_SLEEPONEXIT_Msk EÚ P SCB_CCR_STKALIGN_Pos GÚ P SCB_CCR_STKALIGN_Msk NÚ P SCB_CCR_BFHFNMIGN_Pos Ú P SCB_CCR_BFHFNMIGN_Msk Ú P SCB_CCR_DIV_0_TRP_Pos ÛÚ P SCB_CCR_DIV_0_TRP_Msk âÚ P SCB_CCR_UNALIGN_TRP_Pos ;Ú P SCB_CCR_UNALIGN_TRP_Msk BÚ! P SCB_CCR_USERSETMPEND_Pos ýÚ! P SCB_CCR_USERSETMPEND_Msk Ú# P SCB_CCR_NONBASETHRDENA_Pos Ú# P SCB_CCR_NONBASETHRDENA_Msk Ú" P SCB_SHCSR_USGFAULTENA_Pos °Ú" P SCB_SHCSR_USGFAULTENA_Msk ·Ú" P SCB_SHCSR_BUSFAULTENA_Pos µÚ" P SCB_SHCSR_BUSFAULTENA_Msk ¼Ú" P SCB_SHCSR_MEMFAULTENA_Pos ÀÚ" P SCB_SHCSR_MEMFAULTENA_Msk ÇÚ# P SCB_SHCSR_SVCALLPENDED_Pos xÚ# P SCB_SHCSR_SVCALLPENDED_Msk Ú% P SCB_SHCSR_BUSFAULTPENDED_Pos ÓÚ% P SCB_SHCSR_BUSFAULTPENDED_Msk ÚÚ% P SCB_SHCSR_MEMFAULTPENDED_Pos ÞÚ% P SCB_SHCSR_MEMFAULTPENDED_Msk åÚ% P SCB_SHCSR_USGFAULTPENDED_Pos ÎÚ% P SCB_SHCSR_USGFAULTPENDED_Msk ÕÚ! P SCB_SHCSR_SYSTICKACT_Pos ïÚ! P SCB_SHCSR_SYSTICKACT_Msk öÚ P SCB_SHCSR_PENDSVACT_Pos KÚ P SCB_SHCSR_PENDSVACT_Msk RÚ! P SCB_SHCSR_MONITORACT_Pos ñÚ! P SCB_SHCSR_MONITORACT_Msk øÚ P SCB_SHCSR_SVCALLACT_Pos VÚ P SCB_SHCSR_SVCALLACT_Msk ]Ú" P SCB_SHCSR_USGFAULTACT_Pos ¬Ú" P SCB_SHCSR_USGFAULTACT_Msk ³Ú" P SCB_SHCSR_BUSFAULTACT_Pos ±Ú" P SCB_SHCSR_BUSFAULTACT_Msk ¸Ú" P SCB_SHCSR_MEMFAULTACT_Pos ¼Ú" P SCB_SHCSR_MEMFAULTACT_Msk ÃÚ P SCB_CFSR_USGFAULTSR_Pos 8Ú P SCB_CFSR_USGFAULTSR_Msk ?Ú P SCB_CFSR_BUSFAULTSR_Pos =Ú P SCB_CFSR_BUSFAULTSR_Msk DÚ P SCB_CFSR_MEMFAULTSR_Pos HÚ P SCB_CFSR_MEMFAULTSR_Msk OÚ P SCB_HFSR_DEBUGEVT_Pos ñÚ P SCB_HFSR_DEBUGEVT_Msk øÚ P SCB_HFSR_FORCED_Pos Ú P SCB_HFSR_FORCED_Msk Ú P SCB_HFSR_VECTTBL_Pos 5Ú P SCB_HFSR_VECTTBL_Msk <Ú P SCB_DFSR_EXTERNAL_Pos èÚ P SCB_DFSR_EXTERNAL_Msk ïÚ P SCB_DFSR_VCATCH_Pos Ú P SCB_DFSR_VCATCH_Msk Ú P SCB_DFSR_DWTTRAP_Pos 'Ú P SCB_DFSR_DWTTRAP_Msk .Ú P SCB_DFSR_BKPT_Pos "Ú P SCB_DFSR_BKPT_Msk )Ú P SCB_DFSR_HALTED_Pos Ú P SCB_DFSR_HALTED_Msk ¤Ú 8 |
357 |
"
CPACR ÈÚ SCB_Type Ú" P SCB_CPUID_IMPLEMENTER_Pos »Ú" P SCB_CPUID_IMPLEMENTER_Msk ÂÚ P SCB_CPUID_VARIANT_Pos ðÚ P SCB_CPUID_VARIANT_Msk ÷Ú# P SCB_CPUID_ARCHITECTURE_Pos xÚ# P SCB_CPUID_ARCHITECTURE_Msk Ú P SCB_CPUID_PARTNO_Pos 3Ú P SCB_CPUID_PARTNO_Msk :Ú P SCB_CPUID_REVISION_Pos Ú P SCB_CPUID_REVISION_Msk Ú P SCB_ICSR_NMIPENDSET_Pos NÚ P SCB_ICSR_NMIPENDSET_Msk UÚ P SCB_ICSR_PENDSVSET_Pos Ú P SCB_ICSR_PENDSVSET_Msk Ú P SCB_ICSR_PENDSVCLR_Pos Ú P SCB_ICSR_PENDSVCLR_Msk Ú P SCB_ICSR_PENDSTSET_Pos Ú P SCB_ICSR_PENDSTSET_Msk Ú P SCB_ICSR_PENDSTCLR_Pos Ú P SCB_ICSR_PENDSTCLR_Msk Ú P SCB_ICSR_ISRPREEMPT_Pos :Ú P SCB_ICSR_ISRPREEMPT_Msk AÚ P SCB_ICSR_ISRPENDING_Pos RÚ P SCB_ICSR_ISRPENDING_Msk YÚ! P SCB_ICSR_VECTPENDING_Pos Ú! P SCB_ICSR_VECTPENDING_Msk Ú P SCB_ICSR_RETTOBASE_Pos Ú P SCB_ICSR_RETTOBASE_Msk ¥Ú P SCB_ICSR_VECTACTIVE_Pos WÚ P SCB_ICSR_VECTACTIVE_Msk ^Ú P SCB_VTOR_TBLBASE_Pos 4Ú P SCB_VTOR_TBLBASE_Msk ;Ú P SCB_VTOR_TBLOFF_Pos vÚ P SCB_VTOR_TBLOFF_Msk }Ú P SCB_AIRCR_VECTKEY_Pos îÚ P SCB_AIRCR_VECTKEY_Msk õÚ" P SCB_AIRCR_VECTKEYSTAT_Pos ªÚ" P SCB_AIRCR_VECTKEYSTAT_Msk ±Ú P SCB_AIRCR_ENDIANESS_Pos kÚ P SCB_AIRCR_ENDIANESS_Msk rÚ P SCB_AIRCR_PRIGROUP_Pos Ú P SCB_AIRCR_PRIGROUP_Msk Ú" P SCB_AIRCR_SYSRESETREQ_Pos Ú" P SCB_AIRCR_SYSRESETREQ_Msk Ú$ P SCB_AIRCR_VECTCLRACTIVE_Pos .Ú$ P SCB_AIRCR_VECTCLRACTIVE_Msk 5Ú P SCB_AIRCR_VECTRESET_Pos PÚ P SCB_AIRCR_VECTRESET_Msk WÚ P SCB_SCR_SEVONPEND_Pos àÚ P SCB_SCR_SEVONPEND_Msk çÚ P SCB_SCR_SLEEPDEEP_Pos ûÚ P SCB_SCR_SLEEPDEEP_Msk Ú P SCB_SCR_SLEEPONEXIT_Pos >Ú P SCB_SCR_SLEEPONEXIT_Msk EÚ P SCB_CCR_STKALIGN_Pos GÚ P SCB_CCR_STKALIGN_Msk NÚ P SCB_CCR_BFHFNMIGN_Pos Ú P SCB_CCR_BFHFNMIGN_Msk Ú P SCB_CCR_DIV_0_TRP_Pos ÛÚ P SCB_CCR_DIV_0_TRP_Msk âÚ P SCB_CCR_UNALIGN_TRP_Pos ;Ú P SCB_CCR_UNALIGN_TRP_Msk BÚ! P SCB_CCR_USERSETMPEND_Pos ýÚ! P SCB_CCR_USERSETMPEND_Msk Ú# P SCB_CCR_NONBASETHRDENA_Pos Ú# P SCB_CCR_NONBASETHRDENA_Msk Ú" P SCB_SHCSR_USGFAULTENA_Pos °Ú" P SCB_SHCSR_USGFAULTENA_Msk ·Ú" P SCB_SHCSR_BUSFAULTENA_Pos µÚ" P SCB_SHCSR_BUSFAULTENA_Msk ¼Ú" P SCB_SHCSR_MEMFAULTENA_Pos ÀÚ" P SCB_SHCSR_MEMFAULTENA_Msk ÇÚ# P SCB_SHCSR_SVCALLPENDED_Pos xÚ# P SCB_SHCSR_SVCALLPENDED_Msk Ú% P SCB_SHCSR_BUSFAULTPENDED_Pos ÓÚ% P SCB_SHCSR_BUSFAULTPENDED_Msk ÚÚ% P SCB_SHCSR_MEMFAULTPENDED_Pos ÞÚ% P SCB_SHCSR_MEMFAULTPENDED_Msk åÚ% P SCB_SHCSR_USGFAULTPENDED_Pos ÎÚ% P SCB_SHCSR_USGFAULTPENDED_Msk ÕÚ! P SCB_SHCSR_SYSTICKACT_Pos ïÚ! P SCB_SHCSR_SYSTICKACT_Msk öÚ P SCB_SHCSR_PENDSVACT_Pos KÚ P SCB_SHCSR_PENDSVACT_Msk RÚ! P SCB_SHCSR_MONITORACT_Pos ñÚ! P SCB_SHCSR_MONITORACT_Msk øÚ P SCB_SHCSR_SVCALLACT_Pos VÚ P SCB_SHCSR_SVCALLACT_Msk ]Ú" P SCB_SHCSR_USGFAULTACT_Pos ¬Ú" P SCB_SHCSR_USGFAULTACT_Msk ³Ú" P SCB_SHCSR_BUSFAULTACT_Pos ±Ú" P SCB_SHCSR_BUSFAULTACT_Msk ¸Ú" P SCB_SHCSR_MEMFAULTACT_Pos ¼Ú" P SCB_SHCSR_MEMFAULTACT_Msk ÃÚ P SCB_CFSR_USGFAULTSR_Pos 8Ú P SCB_CFSR_USGFAULTSR_Msk ?Ú P SCB_CFSR_BUSFAULTSR_Pos =Ú P SCB_CFSR_BUSFAULTSR_Msk DÚ P SCB_CFSR_MEMFAULTSR_Pos HÚ P SCB_CFSR_MEMFAULTSR_Msk OÚ P SCB_HFSR_DEBUGEVT_Pos ñÚ P SCB_HFSR_DEBUGEVT_Msk øÚ P SCB_HFSR_FORCED_Pos Ú P SCB_HFSR_FORCED_Msk Ú P SCB_HFSR_VECTTBL_Pos 5Ú P SCB_HFSR_VECTTBL_Msk <Ú P SCB_DFSR_EXTERNAL_Pos èÚ P SCB_DFSR_EXTERNAL_Msk ïÚ P SCB_DFSR_VCATCH_Pos Ú P SCB_DFSR_VCATCH_Msk Ú P SCB_DFSR_DWTTRAP_Pos 'Ú P SCB_DFSR_DWTTRAP_Msk .Ú P SCB_DFSR_BKPT_Pos "Ú P SCB_DFSR_BKPT_Msk )Ú P SCB_DFSR_HALTED_Pos Ú P SCB_DFSR_HALTED_Msk ¤Ú 8 |
| 358 |
<unnamed> QÚ <" |
358 |
<unnamed> QÚ <" |
| 359 |
RESERVED0 [Ú |
359 |
RESERVED0 [Ú |
| 360 |
" ICTR õÚ |
360 |
" ICTR õÚ |
| 361 |
" ACTLR ¯Ú SCnSCB_Type Ú$ P SCnSCB_ICTR_INTLINESNUM_Pos âÚ$ P SCnSCB_ICTR_INTLINESNUM_Msk éÚ! P SCnSCB_ACTLR_DISFOLD_Pos õÚ! P SCnSCB_ACTLR_DISFOLD_Msk üÚ$ P SCnSCB_ACTLR_DISDEFWBUF_Pos Ú$ P SCnSCB_ACTLR_DISDEFWBUF_Msk Ú$ P SCnSCB_ACTLR_DISMCYCINT_Pos ýÚ$ P SCnSCB_ACTLR_DISMCYCINT_Msk Ú 8 |
361 |
" ACTLR ¯Ú SCnSCB_Type Ú$ P SCnSCB_ICTR_INTLINESNUM_Pos âÚ$ P SCnSCB_ICTR_INTLINESNUM_Msk éÚ! P SCnSCB_ACTLR_DISFOLD_Pos õÚ! P SCnSCB_ACTLR_DISFOLD_Msk üÚ$ P SCnSCB_ACTLR_DISDEFWBUF_Pos Ú$ P SCnSCB_ACTLR_DISDEFWBUF_Msk Ú$ P SCnSCB_ACTLR_DISMCYCINT_Pos ýÚ$ P SCnSCB_ACTLR_DISMCYCINT_Msk Ú 8 |
| 362 |
<unnamed> QÚ |
362 |
<unnamed> QÚ |
| 363 |
" CTRL åÚ |
363 |
" CTRL åÚ |
| 364 |
" LOAD úÚ |
364 |
" LOAD úÚ |
| 365 |
" VAL 9Ú |
365 |
" VAL 9Ú |
| 366 |
" CALIB ½Ú
SysTick_Type Ú# P SysTick_CTRL_COUNTFLAG_Pos ¦Ú# P SysTick_CTRL_COUNTFLAG_Msk Ú# P SysTick_CTRL_CLKSOURCE_Pos Ú# P SysTick_CTRL_CLKSOURCE_Msk ¥Ú! P SysTick_CTRL_TICKINT_Pos 7Ú! P SysTick_CTRL_TICKINT_Msk >Ú P SysTick_CTRL_ENABLE_Pos ¨Ú P SysTick_CTRL_ENABLE_Msk ¯Ú P SysTick_LOAD_RELOAD_Pos Ú P SysTick_LOAD_RELOAD_Msk ´Ú P SysTick_VAL_CURRENT_Pos ~Ú P SysTick_VAL_CURRENT_Msk
Ú P SysTick_CALIB_NOREF_Pos ¯Ú P SysTick_CALIB_NOREF_Msk ¶Ú P SysTick_CALIB_SKEW_Pos ñÚ P SysTick_CALIB_SKEW_Msk øÚ P SysTick_CALIB_TENMS_Pos ¢Ú P SysTick_CALIB_TENMS_Msk ©Ú 8 |
366 |
" CALIB ½Ú
SysTick_Type Ú# P SysTick_CTRL_COUNTFLAG_Pos ¦Ú# P SysTick_CTRL_COUNTFLAG_Msk Ú# P SysTick_CTRL_CLKSOURCE_Pos Ú# P SysTick_CTRL_CLKSOURCE_Msk ¥Ú! P SysTick_CTRL_TICKINT_Pos 7Ú! P SysTick_CTRL_TICKINT_Msk >Ú P SysTick_CTRL_ENABLE_Pos ¨Ú P SysTick_CTRL_ENABLE_Msk ¯Ú P SysTick_LOAD_RELOAD_Pos Ú P SysTick_LOAD_RELOAD_Msk ´Ú P SysTick_VAL_CURRENT_Pos ~Ú P SysTick_VAL_CURRENT_Msk
Ú P SysTick_CALIB_NOREF_Pos ¯Ú P SysTick_CALIB_NOREF_Msk ¶Ú P SysTick_CALIB_SKEW_Pos ñÚ P SysTick_CALIB_SKEW_Msk øÚ P SysTick_CALIB_TENMS_Pos ¢Ú P SysTick_CALIB_TENMS_Msk ©Ú 8 |
| 367 |
<unnamed> QÚ 8 |
367 |
<unnamed> QÚ 8 |
| 368 |
<unnamed> SÚ
" ²u8 _Ú " ²u16 %Ú |
368 |
<unnamed> SÚ
" ²u8 _Ú " ²u16 %Ú |
| 369 |
" ²u32 )Ú <" ±PORT
Ú <" ± |
369 |
" ²u32 )Ú <" ±PORT
Ú <" ± |
| 370 |
RESERVED0 Ú |
370 |
RESERVED0 Ú |
| 371 |
" ±TER Ú <" <± |
371 |
" ±TER Ú <" <± |
| 372 |
RESERVED1 ýÚ |
372 |
RESERVED1 ýÚ |
| 373 |
" ±TPR Ú <" <± |
373 |
" ±TPR Ú <" <± |
| 374 |
RESERVED2 üÚ |
374 |
RESERVED2 üÚ |
| 375 |
" ±TCR Ú <" t± |
375 |
" ±TCR Ú <" t± |
| 376 |
RESERVED3 ÃÚ |
376 |
RESERVED3 ÃÚ |
| 377 |
" ±IWR Ú |
377 |
" ±IWR Ú |
| 378 |
" ±IRR Ú |
378 |
" ±IRR Ú |
| 379 |
" ±IMCR ×Ú <" ¬± |
379 |
" ±IMCR ×Ú <" ¬± |
| 380 |
RESERVED4 Ú |
380 |
RESERVED4 Ú |
| 381 |
" ±LAR %Ú |
381 |
" ±LAR %Ú |
| 382 |
" ±LSR Ú <" ± |
382 |
" ±LSR Ú <" ± |
| 383 |
RESERVED5 Ú |
383 |
RESERVED5 Ú |
| 384 |
" ±PID4 ñÚ |
384 |
" ±PID4 ñÚ |
| 385 |
" ±PID5 ðÚ |
385 |
" ±PID5 ðÚ |
| 386 |
" ±PID6 ïÚ |
386 |
" ±PID6 ïÚ |
| 387 |
" ±PID7 îÚ |
387 |
" ±PID7 îÚ |
| 388 |
" ±PID0 õÚ |
388 |
" ±PID0 õÚ |
| 389 |
" ±PID1 ôÚ |
389 |
" ±PID1 ôÚ |
| 390 |
" ±PID2 óÚ |
390 |
" ±PID2 óÚ |
| 391 |
" ±PID3 òÚ |
391 |
" ±PID3 òÚ |
| 392 |
" ±CID0 Ú |
392 |
" ±CID0 Ú |
| 393 |
" ±CID1 Ú |
393 |
" ±CID1 Ú |
| 394 |
" ±CID2 Ú |
394 |
" ±CID2 Ú |
| 395 |
" ±CID3 ÿÚ ITM_Type Ú P ITM_TPR_PRIVMASK_Pos Ú P ITM_TPR_PRIVMASK_Msk Ú P ITM_TCR_BUSY_Pos FÚ P ITM_TCR_BUSY_Msk MÚ P ITM_TCR_TraceBusID_Pos ×Ú P ITM_TCR_TraceBusID_Msk ÞÚ P ITM_TCR_GTSFREQ_Pos gÚ P ITM_TCR_GTSFREQ_Msk nÚ P ITM_TCR_TSPrescale_Pos §Ú P ITM_TCR_TSPrescale_Msk ®Ú P ITM_TCR_SWOENA_Pos ¸Ú P ITM_TCR_SWOENA_Msk ¿Ú P ITM_TCR_DWTENA_Pos ÂÚ P ITM_TCR_DWTENA_Msk ÉÚ P ITM_TCR_SYNCENA_Pos rÚ P ITM_TCR_SYNCENA_Msk yÚ P ITM_TCR_TSENA_Pos Ú P ITM_TCR_TSENA_Msk Ú P ITM_TCR_ITMENA_Pos ÇÚ P ITM_TCR_ITMENA_Msk ÎÚ P ITM_IWR_ATVALIDM_Pos &Ú P ITM_IWR_ATVALIDM_Msk -Ú P ITM_IRR_ATREADYM_Pos &Ú P ITM_IRR_ATREADYM_Msk -Ú! P ITM_IMCR_INTEGRATION_Pos óÚ! P ITM_IMCR_INTEGRATION_Msk úÚ P ITM_LSR_ByteAcc_Pos àÚ P ITM_LSR_ByteAcc_Msk çÚ P ITM_LSR_Access_Pos +Ú P ITM_LSR_Access_Msk 2Ú P ITM_LSR_Present_Pos Ú P ITM_LSR_Present_Msk ¡Ú 8 |
395 |
" ±CID3 ÿÚ ITM_Type Ú P ITM_TPR_PRIVMASK_Pos Ú P ITM_TPR_PRIVMASK_Msk Ú P ITM_TCR_BUSY_Pos FÚ P ITM_TCR_BUSY_Msk MÚ P ITM_TCR_TraceBusID_Pos ×Ú P ITM_TCR_TraceBusID_Msk ÞÚ P ITM_TCR_GTSFREQ_Pos gÚ P ITM_TCR_GTSFREQ_Msk nÚ P ITM_TCR_TSPrescale_Pos §Ú P ITM_TCR_TSPrescale_Msk ®Ú P ITM_TCR_SWOENA_Pos ¸Ú P ITM_TCR_SWOENA_Msk ¿Ú P ITM_TCR_DWTENA_Pos ÂÚ P ITM_TCR_DWTENA_Msk ÉÚ P ITM_TCR_SYNCENA_Pos rÚ P ITM_TCR_SYNCENA_Msk yÚ P ITM_TCR_TSENA_Pos Ú P ITM_TCR_TSENA_Msk Ú P ITM_TCR_ITMENA_Pos ÇÚ P ITM_TCR_ITMENA_Msk ÎÚ P ITM_IWR_ATVALIDM_Pos &Ú P ITM_IWR_ATVALIDM_Msk -Ú P ITM_IRR_ATREADYM_Pos &Ú P ITM_IRR_ATREADYM_Msk -Ú! P ITM_IMCR_INTEGRATION_Pos óÚ! P ITM_IMCR_INTEGRATION_Msk úÚ P ITM_LSR_ByteAcc_Pos àÚ P ITM_LSR_ByteAcc_Msk çÚ P ITM_LSR_Access_Pos +Ú P ITM_LSR_Access_Msk 2Ú P ITM_LSR_Present_Pos Ú P ITM_LSR_Present_Msk ¡Ú 8 |
| 396 |
<unnamed> QÚ |
396 |
<unnamed> QÚ |
| 397 |
" òCTRL Ú |
397 |
" òCTRL Ú |
| 398 |
" òCYCCNT ùÚ |
398 |
" òCYCCNT ùÚ |
| 399 |
" òCPICNT üÚ |
399 |
" òCPICNT üÚ |
| 400 |
" òEXCCNT øÚ |
400 |
" òEXCCNT øÚ |
| 401 |
" ò SLEEPCNT [Ú |
401 |
" ò SLEEPCNT [Ú |
| 402 |
" òLSUCNT äÚ |
402 |
" òLSUCNT äÚ |
| 403 |
" òFOLDCNT ±Ú |
403 |
" òFOLDCNT ±Ú |
| 404 |
" òPCSR Ú |
404 |
" òPCSR Ú |
| 405 |
" òCOMP0 `Ú |
405 |
" òCOMP0 `Ú |
| 406 |
" òMASK0 cÚ |
406 |
" òMASK0 cÚ |
| 407 |
" ò |
407 |
" ò |
| 408 |
FUNCTION0 !Ú <" ò |
408 |
FUNCTION0 !Ú <" ò |
| 409 |
RESERVED0 õÚ |
409 |
RESERVED0 õÚ |
| 410 |
" òCOMP1 _Ú |
410 |
" òCOMP1 _Ú |
| 411 |
" òMASK1 bÚ |
411 |
" òMASK1 bÚ |
| 412 |
" ò |
412 |
" ò |
| 413 |
FUNCTION1 Ú <" ò |
413 |
FUNCTION1 Ú <" ò |
| 414 |
RESERVED1 ôÚ |
414 |
RESERVED1 ôÚ |
| 415 |
" òCOMP2 ^Ú |
415 |
" òCOMP2 ^Ú |
| 416 |
" òMASK2 aÚ |
416 |
" òMASK2 aÚ |
| 417 |
" ò |
417 |
" ò |
| 418 |
FUNCTION2 Ú <" ò |
418 |
FUNCTION2 Ú <" ò |
| 419 |
RESERVED2 óÚ |
419 |
RESERVED2 óÚ |
| 420 |
" òCOMP3 ]Ú |
420 |
" òCOMP3 ]Ú |
| 421 |
" òMASK3 `Ú |
421 |
" òMASK3 `Ú |
| 422 |
" ò |
422 |
" ò |
| 423 |
FUNCTION3 Ú DWT_Type Ú P DWT_CTRL_NUMCOMP_Pos Ú P DWT_CTRL_NUMCOMP_Msk Ú P DWT_CTRL_NOTRCPKT_Pos ¹Ú P DWT_CTRL_NOTRCPKT_Msk ÀÚ P DWT_CTRL_NOEXTTRIG_Pos hÚ P DWT_CTRL_NOEXTTRIG_Msk oÚ P DWT_CTRL_NOCYCCNT_Pos ÍÚ P DWT_CTRL_NOCYCCNT_Msk ÔÚ P DWT_CTRL_NOPRFCNT_Pos ÄÚ P DWT_CTRL_NOPRFCNT_Msk ËÚ P DWT_CTRL_CYCEVTENA_Pos Ú P DWT_CTRL_CYCEVTENA_Msk Ú P DWT_CTRL_FOLDEVTENA_Pos BÚ P DWT_CTRL_FOLDEVTENA_Msk IÚ P DWT_CTRL_LSUEVTENA_Pos uÚ P DWT_CTRL_LSUEVTENA_Msk |Ú! P DWT_CTRL_SLEEPEVTENA_Pos ìÚ! P DWT_CTRL_SLEEPEVTENA_Msk óÚ P DWT_CTRL_EXCEVTENA_Pos Ú P DWT_CTRL_EXCEVTENA_Msk Ú P DWT_CTRL_CPIEVTENA_Pos Ú P DWT_CTRL_CPIEVTENA_Msk Ú P DWT_CTRL_EXCTRCENA_Pos Ú P DWT_CTRL_EXCTRCENA_Msk Ú P DWT_CTRL_PCSAMPLENA_Pos FÚ P DWT_CTRL_PCSAMPLENA_Msk MÚ P DWT_CTRL_SYNCTAP_Pos Ú P DWT_CTRL_SYNCTAP_Msk Ú P DWT_CTRL_CYCTAP_Pos nÚ P DWT_CTRL_CYCTAP_Msk uÚ P DWT_CTRL_POSTINIT_Pos ´Ú P DWT_CTRL_POSTINIT_Msk »Ú P DWT_CTRL_POSTPRESET_Pos Ú P DWT_CTRL_POSTPRESET_Msk Ú P DWT_CTRL_CYCCNTENA_Pos Ú P DWT_CTRL_CYCCNTENA_Msk Ú P DWT_CPICNT_CPICNT_Pos áÚ P DWT_CPICNT_CPICNT_Msk èÚ P DWT_EXCCNT_EXCCNT_Pos ÙÚ P DWT_EXCCNT_EXCCNT_Msk àÚ" P DWT_SLEEPCNT_SLEEPCNT_Pos Ú" P DWT_SLEEPCNT_SLEEPCNT_Msk ¦Ú P DWT_LSUCNT_LSUCNT_Pos ±Ú P DWT_LSUCNT_LSUCNT_Msk ¸Ú P DWT_FOLDCNT_FOLDCNT_Pos KÚ P DWT_FOLDCNT_FOLDCNT_Msk RÚ P DWT_MASK_MASK_Pos Ú P DWT_MASK_MASK_Msk Ú! P DWT_FUNCTION_MATCHED_Pos Ú! P DWT_FUNCTION_MATCHED_Msk Ú$ P DWT_FUNCTION_DATAVADDR1_Pos 5Ú$ P DWT_FUNCTION_DATAVADDR1_Msk <Ú$ P DWT_FUNCTION_DATAVADDR0_Pos 6Ú$ P DWT_FUNCTION_DATAVADDR0_Msk =Ú# P DWT_FUNCTION_DATAVSIZE_Pos HÚ# P DWT_FUNCTION_DATAVSIZE_Msk OÚ! P DWT_FUNCTION_LNK1ENA_Pos
Ú! P DWT_FUNCTION_LNK1ENA_Msk Ú$ P DWT_FUNCTION_DATAVMATCH_Pos Ú$ P DWT_FUNCTION_DATAVMATCH_Msk Ú" P DWT_FUNCTION_CYCMATCH_Pos ©Ú" P DWT_FUNCTION_CYCMATCH_Msk °Ú# P DWT_FUNCTION_EMITRANGE_Pos WÚ# P DWT_FUNCTION_EMITRANGE_Msk ^Ú" P DWT_FUNCTION_FUNCTION_Pos Ú" P DWT_FUNCTION_FUNCTION_Msk Ú 8 |
423 |
FUNCTION3 Ú DWT_Type Ú P DWT_CTRL_NUMCOMP_Pos Ú P DWT_CTRL_NUMCOMP_Msk Ú P DWT_CTRL_NOTRCPKT_Pos ¹Ú P DWT_CTRL_NOTRCPKT_Msk ÀÚ P DWT_CTRL_NOEXTTRIG_Pos hÚ P DWT_CTRL_NOEXTTRIG_Msk oÚ P DWT_CTRL_NOCYCCNT_Pos ÍÚ P DWT_CTRL_NOCYCCNT_Msk ÔÚ P DWT_CTRL_NOPRFCNT_Pos ÄÚ P DWT_CTRL_NOPRFCNT_Msk ËÚ P DWT_CTRL_CYCEVTENA_Pos Ú P DWT_CTRL_CYCEVTENA_Msk Ú P DWT_CTRL_FOLDEVTENA_Pos BÚ P DWT_CTRL_FOLDEVTENA_Msk IÚ P DWT_CTRL_LSUEVTENA_Pos uÚ P DWT_CTRL_LSUEVTENA_Msk |Ú! P DWT_CTRL_SLEEPEVTENA_Pos ìÚ! P DWT_CTRL_SLEEPEVTENA_Msk óÚ P DWT_CTRL_EXCEVTENA_Pos Ú P DWT_CTRL_EXCEVTENA_Msk Ú P DWT_CTRL_CPIEVTENA_Pos Ú P DWT_CTRL_CPIEVTENA_Msk Ú P DWT_CTRL_EXCTRCENA_Pos Ú P DWT_CTRL_EXCTRCENA_Msk Ú P DWT_CTRL_PCSAMPLENA_Pos FÚ P DWT_CTRL_PCSAMPLENA_Msk MÚ P DWT_CTRL_SYNCTAP_Pos Ú P DWT_CTRL_SYNCTAP_Msk Ú P DWT_CTRL_CYCTAP_Pos nÚ P DWT_CTRL_CYCTAP_Msk uÚ P DWT_CTRL_POSTINIT_Pos ´Ú P DWT_CTRL_POSTINIT_Msk »Ú P DWT_CTRL_POSTPRESET_Pos Ú P DWT_CTRL_POSTPRESET_Msk Ú P DWT_CTRL_CYCCNTENA_Pos Ú P DWT_CTRL_CYCCNTENA_Msk Ú P DWT_CPICNT_CPICNT_Pos áÚ P DWT_CPICNT_CPICNT_Msk èÚ P DWT_EXCCNT_EXCCNT_Pos ÙÚ P DWT_EXCCNT_EXCCNT_Msk àÚ" P DWT_SLEEPCNT_SLEEPCNT_Pos Ú" P DWT_SLEEPCNT_SLEEPCNT_Msk ¦Ú P DWT_LSUCNT_LSUCNT_Pos ±Ú P DWT_LSUCNT_LSUCNT_Msk ¸Ú P DWT_FOLDCNT_FOLDCNT_Pos KÚ P DWT_FOLDCNT_FOLDCNT_Msk RÚ P DWT_MASK_MASK_Pos Ú P DWT_MASK_MASK_Msk Ú! P DWT_FUNCTION_MATCHED_Pos Ú! P DWT_FUNCTION_MATCHED_Msk Ú$ P DWT_FUNCTION_DATAVADDR1_Pos 5Ú$ P DWT_FUNCTION_DATAVADDR1_Msk <Ú$ P DWT_FUNCTION_DATAVADDR0_Pos 6Ú$ P DWT_FUNCTION_DATAVADDR0_Msk =Ú# P DWT_FUNCTION_DATAVSIZE_Pos HÚ# P DWT_FUNCTION_DATAVSIZE_Msk OÚ! P DWT_FUNCTION_LNK1ENA_Pos
Ú! P DWT_FUNCTION_LNK1ENA_Msk Ú$ P DWT_FUNCTION_DATAVMATCH_Pos Ú$ P DWT_FUNCTION_DATAVMATCH_Msk Ú" P DWT_FUNCTION_CYCMATCH_Pos ©Ú" P DWT_FUNCTION_CYCMATCH_Msk °Ú# P DWT_FUNCTION_EMITRANGE_Pos WÚ# P DWT_FUNCTION_EMITRANGE_Msk ^Ú" P DWT_FUNCTION_FUNCTION_Pos Ú" P DWT_FUNCTION_FUNCTION_Msk Ú 8 |
| 424 |
<unnamed> QÚ |
424 |
<unnamed> QÚ |
| 425 |
" ÍSSPSR HÚ |
425 |
" ÍSSPSR HÚ |
| 426 |
" ÍCSPSR XÚ <" Í |
426 |
" ÍCSPSR XÚ <" Í |
| 427 |
RESERVED0 Ú |
427 |
RESERVED0 Ú |
| 428 |
" ÍACPR ¿Ú <" ÜÍ |
428 |
" ÍACPR ¿Ú <" ÜÍ |
| 429 |
RESERVED1 >Ú |
429 |
RESERVED1 >Ú |
| 430 |
" ÍSPPR Ú <" Í |
430 |
" ÍSPPR Ú <" Í |
| 431 |
RESERVED2 Ú |
431 |
RESERVED2 Ú |
| 432 |
" ÍFFSR ´Ú |
432 |
" ÍFFSR ´Ú |
| 433 |
" ÍFFCR ÄÚ |
433 |
" ÍFFCR ÄÚ |
| 434 |
" ÍFSCR ·Ú <" ÜÍ |
434 |
" ÍFSCR ·Ú <" ÜÍ |
| 435 |
RESERVED3 &Ú |
435 |
RESERVED3 &Ú |
| 436 |
" ÍTRIGGER ËÚ |
436 |
" ÍTRIGGER ËÚ |
| 437 |
" ÍFIFO0 Ú |
437 |
" ÍFIFO0 Ú |
| 438 |
" Í |
438 |
" Í |
| 439 |
ITATBCTR2 LÚ <" Í |
439 |
ITATBCTR2 LÚ <" Í |
| 440 |
RESERVED4 Ú |
440 |
RESERVED4 Ú |
| 441 |
" Í |
441 |
" Í |
| 442 |
ITATBCTR0 NÚ |
442 |
ITATBCTR0 NÚ |
| 443 |
" ÍFIFO1 Ú |
443 |
" ÍFIFO1 Ú |
| 444 |
" ÍITCTRL Ú <" Í |
444 |
" ÍITCTRL Ú <" Í |
| 445 |
RESERVED5 zÚ |
445 |
RESERVED5 zÚ |
| 446 |
" Í CLAIMSET Ú |
446 |
" Í CLAIMSET Ú |
| 447 |
" Í CLAIMCLR Ú <" Í |
447 |
" Í CLAIMCLR Ú <" Í |
| 448 |
RESERVED7 öÚ |
448 |
RESERVED7 öÚ |
| 449 |
" ÍDEVID wÚ |
449 |
" ÍDEVID wÚ |
| 450 |
" ÍDEVTYPE ¾Ú TPI_Type Ú P TPI_ACPR_PRESCALER_Pos Ú P TPI_ACPR_PRESCALER_Msk £Ú P TPI_SPPR_TXMODE_Pos SÚ P TPI_SPPR_TXMODE_Msk ZÚ P TPI_FFSR_FtNonStop_Pos §Ú P TPI_FFSR_FtNonStop_Msk ®Ú P TPI_FFSR_TCPresent_Pos ºÚ P TPI_FFSR_TCPresent_Msk ÁÚ P TPI_FFSR_FtStopped_Pos Ú P TPI_FFSR_FtStopped_Msk Ú P TPI_FFSR_FlInProg_Pos 3Ú P TPI_FFSR_FlInProg_Msk :Ú P TPI_FFCR_TrigIn_Pos ûÚ P TPI_FFCR_TrigIn_Msk Ú P TPI_FFCR_EnFCont_Pos ¹Ú P TPI_FFCR_EnFCont_Msk ÀÚ P TPI_TRIGGER_TRIGGER_Pos 9Ú P TPI_TRIGGER_TRIGGER_Msk @Ú" P TPI_FIFO0_ITM_ATVALID_Pos »Ú" P TPI_FIFO0_ITM_ATVALID_Msk ÂÚ$ P TPI_FIFO0_ITM_bytecount_Pos ßÚ$ P TPI_FIFO0_ITM_bytecount_Msk æÚ" P TPI_FIFO0_ETM_ATVALID_Pos ¿Ú" P TPI_FIFO0_ETM_ATVALID_Msk ÆÚ$ P TPI_FIFO0_ETM_bytecount_Pos ãÚ$ P TPI_FIFO0_ETM_bytecount_Msk êÚ P TPI_FIFO0_ETM2_Pos ÿÚ P TPI_FIFO0_ETM2_Msk Ú P TPI_FIFO0_ETM1_Pos Ú P TPI_FIFO0_ETM1_Msk Ú P TPI_FIFO0_ETM0_Pos Ú P TPI_FIFO0_ETM0_Msk Ú" P TPI_ITATBCTR2_ATREADY_Pos ÄÚ" P TPI_ITATBCTR2_ATREADY_Msk ËÚ" P TPI_FIFO1_ITM_ATVALID_Pos ºÚ" P TPI_FIFO1_ITM_ATVALID_Msk ÁÚ$ P TPI_FIFO1_ITM_bytecount_Pos ÞÚ$ P TPI_FIFO1_ITM_bytecount_Msk åÚ" P TPI_FIFO1_ETM_ATVALID_Pos ¾Ú" P TPI_FIFO1_ETM_ATVALID_Msk ÅÚ$ P TPI_FIFO1_ETM_bytecount_Pos âÚ$ P TPI_FIFO1_ETM_bytecount_Msk éÚ P TPI_FIFO1_ITM2_Pos úÚ P TPI_FIFO1_ITM2_Msk Ú P TPI_FIFO1_ITM1_Pos ûÚ P TPI_FIFO1_ITM1_Msk Ú P TPI_FIFO1_ITM0_Pos üÚ P TPI_FIFO1_ITM0_Msk Ú" P TPI_ITATBCTR0_ATREADY_Pos ÆÚ" P TPI_ITATBCTR0_ATREADY_Msk ÍÚ P TPI_ITCTRL_Mode_Pos Ú P TPI_ITCTRL_Mode_Msk Ú P TPI_DEVID_NRZVALID_Pos Ú P TPI_DEVID_NRZVALID_Msk Ú P TPI_DEVID_MANCVALID_Pos fÚ P TPI_DEVID_MANCVALID_Msk mÚ P TPI_DEVID_PTINVALID_Pos JÚ P TPI_DEVID_PTINVALID_Msk QÚ P TPI_DEVID_MinBufSz_Pos éÚ P TPI_DEVID_MinBufSz_Msk ðÚ P TPI_DEVID_AsynClkIn_Pos Ú P TPI_DEVID_AsynClkIn_Msk Ú# P TPI_DEVID_NrTraceInput_Pos 0Ú# P TPI_DEVID_NrTraceInput_Msk 7Ú P TPI_DEVTYPE_SubType_Pos tÚ P TPI_DEVTYPE_SubType_Msk {Ú" P TPI_DEVTYPE_MajorType_Pos ¡Ú" P TPI_DEVTYPE_MajorType_Msk ¨Ú 8 |
450 |
" ÍDEVTYPE ¾Ú TPI_Type Ú P TPI_ACPR_PRESCALER_Pos Ú P TPI_ACPR_PRESCALER_Msk £Ú P TPI_SPPR_TXMODE_Pos SÚ P TPI_SPPR_TXMODE_Msk ZÚ P TPI_FFSR_FtNonStop_Pos §Ú P TPI_FFSR_FtNonStop_Msk ®Ú P TPI_FFSR_TCPresent_Pos ºÚ P TPI_FFSR_TCPresent_Msk ÁÚ P TPI_FFSR_FtStopped_Pos Ú P TPI_FFSR_FtStopped_Msk Ú P TPI_FFSR_FlInProg_Pos 3Ú P TPI_FFSR_FlInProg_Msk :Ú P TPI_FFCR_TrigIn_Pos ûÚ P TPI_FFCR_TrigIn_Msk Ú P TPI_FFCR_EnFCont_Pos ¹Ú P TPI_FFCR_EnFCont_Msk ÀÚ P TPI_TRIGGER_TRIGGER_Pos 9Ú P TPI_TRIGGER_TRIGGER_Msk @Ú" P TPI_FIFO0_ITM_ATVALID_Pos »Ú" P TPI_FIFO0_ITM_ATVALID_Msk ÂÚ$ P TPI_FIFO0_ITM_bytecount_Pos ßÚ$ P TPI_FIFO0_ITM_bytecount_Msk æÚ" P TPI_FIFO0_ETM_ATVALID_Pos ¿Ú" P TPI_FIFO0_ETM_ATVALID_Msk ÆÚ$ P TPI_FIFO0_ETM_bytecount_Pos ãÚ$ P TPI_FIFO0_ETM_bytecount_Msk êÚ P TPI_FIFO0_ETM2_Pos ÿÚ P TPI_FIFO0_ETM2_Msk Ú P TPI_FIFO0_ETM1_Pos Ú P TPI_FIFO0_ETM1_Msk Ú P TPI_FIFO0_ETM0_Pos Ú P TPI_FIFO0_ETM0_Msk Ú" P TPI_ITATBCTR2_ATREADY_Pos ÄÚ" P TPI_ITATBCTR2_ATREADY_Msk ËÚ" P TPI_FIFO1_ITM_ATVALID_Pos ºÚ" P TPI_FIFO1_ITM_ATVALID_Msk ÁÚ$ P TPI_FIFO1_ITM_bytecount_Pos ÞÚ$ P TPI_FIFO1_ITM_bytecount_Msk åÚ" P TPI_FIFO1_ETM_ATVALID_Pos ¾Ú" P TPI_FIFO1_ETM_ATVALID_Msk ÅÚ$ P TPI_FIFO1_ETM_bytecount_Pos âÚ$ P TPI_FIFO1_ETM_bytecount_Msk éÚ P TPI_FIFO1_ITM2_Pos úÚ P TPI_FIFO1_ITM2_Msk Ú P TPI_FIFO1_ITM1_Pos ûÚ P TPI_FIFO1_ITM1_Msk Ú P TPI_FIFO1_ITM0_Pos üÚ P TPI_FIFO1_ITM0_Msk Ú" P TPI_ITATBCTR0_ATREADY_Pos ÆÚ" P TPI_ITATBCTR0_ATREADY_Msk ÍÚ P TPI_ITCTRL_Mode_Pos Ú P TPI_ITCTRL_Mode_Msk Ú P TPI_DEVID_NRZVALID_Pos Ú P TPI_DEVID_NRZVALID_Msk Ú P TPI_DEVID_MANCVALID_Pos fÚ P TPI_DEVID_MANCVALID_Msk mÚ P TPI_DEVID_PTINVALID_Pos JÚ P TPI_DEVID_PTINVALID_Msk QÚ P TPI_DEVID_MinBufSz_Pos éÚ P TPI_DEVID_MinBufSz_Msk ðÚ P TPI_DEVID_AsynClkIn_Pos Ú P TPI_DEVID_AsynClkIn_Msk Ú# P TPI_DEVID_NrTraceInput_Pos 0Ú# P TPI_DEVID_NrTraceInput_Msk 7Ú P TPI_DEVTYPE_SubType_Pos tÚ P TPI_DEVTYPE_SubType_Msk {Ú" P TPI_DEVTYPE_MajorType_Pos ¡Ú" P TPI_DEVTYPE_MajorType_Msk ¨Ú 8 |
| 451 |
<unnamed> QÚ |
451 |
<unnamed> QÚ |
| 452 |
" «TYPE ÄÚ |
452 |
" «TYPE ÄÚ |
| 453 |
" «CTRL ÑÚ |
453 |
" «CTRL ÑÚ |
| 454 |
" «RNR Ú |
454 |
" «RNR Ú |
| 455 |
" «RBAR ßÚ |
455 |
" «RBAR ßÚ |
| 456 |
" «RASR ÎÚ |
456 |
" «RASR ÎÚ |
| 457 |
" «RBAR_A1 Ú |
457 |
" «RBAR_A1 Ú |
| 458 |
" «RASR_A1 ÷Ú |
458 |
" «RASR_A1 ÷Ú |
| 459 |
" «RBAR_A2 Ú |
459 |
" «RBAR_A2 Ú |
| 460 |
" «RASR_A2 öÚ |
460 |
" «RASR_A2 öÚ |
| 461 |
" «RBAR_A3 Ú |
461 |
" «RBAR_A3 Ú |
| 462 |
" «RASR_A3 õÚ MPU_Type þÚ P MPU_TYPE_IREGION_Pos Ú P MPU_TYPE_IREGION_Msk Ú P MPU_TYPE_DREGION_Pos Ú P MPU_TYPE_DREGION_Msk Ú P MPU_TYPE_SEPARATE_Pos ÉÚ P MPU_TYPE_SEPARATE_Msk ÐÚ P MPU_CTRL_PRIVDEFENA_Pos CÚ P MPU_CTRL_PRIVDEFENA_Msk JÚ P MPU_CTRL_HFNMIENA_Pos åÚ P MPU_CTRL_HFNMIENA_Msk ìÚ P MPU_CTRL_ENABLE_Pos Ú P MPU_CTRL_ENABLE_Msk Ú P MPU_RNR_REGION_Pos °Ú P MPU_RNR_REGION_Msk ·Ú P MPU_RBAR_ADDR_Pos &Ú P MPU_RBAR_ADDR_Msk -Ú P MPU_RBAR_VALID_Pos ÏÚ P MPU_RBAR_VALID_Msk ÖÚ P MPU_RBAR_REGION_Pos yÚ P MPU_RBAR_REGION_Msk Ú P MPU_RASR_ATTRS_Pos Ú P MPU_RASR_ATTRS_Msk §Ú P MPU_RASR_XN_Pos Ú P MPU_RASR_XN_Msk Ú P MPU_RASR_AP_Pos £Ú P MPU_RASR_AP_Msk ªÚ P MPU_RASR_TEX_Pos AÚ P MPU_RASR_TEX_Msk HÚ P MPU_RASR_S_Pos ãÚ P MPU_RASR_S_Msk êÚ P MPU_RASR_C_Pos óÚ P MPU_RASR_C_Msk úÚ P MPU_RASR_B_Pos ôÚ P MPU_RASR_B_Msk ûÚ P MPU_RASR_SRD_Pos IÚ P MPU_RASR_SRD_Msk PÚ P MPU_RASR_SIZE_Pos õÚ P MPU_RASR_SIZE_Msk üÚ P MPU_RASR_ENABLE_Pos
Ú P MPU_RASR_ENABLE_Msk Ú 8 |
462 |
" «RASR_A3 õÚ MPU_Type þÚ P MPU_TYPE_IREGION_Pos Ú P MPU_TYPE_IREGION_Msk Ú P MPU_TYPE_DREGION_Pos Ú P MPU_TYPE_DREGION_Msk Ú P MPU_TYPE_SEPARATE_Pos ÉÚ P MPU_TYPE_SEPARATE_Msk ÐÚ P MPU_CTRL_PRIVDEFENA_Pos CÚ P MPU_CTRL_PRIVDEFENA_Msk JÚ P MPU_CTRL_HFNMIENA_Pos åÚ P MPU_CTRL_HFNMIENA_Msk ìÚ P MPU_CTRL_ENABLE_Pos Ú P MPU_CTRL_ENABLE_Msk Ú P MPU_RNR_REGION_Pos °Ú P MPU_RNR_REGION_Msk ·Ú P MPU_RBAR_ADDR_Pos &Ú P MPU_RBAR_ADDR_Msk -Ú P MPU_RBAR_VALID_Pos ÏÚ P MPU_RBAR_VALID_Msk ÖÚ P MPU_RBAR_REGION_Pos yÚ P MPU_RBAR_REGION_Msk Ú P MPU_RASR_ATTRS_Pos Ú P MPU_RASR_ATTRS_Msk §Ú P MPU_RASR_XN_Pos Ú P MPU_RASR_XN_Msk Ú P MPU_RASR_AP_Pos £Ú P MPU_RASR_AP_Msk ªÚ P MPU_RASR_TEX_Pos AÚ P MPU_RASR_TEX_Msk HÚ P MPU_RASR_S_Pos ãÚ P MPU_RASR_S_Msk êÚ P MPU_RASR_C_Pos óÚ P MPU_RASR_C_Msk úÚ P MPU_RASR_B_Pos ôÚ P MPU_RASR_B_Msk ûÚ P MPU_RASR_SRD_Pos IÚ P MPU_RASR_SRD_Msk PÚ P MPU_RASR_SIZE_Pos õÚ P MPU_RASR_SIZE_Msk üÚ P MPU_RASR_ENABLE_Pos
Ú P MPU_RASR_ENABLE_Msk Ú 8 |
| 463 |
<unnamed> QÚ |
463 |
<unnamed> QÚ |
| 464 |
" àDHCSR [Ú |
464 |
" àDHCSR [Ú |
| 465 |
" àDCRSR QÚ |
465 |
" àDCRSR QÚ |
| 466 |
" àDCRDR `Ú |
466 |
" àDCRDR `Ú |
| 467 |
" àDEMCR dÚ CoreDebug_Type tÚ# P CoreDebug_DHCSR_DBGKEY_Pos ®Ú# P CoreDebug_DHCSR_DBGKEY_Msk µÚ' P CoreDebug_DHCSR_S_RESET_ST_Pos !Ú' P CoreDebug_DHCSR_S_RESET_ST_Msk (Ú( P CoreDebug_DHCSR_S_RETIRE_ST_Pos ×Ú( P CoreDebug_DHCSR_S_RETIRE_ST_Msk ÞÚ% P CoreDebug_DHCSR_S_LOCKUP_Pos àÚ% P CoreDebug_DHCSR_S_LOCKUP_Msk çÚ$ P CoreDebug_DHCSR_S_SLEEP_Pos 7Ú$ P CoreDebug_DHCSR_S_SLEEP_Msk >Ú# P CoreDebug_DHCSR_S_HALT_Pos Ú# P CoreDebug_DHCSR_S_HALT_Msk Ú% P CoreDebug_DHCSR_S_REGRDY_Pos áÚ% P CoreDebug_DHCSR_S_REGRDY_Msk èÚ( P CoreDebug_DHCSR_C_SNAPSTALL_Pos Ú( P CoreDebug_DHCSR_C_SNAPSTALL_Msk
Ú' P CoreDebug_DHCSR_C_MASKINTS_Pos PÚ' P CoreDebug_DHCSR_C_MASKINTS_Msk WÚ# P CoreDebug_DHCSR_C_STEP_Pos Ú# P CoreDebug_DHCSR_C_STEP_Msk Ú# P CoreDebug_DHCSR_C_HALT_Pos Ú# P CoreDebug_DHCSR_C_HALT_Msk Ú& P CoreDebug_DHCSR_C_DEBUGEN_Pos ÂÚ& P CoreDebug_DHCSR_C_DEBUGEN_Msk ÉÚ# P CoreDebug_DCRSR_REGWnR_Pos eÚ# P CoreDebug_DCRSR_REGWnR_Msk lÚ# P CoreDebug_DCRSR_REGSEL_Pos Ú# P CoreDebug_DCRSR_REGSEL_Msk Ú# P CoreDebug_DEMCR_TRCENA_Pos °Ú# P CoreDebug_DEMCR_TRCENA_Msk ·Ú$ P CoreDebug_DEMCR_MON_REQ_Pos :Ú$ P CoreDebug_DEMCR_MON_REQ_Msk AÚ% P CoreDebug_DEMCR_MON_STEP_Pos äÚ% P CoreDebug_DEMCR_MON_STEP_Msk ëÚ% P CoreDebug_DEMCR_MON_PEND_Pos ùÚ% P CoreDebug_DEMCR_MON_PEND_Msk Ú# P CoreDebug_DEMCR_MON_EN_Pos Ú# P CoreDebug_DEMCR_MON_EN_Msk Ú' P CoreDebug_DEMCR_VC_HARDERR_Pos eÚ' P CoreDebug_DEMCR_VC_HARDERR_Msk lÚ& P CoreDebug_DEMCR_VC_INTERR_Pos Ú& P CoreDebug_DEMCR_VC_INTERR_Msk ¢Ú& P CoreDebug_DEMCR_VC_BUSERR_Pos Ú& P CoreDebug_DEMCR_VC_BUSERR_Msk £Ú' P CoreDebug_DEMCR_VC_STATERR_Pos HÚ' P CoreDebug_DEMCR_VC_STATERR_Msk OÚ& P CoreDebug_DEMCR_VC_CHKERR_Pos °Ú& P CoreDebug_DEMCR_VC_CHKERR_Msk ·Ú' P CoreDebug_DEMCR_VC_NOCPERR_Pos TÚ' P CoreDebug_DEMCR_VC_NOCPERR_Msk [Ú% P CoreDebug_DEMCR_VC_MMERR_Pos îÚ% P CoreDebug_DEMCR_VC_MMERR_Msk õÚ) P !CoreDebug_DEMCR_VC_CORERESET_Pos ½Ú) P !CoreDebug_DEMCR_VC_CORERESET_Msk ÄÚ P SCS_BASE XÚ P ITM_BASE WÚ P DWT_BASE RÚ P TPI_BASE TÚ P CoreDebug_BASE ÅÚ P
SysTick_BASE oÚ P |
467 |
" àDEMCR dÚ CoreDebug_Type tÚ# P CoreDebug_DHCSR_DBGKEY_Pos ®Ú# P CoreDebug_DHCSR_DBGKEY_Msk µÚ' P CoreDebug_DHCSR_S_RESET_ST_Pos !Ú' P CoreDebug_DHCSR_S_RESET_ST_Msk (Ú( P CoreDebug_DHCSR_S_RETIRE_ST_Pos ×Ú( P CoreDebug_DHCSR_S_RETIRE_ST_Msk ÞÚ% P CoreDebug_DHCSR_S_LOCKUP_Pos àÚ% P CoreDebug_DHCSR_S_LOCKUP_Msk çÚ$ P CoreDebug_DHCSR_S_SLEEP_Pos 7Ú$ P CoreDebug_DHCSR_S_SLEEP_Msk >Ú# P CoreDebug_DHCSR_S_HALT_Pos Ú# P CoreDebug_DHCSR_S_HALT_Msk Ú% P CoreDebug_DHCSR_S_REGRDY_Pos áÚ% P CoreDebug_DHCSR_S_REGRDY_Msk èÚ( P CoreDebug_DHCSR_C_SNAPSTALL_Pos Ú( P CoreDebug_DHCSR_C_SNAPSTALL_Msk
Ú' P CoreDebug_DHCSR_C_MASKINTS_Pos PÚ' P CoreDebug_DHCSR_C_MASKINTS_Msk WÚ# P CoreDebug_DHCSR_C_STEP_Pos Ú# P CoreDebug_DHCSR_C_STEP_Msk Ú# P CoreDebug_DHCSR_C_HALT_Pos Ú# P CoreDebug_DHCSR_C_HALT_Msk Ú& P CoreDebug_DHCSR_C_DEBUGEN_Pos ÂÚ& P CoreDebug_DHCSR_C_DEBUGEN_Msk ÉÚ# P CoreDebug_DCRSR_REGWnR_Pos eÚ# P CoreDebug_DCRSR_REGWnR_Msk lÚ# P CoreDebug_DCRSR_REGSEL_Pos Ú# P CoreDebug_DCRSR_REGSEL_Msk Ú# P CoreDebug_DEMCR_TRCENA_Pos °Ú# P CoreDebug_DEMCR_TRCENA_Msk ·Ú$ P CoreDebug_DEMCR_MON_REQ_Pos :Ú$ P CoreDebug_DEMCR_MON_REQ_Msk AÚ% P CoreDebug_DEMCR_MON_STEP_Pos äÚ% P CoreDebug_DEMCR_MON_STEP_Msk ëÚ% P CoreDebug_DEMCR_MON_PEND_Pos ùÚ% P CoreDebug_DEMCR_MON_PEND_Msk Ú# P CoreDebug_DEMCR_MON_EN_Pos Ú# P CoreDebug_DEMCR_MON_EN_Msk Ú' P CoreDebug_DEMCR_VC_HARDERR_Pos eÚ' P CoreDebug_DEMCR_VC_HARDERR_Msk lÚ& P CoreDebug_DEMCR_VC_INTERR_Pos Ú& P CoreDebug_DEMCR_VC_INTERR_Msk ¢Ú& P CoreDebug_DEMCR_VC_BUSERR_Pos Ú& P CoreDebug_DEMCR_VC_BUSERR_Msk £Ú' P CoreDebug_DEMCR_VC_STATERR_Pos HÚ' P CoreDebug_DEMCR_VC_STATERR_Msk OÚ& P CoreDebug_DEMCR_VC_CHKERR_Pos °Ú& P CoreDebug_DEMCR_VC_CHKERR_Msk ·Ú' P CoreDebug_DEMCR_VC_NOCPERR_Pos TÚ' P CoreDebug_DEMCR_VC_NOCPERR_Msk [Ú% P CoreDebug_DEMCR_VC_MMERR_Pos îÚ% P CoreDebug_DEMCR_VC_MMERR_Msk õÚ) P !CoreDebug_DEMCR_VC_CORERESET_Pos ½Ú) P !CoreDebug_DEMCR_VC_CORERESET_Msk ÄÚ P SCS_BASE XÚ P ITM_BASE WÚ P DWT_BASE RÚ P TPI_BASE TÚ P CoreDebug_BASE ÅÚ P
SysTick_BASE oÚ P |
| 468 |
NVIC_BASE Ú P SCB_BASE iÚ P SCnSCB ãÚ P SCB íÚ P SysTick óÚ
P NVIC Ú P ITM ÛÚ P DWT ÖÚ P TPI ØÚ P |
468 |
NVIC_BASE Ú P SCB_BASE iÚ P SCnSCB ãÚ P SCB íÚ P SysTick óÚ
P NVIC Ú P ITM ÛÚ P DWT ÖÚ P TPI ØÚ P |
| 469 |
CoreDebug IÚ P MPU_BASE OÚ P MPU ÓÚ! NVIC_SetPriorityGrouping \Ú , |
469 |
CoreDebug IÚ P MPU_BASE OÚ P MPU ÓÚ! NVIC_SetPriorityGrouping \Ú , |
| 470 |
" ®PriorityGroup uÚ |
470 |
" ®PriorityGroup uÚ |
| 471 |
" ® |
471 |
" ® |
| 472 |
reg_value VÚ |
472 |
reg_value VÚ |
| 473 |
" ®PriorityGroupTmp bÚ! NVIC_GetPriorityGrouping hÚ NVIC_EnableIRQ Ú ,"" ³IRQn Ú NVIC_DisableIRQ §Ú ,"" µIRQn Ú NVIC_GetPendingIRQ pÚ ,"" ·IRQn ~Ú NVIC_SetPendingIRQ dÚ ,"" ¹IRQn |Ú NVIC_ClearPendingIRQ ¥Ú ,"" »IRQn zÚ NVIC_GetActive ÍÚ ,"" ½IRQn xÚ NVIC_SetPriority ·Ú ,"" ¿IRQn vÚ , |
473 |
" ®PriorityGroupTmp bÚ! NVIC_GetPriorityGrouping hÚ NVIC_EnableIRQ Ú ,"" ³IRQn Ú NVIC_DisableIRQ §Ú ,"" µIRQn Ú NVIC_GetPendingIRQ pÚ ,"" ·IRQn ~Ú NVIC_SetPendingIRQ dÚ ,"" ¹IRQn |Ú NVIC_ClearPendingIRQ ¥Ú ,"" »IRQn zÚ NVIC_GetActive ÍÚ ,"" ½IRQn xÚ NVIC_SetPriority ·Ú ,"" ¿IRQn vÚ , |
| 474 |
" ¿ priority [Ú NVIC_GetPriority ÃÚ ,"" ÂIRQn sÚ NVIC_EncodePriority Ú , |
474 |
" ¿ priority [Ú NVIC_GetPriority ÃÚ ,"" ÂIRQn sÚ NVIC_EncodePriority Ú , |
| 475 |
" ÄPriorityGroup _Ú , |
475 |
" ÄPriorityGroup _Ú , |
| 476 |
" ÄPreemptPriority Ú , |
476 |
" ÄPreemptPriority Ú , |
| 477 |
" Ä SubPriority FÚ |
477 |
" Ä SubPriority FÚ |
| 478 |
" ÄPriorityGroupTmp LÚ |
478 |
" ÄPriorityGroupTmp LÚ |
| 479 |
" ÄPreemptPriorityBits Ú |
479 |
" ÄPreemptPriorityBits Ú |
| 480 |
" ÄSubPriorityBits ÐÚ NVIC_DecodePriority Ú , |
480 |
" ÄSubPriorityBits ÐÚ NVIC_DecodePriority Ú , |
| 481 |
" Ë Priority oÚ , |
481 |
" Ë Priority oÚ , |
| 482 |
" ËPriorityGroup XÚ ," ËpPreemptPriority Ú ," Ë
pSubPriority ¿Ú |
482 |
" ËPriorityGroup XÚ ," ËpPreemptPriority Ú ," Ë
pSubPriority ¿Ú |
| 483 |
" ËPriorityGroupTmp EÚ |
483 |
" ËPriorityGroupTmp EÚ |
| 484 |
" ËPreemptPriorityBits Ú |
484 |
" ËPreemptPriorityBits Ú |
| 485 |
" ËSubPriorityBits ÉÚ NVIC_SystemReset ½Ú __dsb çÚ SysTick_Config YÚ , |
485 |
" ËSubPriorityBits ÉÚ NVIC_SystemReset ½Ú __dsb çÚ SysTick_Config YÚ , |
| 486 |
" Õticks ¯Ú
ITM_RxBuffer xÚ P ITM_RXBUFFER_EMPTY Ú
ITM_SendChar Ú
, |
486 |
" Õticks ¯Ú
ITM_RxBuffer xÚ P ITM_RXBUFFER_EMPTY Ú
ITM_SendChar Ú
, |
| 487 |
" Ùch Ú ITM_ReceiveChar LÚ
" Ûch (Ú ITM_CheckChar 5Ú RESET pÚ SET Ú FlagStatus ïÚ ITStatus ÐÚ DISABLE ûÚ ENABLE JÚ FunctionalState ÏÚ P IS_FUNCTIONAL_STATE ×Ú ERROR iÚ SUCCESS ÖÚ ErrorStatus ]Ú P __RAM_FUNC Ú 8 |
487 |
" Ùch Ú ITM_ReceiveChar LÚ
" Ûch (Ú ITM_CheckChar 5Ú RESET pÚ SET Ú FlagStatus ïÚ ITStatus ÐÚ DISABLE ûÚ ENABLE JÚ FunctionalState ÏÚ P IS_FUNCTIONAL_STATE ×Ú ERROR iÚ SUCCESS ÖÚ ErrorStatus ]Ú P __RAM_FUNC Ú 8 |
| 488 |
<unnamed> QÚ
|
488 |
<unnamed> QÚ
|
| 489 |
" êSR %Ú |
489 |
" êSR %Ú |
| 490 |
" êCR1 Ú |
490 |
" êCR1 Ú |
| 491 |
" êCR2 Ú |
491 |
" êCR2 Ú |
| 492 |
" êSMPR1 QÚ |
492 |
" êSMPR1 QÚ |
| 493 |
" êSMPR2 PÚ |
493 |
" êSMPR2 PÚ |
| 494 |
" êSMPR3 OÚ |
494 |
" êSMPR3 OÚ |
| 495 |
" êJOFR1 bÚ |
495 |
" êJOFR1 bÚ |
| 496 |
" êJOFR2 aÚ |
496 |
" êJOFR2 aÚ |
| 497 |
" êJOFR3 `Ú |
497 |
" êJOFR3 `Ú |
| 498 |
" êJOFR4 _Ú |
498 |
" êJOFR4 _Ú |
| 499 |
" êHTR ÚÚ |
499 |
" êHTR ÚÚ |
| 500 |
" êLTR ÖÚ |
500 |
" êLTR ÖÚ |
| 501 |
" êSQR1 Ú |
501 |
" êSQR1 Ú |
| 502 |
" êSQR2 Ú |
502 |
" êSQR2 Ú |
| 503 |
" êSQR3 Ú |
503 |
" êSQR3 Ú |
| 504 |
" êSQR4 Ú |
504 |
" êSQR4 Ú |
| 505 |
" êSQR5 Ú |
505 |
" êSQR5 Ú |
| 506 |
" êJSQR Ú |
506 |
" êJSQR Ú |
| 507 |
" êJDR1 µÚ |
507 |
" êJDR1 µÚ |
| 508 |
" êJDR2 ´Ú |
508 |
" êJDR2 ´Ú |
| 509 |
" êJDR3 ³Ú |
509 |
" êJDR3 ³Ú |
| 510 |
" êJDR4 ²Ú
|
510 |
" êJDR4 ²Ú
|
| 511 |
" êDR 4Ú |
511 |
" êDR 4Ú |
| 512 |
" êSMPR0 RÚ ADC_TypeDef Ú 8 |
512 |
" êSMPR0 RÚ ADC_TypeDef Ú 8 |
| 513 |
<unnamed> QÚ |
513 |
<unnamed> QÚ |
| 514 |
" CSR EÚ |
514 |
" CSR EÚ |
| 515 |
" CCR UÚ ADC_Common_TypeDef =Ú 8 |
515 |
" CCR UÚ ADC_Common_TypeDef =Ú 8 |
| 516 |
<unnamed> QÚ
|
516 |
<unnamed> QÚ
|
| 517 |
" CR Ú
|
517 |
" CR Ú
|
| 518 |
" SR Ú |
518 |
" SR Ú |
| 519 |
" DINR úÚ |
519 |
" DINR úÚ |
| 520 |
" DOUTR Ú |
520 |
" DOUTR Ú |
| 521 |
" KEYR0 ºÚ |
521 |
" KEYR0 ºÚ |
| 522 |
" KEYR1 ¹Ú |
522 |
" KEYR1 ¹Ú |
| 523 |
" KEYR2 ¸Ú |
523 |
" KEYR2 ¸Ú |
| 524 |
" KEYR3 ·Ú |
524 |
" KEYR3 ·Ú |
| 525 |
" IVR0 Ú |
525 |
" IVR0 Ú |
| 526 |
" IVR1 Ú |
526 |
" IVR1 Ú |
| 527 |
" IVR2 Ú |
527 |
" IVR2 Ú |
| 528 |
" IVR3 Ú AES_TypeDef Ú 8 |
528 |
" IVR3 Ú AES_TypeDef Ú 8 |
| 529 |
<unnamed> QÚ |
529 |
<unnamed> QÚ |
| 530 |
" CSR 3Ú
COMP_TypeDef ªÚ 8 |
530 |
" CSR 3Ú
COMP_TypeDef ªÚ 8 |
| 531 |
<unnamed> QÚ
|
531 |
<unnamed> QÚ
|
| 532 |
" DR Ú " IDR @Ú " |
532 |
" DR Ú " IDR @Ú " |
| 533 |
RESERVED0 Ú " |
533 |
RESERVED0 Ú " |
| 534 |
RESERVED1 yÚ
|
534 |
RESERVED1 yÚ
|
| 535 |
" CR
Ú CRC_TypeDef Ú 8 |
535 |
" CR
Ú CRC_TypeDef Ú 8 |
| 536 |
<unnamed> QÚ
|
536 |
<unnamed> QÚ
|
| 537 |
" CR ~Ú |
537 |
" CR ~Ú |
| 538 |
" SWTRIGR ×Ú |
538 |
" SWTRIGR ×Ú |
| 539 |
" DHR12R1 EÚ |
539 |
" DHR12R1 EÚ |
| 540 |
" DHR12L1 KÚ |
540 |
" DHR12L1 KÚ |
| 541 |
" DHR8R1 rÚ |
541 |
" DHR8R1 rÚ |
| 542 |
" DHR12R2 DÚ |
542 |
" DHR12R2 DÚ |
| 543 |
" DHR12L2 JÚ |
543 |
" DHR12L2 JÚ |
| 544 |
" DHR8R2 qÚ |
544 |
" DHR8R2 qÚ |
| 545 |
" DHR12RD 2Ú |
545 |
" DHR12RD 2Ú |
| 546 |
" DHR12LD 8Ú |
546 |
" DHR12LD 8Ú |
| 547 |
" DHR8RD _Ú |
547 |
" DHR8RD _Ú |
| 548 |
" DOR1 ùÚ |
548 |
" DOR1 ùÚ |
| 549 |
" DOR2 øÚ
|
549 |
" DOR2 øÚ
|
| 550 |
" SR nÚ DAC_TypeDef Ú 8 |
550 |
" SR nÚ DAC_TypeDef Ú 8 |
| 551 |
<unnamed> QÚ |
551 |
<unnamed> QÚ |
| 552 |
" °IDCODE SÚ
|
552 |
" °IDCODE SÚ
|
| 553 |
" °CR nÚ |
553 |
" °CR nÚ |
| 554 |
" °APB1FZ WÚ |
554 |
" °APB1FZ WÚ |
| 555 |
" °APB2FZ VÚ DBGMCU_TypeDef #Ú 8 |
555 |
" °APB2FZ VÚ DBGMCU_TypeDef #Ú 8 |
| 556 |
<unnamed> QÚ |
556 |
<unnamed> QÚ |
| 557 |
" ¶CCR #Ú |
557 |
" ¶CCR #Ú |
| 558 |
" ¶CNDTR |Ú |
558 |
" ¶CNDTR |Ú |
| 559 |
" ¶CPAR ÓÚ |
559 |
" ¶CPAR ÓÚ |
| 560 |
" ¶CMAR ÖÚ DMA_Channel_TypeDef áÚ 8 |
560 |
" ¶CMAR ÖÚ DMA_Channel_TypeDef áÚ 8 |
| 561 |
<unnamed> QÚ |
561 |
<unnamed> QÚ |
| 562 |
" ¼ISR Ú |
562 |
" ¼ISR Ú |
| 563 |
" ¼IFCR ÏÚ DMA_TypeDef Ú 8 |
563 |
" ¼IFCR ÏÚ DMA_TypeDef Ú 8 |
| 564 |
<unnamed> QÚ |
564 |
<unnamed> QÚ |
| 565 |
" ÀIMR Ú |
565 |
" ÀIMR Ú |
| 566 |
" ÀEMR
Ú |
566 |
" ÀEMR
Ú |
| 567 |
" ÀRTSR ¤Ú |
567 |
" ÀRTSR ¤Ú |
| 568 |
" ÀFTSR °Ú |
568 |
" ÀFTSR °Ú |
| 569 |
" ÀSWIER cÚ
|
569 |
" ÀSWIER cÚ
|
| 570 |
" ÀPR QÚ
EXTI_TypeDef Ú 8 |
570 |
" ÀPR QÚ
EXTI_TypeDef Ú 8 |
| 571 |
<unnamed> QÚ |
571 |
<unnamed> QÚ |
| 572 |
" ÈACR Ú |
572 |
" ÈACR Ú |
| 573 |
" ÈPECR ½Ú |
573 |
" ÈPECR ½Ú |
| 574 |
" ÈPDKEYR Ú |
574 |
" ÈPDKEYR Ú |
| 575 |
" ÈPEKEYR Ú |
575 |
" ÈPEKEYR Ú |
| 576 |
" ÈPRGKEYR ½Ú |
576 |
" ÈPRGKEYR ½Ú |
| 577 |
" ÈOPTKEYR ³Ú
|
577 |
" ÈOPTKEYR ³Ú
|
| 578 |
" ÈSR FÚ |
578 |
" ÈSR FÚ |
| 579 |
" ÈOBR Ú |
579 |
" ÈOBR Ú |
| 580 |
" ÈWRPR Ú <" \È RESERVED õÚ |
580 |
" ÈWRPR Ú <" \È RESERVED õÚ |
| 581 |
" ÈWRPR1 iÚ |
581 |
" ÈWRPR1 iÚ |
| 582 |
" ÈWRPR2 hÚ FLASH_TypeDef iÚ 8 |
582 |
" ÈWRPR2 hÚ FLASH_TypeDef iÚ 8 |
| 583 |
<unnamed> QÚ |
583 |
<unnamed> QÚ |
| 584 |
" ÖRDP õÚ |
584 |
" ÖRDP õÚ |
| 585 |
" ÖUSER Ú |
585 |
" ÖUSER Ú |
| 586 |
" ÖWRP01 }Ú |
586 |
" ÖWRP01 }Ú |
| 587 |
" ÖWRP23 yÚ |
587 |
" ÖWRP23 yÚ |
| 588 |
" ÖWRP45 uÚ |
588 |
" ÖWRP45 uÚ |
| 589 |
" ÖWRP67 qÚ |
589 |
" ÖWRP67 qÚ |
| 590 |
" ÖWRP89 mÚ |
590 |
" ÖWRP89 mÚ |
| 591 |
" ÖWRP1011 Ú OB_TypeDef LÚ 8 |
591 |
" ÖWRP1011 Ú OB_TypeDef LÚ 8 |
| 592 |
<unnamed> QÚ |
592 |
<unnamed> QÚ |
| 593 |
" àCSR éÚ |
593 |
" àCSR éÚ |
| 594 |
" àOTR ÜÚ |
594 |
" àOTR ÜÚ |
| 595 |
" àLPOTR <Ú OPAMP_TypeDef ZÚ 8 |
595 |
" àLPOTR <Ú OPAMP_TypeDef ZÚ 8 |
| 596 |
<unnamed> QÚ <" åBTCR QÚ FSMC_Bank1_TypeDef Ú 8 |
596 |
<unnamed> QÚ <" åBTCR QÚ FSMC_Bank1_TypeDef Ú 8 |
| 597 |
<unnamed> QÚ <" èBWTR >Ú FSMC_Bank1E_TypeDef QÚ 8 |
597 |
<unnamed> QÚ <" èBWTR >Ú FSMC_Bank1E_TypeDef QÚ 8 |
| 598 |
<unnamed> QÚ |
598 |
<unnamed> QÚ |
| 599 |
" ëMEMRMP òÚ |
599 |
" ëMEMRMP òÚ |
| 600 |
" ëPMC æÚ <" ëEXTICR ³Ú SYSCFG_TypeDef Ú 8 |
600 |
" ëPMC æÚ <" ëEXTICR ³Ú SYSCFG_TypeDef Ú 8 |
| 601 |
<unnamed> QÚ " ðCR1 ùÚ " ð |
601 |
<unnamed> QÚ " ðCR1 ùÚ " ð |
| 602 |
RESERVED0 #Ú " ðCR2 øÚ " ð |
602 |
RESERVED0 #Ú " ðCR2 øÚ " ð |
| 603 |
RESERVED1 "Ú " ðOAR1 ªÚ " ð |
603 |
RESERVED1 "Ú " ðOAR1 ªÚ " ð |
| 604 |
RESERVED2 !Ú " ðOAR2 ©Ú " ð |
604 |
RESERVED2 !Ú " ðOAR2 ©Ú " ð |
| 605 |
RESERVED3 Ú
" ðDR +Ú " ð |
605 |
RESERVED3 Ú
" ðDR +Ú " ð |
| 606 |
RESERVED4 Ú " ðSR1 éÚ " ð |
606 |
RESERVED4 Ú " ðSR1 éÚ " ð |
| 607 |
RESERVED5 Ú " ðSR2 èÚ " ð |
607 |
RESERVED5 Ú " ðSR2 èÚ " ð |
| 608 |
RESERVED6 Ú " ðCCR çÚ " ð |
608 |
RESERVED6 Ú " ðCCR çÚ " ð |
| 609 |
RESERVED7 Ú " ðTRISE 4Ú " ð |
609 |
RESERVED7 Ú " ðTRISE 4Ú " ð |
| 610 |
RESERVED8 Ú I2C_TypeDef Ú 8 |
610 |
RESERVED8 Ú I2C_TypeDef Ú 8 |
| 611 |
<unnamed> QÚ
|
611 |
<unnamed> QÚ
|
| 612 |
" KR Ú
|
612 |
" KR Ú
|
| 613 |
" PR Ú |
613 |
" PR Ú |
| 614 |
" RLR <Ú
|
614 |
" RLR <Ú
|
| 615 |
" SR Ú
IWDG_TypeDef ®Ú 8 |
615 |
" SR Ú
IWDG_TypeDef ®Ú 8 |
| 616 |
<unnamed> QÚ
|
616 |
<unnamed> QÚ
|
| 617 |
" CR Ú |
617 |
" CR Ú |
| 618 |
" FCR KÚ
|
618 |
" FCR KÚ
|
| 619 |
" SR Ú |
619 |
" SR Ú |
| 620 |
" CLR EÚ |
620 |
" CLR EÚ |
| 621 |
" RESERVED ¼Ú <" @RAM ØÚ LCD_TypeDef Ú 8 |
621 |
" RESERVED ¼Ú <" @RAM ØÚ LCD_TypeDef Ú 8 |
| 622 |
<unnamed> QÚ
|
622 |
<unnamed> QÚ
|
| 623 |
" CR Ú |
623 |
" CR Ú |
| 624 |
" CSR 6Ú PWR_TypeDef âÚ 8 |
624 |
" CSR 6Ú PWR_TypeDef âÚ 8 |
| 625 |
<unnamed> QÚ
|
625 |
<unnamed> QÚ
|
| 626 |
" CR Ú |
626 |
" CR Ú |
| 627 |
" ICSCR ¢Ú |
627 |
" ICSCR ¢Ú |
| 628 |
" CFGR öÚ |
628 |
" CFGR öÚ |
| 629 |
" CIR <Ú |
629 |
" CIR <Ú |
| 630 |
" AHBRSTR üÚ |
630 |
" AHBRSTR üÚ |
| 631 |
" APB2RSTR ÀÚ |
631 |
" APB2RSTR ÀÚ |
| 632 |
" APB1RSTR ÁÚ |
632 |
" APB1RSTR ÁÚ |
| 633 |
" AHBENR dÚ |
633 |
" AHBENR dÚ |
| 634 |
" APB2ENR (Ú |
634 |
" APB2ENR (Ú |
| 635 |
" APB1ENR )Ú |
635 |
" APB1ENR )Ú |
| 636 |
" AHBLPENR ÄÚ |
636 |
" AHBLPENR ÄÚ |
| 637 |
" |
637 |
" |
| 638 |
APB2LPENR Ú |
638 |
APB2LPENR Ú |
| 639 |
" |
639 |
" |
| 640 |
APB1LPENR Ú |
640 |
APB1LPENR Ú |
| 641 |
" CSR 2Ú RCC_TypeDef Ú 8 |
641 |
" CSR 2Ú RCC_TypeDef Ú 8 |
| 642 |
<unnamed> QÚ |
642 |
<unnamed> QÚ |
| 643 |
" ¦ICR ,Ú |
643 |
" ¦ICR ,Ú |
| 644 |
" ¦ASCR1 ¬Ú |
644 |
" ¦ASCR1 ¬Ú |
| 645 |
" ¦ASCR2 «Ú |
645 |
" ¦ASCR2 «Ú |
| 646 |
" ¦HYSCR1 JÚ |
646 |
" ¦HYSCR1 JÚ |
| 647 |
" ¦HYSCR2 IÚ |
647 |
" ¦HYSCR2 IÚ |
| 648 |
" ¦HYSCR3 HÚ |
648 |
" ¦HYSCR3 HÚ |
| 649 |
" ¦HYSCR4 GÚ RI_TypeDef BÚ 8 |
649 |
" ¦HYSCR4 GÚ RI_TypeDef BÚ 8 |
| 650 |
<unnamed> QÚ
|
650 |
<unnamed> QÚ
|
| 651 |
" ¯TR ]Ú
|
651 |
" ¯TR ]Ú
|
| 652 |
" ¯DR mÚ
|
652 |
" ¯DR mÚ
|
| 653 |
" ¯CR nÚ |
653 |
" ¯CR nÚ |
| 654 |
" ¯ISR Ú |
654 |
" ¯ISR Ú |
| 655 |
" ¯PRER ÆÚ |
655 |
" ¯PRER ÆÚ |
| 656 |
" ¯WUTR Ú |
656 |
" ¯WUTR Ú |
| 657 |
" ¯CALIBR NÚ |
657 |
" ¯CALIBR NÚ |
| 658 |
" ¯ALRMAR <Ú |
658 |
" ¯ALRMAR <Ú |
| 659 |
" ¯ALRMBR ;Ú |
659 |
" ¯ALRMBR ;Ú |
| 660 |
" ¯WPR Ú |
660 |
" ¯WPR Ú |
| 661 |
" ¯SSR Ú |
661 |
" ¯SSR Ú |
| 662 |
" ¯SHIFTR +Ú |
662 |
" ¯SHIFTR +Ú |
| 663 |
" ¯TSTR ²Ú |
663 |
" ¯TSTR ²Ú |
| 664 |
" ¯TSDR ÂÚ |
664 |
" ¯TSDR ÂÚ |
| 665 |
" ¯TSSSR ^Ú |
665 |
" ¯TSSSR ^Ú |
| 666 |
" ¯CALR ÝÚ |
666 |
" ¯CALR ÝÚ |
| 667 |
" ¯TAFCR Ú |
667 |
" ¯TAFCR Ú |
| 668 |
" ¯ ALRMASSR Ú |
668 |
" ¯ ALRMASSR Ú |
| 669 |
" ¯ ALRMBSSR Ú |
669 |
" ¯ ALRMBSSR Ú |
| 670 |
" ¯ |
670 |
" ¯ |
| 671 |
RESERVED7 ^Ú |
671 |
RESERVED7 ^Ú |
| 672 |
" ¯BKP0R Ú |
672 |
" ¯BKP0R Ú |
| 673 |
" ¯BKP1R Ú |
673 |
" ¯BKP1R Ú |
| 674 |
" ¯BKP2R Ú |
674 |
" ¯BKP2R Ú |
| 675 |
" ¯BKP3R Ú |
675 |
" ¯BKP3R Ú |
| 676 |
" ¯BKP4R Ú |
676 |
" ¯BKP4R Ú |
| 677 |
" ¯BKP5R Ú |
677 |
" ¯BKP5R Ú |
| 678 |
" ¯BKP6R Ú |
678 |
" ¯BKP6R Ú |
| 679 |
" ¯BKP7R Ú |
679 |
" ¯BKP7R Ú |
| 680 |
" ¯BKP8R Ú |
680 |
" ¯BKP8R Ú |
| 681 |
" ¯BKP9R Ú |
681 |
" ¯BKP9R Ú |
| 682 |
" ¯BKP10R kÚ |
682 |
" ¯BKP10R kÚ |
| 683 |
" ¯BKP11R jÚ |
683 |
" ¯BKP11R jÚ |
| 684 |
" ¯BKP12R iÚ |
684 |
" ¯BKP12R iÚ |
| 685 |
" ¯BKP13R hÚ |
685 |
" ¯BKP13R hÚ |
| 686 |
" ¯BKP14R gÚ |
686 |
" ¯BKP14R gÚ |
| 687 |
" ¯BKP15R fÚ |
687 |
" ¯BKP15R fÚ |
| 688 |
" ¯BKP16R eÚ |
688 |
" ¯BKP16R eÚ |
| 689 |
" ¯BKP17R dÚ |
689 |
" ¯BKP17R dÚ |
| 690 |
" ¯BKP18R cÚ |
690 |
" ¯BKP18R cÚ |
| 691 |
" ¯BKP19R bÚ |
691 |
" ¯BKP19R bÚ |
| 692 |
" ¯BKP20R jÚ |
692 |
" ¯BKP20R jÚ |
| 693 |
" ¯BKP21R iÚ |
693 |
" ¯BKP21R iÚ |
| 694 |
" ¯BKP22R hÚ |
694 |
" ¯BKP22R hÚ |
| 695 |
" ¯BKP23R gÚ |
695 |
" ¯BKP23R gÚ |
| 696 |
" ¯BKP24R fÚ |
696 |
" ¯BKP24R fÚ |
| 697 |
" ¯BKP25R eÚ |
697 |
" ¯BKP25R eÚ |
| 698 |
" ¯BKP26R dÚ |
698 |
" ¯BKP26R dÚ |
| 699 |
" ¯BKP27R cÚ |
699 |
" ¯BKP27R cÚ |
| 700 |
" ¯BKP28R bÚ |
700 |
" ¯BKP28R bÚ |
| 701 |
" ¯BKP29R aÚ |
701 |
" ¯BKP29R aÚ |
| 702 |
" ¯BKP30R iÚ |
702 |
" ¯BKP30R iÚ |
| 703 |
" ¯BKP31R hÚ RTC_TypeDef òÚ 8 |
703 |
" ¯BKP31R hÚ RTC_TypeDef òÚ 8 |
| 704 |
<unnamed> QÚ |
704 |
<unnamed> QÚ |
| 705 |
" åPOWER :Ú |
705 |
" åPOWER :Ú |
| 706 |
" åCLKCR XÚ |
706 |
" åCLKCR XÚ |
| 707 |
" åARG ñÚ |
707 |
" åARG ñÚ |
| 708 |
" åCMD ÷Ú |
708 |
" åCMD ÷Ú |
| 709 |
" åRESPCMD µÚ |
709 |
" åRESPCMD µÚ |
| 710 |
" åRESP1 \Ú |
710 |
" åRESP1 \Ú |
| 711 |
" åRESP2 [Ú |
711 |
" åRESP2 [Ú |
| 712 |
" åRESP3 ZÚ |
712 |
" åRESP3 ZÚ |
| 713 |
" åRESP4 YÚ |
713 |
" åRESP4 YÚ |
| 714 |
" åDTIMER Ú |
714 |
" åDTIMER Ú |
| 715 |
" åDLEN ¦Ú |
715 |
" åDLEN ¦Ú |
| 716 |
" åDCTRL NÚ |
716 |
" åDCTRL NÚ |
| 717 |
" åDCOUNT øÚ |
717 |
" åDCOUNT øÚ |
| 718 |
" åSTA ãÚ |
718 |
" åSTA ãÚ |
| 719 |
" åICR íÚ |
719 |
" åICR íÚ |
| 720 |
" åMASK Ú <" å |
720 |
" åMASK Ú <" å |
| 721 |
RESERVED0 ùÚ |
721 |
RESERVED0 ùÚ |
| 722 |
" åFIFOCNT ºÚ <" 4å |
722 |
" åFIFOCNT ºÚ <" 4å |
| 723 |
RESERVED1 ÌÚ |
723 |
RESERVED1 ÌÚ |
| 724 |
" åFIFO ¥Ú
SDIO_TypeDef ªÚ 8 |
724 |
" åFIFO ¥Ú
SDIO_TypeDef ªÚ 8 |
| 725 |
<unnamed> QÚ " ûCR1 íÚ " û |
725 |
<unnamed> QÚ " ûCR1 íÚ " û |
| 726 |
RESERVED0 Ú " ûCR2 ìÚ " û |
726 |
RESERVED0 Ú " ûCR2 ìÚ " û |
| 727 |
RESERVED1 Ú
" ûSR Ú " û |
727 |
RESERVED1 Ú
" ûSR Ú " û |
| 728 |
RESERVED2 Ú
" ûDR Ú " û |
728 |
RESERVED2 Ú
" ûDR Ú " û |
| 729 |
RESERVED3 Ú " ûCRCPR 5Ú " û |
729 |
RESERVED3 Ú " ûCRCPR 5Ú " û |
| 730 |
RESERVED4 Ú " ûRXCRCR ÙÚ " û |
730 |
RESERVED4 Ú " ûRXCRCR ÙÚ " û |
| 731 |
RESERVED5 Ú " ûTXCRCR ×Ú " û |
731 |
RESERVED5 Ú " ûTXCRCR ×Ú " û |
| 732 |
RESERVED6 Ú " ûI2SCFGR »Ú " û |
732 |
RESERVED6 Ú " ûI2SCFGR »Ú " û |
| 733 |
RESERVED7 Ú " ûI2SPR ?Ú " û |
733 |
RESERVED7 Ú " ûI2SPR ?Ú " û |
| 734 |
RESERVED8 Ú SPI_TypeDef ïÚ 8 |
734 |
RESERVED8 Ú SPI_TypeDef ïÚ 8 |
| 735 |
<unnamed> QÚ " CR1 XÚ " |
735 |
<unnamed> QÚ " CR1 XÚ " |
| 736 |
RESERVED0 Ú " CR2 WÚ " |
736 |
RESERVED0 Ú " CR2 WÚ " |
| 737 |
RESERVED1 Ú " SMCR çÚ " |
737 |
RESERVED1 Ú " SMCR çÚ " |
| 738 |
RESERVED2 Ú " DIER øÚ " |
738 |
RESERVED2 Ú " DIER øÚ " |
| 739 |
RESERVED3 Ú
" SR {Ú " |
739 |
RESERVED3 Ú
" SR {Ú " |
| 740 |
RESERVED4 ~Ú " EGR @Ú " |
740 |
RESERVED4 ~Ú " EGR @Ú " |
| 741 |
RESERVED5 }Ú " CCMR1 ÄÚ " |
741 |
RESERVED5 }Ú " CCMR1 ÄÚ " |
| 742 |
RESERVED6 |Ú " CCMR2 ÃÚ " |
742 |
RESERVED6 |Ú " CCMR2 ÃÚ " |
| 743 |
RESERVED7 {Ú " CCER ÿÚ " |
743 |
RESERVED7 {Ú " CCER ÿÚ " |
| 744 |
RESERVED8 zÚ |
744 |
RESERVED8 zÚ |
| 745 |
" CNT ;Ú " PSC 8Ú " RESERVED10 OÚ |
745 |
" CNT ;Ú " PSC 8Ú " RESERVED10 OÚ |
| 746 |
" ARR ;Ú |
746 |
" ARR ;Ú |
| 747 |
" RESERVED12 OÚ |
747 |
" RESERVED12 OÚ |
| 748 |
" CCR1 Ú |
748 |
" CCR1 Ú |
| 749 |
" CCR2 Ú |
749 |
" CCR2 Ú |
| 750 |
" CCR3 Ú |
750 |
" CCR3 Ú |
| 751 |
" CCR4 Ú |
751 |
" CCR4 Ú |
| 752 |
" RESERVED17 JÚ " DCR EÚ " RESERVED18 GÚ " DMAR øÚ " RESERVED19 FÚ
" OR Ú " RESERVED20 NÚ TIM_TypeDef ñÚ 8 |
752 |
" RESERVED17 JÚ " DCR EÚ " RESERVED18 GÚ " DMAR øÚ " RESERVED19 FÚ
" OR Ú " RESERVED20 NÚ TIM_TypeDef ñÚ 8 |
| 753 |
<unnamed> QÚ
" ³SR WÚ " ³ |
753 |
<unnamed> QÚ
" ³SR WÚ " ³ |
| 754 |
RESERVED0 ^Ú
" ³DR fÚ " ³ |
754 |
RESERVED0 ^Ú
" ³DR fÚ " ³ |
| 755 |
RESERVED1 ]Ú " ³BRR Ú " ³ |
755 |
RESERVED1 ]Ú " ³BRR Ú " ³ |
| 756 |
RESERVED2 \Ú " ³CR1 4Ú " ³ |
756 |
RESERVED2 \Ú " ³CR1 4Ú " ³ |
| 757 |
RESERVED3 [Ú " ³CR2 3Ú " ³ |
757 |
RESERVED3 [Ú " ³CR2 3Ú " ³ |
| 758 |
RESERVED4 ZÚ " ³CR3 2Ú " ³ |
758 |
RESERVED4 ZÚ " ³CR3 2Ú " ³ |
| 759 |
RESERVED5 YÚ " ³GTPR »Ú " ³ |
759 |
RESERVED5 YÚ " ³GTPR »Ú " ³ |
| 760 |
RESERVED6 XÚ USART_TypeDef HÚ 8 |
760 |
RESERVED6 XÚ USART_TypeDef HÚ 8 |
| 761 |
<unnamed> QÚ
|
761 |
<unnamed> QÚ
|
| 762 |
" ÃCR YÚ |
762 |
" ÃCR YÚ |
| 763 |
" ÃCFR Ú
|
763 |
" ÃCFR Ú
|
| 764 |
" ÃSR IÚ
WWDG_TypeDef Ú P FLASH_BASE ÏÚ P |
764 |
" ÃSR IÚ
WWDG_TypeDef Ú P FLASH_BASE ÏÚ P |
| 765 |
SRAM_BASE Ú P PERIPH_BASE sÚ P
SRAM_BB_BASE #Ú P PERIPH_BB_BASE Ú P FSMC_R_BASE aÚ P APB1PERIPH_BASE gÚ P APB2PERIPH_BASE fÚ P AHBPERIPH_BASE ¢Ú P |
765 |
SRAM_BASE Ú P PERIPH_BASE sÚ P
SRAM_BB_BASE #Ú P PERIPH_BB_BASE Ú P FSMC_R_BASE aÚ P APB1PERIPH_BASE gÚ P APB2PERIPH_BASE fÚ P AHBPERIPH_BASE ¢Ú P |
| 766 |
TIM2_BASE #Ú P |
766 |
TIM2_BASE #Ú P |
| 767 |
TIM3_BASE "Ú P |
767 |
TIM3_BASE "Ú P |
| 768 |
TIM4_BASE !Ú P |
768 |
TIM4_BASE !Ú P |
| 769 |
TIM5_BASE Ú P |
769 |
TIM5_BASE Ú P |
| 770 |
TIM6_BASE Ú P |
770 |
TIM6_BASE Ú P |
| 771 |
TIM7_BASE Ú P LCD_BASE nÚ P RTC_BASE XÚ P |
771 |
TIM7_BASE Ú P LCD_BASE nÚ P RTC_BASE XÚ P |
| 772 |
WWDG_BASE Ú P |
772 |
WWDG_BASE Ú P |
| 773 |
IWDG_BASE Ú P |
773 |
IWDG_BASE Ú P |
| 774 |
SPI2_BASE !Ú P |
774 |
SPI2_BASE !Ú P |
| 775 |
SPI3_BASE Ú P USART2_BASE zÚ P USART3_BASE yÚ P UART4_BASE ÍÚ P UART5_BASE ÌÚ P |
775 |
SPI3_BASE Ú P USART2_BASE zÚ P USART3_BASE yÚ P UART4_BASE ÍÚ P UART5_BASE ÌÚ P |
| 776 |
I2C1_BASE PÚ P |
776 |
I2C1_BASE PÚ P |
| 777 |
I2C2_BASE OÚ P PWR_BASE HÚ P DAC_BASE yÚ P |
777 |
I2C2_BASE OÚ P PWR_BASE HÚ P DAC_BASE yÚ P |
| 778 |
COMP_BASE Ú P RI_BASE ¨Ú P OPAMP_BASE ÀÚ P SYSCFG_BASE lÚ P |
778 |
COMP_BASE Ú P RI_BASE ¨Ú P OPAMP_BASE ÀÚ P SYSCFG_BASE lÚ P |
| 779 |
EXTI_BASE Ú P |
779 |
EXTI_BASE Ú P |
| 780 |
TIM9_BASE Ú P TIM10_BASE òÚ P TIM11_BASE ñÚ P |
780 |
TIM9_BASE Ú P TIM10_BASE òÚ P TIM11_BASE ñÚ P |
| 781 |
ADC1_BASE FÚ P ADC_BASE yÚ P |
781 |
ADC1_BASE FÚ P ADC_BASE yÚ P |
| 782 |
SDIO_BASE Ú P |
782 |
SDIO_BASE Ú P |
| 783 |
SPI1_BASE "Ú P USART1_BASE {Ú P GPIOA_BASE ÍÚ P GPIOB_BASE ÌÚ P GPIOC_BASE ËÚ P GPIOD_BASE ÊÚ P GPIOE_BASE ÉÚ P GPIOH_BASE ÆÚ P GPIOF_BASE ÈÚ P GPIOG_BASE ÇÚ P CRC_BASE iÚ P RCC_BASE iÚ P
FLASH_R_BASE Ú P OB_BASE ²Ú P |
783 |
SPI1_BASE "Ú P USART1_BASE {Ú P GPIOA_BASE ÍÚ P GPIOB_BASE ÌÚ P GPIOC_BASE ËÚ P GPIOD_BASE ÊÚ P GPIOE_BASE ÉÚ P GPIOH_BASE ÆÚ P GPIOF_BASE ÈÚ P GPIOG_BASE ÇÚ P CRC_BASE iÚ P RCC_BASE iÚ P
FLASH_R_BASE Ú P OB_BASE ²Ú P |
| 784 |
DMA1_BASE <Ú P DMA1_Channel1_BASE áÚ P DMA1_Channel2_BASE àÚ P DMA1_Channel3_BASE ßÚ P DMA1_Channel4_BASE ÞÚ P DMA1_Channel5_BASE ÝÚ P DMA1_Channel6_BASE ÜÚ P DMA1_Channel7_BASE ÛÚ P |
784 |
DMA1_BASE <Ú P DMA1_Channel1_BASE áÚ P DMA1_Channel2_BASE àÚ P DMA1_Channel3_BASE ßÚ P DMA1_Channel4_BASE ÞÚ P DMA1_Channel5_BASE ÝÚ P DMA1_Channel6_BASE ÜÚ P DMA1_Channel7_BASE ÛÚ P |
| 785 |
DMA2_BASE ;Ú P DMA2_Channel1_BASE àÚ P DMA2_Channel2_BASE ßÚ P DMA2_Channel3_BASE ÞÚ P DMA2_Channel4_BASE ÝÚ P DMA2_Channel5_BASE ÜÚ P AES_BASE hÚ P FSMC_Bank1_R_BASE IÚ P FSMC_Bank1E_R_BASE Ú P DBGMCU_BASE Ú
P TIM2 §Ú
P TIM3 ¦Ú
P TIM4 ¥Ú
P TIM5 ¤Ú
P TIM6 £Ú
P TIM7 ¢Ú P LCD òÚ P RTC ÜÚ
P WWDG Ú
P IWDG Ú
P SPI2 ¥Ú
P SPI3 ¤Ú P USART2 þÚ P USART3 ýÚ P UART4 QÚ P UART5 PÚ
P I2C1 ÔÚ
P I2C2 ÓÚ P PWR ÌÚ P DAC ýÚ
P COMP Ú P RI ,Ú P OPAMP DÚ P SYSCFG ðÚ
P EXTI Ú
P ADC1 ÊÚ P ADC ýÚ
P SDIO Ú
P TIM9 Ú P TIM10 vÚ P TIM11 uÚ
P SPI1 ¦Ú P USART1 ÿÚ
P DMA1 ÀÚ P DMA1_Channel1 eÚ P DMA1_Channel2 dÚ P DMA1_Channel3 cÚ P DMA1_Channel4 bÚ P DMA1_Channel5 aÚ P DMA1_Channel6 `Ú P DMA1_Channel7 _Ú
P DMA2 ¿Ú P DMA2_Channel1 dÚ P DMA2_Channel2 cÚ P DMA2_Channel3 bÚ P DMA2_Channel4 aÚ P DMA2_Channel5 `Ú P RCC íÚ P CRC íÚ P GPIOA QÚ P GPIOB PÚ P GPIOC OÚ P GPIOD NÚ P GPIOE MÚ P GPIOH JÚ P GPIOF LÚ P GPIOG KÚ P FLASH SÚ P OB 6Ú P AES ìÚ P FSMC_Bank1 Ú P FSMC_Bank1E ;Ú P DBGMCU
Ú P ADC_SR_AWD °Ú P ADC_SR_EOC µÚ P ADC_SR_JEOC iÚ P
ADC_SR_JSTRT ñÚ P ADC_SR_STRT =Ú P ADC_SR_OVR Ú P
ADC_SR_ADONS Ú P ADC_SR_RCNR UÚ P ADC_SR_JCNR ]Ú P ADC_CR1_AWDCH þÚ P ADC_CR1_AWDCH_0 kÚ P ADC_CR1_AWDCH_1 jÚ P ADC_CR1_AWDCH_2 iÚ P ADC_CR1_AWDCH_3 hÚ P ADC_CR1_AWDCH_4 gÚ P ADC_CR1_EOCIE Ú P ADC_CR1_AWDIE ûÚ P ADC_CR1_JEOCIE ´Ú P
ADC_CR1_SCAN BÚ P ADC_CR1_AWDSGL ¡Ú P ADC_CR1_JAUTO âÚ P ADC_CR1_DISCEN Ú P ADC_CR1_JDISCEN aÚ P ADC_CR1_DISCNUM NÚ P ADC_CR1_DISCNUM_0 »Ú P ADC_CR1_DISCNUM_1 ºÚ P ADC_CR1_DISCNUM_2 ¹Ú P ADC_CR1_PDD Ú P ADC_CR1_PDI Ú P ADC_CR1_JAWDEN ªÚ P ADC_CR1_AWDEN öÚ P ADC_CR1_RES Ú P ADC_CR1_RES_0 ìÚ P ADC_CR1_RES_1 ëÚ P ADC_CR1_OVRIE àÚ P
ADC_CR2_ADON DÚ P
ADC_CR2_CONT 2Ú P ADC_CR2_CFG Ú P
ADC_CR2_DELS >Ú P ADC_CR2_DELS_0 «Ú P ADC_CR2_DELS_1 ªÚ P ADC_CR2_DELS_2 ©Ú P ADC_CR2_DMA Ú P ADC_CR2_DDS Ú P
ADC_CR2_EOCS <Ú P ADC_CR2_ALIGN ùÚ P ADC_CR2_JEXTSEL AÚ P ADC_CR2_JEXTSEL_0 ®Ú P ADC_CR2_JEXTSEL_1 Ú P ADC_CR2_JEXTSEL_2 ¬Ú P ADC_CR2_JEXTSEL_3 «Ú P ADC_CR2_JEXTEN Ú P ADC_CR2_JEXTEN_0 Ú P ADC_CR2_JEXTEN_1 Ú P ADC_CR2_JSWSTART ÜÚ P ADC_CR2_EXTSEL Ú P ADC_CR2_EXTSEL_0 úÚ P ADC_CR2_EXTSEL_1 ùÚ P ADC_CR2_EXTSEL_2 øÚ P ADC_CR2_EXTSEL_3 ÷Ú P ADC_CR2_EXTEN àÚ P ADC_CR2_EXTEN_0 MÚ P ADC_CR2_EXTEN_1 LÚ P ADC_CR2_SWSTART (Ú P ADC_SMPR1_SMP20 bÚ P ADC_SMPR1_SMP20_0 ÏÚ P ADC_SMPR1_SMP20_1 ÎÚ P ADC_SMPR1_SMP20_2 ÍÚ P ADC_SMPR1_SMP21 aÚ P ADC_SMPR1_SMP21_0 ÎÚ P ADC_SMPR1_SMP21_1 ÍÚ P ADC_SMPR1_SMP21_2 ÌÚ P ADC_SMPR1_SMP22 `Ú P ADC_SMPR1_SMP22_0 ÍÚ P ADC_SMPR1_SMP22_1 ÌÚ P ADC_SMPR1_SMP22_2 ËÚ P ADC_SMPR1_SMP23 _Ú P ADC_SMPR1_SMP23_0 ÌÚ P ADC_SMPR1_SMP23_1 ËÚ P ADC_SMPR1_SMP23_2 ÊÚ P ADC_SMPR1_SMP24 ^Ú P ADC_SMPR1_SMP24_0 ËÚ P ADC_SMPR1_SMP24_1 ÊÚ P ADC_SMPR1_SMP24_2 ÉÚ P ADC_SMPR1_SMP25 ]Ú P ADC_SMPR1_SMP25_0 ÊÚ P ADC_SMPR1_SMP25_1 ÉÚ P ADC_SMPR1_SMP25_2 ÈÚ P ADC_SMPR1_SMP26 \Ú P ADC_SMPR1_SMP26_0 ÉÚ P ADC_SMPR1_SMP26_1 ÈÚ P ADC_SMPR1_SMP26_2 ÇÚ P ADC_SMPR1_SMP27 [Ú P ADC_SMPR1_SMP27_0 ÈÚ P ADC_SMPR1_SMP27_1 ÇÚ P ADC_SMPR1_SMP27_2 ÆÚ P ADC_SMPR1_SMP28 ZÚ P ADC_SMPR1_SMP28_0 ÇÚ P ADC_SMPR1_SMP28_1 ÆÚ P ADC_SMPR1_SMP28_2 ÅÚ P ADC_SMPR1_SMP29 YÚ P ADC_SMPR1_SMP29_0 ÆÚ P ADC_SMPR1_SMP29_1 ÅÚ P ADC_SMPR1_SMP29_2 ÄÚ P ADC_SMPR2_SMP10 bÚ P ADC_SMPR2_SMP10_0 ÏÚ P ADC_SMPR2_SMP10_1 ÎÚ P ADC_SMPR2_SMP10_2 ÍÚ P ADC_SMPR2_SMP11 aÚ P ADC_SMPR2_SMP11_0 ÎÚ P ADC_SMPR2_SMP11_1 ÍÚ P ADC_SMPR2_SMP11_2 ÌÚ P ADC_SMPR2_SMP12 `Ú P ADC_SMPR2_SMP12_0 ÍÚ P ADC_SMPR2_SMP12_1 ÌÚ P ADC_SMPR2_SMP12_2 ËÚ P ADC_SMPR2_SMP13 _Ú P ADC_SMPR2_SMP13_0 ÌÚ P ADC_SMPR2_SMP13_1 ËÚ P ADC_SMPR2_SMP13_2 ÊÚ P ADC_SMPR2_SMP14 ^Ú P ADC_SMPR2_SMP14_0 ËÚ P ADC_SMPR2_SMP14_1 ÊÚ P ADC_SMPR2_SMP14_2 ÉÚ P ADC_SMPR2_SMP15 ]Ú P ADC_SMPR2_SMP15_0 ÊÚ P ADC_SMPR2_SMP15_1 ÉÚ P ADC_SMPR2_SMP15_2 ÈÚ P ADC_SMPR2_SMP16 \Ú P ADC_SMPR2_SMP16_0 ÉÚ P ADC_SMPR2_SMP16_1 ÈÚ P ADC_SMPR2_SMP16_2 ÇÚ P ADC_SMPR2_SMP17 [Ú P ADC_SMPR2_SMP17_0 ÈÚ P ADC_SMPR2_SMP17_1 ÇÚ P ADC_SMPR2_SMP17_2 ÆÚ P ADC_SMPR2_SMP18 ZÚ P ADC_SMPR2_SMP18_0 ÇÚ P ADC_SMPR2_SMP18_1 ÆÚ P ADC_SMPR2_SMP18_2 ÅÚ P ADC_SMPR2_SMP19 YÚ P ADC_SMPR2_SMP19_0 ÆÚ P ADC_SMPR2_SMP19_1 ÅÚ P ADC_SMPR2_SMP19_2 ÄÚ P ADC_SMPR3_SMP0 Ú P ADC_SMPR3_SMP0_0 Ú P ADC_SMPR3_SMP0_1 Ú P ADC_SMPR3_SMP0_2 ÿÚ P ADC_SMPR3_SMP1 Ú P ADC_SMPR3_SMP1_0 Ú P ADC_SMPR3_SMP1_1 ÿÚ P ADC_SMPR3_SMP1_2 þÚ P ADC_SMPR3_SMP2 Ú P ADC_SMPR3_SMP2_0 ÿÚ P ADC_SMPR3_SMP2_1 þÚ P ADC_SMPR3_SMP2_2 ýÚ P ADC_SMPR3_SMP3 Ú P ADC_SMPR3_SMP3_0 þÚ P ADC_SMPR3_SMP3_1 ýÚ P ADC_SMPR3_SMP3_2 üÚ P ADC_SMPR3_SMP4 Ú P ADC_SMPR3_SMP4_0 ýÚ P ADC_SMPR3_SMP4_1 üÚ P ADC_SMPR3_SMP4_2 ûÚ P ADC_SMPR3_SMP5 Ú P ADC_SMPR3_SMP5_0 üÚ P ADC_SMPR3_SMP5_1 ûÚ P ADC_SMPR3_SMP5_2 úÚ P ADC_SMPR3_SMP6 Ú P ADC_SMPR3_SMP6_0 ûÚ P ADC_SMPR3_SMP6_1 úÚ P ADC_SMPR3_SMP6_2 ùÚ P ADC_SMPR3_SMP7 Ú P ADC_SMPR3_SMP7_0 úÚ P ADC_SMPR3_SMP7_1 ùÚ P ADC_SMPR3_SMP7_2 øÚ P ADC_SMPR3_SMP8 Ú P ADC_SMPR3_SMP8_0 ùÚ P ADC_SMPR3_SMP8_1 øÚ P ADC_SMPR3_SMP8_2 ÷Ú P ADC_SMPR3_SMP9 Ú P ADC_SMPR3_SMP9_0 øÚ P ADC_SMPR3_SMP9_1 ÷Ú P ADC_SMPR3_SMP9_2 öÚ P ADC_JOFR1_JOFFSET1 }Ú P ADC_JOFR2_JOFFSET2 {Ú P ADC_JOFR3_JOFFSET3 yÚ P ADC_JOFR4_JOFFSET4 wÚ P ADC_HTR_HT §Ú P ADC_LTR_LT Ú P ADC_SQR1_L ¾Ú P
ADC_SQR1_L_0 +Ú P
ADC_SQR1_L_1 *Ú P
ADC_SQR1_L_2 )Ú P
ADC_SQR1_L_3 (Ú P ADC_SQR1_SQ28 öÚ P ADC_SQR1_SQ28_0 cÚ P ADC_SQR1_SQ28_1 bÚ P ADC_SQR1_SQ28_2 aÚ P ADC_SQR1_SQ28_3 `Ú P ADC_SQR1_SQ28_4 _Ú P ADC_SQR1_SQ27 ÷Ú P ADC_SQR1_SQ27_0 dÚ P ADC_SQR1_SQ27_1 cÚ P ADC_SQR1_SQ27_2 bÚ P ADC_SQR1_SQ27_3 aÚ P ADC_SQR1_SQ27_4 `Ú P ADC_SQR1_SQ26 øÚ P ADC_SQR1_SQ26_0 eÚ P ADC_SQR1_SQ26_1 dÚ P ADC_SQR1_SQ26_2 cÚ P ADC_SQR1_SQ26_3 bÚ P ADC_SQR1_SQ26_4 aÚ P ADC_SQR1_SQ25 ùÚ P ADC_SQR1_SQ25_0 fÚ P ADC_SQR1_SQ25_1 eÚ P ADC_SQR1_SQ25_2 dÚ P ADC_SQR1_SQ25_3 cÚ P ADC_SQR1_SQ25_4 bÚ P ADC_SQR2_SQ19 õÚ P ADC_SQR2_SQ19_0 bÚ P ADC_SQR2_SQ19_1 aÚ P ADC_SQR2_SQ19_2 `Ú P ADC_SQR2_SQ19_3 _Ú P ADC_SQR2_SQ19_4 ^Ú P ADC_SQR2_SQ20 ýÚ P ADC_SQR2_SQ20_0 jÚ P ADC_SQR2_SQ20_1 iÚ P ADC_SQR2_SQ20_2 hÚ P ADC_SQR2_SQ20_3 gÚ P ADC_SQR2_SQ20_4 fÚ P ADC_SQR2_SQ21 üÚ P ADC_SQR2_SQ21_0 iÚ P ADC_SQR2_SQ21_1 hÚ P ADC_SQR2_SQ21_2 gÚ P ADC_SQR2_SQ21_3 fÚ P ADC_SQR2_SQ21_4 eÚ P ADC_SQR2_SQ22 ûÚ P ADC_SQR2_SQ22_0 hÚ P ADC_SQR2_SQ22_1 gÚ P ADC_SQR2_SQ22_2 fÚ P ADC_SQR2_SQ22_3 eÚ P ADC_SQR2_SQ22_4 dÚ P ADC_SQR2_SQ23 úÚ P ADC_SQR2_SQ23_0 gÚ P ADC_SQR2_SQ23_1 fÚ P ADC_SQR2_SQ23_2 eÚ P ADC_SQR2_SQ23_3 dÚ P ADC_SQR2_SQ23_4 cÚ P ADC_SQR2_SQ24 ùÚ P ADC_SQR2_SQ24_0 fÚ P ADC_SQR2_SQ24_1 eÚ P ADC_SQR2_SQ24_2 dÚ P ADC_SQR2_SQ24_3 cÚ P ADC_SQR2_SQ24_4 bÚ P ADC_SQR3_SQ13 úÚ P ADC_SQR3_SQ13_0 gÚ P ADC_SQR3_SQ13_1 fÚ P ADC_SQR3_SQ13_2 eÚ P ADC_SQR3_SQ13_3 dÚ P ADC_SQR3_SQ13_4 cÚ P ADC_SQR3_SQ14 ùÚ P ADC_SQR3_SQ14_0 fÚ P ADC_SQR3_SQ14_1 eÚ P ADC_SQR3_SQ14_2 dÚ P ADC_SQR3_SQ14_3 cÚ P ADC_SQR3_SQ14_4 bÚ P ADC_SQR3_SQ15 øÚ P ADC_SQR3_SQ15_0 eÚ P ADC_SQR3_SQ15_1 dÚ P ADC_SQR3_SQ15_2 cÚ P ADC_SQR3_SQ15_3 bÚ P ADC_SQR3_SQ15_4 aÚ P ADC_SQR3_SQ16 ÷Ú P ADC_SQR3_SQ16_0 dÚ P ADC_SQR3_SQ16_1 cÚ P ADC_SQR3_SQ16_2 bÚ P ADC_SQR3_SQ16_3 aÚ P ADC_SQR3_SQ16_4 `Ú P ADC_SQR3_SQ17 öÚ P ADC_SQR3_SQ17_0 cÚ P ADC_SQR3_SQ17_1 bÚ P ADC_SQR3_SQ17_2 aÚ P ADC_SQR3_SQ17_3 `Ú P ADC_SQR3_SQ17_4 _Ú P ADC_SQR3_SQ18 õÚ P ADC_SQR3_SQ18_0 bÚ P ADC_SQR3_SQ18_1 aÚ P ADC_SQR3_SQ18_2 `Ú P ADC_SQR3_SQ18_3 _Ú P ADC_SQR3_SQ18_4 ^Ú P
ADC_SQR4_SQ7 (Ú P ADC_SQR4_SQ7_0 Ú P ADC_SQR4_SQ7_1 Ú P ADC_SQR4_SQ7_2 Ú P ADC_SQR4_SQ7_3 Ú P ADC_SQR4_SQ7_4 Ú P
ADC_SQR4_SQ8 'Ú P ADC_SQR4_SQ8_0 Ú P ADC_SQR4_SQ8_1 Ú P ADC_SQR4_SQ8_2 Ú P ADC_SQR4_SQ8_3 Ú P ADC_SQR4_SQ8_4 Ú P
ADC_SQR4_SQ9 &Ú P ADC_SQR4_SQ9_0 Ú P ADC_SQR4_SQ9_1 Ú P ADC_SQR4_SQ9_2 Ú P ADC_SQR4_SQ9_3 Ú P ADC_SQR4_SQ9_4 Ú P ADC_SQR4_SQ10 üÚ P ADC_SQR4_SQ10_0 iÚ P ADC_SQR4_SQ10_1 hÚ P ADC_SQR4_SQ10_2 gÚ P ADC_SQR4_SQ10_3 fÚ P ADC_SQR4_SQ10_4 eÚ P ADC_SQR4_SQ11 ûÚ P ADC_SQR4_SQ11_0 hÚ P ADC_SQR4_SQ11_1 gÚ P ADC_SQR4_SQ11_2 fÚ P ADC_SQR4_SQ11_3 eÚ P ADC_SQR4_SQ11_4 dÚ P ADC_SQR4_SQ12 úÚ P ADC_SQR4_SQ12_0 gÚ P ADC_SQR4_SQ12_1 fÚ P ADC_SQR4_SQ12_2 eÚ P ADC_SQR4_SQ12_3 dÚ P ADC_SQR4_SQ12_4 cÚ P
ADC_SQR5_SQ1 -Ú P ADC_SQR5_SQ1_0 Ú P ADC_SQR5_SQ1_1 Ú P ADC_SQR5_SQ1_2 Ú P ADC_SQR5_SQ1_3 Ú P ADC_SQR5_SQ1_4 Ú P
ADC_SQR5_SQ2 ,Ú P ADC_SQR5_SQ2_0 Ú P ADC_SQR5_SQ2_1 Ú P ADC_SQR5_SQ2_2 Ú P ADC_SQR5_SQ2_3 Ú P ADC_SQR5_SQ2_4 Ú P
ADC_SQR5_SQ3 +Ú P ADC_SQR5_SQ3_0 Ú P ADC_SQR5_SQ3_1 Ú P ADC_SQR5_SQ3_2 Ú P ADC_SQR5_SQ3_3 Ú P ADC_SQR5_SQ3_4 Ú P
ADC_SQR5_SQ4 *Ú P ADC_SQR5_SQ4_0 Ú P ADC_SQR5_SQ4_1 Ú P ADC_SQR5_SQ4_2 Ú P ADC_SQR5_SQ4_3 Ú P ADC_SQR5_SQ4_4 Ú P
ADC_SQR5_SQ5 )Ú P ADC_SQR5_SQ5_0 Ú P ADC_SQR5_SQ5_1 Ú P ADC_SQR5_SQ5_2 Ú P ADC_SQR5_SQ5_3 Ú P ADC_SQR5_SQ5_4 Ú P
ADC_SQR5_SQ6 (Ú P ADC_SQR5_SQ6_0 Ú P ADC_SQR5_SQ6_1 Ú P ADC_SQR5_SQ6_2 Ú P ADC_SQR5_SQ6_3 Ú P ADC_SQR5_SQ6_4 Ú P ADC_JSQR_JSQ1 ÌÚ P ADC_JSQR_JSQ1_0 9Ú P ADC_JSQR_JSQ1_1 8Ú P ADC_JSQR_JSQ1_2 7Ú P ADC_JSQR_JSQ1_3 6Ú P ADC_JSQR_JSQ1_4 5Ú P ADC_JSQR_JSQ2 ËÚ P ADC_JSQR_JSQ2_0 8Ú P ADC_JSQR_JSQ2_1 7Ú P ADC_JSQR_JSQ2_2 6Ú P ADC_JSQR_JSQ2_3 5Ú P ADC_JSQR_JSQ2_4 4Ú P ADC_JSQR_JSQ3 ÊÚ P ADC_JSQR_JSQ3_0 7Ú P ADC_JSQR_JSQ3_1 6Ú P ADC_JSQR_JSQ3_2 5Ú P ADC_JSQR_JSQ3_3 4Ú P ADC_JSQR_JSQ3_4 3Ú P ADC_JSQR_JSQ4 ÉÚ P ADC_JSQR_JSQ4_0 6Ú P ADC_JSQR_JSQ4_1 5Ú P ADC_JSQR_JSQ4_2 4Ú P ADC_JSQR_JSQ4_3 3Ú P ADC_JSQR_JSQ4_4 2Ú P ADC_JSQR_JL YÚ P ADC_JSQR_JL_0 ÆÚ P ADC_JSQR_JL_1 ÅÚ P ADC_JDR1_JDATA ´Ú P ADC_JDR2_JDATA ³Ú P ADC_JDR3_JDATA ²Ú P ADC_JDR4_JDATA ±Ú P ADC_DR_DATA Ú P ADC_SMPR3_SMP30 _Ú P ADC_SMPR3_SMP30_0 ÌÚ P ADC_SMPR3_SMP30_1 ËÚ P ADC_SMPR3_SMP30_2 ÊÚ P ADC_SMPR3_SMP31 ^Ú P ADC_SMPR3_SMP31_0 ËÚ P ADC_SMPR3_SMP31_1 ÊÚ P ADC_SMPR3_SMP31_2 ÉÚ P
ADC_CSR_AWD1 8Ú P
ADC_CSR_EOC1 =Ú P ADC_CSR_JEOC1 ñÚ P ADC_CSR_JSTRT1 yÚ P ADC_CSR_STRT1 ÅÚ P
ADC_CSR_OVR1 Ú P ADC_CSR_ADONS1 Ú P ADC_CCR_ADCPRE ¢Ú P ADC_CCR_ADCPRE_0 Ú P ADC_CCR_ADCPRE_1 Ú P ADC_CCR_TSVREFE 0Ú P |
785 |
DMA2_BASE ;Ú P DMA2_Channel1_BASE àÚ P DMA2_Channel2_BASE ßÚ P DMA2_Channel3_BASE ÞÚ P DMA2_Channel4_BASE ÝÚ P DMA2_Channel5_BASE ÜÚ P AES_BASE hÚ P FSMC_Bank1_R_BASE IÚ P FSMC_Bank1E_R_BASE Ú P DBGMCU_BASE Ú
P TIM2 §Ú
P TIM3 ¦Ú
P TIM4 ¥Ú
P TIM5 ¤Ú
P TIM6 £Ú
P TIM7 ¢Ú P LCD òÚ P RTC ÜÚ
P WWDG Ú
P IWDG Ú
P SPI2 ¥Ú
P SPI3 ¤Ú P USART2 þÚ P USART3 ýÚ P UART4 QÚ P UART5 PÚ
P I2C1 ÔÚ
P I2C2 ÓÚ P PWR ÌÚ P DAC ýÚ
P COMP Ú P RI ,Ú P OPAMP DÚ P SYSCFG ðÚ
P EXTI Ú
P ADC1 ÊÚ P ADC ýÚ
P SDIO Ú
P TIM9 Ú P TIM10 vÚ P TIM11 uÚ
P SPI1 ¦Ú P USART1 ÿÚ
P DMA1 ÀÚ P DMA1_Channel1 eÚ P DMA1_Channel2 dÚ P DMA1_Channel3 cÚ P DMA1_Channel4 bÚ P DMA1_Channel5 aÚ P DMA1_Channel6 `Ú P DMA1_Channel7 _Ú
P DMA2 ¿Ú P DMA2_Channel1 dÚ P DMA2_Channel2 cÚ P DMA2_Channel3 bÚ P DMA2_Channel4 aÚ P DMA2_Channel5 `Ú P RCC íÚ P CRC íÚ P GPIOA QÚ P GPIOB PÚ P GPIOC OÚ P GPIOD NÚ P GPIOE MÚ P GPIOH JÚ P GPIOF LÚ P GPIOG KÚ P FLASH SÚ P OB 6Ú P AES ìÚ P FSMC_Bank1 Ú P FSMC_Bank1E ;Ú P DBGMCU
Ú P ADC_SR_AWD °Ú P ADC_SR_EOC µÚ P ADC_SR_JEOC iÚ P
ADC_SR_JSTRT ñÚ P ADC_SR_STRT =Ú P ADC_SR_OVR Ú P
ADC_SR_ADONS Ú P ADC_SR_RCNR UÚ P ADC_SR_JCNR ]Ú P ADC_CR1_AWDCH þÚ P ADC_CR1_AWDCH_0 kÚ P ADC_CR1_AWDCH_1 jÚ P ADC_CR1_AWDCH_2 iÚ P ADC_CR1_AWDCH_3 hÚ P ADC_CR1_AWDCH_4 gÚ P ADC_CR1_EOCIE Ú P ADC_CR1_AWDIE ûÚ P ADC_CR1_JEOCIE ´Ú P
ADC_CR1_SCAN BÚ P ADC_CR1_AWDSGL ¡Ú P ADC_CR1_JAUTO âÚ P ADC_CR1_DISCEN Ú P ADC_CR1_JDISCEN aÚ P ADC_CR1_DISCNUM NÚ P ADC_CR1_DISCNUM_0 »Ú P ADC_CR1_DISCNUM_1 ºÚ P ADC_CR1_DISCNUM_2 ¹Ú P ADC_CR1_PDD Ú P ADC_CR1_PDI Ú P ADC_CR1_JAWDEN ªÚ P ADC_CR1_AWDEN öÚ P ADC_CR1_RES Ú P ADC_CR1_RES_0 ìÚ P ADC_CR1_RES_1 ëÚ P ADC_CR1_OVRIE àÚ P
ADC_CR2_ADON DÚ P
ADC_CR2_CONT 2Ú P ADC_CR2_CFG Ú P
ADC_CR2_DELS >Ú P ADC_CR2_DELS_0 «Ú P ADC_CR2_DELS_1 ªÚ P ADC_CR2_DELS_2 ©Ú P ADC_CR2_DMA Ú P ADC_CR2_DDS Ú P
ADC_CR2_EOCS <Ú P ADC_CR2_ALIGN ùÚ P ADC_CR2_JEXTSEL AÚ P ADC_CR2_JEXTSEL_0 ®Ú P ADC_CR2_JEXTSEL_1 Ú P ADC_CR2_JEXTSEL_2 ¬Ú P ADC_CR2_JEXTSEL_3 «Ú P ADC_CR2_JEXTEN Ú P ADC_CR2_JEXTEN_0 Ú P ADC_CR2_JEXTEN_1 Ú P ADC_CR2_JSWSTART ÜÚ P ADC_CR2_EXTSEL Ú P ADC_CR2_EXTSEL_0 úÚ P ADC_CR2_EXTSEL_1 ùÚ P ADC_CR2_EXTSEL_2 øÚ P ADC_CR2_EXTSEL_3 ÷Ú P ADC_CR2_EXTEN àÚ P ADC_CR2_EXTEN_0 MÚ P ADC_CR2_EXTEN_1 LÚ P ADC_CR2_SWSTART (Ú P ADC_SMPR1_SMP20 bÚ P ADC_SMPR1_SMP20_0 ÏÚ P ADC_SMPR1_SMP20_1 ÎÚ P ADC_SMPR1_SMP20_2 ÍÚ P ADC_SMPR1_SMP21 aÚ P ADC_SMPR1_SMP21_0 ÎÚ P ADC_SMPR1_SMP21_1 ÍÚ P ADC_SMPR1_SMP21_2 ÌÚ P ADC_SMPR1_SMP22 `Ú P ADC_SMPR1_SMP22_0 ÍÚ P ADC_SMPR1_SMP22_1 ÌÚ P ADC_SMPR1_SMP22_2 ËÚ P ADC_SMPR1_SMP23 _Ú P ADC_SMPR1_SMP23_0 ÌÚ P ADC_SMPR1_SMP23_1 ËÚ P ADC_SMPR1_SMP23_2 ÊÚ P ADC_SMPR1_SMP24 ^Ú P ADC_SMPR1_SMP24_0 ËÚ P ADC_SMPR1_SMP24_1 ÊÚ P ADC_SMPR1_SMP24_2 ÉÚ P ADC_SMPR1_SMP25 ]Ú P ADC_SMPR1_SMP25_0 ÊÚ P ADC_SMPR1_SMP25_1 ÉÚ P ADC_SMPR1_SMP25_2 ÈÚ P ADC_SMPR1_SMP26 \Ú P ADC_SMPR1_SMP26_0 ÉÚ P ADC_SMPR1_SMP26_1 ÈÚ P ADC_SMPR1_SMP26_2 ÇÚ P ADC_SMPR1_SMP27 [Ú P ADC_SMPR1_SMP27_0 ÈÚ P ADC_SMPR1_SMP27_1 ÇÚ P ADC_SMPR1_SMP27_2 ÆÚ P ADC_SMPR1_SMP28 ZÚ P ADC_SMPR1_SMP28_0 ÇÚ P ADC_SMPR1_SMP28_1 ÆÚ P ADC_SMPR1_SMP28_2 ÅÚ P ADC_SMPR1_SMP29 YÚ P ADC_SMPR1_SMP29_0 ÆÚ P ADC_SMPR1_SMP29_1 ÅÚ P ADC_SMPR1_SMP29_2 ÄÚ P ADC_SMPR2_SMP10 bÚ P ADC_SMPR2_SMP10_0 ÏÚ P ADC_SMPR2_SMP10_1 ÎÚ P ADC_SMPR2_SMP10_2 ÍÚ P ADC_SMPR2_SMP11 aÚ P ADC_SMPR2_SMP11_0 ÎÚ P ADC_SMPR2_SMP11_1 ÍÚ P ADC_SMPR2_SMP11_2 ÌÚ P ADC_SMPR2_SMP12 `Ú P ADC_SMPR2_SMP12_0 ÍÚ P ADC_SMPR2_SMP12_1 ÌÚ P ADC_SMPR2_SMP12_2 ËÚ P ADC_SMPR2_SMP13 _Ú P ADC_SMPR2_SMP13_0 ÌÚ P ADC_SMPR2_SMP13_1 ËÚ P ADC_SMPR2_SMP13_2 ÊÚ P ADC_SMPR2_SMP14 ^Ú P ADC_SMPR2_SMP14_0 ËÚ P ADC_SMPR2_SMP14_1 ÊÚ P ADC_SMPR2_SMP14_2 ÉÚ P ADC_SMPR2_SMP15 ]Ú P ADC_SMPR2_SMP15_0 ÊÚ P ADC_SMPR2_SMP15_1 ÉÚ P ADC_SMPR2_SMP15_2 ÈÚ P ADC_SMPR2_SMP16 \Ú P ADC_SMPR2_SMP16_0 ÉÚ P ADC_SMPR2_SMP16_1 ÈÚ P ADC_SMPR2_SMP16_2 ÇÚ P ADC_SMPR2_SMP17 [Ú P ADC_SMPR2_SMP17_0 ÈÚ P ADC_SMPR2_SMP17_1 ÇÚ P ADC_SMPR2_SMP17_2 ÆÚ P ADC_SMPR2_SMP18 ZÚ P ADC_SMPR2_SMP18_0 ÇÚ P ADC_SMPR2_SMP18_1 ÆÚ P ADC_SMPR2_SMP18_2 ÅÚ P ADC_SMPR2_SMP19 YÚ P ADC_SMPR2_SMP19_0 ÆÚ P ADC_SMPR2_SMP19_1 ÅÚ P ADC_SMPR2_SMP19_2 ÄÚ P ADC_SMPR3_SMP0 Ú P ADC_SMPR3_SMP0_0 Ú P ADC_SMPR3_SMP0_1 Ú P ADC_SMPR3_SMP0_2 ÿÚ P ADC_SMPR3_SMP1 Ú P ADC_SMPR3_SMP1_0 Ú P ADC_SMPR3_SMP1_1 ÿÚ P ADC_SMPR3_SMP1_2 þÚ P ADC_SMPR3_SMP2 Ú P ADC_SMPR3_SMP2_0 ÿÚ P ADC_SMPR3_SMP2_1 þÚ P ADC_SMPR3_SMP2_2 ýÚ P ADC_SMPR3_SMP3 Ú P ADC_SMPR3_SMP3_0 þÚ P ADC_SMPR3_SMP3_1 ýÚ P ADC_SMPR3_SMP3_2 üÚ P ADC_SMPR3_SMP4 Ú P ADC_SMPR3_SMP4_0 ýÚ P ADC_SMPR3_SMP4_1 üÚ P ADC_SMPR3_SMP4_2 ûÚ P ADC_SMPR3_SMP5 Ú P ADC_SMPR3_SMP5_0 üÚ P ADC_SMPR3_SMP5_1 ûÚ P ADC_SMPR3_SMP5_2 úÚ P ADC_SMPR3_SMP6 Ú P ADC_SMPR3_SMP6_0 ûÚ P ADC_SMPR3_SMP6_1 úÚ P ADC_SMPR3_SMP6_2 ùÚ P ADC_SMPR3_SMP7 Ú P ADC_SMPR3_SMP7_0 úÚ P ADC_SMPR3_SMP7_1 ùÚ P ADC_SMPR3_SMP7_2 øÚ P ADC_SMPR3_SMP8 Ú P ADC_SMPR3_SMP8_0 ùÚ P ADC_SMPR3_SMP8_1 øÚ P ADC_SMPR3_SMP8_2 ÷Ú P ADC_SMPR3_SMP9 Ú P ADC_SMPR3_SMP9_0 øÚ P ADC_SMPR3_SMP9_1 ÷Ú P ADC_SMPR3_SMP9_2 öÚ P ADC_JOFR1_JOFFSET1 }Ú P ADC_JOFR2_JOFFSET2 {Ú P ADC_JOFR3_JOFFSET3 yÚ P ADC_JOFR4_JOFFSET4 wÚ P ADC_HTR_HT §Ú P ADC_LTR_LT Ú P ADC_SQR1_L ¾Ú P
ADC_SQR1_L_0 +Ú P
ADC_SQR1_L_1 *Ú P
ADC_SQR1_L_2 )Ú P
ADC_SQR1_L_3 (Ú P ADC_SQR1_SQ28 öÚ P ADC_SQR1_SQ28_0 cÚ P ADC_SQR1_SQ28_1 bÚ P ADC_SQR1_SQ28_2 aÚ P ADC_SQR1_SQ28_3 `Ú P ADC_SQR1_SQ28_4 _Ú P ADC_SQR1_SQ27 ÷Ú P ADC_SQR1_SQ27_0 dÚ P ADC_SQR1_SQ27_1 cÚ P ADC_SQR1_SQ27_2 bÚ P ADC_SQR1_SQ27_3 aÚ P ADC_SQR1_SQ27_4 `Ú P ADC_SQR1_SQ26 øÚ P ADC_SQR1_SQ26_0 eÚ P ADC_SQR1_SQ26_1 dÚ P ADC_SQR1_SQ26_2 cÚ P ADC_SQR1_SQ26_3 bÚ P ADC_SQR1_SQ26_4 aÚ P ADC_SQR1_SQ25 ùÚ P ADC_SQR1_SQ25_0 fÚ P ADC_SQR1_SQ25_1 eÚ P ADC_SQR1_SQ25_2 dÚ P ADC_SQR1_SQ25_3 cÚ P ADC_SQR1_SQ25_4 bÚ P ADC_SQR2_SQ19 õÚ P ADC_SQR2_SQ19_0 bÚ P ADC_SQR2_SQ19_1 aÚ P ADC_SQR2_SQ19_2 `Ú P ADC_SQR2_SQ19_3 _Ú P ADC_SQR2_SQ19_4 ^Ú P ADC_SQR2_SQ20 ýÚ P ADC_SQR2_SQ20_0 jÚ P ADC_SQR2_SQ20_1 iÚ P ADC_SQR2_SQ20_2 hÚ P ADC_SQR2_SQ20_3 gÚ P ADC_SQR2_SQ20_4 fÚ P ADC_SQR2_SQ21 üÚ P ADC_SQR2_SQ21_0 iÚ P ADC_SQR2_SQ21_1 hÚ P ADC_SQR2_SQ21_2 gÚ P ADC_SQR2_SQ21_3 fÚ P ADC_SQR2_SQ21_4 eÚ P ADC_SQR2_SQ22 ûÚ P ADC_SQR2_SQ22_0 hÚ P ADC_SQR2_SQ22_1 gÚ P ADC_SQR2_SQ22_2 fÚ P ADC_SQR2_SQ22_3 eÚ P ADC_SQR2_SQ22_4 dÚ P ADC_SQR2_SQ23 úÚ P ADC_SQR2_SQ23_0 gÚ P ADC_SQR2_SQ23_1 fÚ P ADC_SQR2_SQ23_2 eÚ P ADC_SQR2_SQ23_3 dÚ P ADC_SQR2_SQ23_4 cÚ P ADC_SQR2_SQ24 ùÚ P ADC_SQR2_SQ24_0 fÚ P ADC_SQR2_SQ24_1 eÚ P ADC_SQR2_SQ24_2 dÚ P ADC_SQR2_SQ24_3 cÚ P ADC_SQR2_SQ24_4 bÚ P ADC_SQR3_SQ13 úÚ P ADC_SQR3_SQ13_0 gÚ P ADC_SQR3_SQ13_1 fÚ P ADC_SQR3_SQ13_2 eÚ P ADC_SQR3_SQ13_3 dÚ P ADC_SQR3_SQ13_4 cÚ P ADC_SQR3_SQ14 ùÚ P ADC_SQR3_SQ14_0 fÚ P ADC_SQR3_SQ14_1 eÚ P ADC_SQR3_SQ14_2 dÚ P ADC_SQR3_SQ14_3 cÚ P ADC_SQR3_SQ14_4 bÚ P ADC_SQR3_SQ15 øÚ P ADC_SQR3_SQ15_0 eÚ P ADC_SQR3_SQ15_1 dÚ P ADC_SQR3_SQ15_2 cÚ P ADC_SQR3_SQ15_3 bÚ P ADC_SQR3_SQ15_4 aÚ P ADC_SQR3_SQ16 ÷Ú P ADC_SQR3_SQ16_0 dÚ P ADC_SQR3_SQ16_1 cÚ P ADC_SQR3_SQ16_2 bÚ P ADC_SQR3_SQ16_3 aÚ P ADC_SQR3_SQ16_4 `Ú P ADC_SQR3_SQ17 öÚ P ADC_SQR3_SQ17_0 cÚ P ADC_SQR3_SQ17_1 bÚ P ADC_SQR3_SQ17_2 aÚ P ADC_SQR3_SQ17_3 `Ú P ADC_SQR3_SQ17_4 _Ú P ADC_SQR3_SQ18 õÚ P ADC_SQR3_SQ18_0 bÚ P ADC_SQR3_SQ18_1 aÚ P ADC_SQR3_SQ18_2 `Ú P ADC_SQR3_SQ18_3 _Ú P ADC_SQR3_SQ18_4 ^Ú P
ADC_SQR4_SQ7 (Ú P ADC_SQR4_SQ7_0 Ú P ADC_SQR4_SQ7_1 Ú P ADC_SQR4_SQ7_2 Ú P ADC_SQR4_SQ7_3 Ú P ADC_SQR4_SQ7_4 Ú P
ADC_SQR4_SQ8 'Ú P ADC_SQR4_SQ8_0 Ú P ADC_SQR4_SQ8_1 Ú P ADC_SQR4_SQ8_2 Ú P ADC_SQR4_SQ8_3 Ú P ADC_SQR4_SQ8_4 Ú P
ADC_SQR4_SQ9 &Ú P ADC_SQR4_SQ9_0 Ú P ADC_SQR4_SQ9_1 Ú P ADC_SQR4_SQ9_2 Ú P ADC_SQR4_SQ9_3 Ú P ADC_SQR4_SQ9_4 Ú P ADC_SQR4_SQ10 üÚ P ADC_SQR4_SQ10_0 iÚ P ADC_SQR4_SQ10_1 hÚ P ADC_SQR4_SQ10_2 gÚ P ADC_SQR4_SQ10_3 fÚ P ADC_SQR4_SQ10_4 eÚ P ADC_SQR4_SQ11 ûÚ P ADC_SQR4_SQ11_0 hÚ P ADC_SQR4_SQ11_1 gÚ P ADC_SQR4_SQ11_2 fÚ P ADC_SQR4_SQ11_3 eÚ P ADC_SQR4_SQ11_4 dÚ P ADC_SQR4_SQ12 úÚ P ADC_SQR4_SQ12_0 gÚ P ADC_SQR4_SQ12_1 fÚ P ADC_SQR4_SQ12_2 eÚ P ADC_SQR4_SQ12_3 dÚ P ADC_SQR4_SQ12_4 cÚ P
ADC_SQR5_SQ1 -Ú P ADC_SQR5_SQ1_0 Ú P ADC_SQR5_SQ1_1 Ú P ADC_SQR5_SQ1_2 Ú P ADC_SQR5_SQ1_3 Ú P ADC_SQR5_SQ1_4 Ú P
ADC_SQR5_SQ2 ,Ú P ADC_SQR5_SQ2_0 Ú P ADC_SQR5_SQ2_1 Ú P ADC_SQR5_SQ2_2 Ú P ADC_SQR5_SQ2_3 Ú P ADC_SQR5_SQ2_4 Ú P
ADC_SQR5_SQ3 +Ú P ADC_SQR5_SQ3_0 Ú P ADC_SQR5_SQ3_1 Ú P ADC_SQR5_SQ3_2 Ú P ADC_SQR5_SQ3_3 Ú P ADC_SQR5_SQ3_4 Ú P
ADC_SQR5_SQ4 *Ú P ADC_SQR5_SQ4_0 Ú P ADC_SQR5_SQ4_1 Ú P ADC_SQR5_SQ4_2 Ú P ADC_SQR5_SQ4_3 Ú P ADC_SQR5_SQ4_4 Ú P
ADC_SQR5_SQ5 )Ú P ADC_SQR5_SQ5_0 Ú P ADC_SQR5_SQ5_1 Ú P ADC_SQR5_SQ5_2 Ú P ADC_SQR5_SQ5_3 Ú P ADC_SQR5_SQ5_4 Ú P
ADC_SQR5_SQ6 (Ú P ADC_SQR5_SQ6_0 Ú P ADC_SQR5_SQ6_1 Ú P ADC_SQR5_SQ6_2 Ú P ADC_SQR5_SQ6_3 Ú P ADC_SQR5_SQ6_4 Ú P ADC_JSQR_JSQ1 ÌÚ P ADC_JSQR_JSQ1_0 9Ú P ADC_JSQR_JSQ1_1 8Ú P ADC_JSQR_JSQ1_2 7Ú P ADC_JSQR_JSQ1_3 6Ú P ADC_JSQR_JSQ1_4 5Ú P ADC_JSQR_JSQ2 ËÚ P ADC_JSQR_JSQ2_0 8Ú P ADC_JSQR_JSQ2_1 7Ú P ADC_JSQR_JSQ2_2 6Ú P ADC_JSQR_JSQ2_3 5Ú P ADC_JSQR_JSQ2_4 4Ú P ADC_JSQR_JSQ3 ÊÚ P ADC_JSQR_JSQ3_0 7Ú P ADC_JSQR_JSQ3_1 6Ú P ADC_JSQR_JSQ3_2 5Ú P ADC_JSQR_JSQ3_3 4Ú P ADC_JSQR_JSQ3_4 3Ú P ADC_JSQR_JSQ4 ÉÚ P ADC_JSQR_JSQ4_0 6Ú P ADC_JSQR_JSQ4_1 5Ú P ADC_JSQR_JSQ4_2 4Ú P ADC_JSQR_JSQ4_3 3Ú P ADC_JSQR_JSQ4_4 2Ú P ADC_JSQR_JL YÚ P ADC_JSQR_JL_0 ÆÚ P ADC_JSQR_JL_1 ÅÚ P ADC_JDR1_JDATA ´Ú P ADC_JDR2_JDATA ³Ú P ADC_JDR3_JDATA ²Ú P ADC_JDR4_JDATA ±Ú P ADC_DR_DATA Ú P ADC_SMPR3_SMP30 _Ú P ADC_SMPR3_SMP30_0 ÌÚ P ADC_SMPR3_SMP30_1 ËÚ P ADC_SMPR3_SMP30_2 ÊÚ P ADC_SMPR3_SMP31 ^Ú P ADC_SMPR3_SMP31_0 ËÚ P ADC_SMPR3_SMP31_1 ÊÚ P ADC_SMPR3_SMP31_2 ÉÚ P
ADC_CSR_AWD1 8Ú P
ADC_CSR_EOC1 =Ú P ADC_CSR_JEOC1 ñÚ P ADC_CSR_JSTRT1 yÚ P ADC_CSR_STRT1 ÅÚ P
ADC_CSR_OVR1 Ú P ADC_CSR_ADONS1 Ú P ADC_CCR_ADCPRE ¢Ú P ADC_CCR_ADCPRE_0 Ú P ADC_CCR_ADCPRE_1 Ú P ADC_CCR_TSVREFE 0Ú P |
| 786 |
AES_CR_EN úÚ P AES_CR_DATATYPE %Ú P AES_CR_DATATYPE_0 Ú P AES_CR_DATATYPE_1 Ú P AES_CR_MODE dÚ P AES_CR_MODE_0 ÑÚ P AES_CR_MODE_1 ÐÚ P
AES_CR_CHMOD Ú P AES_CR_CHMOD_0 Ú P AES_CR_CHMOD_1 Ú P AES_CR_CCFC zÚ P AES_CR_ERRC ]Ú P AES_CR_CCIE uÚ P
AES_CR_ERRIE Ú P AES_CR_DMAINEN Ú P AES_CR_DMAOUTEN $Ú P AES_SR_CCF ¯Ú P
AES_SR_RDERR øÚ P
AES_SR_WRERR åÚ P AES_DINR VÚ P |
786 |
AES_CR_EN úÚ P AES_CR_DATATYPE %Ú P AES_CR_DATATYPE_0 Ú P AES_CR_DATATYPE_1 Ú P AES_CR_MODE dÚ P AES_CR_MODE_0 ÑÚ P AES_CR_MODE_1 ÐÚ P
AES_CR_CHMOD Ú P AES_CR_CHMOD_0 Ú P AES_CR_CHMOD_1 Ú P AES_CR_CCFC zÚ P AES_CR_ERRC ]Ú P AES_CR_CCIE uÚ P
AES_CR_ERRIE Ú P AES_CR_DMAINEN Ú P AES_CR_DMAOUTEN $Ú P AES_SR_CCF ¯Ú P
AES_SR_RDERR øÚ P
AES_SR_WRERR åÚ P AES_DINR VÚ P |
| 787 |
AES_DOUTR óÚ P |
787 |
AES_DOUTR óÚ P |
| 788 |
AES_KEYR0 Ú P |
788 |
AES_KEYR0 Ú P |
| 789 |
AES_KEYR1 Ú P |
789 |
AES_KEYR1 Ú P |
| 790 |
AES_KEYR2 Ú P |
790 |
AES_KEYR2 Ú P |
| 791 |
AES_KEYR3 Ú P AES_IVR0 bÚ P AES_IVR1 aÚ P AES_IVR2 `Ú P AES_IVR3 _Ú P COMP_CSR_10KPU Ú P COMP_CSR_400KPU TÚ P COMP_CSR_10KPD Ú P COMP_CSR_400KPD eÚ P COMP_CSR_CMP1EN 4Ú P
COMP_CSR_SW1 Ú P COMP_CSR_CMP1OUT ÍÚ P COMP_CSR_SPEED iÚ P COMP_CSR_CMP2OUT ÌÚ P COMP_CSR_VREFOUTEN Ú P COMP_CSR_WNDWE UÚ P COMP_CSR_INSEL _Ú P COMP_CSR_INSEL_0 ÌÚ P COMP_CSR_INSEL_1 ËÚ P COMP_CSR_INSEL_2 ÊÚ P COMP_CSR_OUTSEL üÚ P COMP_CSR_OUTSEL_0 iÚ P COMP_CSR_OUTSEL_1 hÚ P COMP_CSR_OUTSEL_2 gÚ P COMP_CSR_FCH3 ØÚ P COMP_CSR_FCH8 ÓÚ P COMP_CSR_RCH13 Ú P COMP_CSR_CAIE ÊÚ P COMP_CSR_CAIF ÉÚ P COMP_CSR_TSUSP ;Ú P OPAMP_CSR_OPA1PD ãÚ P OPAMP_CSR_S3SEL1 íÚ P OPAMP_CSR_S4SEL1 ìÚ P OPAMP_CSR_S5SEL1 ëÚ P OPAMP_CSR_S6SEL1 êÚ P OPAMP_CSR_OPA1CAL_L öÚ P OPAMP_CSR_OPA1CAL_H úÚ P OPAMP_CSR_OPA1LPM Ú P OPAMP_CSR_OPA2PD âÚ P OPAMP_CSR_S3SEL2 ìÚ P OPAMP_CSR_S4SEL2 ëÚ P OPAMP_CSR_S5SEL2 êÚ P OPAMP_CSR_S6SEL2 éÚ P OPAMP_CSR_OPA2CAL_L õÚ P OPAMP_CSR_OPA2CAL_H ùÚ P OPAMP_CSR_OPA2LPM Ú P OPAMP_CSR_OPA3PD áÚ P OPAMP_CSR_S3SEL3 ëÚ P OPAMP_CSR_S4SEL3 êÚ P OPAMP_CSR_S5SEL3 éÚ P OPAMP_CSR_S6SEL3 èÚ P OPAMP_CSR_OPA3CAL_L ôÚ P OPAMP_CSR_OPA3CAL_H øÚ P OPAMP_CSR_OPA3LPM Ú P OPAMP_CSR_ANAWSEL1 HÚ P OPAMP_CSR_ANAWSEL2 GÚ P OPAMP_CSR_ANAWSEL3 FÚ P OPAMP_CSR_S7SEL2 èÚ P OPAMP_CSR_AOP_RANGE ÖÚ P OPAMP_CSR_OPA1CALOUT §Ú P OPAMP_CSR_OPA2CALOUT ¦Ú P OPAMP_CSR_OPA3CALOUT ¥Ú& P OPAMP_OTR_AO1_OPT_OFFSET_TRIM Ú& P OPAMP_OTR_AO2_OPT_OFFSET_TRIM Ú& P OPAMP_OTR_AO3_OPT_OFFSET_TRIM Ú P OPAMP_OTR_OT_USER 8Ú, P $OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP Ú, P $OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP Ú, P $OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP Ú P |
791 |
AES_KEYR3 Ú P AES_IVR0 bÚ P AES_IVR1 aÚ P AES_IVR2 `Ú P AES_IVR3 _Ú P COMP_CSR_10KPU Ú P COMP_CSR_400KPU TÚ P COMP_CSR_10KPD Ú P COMP_CSR_400KPD eÚ P COMP_CSR_CMP1EN 4Ú P
COMP_CSR_SW1 Ú P COMP_CSR_CMP1OUT ÍÚ P COMP_CSR_SPEED iÚ P COMP_CSR_CMP2OUT ÌÚ P COMP_CSR_VREFOUTEN Ú P COMP_CSR_WNDWE UÚ P COMP_CSR_INSEL _Ú P COMP_CSR_INSEL_0 ÌÚ P COMP_CSR_INSEL_1 ËÚ P COMP_CSR_INSEL_2 ÊÚ P COMP_CSR_OUTSEL üÚ P COMP_CSR_OUTSEL_0 iÚ P COMP_CSR_OUTSEL_1 hÚ P COMP_CSR_OUTSEL_2 gÚ P COMP_CSR_FCH3 ØÚ P COMP_CSR_FCH8 ÓÚ P COMP_CSR_RCH13 Ú P COMP_CSR_CAIE ÊÚ P COMP_CSR_CAIF ÉÚ P COMP_CSR_TSUSP ;Ú P OPAMP_CSR_OPA1PD ãÚ P OPAMP_CSR_S3SEL1 íÚ P OPAMP_CSR_S4SEL1 ìÚ P OPAMP_CSR_S5SEL1 ëÚ P OPAMP_CSR_S6SEL1 êÚ P OPAMP_CSR_OPA1CAL_L öÚ P OPAMP_CSR_OPA1CAL_H úÚ P OPAMP_CSR_OPA1LPM Ú P OPAMP_CSR_OPA2PD âÚ P OPAMP_CSR_S3SEL2 ìÚ P OPAMP_CSR_S4SEL2 ëÚ P OPAMP_CSR_S5SEL2 êÚ P OPAMP_CSR_S6SEL2 éÚ P OPAMP_CSR_OPA2CAL_L õÚ P OPAMP_CSR_OPA2CAL_H ùÚ P OPAMP_CSR_OPA2LPM Ú P OPAMP_CSR_OPA3PD áÚ P OPAMP_CSR_S3SEL3 ëÚ P OPAMP_CSR_S4SEL3 êÚ P OPAMP_CSR_S5SEL3 éÚ P OPAMP_CSR_S6SEL3 èÚ P OPAMP_CSR_OPA3CAL_L ôÚ P OPAMP_CSR_OPA3CAL_H øÚ P OPAMP_CSR_OPA3LPM Ú P OPAMP_CSR_ANAWSEL1 HÚ P OPAMP_CSR_ANAWSEL2 GÚ P OPAMP_CSR_ANAWSEL3 FÚ P OPAMP_CSR_S7SEL2 èÚ P OPAMP_CSR_AOP_RANGE ÖÚ P OPAMP_CSR_OPA1CALOUT §Ú P OPAMP_CSR_OPA2CALOUT ¦Ú P OPAMP_CSR_OPA3CALOUT ¥Ú& P OPAMP_OTR_AO1_OPT_OFFSET_TRIM Ú& P OPAMP_OTR_AO2_OPT_OFFSET_TRIM Ú& P OPAMP_OTR_AO3_OPT_OFFSET_TRIM Ú P OPAMP_OTR_OT_USER 8Ú, P $OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP Ú, P $OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP Ú, P $OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP Ú P |
| 792 |
CRC_DR_DR ÷Ú P CRC_IDR_IDR aÚ P
CRC_CR_RESET Ú P DAC_CR_EN1 ØÚ P
DAC_CR_BOFF1 JÚ P DAC_CR_TEN1 Ú P
DAC_CR_TSEL1 /Ú P DAC_CR_TSEL1_0 Ú P DAC_CR_TSEL1_1 Ú P DAC_CR_TSEL1_2 Ú P
DAC_CR_WAVE1 4Ú P DAC_CR_WAVE1_0 ¡Ú P DAC_CR_WAVE1_1 Ú P
DAC_CR_MAMP1 <Ú P DAC_CR_MAMP1_0 ©Ú P DAC_CR_MAMP1_1 ¨Ú P DAC_CR_MAMP1_2 §Ú P DAC_CR_MAMP1_3 ¦Ú P DAC_CR_DMAEN1 Ú P DAC_CR_DMAUDRIE1 Ú P DAC_CR_EN2 ×Ú P
DAC_CR_BOFF2 IÚ P DAC_CR_TEN2 Ú P
DAC_CR_TSEL2 .Ú P DAC_CR_TSEL2_0 Ú P DAC_CR_TSEL2_1 Ú P DAC_CR_TSEL2_2 Ú P
DAC_CR_WAVE2 3Ú P DAC_CR_WAVE2_0 Ú P DAC_CR_WAVE2_1 Ú P
DAC_CR_MAMP2 ;Ú P DAC_CR_MAMP2_0 ¨Ú P DAC_CR_MAMP2_1 §Ú P DAC_CR_MAMP2_2 ¦Ú P DAC_CR_MAMP2_3 ¥Ú P DAC_CR_DMAEN2 ÿÚ P DAC_CR_DMAUDRIE2 Ú P DAC_SWTRIGR_SWTRIG1 ÜÚ P DAC_SWTRIGR_SWTRIG2 ÛÚ P DAC_DHR12R1_DACC1DHR ?Ú P DAC_DHR12L1_DACC1DHR EÚ P DAC_DHR8R1_DACC1DHR lÚ P DAC_DHR12R2_DACC2DHR =Ú P DAC_DHR12L2_DACC2DHR CÚ P DAC_DHR8R2_DACC2DHR jÚ P DAC_DHR12RD_DACC1DHR ,Ú P DAC_DHR12RD_DACC2DHR +Ú P DAC_DHR12LD_DACC1DHR 2Ú P DAC_DHR12LD_DACC2DHR 1Ú P DAC_DHR8RD_DACC1DHR YÚ P DAC_DHR8RD_DACC2DHR XÚ P DAC_DOR1_DACC1DOR ìÚ P DAC_DOR2_DACC2DOR êÚ P DAC_SR_DMAUDR1 Ú P DAC_SR_DMAUDR2 Ú P DBGMCU_IDCODE_DEV_ID ÀÚ P DBGMCU_IDCODE_REV_ID ²Ú P DBGMCU_IDCODE_REV_ID_0 Ú P DBGMCU_IDCODE_REV_ID_1 Ú P DBGMCU_IDCODE_REV_ID_2 Ú P DBGMCU_IDCODE_REV_ID_3 Ú P DBGMCU_IDCODE_REV_ID_4 Ú P DBGMCU_IDCODE_REV_ID_5 Ú P DBGMCU_IDCODE_REV_ID_6 Ú P DBGMCU_IDCODE_REV_ID_7 Ú P DBGMCU_IDCODE_REV_ID_8 Ú P DBGMCU_IDCODE_REV_ID_9 Ú P DBGMCU_IDCODE_REV_ID_10 ìÚ P DBGMCU_IDCODE_REV_ID_11 ëÚ P DBGMCU_IDCODE_REV_ID_12 êÚ P DBGMCU_IDCODE_REV_ID_13 éÚ P DBGMCU_IDCODE_REV_ID_14 èÚ P DBGMCU_IDCODE_REV_ID_15 çÚ P DBGMCU_CR_DBG_SLEEP ûÚ P DBGMCU_CR_DBG_STOP 0Ú P DBGMCU_CR_DBG_STANDBY [Ú P DBGMCU_CR_TRACE_IOEN ¥Ú P DBGMCU_CR_TRACE_MODE «Ú P DBGMCU_CR_TRACE_MODE_0 Ú P DBGMCU_CR_TRACE_MODE_1 Ú% P DBGMCU_APB1_FZ_DBG_TIM2_STOP 3Ú% P DBGMCU_APB1_FZ_DBG_TIM3_STOP 2Ú% P DBGMCU_APB1_FZ_DBG_TIM4_STOP 1Ú% P DBGMCU_APB1_FZ_DBG_TIM5_STOP 0Ú% P DBGMCU_APB1_FZ_DBG_TIM6_STOP /Ú% P DBGMCU_APB1_FZ_DBG_TIM7_STOP .Ú$ P DBGMCU_APB1_FZ_DBG_RTC_STOP hÚ% P DBGMCU_APB1_FZ_DBG_WWDG_STOP Ú% P DBGMCU_APB1_FZ_DBG_IWDG_STOP $Ú. P &DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT Ú. P &DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT Ú% P DBGMCU_APB2_FZ_DBG_TIM9_STOP +Ú& P DBGMCU_APB2_FZ_DBG_TIM10_STOP Ú& P DBGMCU_APB2_FZ_DBG_TIM11_STOP Ú P
DMA_ISR_GIF1 .Ú P DMA_ISR_TCIF1 ÜÚ P DMA_ISR_HTIF1 ×Ú P DMA_ISR_TEIF1 ÚÚ P
DMA_ISR_GIF2 -Ú P DMA_ISR_TCIF2 ÛÚ P DMA_ISR_HTIF2 ÖÚ P DMA_ISR_TEIF2 ÙÚ P
DMA_ISR_GIF3 ,Ú P DMA_ISR_TCIF3 ÚÚ P DMA_ISR_HTIF3 ÕÚ P DMA_ISR_TEIF3 ØÚ P
DMA_ISR_GIF4 +Ú P DMA_ISR_TCIF4 ÙÚ P DMA_ISR_HTIF4 ÔÚ P DMA_ISR_TEIF4 ×Ú P
DMA_ISR_GIF5 *Ú P DMA_ISR_TCIF5 ØÚ P DMA_ISR_HTIF5 ÓÚ P DMA_ISR_TEIF5 ÖÚ P
DMA_ISR_GIF6 )Ú P DMA_ISR_TCIF6 ×Ú P DMA_ISR_HTIF6 ÒÚ P DMA_ISR_TEIF6 ÕÚ P
DMA_ISR_GIF7 (Ú P DMA_ISR_TCIF7 ÖÚ P DMA_ISR_HTIF7 ÑÚ P DMA_ISR_TEIF7 ÔÚ P DMA_IFCR_CGIF1 ±Ú P DMA_IFCR_CTCIF1 _Ú P DMA_IFCR_CHTIF1 ZÚ P DMA_IFCR_CTEIF1 ]Ú P DMA_IFCR_CGIF2 °Ú P DMA_IFCR_CTCIF2 ^Ú P DMA_IFCR_CHTIF2 YÚ P DMA_IFCR_CTEIF2 \Ú P DMA_IFCR_CGIF3 ¯Ú P DMA_IFCR_CTCIF3 ]Ú P DMA_IFCR_CHTIF3 XÚ P DMA_IFCR_CTEIF3 [Ú P DMA_IFCR_CGIF4 ®Ú P DMA_IFCR_CTCIF4 \Ú P DMA_IFCR_CHTIF4 WÚ P DMA_IFCR_CTEIF4 ZÚ P DMA_IFCR_CGIF5 Ú P DMA_IFCR_CTCIF5 [Ú P DMA_IFCR_CHTIF5 VÚ P DMA_IFCR_CTEIF5 YÚ P DMA_IFCR_CGIF6 ¬Ú P DMA_IFCR_CTCIF6 ZÚ P DMA_IFCR_CHTIF6 UÚ P DMA_IFCR_CTEIF6 XÚ P DMA_IFCR_CGIF7 «Ú P DMA_IFCR_CTCIF7 YÚ P DMA_IFCR_CHTIF7 TÚ P DMA_IFCR_CTEIF7 WÚ P DMA_CCR1_EN Ú P DMA_CCR1_TCIE óÚ P DMA_CCR1_HTIE îÚ P DMA_CCR1_TEIE ñÚ P
DMA_CCR1_DIR ;Ú P DMA_CCR1_CIRC ÷Ú P DMA_CCR1_PINC îÚ P DMA_CCR1_MINC ñÚ P DMA_CCR1_PSIZE Ú P DMA_CCR1_PSIZE_0 øÚ P DMA_CCR1_PSIZE_1 ÷Ú P DMA_CCR1_MSIZE Ú P DMA_CCR1_MSIZE_0 ûÚ P DMA_CCR1_MSIZE_1 úÚ P DMA_CCR1_PL Ú P DMA_CCR1_PL_0 íÚ P DMA_CCR1_PL_1 ìÚ P DMA_CCR1_MEM2MEM "Ú P DMA_CCR2_EN Ú P DMA_CCR2_TCIE òÚ P DMA_CCR2_HTIE íÚ P DMA_CCR2_TEIE ðÚ P
DMA_CCR2_DIR :Ú P DMA_CCR2_CIRC öÚ P DMA_CCR2_PINC íÚ P DMA_CCR2_MINC ðÚ P DMA_CCR2_PSIZE Ú P DMA_CCR2_PSIZE_0 ÷Ú P DMA_CCR2_PSIZE_1 öÚ P DMA_CCR2_MSIZE Ú P DMA_CCR2_MSIZE_0 úÚ P DMA_CCR2_MSIZE_1 ùÚ P DMA_CCR2_PL Ú P DMA_CCR2_PL_0 ìÚ P DMA_CCR2_PL_1 ëÚ P DMA_CCR2_MEM2MEM !Ú P DMA_CCR3_EN Ú P DMA_CCR3_TCIE ñÚ P DMA_CCR3_HTIE ìÚ P DMA_CCR3_TEIE ïÚ P
DMA_CCR3_DIR 9Ú P DMA_CCR3_CIRC õÚ P DMA_CCR3_PINC ìÚ P DMA_CCR3_MINC ïÚ P DMA_CCR3_PSIZE Ú P DMA_CCR3_PSIZE_0 öÚ P DMA_CCR3_PSIZE_1 õÚ P DMA_CCR3_MSIZE Ú P DMA_CCR3_MSIZE_0 ùÚ P DMA_CCR3_MSIZE_1 øÚ P DMA_CCR3_PL ~Ú P DMA_CCR3_PL_0 ëÚ P DMA_CCR3_PL_1 êÚ P DMA_CCR3_MEM2MEM Ú P DMA_CCR4_EN Ú P DMA_CCR4_TCIE ðÚ P DMA_CCR4_HTIE ëÚ P DMA_CCR4_TEIE îÚ P
DMA_CCR4_DIR 8Ú P DMA_CCR4_CIRC ôÚ P DMA_CCR4_PINC ëÚ P DMA_CCR4_MINC îÚ P DMA_CCR4_PSIZE Ú P DMA_CCR4_PSIZE_0 õÚ P DMA_CCR4_PSIZE_1 ôÚ P DMA_CCR4_MSIZE Ú P DMA_CCR4_MSIZE_0 øÚ P DMA_CCR4_MSIZE_1 ÷Ú P DMA_CCR4_PL }Ú P DMA_CCR4_PL_0 êÚ P DMA_CCR4_PL_1 éÚ P DMA_CCR4_MEM2MEM Ú P DMA_CCR5_EN
Ú P DMA_CCR5_TCIE ïÚ P DMA_CCR5_HTIE êÚ P DMA_CCR5_TEIE íÚ P
DMA_CCR5_DIR 7Ú P DMA_CCR5_CIRC óÚ P DMA_CCR5_PINC êÚ P DMA_CCR5_MINC íÚ P DMA_CCR5_PSIZE Ú P DMA_CCR5_PSIZE_0 ôÚ P DMA_CCR5_PSIZE_1 óÚ P DMA_CCR5_MSIZE Ú P DMA_CCR5_MSIZE_0 ÷Ú P DMA_CCR5_MSIZE_1 öÚ P DMA_CCR5_PL |Ú P DMA_CCR5_PL_0 éÚ P DMA_CCR5_PL_1 èÚ P DMA_CCR5_MEM2MEM Ú P DMA_CCR6_EN Ú P DMA_CCR6_TCIE îÚ P DMA_CCR6_HTIE éÚ P DMA_CCR6_TEIE ìÚ P
DMA_CCR6_DIR 6Ú P DMA_CCR6_CIRC òÚ P DMA_CCR6_PINC éÚ P DMA_CCR6_MINC ìÚ P DMA_CCR6_PSIZE Ú P DMA_CCR6_PSIZE_0 óÚ P DMA_CCR6_PSIZE_1 òÚ P DMA_CCR6_MSIZE Ú P DMA_CCR6_MSIZE_0 öÚ P DMA_CCR6_MSIZE_1 õÚ P DMA_CCR6_PL {Ú P DMA_CCR6_PL_0 èÚ P DMA_CCR6_PL_1 çÚ P DMA_CCR6_MEM2MEM Ú P DMA_CCR7_EN Ú P DMA_CCR7_TCIE íÚ P DMA_CCR7_HTIE èÚ P DMA_CCR7_TEIE ëÚ P
DMA_CCR7_DIR 5Ú P DMA_CCR7_CIRC ñÚ P DMA_CCR7_PINC èÚ P DMA_CCR7_MINC ëÚ P DMA_CCR7_PSIZE
Ú P DMA_CCR7_PSIZE_0 òÚ P DMA_CCR7_PSIZE_1 ñÚ P DMA_CCR7_MSIZE Ú P DMA_CCR7_MSIZE_0 õÚ P DMA_CCR7_MSIZE_1 ôÚ P DMA_CCR7_PL zÚ P DMA_CCR7_PL_0 çÚ P DMA_CCR7_PL_1 æÚ P DMA_CCR7_MEM2MEM Ú P DMA_CNDTR1_NDT Ú P DMA_CNDTR2_NDT Ú P DMA_CNDTR3_NDT Ú P DMA_CNDTR4_NDT Ú P DMA_CNDTR5_NDT Ú P DMA_CNDTR6_NDT Ú P DMA_CNDTR7_NDT Ú P
DMA_CPAR1_PA ;Ú P
DMA_CPAR2_PA :Ú P
DMA_CPAR3_PA 9Ú P
DMA_CPAR4_PA 8Ú P
DMA_CPAR5_PA 7Ú P
DMA_CPAR6_PA 6Ú P
DMA_CPAR7_PA 5Ú P
DMA_CMAR1_MA AÚ P
DMA_CMAR2_MA @Ú P
DMA_CMAR3_MA ?Ú P
DMA_CMAR4_MA >Ú P
DMA_CMAR5_MA =Ú P
DMA_CMAR6_MA <Ú P
DMA_CMAR7_MA ;Ú P
EXTI_IMR_MR0 Ú P
EXTI_IMR_MR1 Ú P
EXTI_IMR_MR2 Ú P
EXTI_IMR_MR3 Ú P
EXTI_IMR_MR4 Ú P
EXTI_IMR_MR5 ÿÚ P
EXTI_IMR_MR6 þÚ P
EXTI_IMR_MR7 ýÚ P
EXTI_IMR_MR8 üÚ P
EXTI_IMR_MR9 ûÚ P EXTI_IMR_MR10 ÑÚ P EXTI_IMR_MR11 ÐÚ P EXTI_IMR_MR12 ÏÚ P EXTI_IMR_MR13 ÎÚ P EXTI_IMR_MR14 ÍÚ P EXTI_IMR_MR15 ÌÚ P EXTI_IMR_MR16 ËÚ P EXTI_IMR_MR17 ÊÚ P EXTI_IMR_MR18 ÉÚ P EXTI_IMR_MR19 ÈÚ P EXTI_IMR_MR20 ÐÚ P EXTI_IMR_MR21 ÏÚ P EXTI_IMR_MR22 ÎÚ P EXTI_IMR_MR23 ÍÚ P
EXTI_EMR_MR0 Ú P
EXTI_EMR_MR1 Ú P
EXTI_EMR_MR2 Ú P
EXTI_EMR_MR3 Ú P
EXTI_EMR_MR4 Ú P
EXTI_EMR_MR5 Ú P
EXTI_EMR_MR6 Ú P
EXTI_EMR_MR7 Ú P
EXTI_EMR_MR8 Ú P
EXTI_EMR_MR9 ÿÚ P EXTI_EMR_MR10 ÕÚ P EXTI_EMR_MR11 ÔÚ P EXTI_EMR_MR12 ÓÚ P EXTI_EMR_MR13 ÒÚ P EXTI_EMR_MR14 ÑÚ P EXTI_EMR_MR15 ÐÚ P EXTI_EMR_MR16 ÏÚ P EXTI_EMR_MR17 ÎÚ P EXTI_EMR_MR18 ÍÚ P EXTI_EMR_MR19 ÌÚ P EXTI_EMR_MR20 ÔÚ P EXTI_EMR_MR21 ÓÚ P EXTI_EMR_MR22 ÒÚ P EXTI_EMR_MR23 ÑÚ P EXTI_RTSR_TR0 Ú P EXTI_RTSR_TR1 Ú P EXTI_RTSR_TR2 Ú P EXTI_RTSR_TR3 Ú P EXTI_RTSR_TR4 Ú P EXTI_RTSR_TR5 Ú P EXTI_RTSR_TR6 Ú P EXTI_RTSR_TR7 Ú P EXTI_RTSR_TR8 Ú P EXTI_RTSR_TR9 Ú P EXTI_RTSR_TR10 eÚ P EXTI_RTSR_TR11 dÚ P EXTI_RTSR_TR12 cÚ P EXTI_RTSR_TR13 bÚ P EXTI_RTSR_TR14 aÚ P EXTI_RTSR_TR15 `Ú P EXTI_RTSR_TR16 _Ú P EXTI_RTSR_TR17 ^Ú P EXTI_RTSR_TR18 ]Ú P EXTI_RTSR_TR19 \Ú P EXTI_RTSR_TR20 dÚ P EXTI_RTSR_TR21 cÚ P EXTI_RTSR_TR22 bÚ P EXTI_RTSR_TR23 aÚ P EXTI_FTSR_TR0 ¤Ú P EXTI_FTSR_TR1 £Ú P EXTI_FTSR_TR2 ¢Ú P EXTI_FTSR_TR3 ¡Ú P EXTI_FTSR_TR4 Ú P EXTI_FTSR_TR5 Ú P EXTI_FTSR_TR6 Ú P EXTI_FTSR_TR7 Ú P EXTI_FTSR_TR8 Ú P EXTI_FTSR_TR9 Ú P EXTI_FTSR_TR10 qÚ P EXTI_FTSR_TR11 pÚ P EXTI_FTSR_TR12 oÚ P EXTI_FTSR_TR13 nÚ P EXTI_FTSR_TR14 mÚ P EXTI_FTSR_TR15 lÚ P EXTI_FTSR_TR16 kÚ P EXTI_FTSR_TR17 jÚ P EXTI_FTSR_TR18 iÚ P EXTI_FTSR_TR19 hÚ P EXTI_FTSR_TR20 pÚ P EXTI_FTSR_TR21 oÚ P EXTI_FTSR_TR22 nÚ P EXTI_FTSR_TR23 mÚ P EXTI_SWIER_SWIER0 mÚ P EXTI_SWIER_SWIER1 lÚ P EXTI_SWIER_SWIER2 kÚ P EXTI_SWIER_SWIER3 jÚ P EXTI_SWIER_SWIER4 iÚ P EXTI_SWIER_SWIER5 hÚ P EXTI_SWIER_SWIER6 gÚ P EXTI_SWIER_SWIER7 fÚ P EXTI_SWIER_SWIER8 eÚ P EXTI_SWIER_SWIER9 dÚ P EXTI_SWIER_SWIER10 :Ú P EXTI_SWIER_SWIER11 9Ú P EXTI_SWIER_SWIER12 8Ú P EXTI_SWIER_SWIER13 7Ú P EXTI_SWIER_SWIER14 6Ú P EXTI_SWIER_SWIER15 5Ú P EXTI_SWIER_SWIER16 4Ú P EXTI_SWIER_SWIER17 3Ú P EXTI_SWIER_SWIER18 2Ú P EXTI_SWIER_SWIER19 1Ú P EXTI_SWIER_SWIER20 9Ú P EXTI_SWIER_SWIER21 8Ú P EXTI_SWIER_SWIER22 7Ú P EXTI_SWIER_SWIER23 6Ú P EXTI_PR_PR0 IÚ P EXTI_PR_PR1 HÚ P EXTI_PR_PR2 GÚ P EXTI_PR_PR3 FÚ P EXTI_PR_PR4 EÚ P EXTI_PR_PR5 DÚ P EXTI_PR_PR6 CÚ P EXTI_PR_PR7 BÚ P EXTI_PR_PR8 AÚ P EXTI_PR_PR9 @Ú P
EXTI_PR_PR10 Ú P
EXTI_PR_PR11 Ú P
EXTI_PR_PR12 Ú P
EXTI_PR_PR13 Ú P
EXTI_PR_PR14 Ú P
EXTI_PR_PR15 Ú P
EXTI_PR_PR16 Ú P
EXTI_PR_PR17 Ú P
EXTI_PR_PR18 Ú P
EXTI_PR_PR19
Ú P
EXTI_PR_PR20 Ú P
EXTI_PR_PR21 Ú P
EXTI_PR_PR22 Ú P
EXTI_PR_PR23 Ú P FLASH_ACR_LATENCY Ú P FLASH_ACR_PRFTEN ÚÚ P FLASH_ACR_ACC64 zÚ P FLASH_ACR_SLEEP_PD 9Ú P FLASH_ACR_RUN_PD ÁÚ P FLASH_PECR_PELOCK Ú P FLASH_PECR_PRGLOCK ?Ú P FLASH_PECR_OPTLOCK 5Ú P FLASH_PECR_PROG Ú P FLASH_PECR_DATA =Ú P FLASH_PECR_FTDW "Ú P FLASH_PECR_ERASE åÚ P FLASH_PECR_FPRG (Ú P FLASH_PECR_PARALLBANK sÚ P FLASH_PECR_EOPIE ãÚ P FLASH_PECR_ERRIE ÞÚ P FLASH_PECR_OBL_LAUNCH TÚ P FLASH_PDKEYR_PDKEYR ÛÚ P FLASH_PEKEYR_PEKEYR ÙÚ P FLASH_PRGKEYR_PRGKEYR -Ú P FLASH_OPTKEYR_OPTKEYR Ú P
FLASH_SR_BSY ôÚ P
FLASH_SR_EOP þÚ P FLASH_SR_ENHV ¯Ú P FLASH_SR_READY iÚ P FLASH_SR_WRPERR úÚ P FLASH_SR_PGAERR Ú P FLASH_SR_SIZERR ýÚ P FLASH_SR_OPTVERR ¨Ú P FLASH_SR_OPTVERRUSR ¨Ú P FLASH_OBR_RDPRT Ú P FLASH_OBR_BOR_LEV qÚ P FLASH_OBR_USER aÚ P FLASH_OBR_IWDG_SW fÚ P FLASH_OBR_nRST_STOP Ú P FLASH_OBR_nRST_STDBY HÚ P FLASH_OBR_nRST_BFB2 ÔÚ P FLASH_WRPR_WRP ?Ú P FLASH_WRPR1_WRP Ú P FLASH_WRPR2_WRP Ú P FSMC_BCR1_MBKEN QÚ P FSMC_BCR1_MUXEN 1Ú P FSMC_BCR1_MTYP vÚ P FSMC_BCR1_MTYP_0 ãÚ P FSMC_BCR1_MTYP_1 âÚ P FSMC_BCR1_MWID Ú P FSMC_BCR1_MWID_0 üÚ P FSMC_BCR1_MWID_1 ûÚ P FSMC_BCR1_FACCEN Ú P FSMC_BCR1_BURSTEN Ú P FSMC_BCR1_WAITPOL Ú P FSMC_BCR1_WRAPMOD Ú P FSMC_BCR1_WAITCFG µÚ P FSMC_BCR1_WREN Ú P FSMC_BCR1_WAITEN ôÚ P FSMC_BCR1_EXTMOD ëÚ P FSMC_BCR1_ASYNCWAIT Ú P FSMC_BCR1_CBURSTRW <Ú P FSMC_BCR2_MBKEN PÚ P FSMC_BCR2_MUXEN 0Ú P FSMC_BCR2_MTYP uÚ P FSMC_BCR2_MTYP_0 âÚ P FSMC_BCR2_MTYP_1 áÚ P FSMC_BCR2_MWID Ú P FSMC_BCR2_MWID_0 ûÚ P FSMC_BCR2_MWID_1 úÚ P FSMC_BCR2_FACCEN Ú P FSMC_BCR2_BURSTEN Ú P FSMC_BCR2_WAITPOL Ú P FSMC_BCR2_WRAPMOD Ú P FSMC_BCR2_WAITCFG ´Ú P FSMC_BCR2_WREN Ú P FSMC_BCR2_WAITEN óÚ P FSMC_BCR2_EXTMOD êÚ P FSMC_BCR2_ASYNCWAIT Ú P FSMC_BCR2_CBURSTRW ;Ú P FSMC_BCR3_MBKEN OÚ P FSMC_BCR3_MUXEN /Ú P FSMC_BCR3_MTYP tÚ P FSMC_BCR3_MTYP_0 áÚ P FSMC_BCR3_MTYP_1 àÚ P FSMC_BCR3_MWID Ú P FSMC_BCR3_MWID_0 úÚ P FSMC_BCR3_MWID_1 ùÚ P FSMC_BCR3_FACCEN Ú P FSMC_BCR3_BURSTEN Ú P FSMC_BCR3_WAITPOL Ú P FSMC_BCR3_WRAPMOD Ú P FSMC_BCR3_WAITCFG ³Ú P FSMC_BCR3_WREN Ú P FSMC_BCR3_WAITEN òÚ P FSMC_BCR3_EXTMOD éÚ P FSMC_BCR3_ASYNCWAIT Ú P FSMC_BCR3_CBURSTRW :Ú P FSMC_BCR4_MBKEN NÚ P FSMC_BCR4_MUXEN .Ú P FSMC_BCR4_MTYP sÚ P FSMC_BCR4_MTYP_0 àÚ P FSMC_BCR4_MTYP_1 ßÚ P FSMC_BCR4_MWID Ú P FSMC_BCR4_MWID_0 ùÚ P FSMC_BCR4_MWID_1 øÚ P FSMC_BCR4_FACCEN Ú P FSMC_BCR4_BURSTEN Ú P FSMC_BCR4_WAITPOL Ú P FSMC_BCR4_WRAPMOD Ú P FSMC_BCR4_WAITCFG ²Ú P FSMC_BCR4_WREN Ú P FSMC_BCR4_WAITEN ñÚ P FSMC_BCR4_EXTMOD èÚ P FSMC_BCR4_ASYNCWAIT Ú P FSMC_BCR4_CBURSTRW 9Ú P FSMC_BTR1_ADDSET öÚ P FSMC_BTR1_ADDSET_0 cÚ P FSMC_BTR1_ADDSET_1 bÚ P FSMC_BTR1_ADDSET_2 aÚ P FSMC_BTR1_ADDSET_3 `Ú P FSMC_BTR1_ADDHLD |
792 |
CRC_DR_DR ÷Ú P CRC_IDR_IDR aÚ P
CRC_CR_RESET Ú P DAC_CR_EN1 ØÚ P
DAC_CR_BOFF1 JÚ P DAC_CR_TEN1 Ú P
DAC_CR_TSEL1 /Ú P DAC_CR_TSEL1_0 Ú P DAC_CR_TSEL1_1 Ú P DAC_CR_TSEL1_2 Ú P
DAC_CR_WAVE1 4Ú P DAC_CR_WAVE1_0 ¡Ú P DAC_CR_WAVE1_1 Ú P
DAC_CR_MAMP1 <Ú P DAC_CR_MAMP1_0 ©Ú P DAC_CR_MAMP1_1 ¨Ú P DAC_CR_MAMP1_2 §Ú P DAC_CR_MAMP1_3 ¦Ú P DAC_CR_DMAEN1 Ú P DAC_CR_DMAUDRIE1 Ú P DAC_CR_EN2 ×Ú P
DAC_CR_BOFF2 IÚ P DAC_CR_TEN2 Ú P
DAC_CR_TSEL2 .Ú P DAC_CR_TSEL2_0 Ú P DAC_CR_TSEL2_1 Ú P DAC_CR_TSEL2_2 Ú P
DAC_CR_WAVE2 3Ú P DAC_CR_WAVE2_0 Ú P DAC_CR_WAVE2_1 Ú P
DAC_CR_MAMP2 ;Ú P DAC_CR_MAMP2_0 ¨Ú P DAC_CR_MAMP2_1 §Ú P DAC_CR_MAMP2_2 ¦Ú P DAC_CR_MAMP2_3 ¥Ú P DAC_CR_DMAEN2 ÿÚ P DAC_CR_DMAUDRIE2 Ú P DAC_SWTRIGR_SWTRIG1 ÜÚ P DAC_SWTRIGR_SWTRIG2 ÛÚ P DAC_DHR12R1_DACC1DHR ?Ú P DAC_DHR12L1_DACC1DHR EÚ P DAC_DHR8R1_DACC1DHR lÚ P DAC_DHR12R2_DACC2DHR =Ú P DAC_DHR12L2_DACC2DHR CÚ P DAC_DHR8R2_DACC2DHR jÚ P DAC_DHR12RD_DACC1DHR ,Ú P DAC_DHR12RD_DACC2DHR +Ú P DAC_DHR12LD_DACC1DHR 2Ú P DAC_DHR12LD_DACC2DHR 1Ú P DAC_DHR8RD_DACC1DHR YÚ P DAC_DHR8RD_DACC2DHR XÚ P DAC_DOR1_DACC1DOR ìÚ P DAC_DOR2_DACC2DOR êÚ P DAC_SR_DMAUDR1 Ú P DAC_SR_DMAUDR2 Ú P DBGMCU_IDCODE_DEV_ID ÀÚ P DBGMCU_IDCODE_REV_ID ²Ú P DBGMCU_IDCODE_REV_ID_0 Ú P DBGMCU_IDCODE_REV_ID_1 Ú P DBGMCU_IDCODE_REV_ID_2 Ú P DBGMCU_IDCODE_REV_ID_3 Ú P DBGMCU_IDCODE_REV_ID_4 Ú P DBGMCU_IDCODE_REV_ID_5 Ú P DBGMCU_IDCODE_REV_ID_6 Ú P DBGMCU_IDCODE_REV_ID_7 Ú P DBGMCU_IDCODE_REV_ID_8 Ú P DBGMCU_IDCODE_REV_ID_9 Ú P DBGMCU_IDCODE_REV_ID_10 ìÚ P DBGMCU_IDCODE_REV_ID_11 ëÚ P DBGMCU_IDCODE_REV_ID_12 êÚ P DBGMCU_IDCODE_REV_ID_13 éÚ P DBGMCU_IDCODE_REV_ID_14 èÚ P DBGMCU_IDCODE_REV_ID_15 çÚ P DBGMCU_CR_DBG_SLEEP ûÚ P DBGMCU_CR_DBG_STOP 0Ú P DBGMCU_CR_DBG_STANDBY [Ú P DBGMCU_CR_TRACE_IOEN ¥Ú P DBGMCU_CR_TRACE_MODE «Ú P DBGMCU_CR_TRACE_MODE_0 Ú P DBGMCU_CR_TRACE_MODE_1 Ú% P DBGMCU_APB1_FZ_DBG_TIM2_STOP 3Ú% P DBGMCU_APB1_FZ_DBG_TIM3_STOP 2Ú% P DBGMCU_APB1_FZ_DBG_TIM4_STOP 1Ú% P DBGMCU_APB1_FZ_DBG_TIM5_STOP 0Ú% P DBGMCU_APB1_FZ_DBG_TIM6_STOP /Ú% P DBGMCU_APB1_FZ_DBG_TIM7_STOP .Ú$ P DBGMCU_APB1_FZ_DBG_RTC_STOP hÚ% P DBGMCU_APB1_FZ_DBG_WWDG_STOP Ú% P DBGMCU_APB1_FZ_DBG_IWDG_STOP $Ú. P &DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT Ú. P &DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT Ú% P DBGMCU_APB2_FZ_DBG_TIM9_STOP +Ú& P DBGMCU_APB2_FZ_DBG_TIM10_STOP Ú& P DBGMCU_APB2_FZ_DBG_TIM11_STOP Ú P
DMA_ISR_GIF1 .Ú P DMA_ISR_TCIF1 ÜÚ P DMA_ISR_HTIF1 ×Ú P DMA_ISR_TEIF1 ÚÚ P
DMA_ISR_GIF2 -Ú P DMA_ISR_TCIF2 ÛÚ P DMA_ISR_HTIF2 ÖÚ P DMA_ISR_TEIF2 ÙÚ P
DMA_ISR_GIF3 ,Ú P DMA_ISR_TCIF3 ÚÚ P DMA_ISR_HTIF3 ÕÚ P DMA_ISR_TEIF3 ØÚ P
DMA_ISR_GIF4 +Ú P DMA_ISR_TCIF4 ÙÚ P DMA_ISR_HTIF4 ÔÚ P DMA_ISR_TEIF4 ×Ú P
DMA_ISR_GIF5 *Ú P DMA_ISR_TCIF5 ØÚ P DMA_ISR_HTIF5 ÓÚ P DMA_ISR_TEIF5 ÖÚ P
DMA_ISR_GIF6 )Ú P DMA_ISR_TCIF6 ×Ú P DMA_ISR_HTIF6 ÒÚ P DMA_ISR_TEIF6 ÕÚ P
DMA_ISR_GIF7 (Ú P DMA_ISR_TCIF7 ÖÚ P DMA_ISR_HTIF7 ÑÚ P DMA_ISR_TEIF7 ÔÚ P DMA_IFCR_CGIF1 ±Ú P DMA_IFCR_CTCIF1 _Ú P DMA_IFCR_CHTIF1 ZÚ P DMA_IFCR_CTEIF1 ]Ú P DMA_IFCR_CGIF2 °Ú P DMA_IFCR_CTCIF2 ^Ú P DMA_IFCR_CHTIF2 YÚ P DMA_IFCR_CTEIF2 \Ú P DMA_IFCR_CGIF3 ¯Ú P DMA_IFCR_CTCIF3 ]Ú P DMA_IFCR_CHTIF3 XÚ P DMA_IFCR_CTEIF3 [Ú P DMA_IFCR_CGIF4 ®Ú P DMA_IFCR_CTCIF4 \Ú P DMA_IFCR_CHTIF4 WÚ P DMA_IFCR_CTEIF4 ZÚ P DMA_IFCR_CGIF5 Ú P DMA_IFCR_CTCIF5 [Ú P DMA_IFCR_CHTIF5 VÚ P DMA_IFCR_CTEIF5 YÚ P DMA_IFCR_CGIF6 ¬Ú P DMA_IFCR_CTCIF6 ZÚ P DMA_IFCR_CHTIF6 UÚ P DMA_IFCR_CTEIF6 XÚ P DMA_IFCR_CGIF7 «Ú P DMA_IFCR_CTCIF7 YÚ P DMA_IFCR_CHTIF7 TÚ P DMA_IFCR_CTEIF7 WÚ P DMA_CCR1_EN Ú P DMA_CCR1_TCIE óÚ P DMA_CCR1_HTIE îÚ P DMA_CCR1_TEIE ñÚ P
DMA_CCR1_DIR ;Ú P DMA_CCR1_CIRC ÷Ú P DMA_CCR1_PINC îÚ P DMA_CCR1_MINC ñÚ P DMA_CCR1_PSIZE Ú P DMA_CCR1_PSIZE_0 øÚ P DMA_CCR1_PSIZE_1 ÷Ú P DMA_CCR1_MSIZE Ú P DMA_CCR1_MSIZE_0 ûÚ P DMA_CCR1_MSIZE_1 úÚ P DMA_CCR1_PL Ú P DMA_CCR1_PL_0 íÚ P DMA_CCR1_PL_1 ìÚ P DMA_CCR1_MEM2MEM "Ú P DMA_CCR2_EN Ú P DMA_CCR2_TCIE òÚ P DMA_CCR2_HTIE íÚ P DMA_CCR2_TEIE ðÚ P
DMA_CCR2_DIR :Ú P DMA_CCR2_CIRC öÚ P DMA_CCR2_PINC íÚ P DMA_CCR2_MINC ðÚ P DMA_CCR2_PSIZE Ú P DMA_CCR2_PSIZE_0 ÷Ú P DMA_CCR2_PSIZE_1 öÚ P DMA_CCR2_MSIZE Ú P DMA_CCR2_MSIZE_0 úÚ P DMA_CCR2_MSIZE_1 ùÚ P DMA_CCR2_PL Ú P DMA_CCR2_PL_0 ìÚ P DMA_CCR2_PL_1 ëÚ P DMA_CCR2_MEM2MEM !Ú P DMA_CCR3_EN Ú P DMA_CCR3_TCIE ñÚ P DMA_CCR3_HTIE ìÚ P DMA_CCR3_TEIE ïÚ P
DMA_CCR3_DIR 9Ú P DMA_CCR3_CIRC õÚ P DMA_CCR3_PINC ìÚ P DMA_CCR3_MINC ïÚ P DMA_CCR3_PSIZE Ú P DMA_CCR3_PSIZE_0 öÚ P DMA_CCR3_PSIZE_1 õÚ P DMA_CCR3_MSIZE Ú P DMA_CCR3_MSIZE_0 ùÚ P DMA_CCR3_MSIZE_1 øÚ P DMA_CCR3_PL ~Ú P DMA_CCR3_PL_0 ëÚ P DMA_CCR3_PL_1 êÚ P DMA_CCR3_MEM2MEM Ú P DMA_CCR4_EN Ú P DMA_CCR4_TCIE ðÚ P DMA_CCR4_HTIE ëÚ P DMA_CCR4_TEIE îÚ P
DMA_CCR4_DIR 8Ú P DMA_CCR4_CIRC ôÚ P DMA_CCR4_PINC ëÚ P DMA_CCR4_MINC îÚ P DMA_CCR4_PSIZE Ú P DMA_CCR4_PSIZE_0 õÚ P DMA_CCR4_PSIZE_1 ôÚ P DMA_CCR4_MSIZE Ú P DMA_CCR4_MSIZE_0 øÚ P DMA_CCR4_MSIZE_1 ÷Ú P DMA_CCR4_PL }Ú P DMA_CCR4_PL_0 êÚ P DMA_CCR4_PL_1 éÚ P DMA_CCR4_MEM2MEM Ú P DMA_CCR5_EN
Ú P DMA_CCR5_TCIE ïÚ P DMA_CCR5_HTIE êÚ P DMA_CCR5_TEIE íÚ P
DMA_CCR5_DIR 7Ú P DMA_CCR5_CIRC óÚ P DMA_CCR5_PINC êÚ P DMA_CCR5_MINC íÚ P DMA_CCR5_PSIZE Ú P DMA_CCR5_PSIZE_0 ôÚ P DMA_CCR5_PSIZE_1 óÚ P DMA_CCR5_MSIZE Ú P DMA_CCR5_MSIZE_0 ÷Ú P DMA_CCR5_MSIZE_1 öÚ P DMA_CCR5_PL |Ú P DMA_CCR5_PL_0 éÚ P DMA_CCR5_PL_1 èÚ P DMA_CCR5_MEM2MEM Ú P DMA_CCR6_EN Ú P DMA_CCR6_TCIE îÚ P DMA_CCR6_HTIE éÚ P DMA_CCR6_TEIE ìÚ P
DMA_CCR6_DIR 6Ú P DMA_CCR6_CIRC òÚ P DMA_CCR6_PINC éÚ P DMA_CCR6_MINC ìÚ P DMA_CCR6_PSIZE Ú P DMA_CCR6_PSIZE_0 óÚ P DMA_CCR6_PSIZE_1 òÚ P DMA_CCR6_MSIZE Ú P DMA_CCR6_MSIZE_0 öÚ P DMA_CCR6_MSIZE_1 õÚ P DMA_CCR6_PL {Ú P DMA_CCR6_PL_0 èÚ P DMA_CCR6_PL_1 çÚ P DMA_CCR6_MEM2MEM Ú P DMA_CCR7_EN Ú P DMA_CCR7_TCIE íÚ P DMA_CCR7_HTIE èÚ P DMA_CCR7_TEIE ëÚ P
DMA_CCR7_DIR 5Ú P DMA_CCR7_CIRC ñÚ P DMA_CCR7_PINC èÚ P DMA_CCR7_MINC ëÚ P DMA_CCR7_PSIZE
Ú P DMA_CCR7_PSIZE_0 òÚ P DMA_CCR7_PSIZE_1 ñÚ P DMA_CCR7_MSIZE Ú P DMA_CCR7_MSIZE_0 õÚ P DMA_CCR7_MSIZE_1 ôÚ P DMA_CCR7_PL zÚ P DMA_CCR7_PL_0 çÚ P DMA_CCR7_PL_1 æÚ P DMA_CCR7_MEM2MEM Ú P DMA_CNDTR1_NDT Ú P DMA_CNDTR2_NDT Ú P DMA_CNDTR3_NDT Ú P DMA_CNDTR4_NDT Ú P DMA_CNDTR5_NDT Ú P DMA_CNDTR6_NDT Ú P DMA_CNDTR7_NDT Ú P
DMA_CPAR1_PA ;Ú P
DMA_CPAR2_PA :Ú P
DMA_CPAR3_PA 9Ú P
DMA_CPAR4_PA 8Ú P
DMA_CPAR5_PA 7Ú P
DMA_CPAR6_PA 6Ú P
DMA_CPAR7_PA 5Ú P
DMA_CMAR1_MA AÚ P
DMA_CMAR2_MA @Ú P
DMA_CMAR3_MA ?Ú P
DMA_CMAR4_MA >Ú P
DMA_CMAR5_MA =Ú P
DMA_CMAR6_MA <Ú P
DMA_CMAR7_MA ;Ú P
EXTI_IMR_MR0 Ú P
EXTI_IMR_MR1 Ú P
EXTI_IMR_MR2 Ú P
EXTI_IMR_MR3 Ú P
EXTI_IMR_MR4 Ú P
EXTI_IMR_MR5 ÿÚ P
EXTI_IMR_MR6 þÚ P
EXTI_IMR_MR7 ýÚ P
EXTI_IMR_MR8 üÚ P
EXTI_IMR_MR9 ûÚ P EXTI_IMR_MR10 ÑÚ P EXTI_IMR_MR11 ÐÚ P EXTI_IMR_MR12 ÏÚ P EXTI_IMR_MR13 ÎÚ P EXTI_IMR_MR14 ÍÚ P EXTI_IMR_MR15 ÌÚ P EXTI_IMR_MR16 ËÚ P EXTI_IMR_MR17 ÊÚ P EXTI_IMR_MR18 ÉÚ P EXTI_IMR_MR19 ÈÚ P EXTI_IMR_MR20 ÐÚ P EXTI_IMR_MR21 ÏÚ P EXTI_IMR_MR22 ÎÚ P EXTI_IMR_MR23 ÍÚ P
EXTI_EMR_MR0 Ú P
EXTI_EMR_MR1 Ú P
EXTI_EMR_MR2 Ú P
EXTI_EMR_MR3 Ú P
EXTI_EMR_MR4 Ú P
EXTI_EMR_MR5 Ú P
EXTI_EMR_MR6 Ú P
EXTI_EMR_MR7 Ú P
EXTI_EMR_MR8 Ú P
EXTI_EMR_MR9 ÿÚ P EXTI_EMR_MR10 ÕÚ P EXTI_EMR_MR11 ÔÚ P EXTI_EMR_MR12 ÓÚ P EXTI_EMR_MR13 ÒÚ P EXTI_EMR_MR14 ÑÚ P EXTI_EMR_MR15 ÐÚ P EXTI_EMR_MR16 ÏÚ P EXTI_EMR_MR17 ÎÚ P EXTI_EMR_MR18 ÍÚ P EXTI_EMR_MR19 ÌÚ P EXTI_EMR_MR20 ÔÚ P EXTI_EMR_MR21 ÓÚ P EXTI_EMR_MR22 ÒÚ P EXTI_EMR_MR23 ÑÚ P EXTI_RTSR_TR0 Ú P EXTI_RTSR_TR1 Ú P EXTI_RTSR_TR2 Ú P EXTI_RTSR_TR3 Ú P EXTI_RTSR_TR4 Ú P EXTI_RTSR_TR5 Ú P EXTI_RTSR_TR6 Ú P EXTI_RTSR_TR7 Ú P EXTI_RTSR_TR8 Ú P EXTI_RTSR_TR9 Ú P EXTI_RTSR_TR10 eÚ P EXTI_RTSR_TR11 dÚ P EXTI_RTSR_TR12 cÚ P EXTI_RTSR_TR13 bÚ P EXTI_RTSR_TR14 aÚ P EXTI_RTSR_TR15 `Ú P EXTI_RTSR_TR16 _Ú P EXTI_RTSR_TR17 ^Ú P EXTI_RTSR_TR18 ]Ú P EXTI_RTSR_TR19 \Ú P EXTI_RTSR_TR20 dÚ P EXTI_RTSR_TR21 cÚ P EXTI_RTSR_TR22 bÚ P EXTI_RTSR_TR23 aÚ P EXTI_FTSR_TR0 ¤Ú P EXTI_FTSR_TR1 £Ú P EXTI_FTSR_TR2 ¢Ú P EXTI_FTSR_TR3 ¡Ú P EXTI_FTSR_TR4 Ú P EXTI_FTSR_TR5 Ú P EXTI_FTSR_TR6 Ú P EXTI_FTSR_TR7 Ú P EXTI_FTSR_TR8 Ú P EXTI_FTSR_TR9 Ú P EXTI_FTSR_TR10 qÚ P EXTI_FTSR_TR11 pÚ P EXTI_FTSR_TR12 oÚ P EXTI_FTSR_TR13 nÚ P EXTI_FTSR_TR14 mÚ P EXTI_FTSR_TR15 lÚ P EXTI_FTSR_TR16 kÚ P EXTI_FTSR_TR17 jÚ P EXTI_FTSR_TR18 iÚ P EXTI_FTSR_TR19 hÚ P EXTI_FTSR_TR20 pÚ P EXTI_FTSR_TR21 oÚ P EXTI_FTSR_TR22 nÚ P EXTI_FTSR_TR23 mÚ P EXTI_SWIER_SWIER0 mÚ P EXTI_SWIER_SWIER1 lÚ P EXTI_SWIER_SWIER2 kÚ P EXTI_SWIER_SWIER3 jÚ P EXTI_SWIER_SWIER4 iÚ P EXTI_SWIER_SWIER5 hÚ P EXTI_SWIER_SWIER6 gÚ P EXTI_SWIER_SWIER7 fÚ P EXTI_SWIER_SWIER8 eÚ P EXTI_SWIER_SWIER9 dÚ P EXTI_SWIER_SWIER10 :Ú P EXTI_SWIER_SWIER11 9Ú P EXTI_SWIER_SWIER12 8Ú P EXTI_SWIER_SWIER13 7Ú P EXTI_SWIER_SWIER14 6Ú P EXTI_SWIER_SWIER15 5Ú P EXTI_SWIER_SWIER16 4Ú P EXTI_SWIER_SWIER17 3Ú P EXTI_SWIER_SWIER18 2Ú P EXTI_SWIER_SWIER19 1Ú P EXTI_SWIER_SWIER20 9Ú P EXTI_SWIER_SWIER21 8Ú P EXTI_SWIER_SWIER22 7Ú P EXTI_SWIER_SWIER23 6Ú P EXTI_PR_PR0 IÚ P EXTI_PR_PR1 HÚ P EXTI_PR_PR2 GÚ P EXTI_PR_PR3 FÚ P EXTI_PR_PR4 EÚ P EXTI_PR_PR5 DÚ P EXTI_PR_PR6 CÚ P EXTI_PR_PR7 BÚ P EXTI_PR_PR8 AÚ P EXTI_PR_PR9 @Ú P
EXTI_PR_PR10 Ú P
EXTI_PR_PR11 Ú P
EXTI_PR_PR12 Ú P
EXTI_PR_PR13 Ú P
EXTI_PR_PR14 Ú P
EXTI_PR_PR15 Ú P
EXTI_PR_PR16 Ú P
EXTI_PR_PR17 Ú P
EXTI_PR_PR18 Ú P
EXTI_PR_PR19
Ú P
EXTI_PR_PR20 Ú P
EXTI_PR_PR21 Ú P
EXTI_PR_PR22 Ú P
EXTI_PR_PR23 Ú P FLASH_ACR_LATENCY Ú P FLASH_ACR_PRFTEN ÚÚ P FLASH_ACR_ACC64 zÚ P FLASH_ACR_SLEEP_PD 9Ú P FLASH_ACR_RUN_PD ÁÚ P FLASH_PECR_PELOCK Ú P FLASH_PECR_PRGLOCK ?Ú P FLASH_PECR_OPTLOCK 5Ú P FLASH_PECR_PROG Ú P FLASH_PECR_DATA =Ú P FLASH_PECR_FTDW "Ú P FLASH_PECR_ERASE åÚ P FLASH_PECR_FPRG (Ú P FLASH_PECR_PARALLBANK sÚ P FLASH_PECR_EOPIE ãÚ P FLASH_PECR_ERRIE ÞÚ P FLASH_PECR_OBL_LAUNCH TÚ P FLASH_PDKEYR_PDKEYR ÛÚ P FLASH_PEKEYR_PEKEYR ÙÚ P FLASH_PRGKEYR_PRGKEYR -Ú P FLASH_OPTKEYR_OPTKEYR Ú P
FLASH_SR_BSY ôÚ P
FLASH_SR_EOP þÚ P FLASH_SR_ENHV ¯Ú P FLASH_SR_READY iÚ P FLASH_SR_WRPERR úÚ P FLASH_SR_PGAERR Ú P FLASH_SR_SIZERR ýÚ P FLASH_SR_OPTVERR ¨Ú P FLASH_SR_OPTVERRUSR ¨Ú P FLASH_OBR_RDPRT Ú P FLASH_OBR_BOR_LEV qÚ P FLASH_OBR_USER aÚ P FLASH_OBR_IWDG_SW fÚ P FLASH_OBR_nRST_STOP Ú P FLASH_OBR_nRST_STDBY HÚ P FLASH_OBR_nRST_BFB2 ÔÚ P FLASH_WRPR_WRP ?Ú P FLASH_WRPR1_WRP Ú P FLASH_WRPR2_WRP Ú P FSMC_BCR1_MBKEN QÚ P FSMC_BCR1_MUXEN 1Ú P FSMC_BCR1_MTYP vÚ P FSMC_BCR1_MTYP_0 ãÚ P FSMC_BCR1_MTYP_1 âÚ P FSMC_BCR1_MWID Ú P FSMC_BCR1_MWID_0 üÚ P FSMC_BCR1_MWID_1 ûÚ P FSMC_BCR1_FACCEN Ú P FSMC_BCR1_BURSTEN Ú P FSMC_BCR1_WAITPOL Ú P FSMC_BCR1_WRAPMOD Ú P FSMC_BCR1_WAITCFG µÚ P FSMC_BCR1_WREN Ú P FSMC_BCR1_WAITEN ôÚ P FSMC_BCR1_EXTMOD ëÚ P FSMC_BCR1_ASYNCWAIT Ú P FSMC_BCR1_CBURSTRW <Ú P FSMC_BCR2_MBKEN PÚ P FSMC_BCR2_MUXEN 0Ú P FSMC_BCR2_MTYP uÚ P FSMC_BCR2_MTYP_0 âÚ P FSMC_BCR2_MTYP_1 áÚ P FSMC_BCR2_MWID Ú P FSMC_BCR2_MWID_0 ûÚ P FSMC_BCR2_MWID_1 úÚ P FSMC_BCR2_FACCEN Ú P FSMC_BCR2_BURSTEN Ú P FSMC_BCR2_WAITPOL Ú P FSMC_BCR2_WRAPMOD Ú P FSMC_BCR2_WAITCFG ´Ú P FSMC_BCR2_WREN Ú P FSMC_BCR2_WAITEN óÚ P FSMC_BCR2_EXTMOD êÚ P FSMC_BCR2_ASYNCWAIT Ú P FSMC_BCR2_CBURSTRW ;Ú P FSMC_BCR3_MBKEN OÚ P FSMC_BCR3_MUXEN /Ú P FSMC_BCR3_MTYP tÚ P FSMC_BCR3_MTYP_0 áÚ P FSMC_BCR3_MTYP_1 àÚ P FSMC_BCR3_MWID Ú P FSMC_BCR3_MWID_0 úÚ P FSMC_BCR3_MWID_1 ùÚ P FSMC_BCR3_FACCEN Ú P FSMC_BCR3_BURSTEN Ú P FSMC_BCR3_WAITPOL Ú P FSMC_BCR3_WRAPMOD Ú P FSMC_BCR3_WAITCFG ³Ú P FSMC_BCR3_WREN Ú P FSMC_BCR3_WAITEN òÚ P FSMC_BCR3_EXTMOD éÚ P FSMC_BCR3_ASYNCWAIT Ú P FSMC_BCR3_CBURSTRW :Ú P FSMC_BCR4_MBKEN NÚ P FSMC_BCR4_MUXEN .Ú P FSMC_BCR4_MTYP sÚ P FSMC_BCR4_MTYP_0 àÚ P FSMC_BCR4_MTYP_1 ßÚ P FSMC_BCR4_MWID Ú P FSMC_BCR4_MWID_0 ùÚ P FSMC_BCR4_MWID_1 øÚ P FSMC_BCR4_FACCEN Ú P FSMC_BCR4_BURSTEN Ú P FSMC_BCR4_WAITPOL Ú P FSMC_BCR4_WRAPMOD Ú P FSMC_BCR4_WAITCFG ²Ú P FSMC_BCR4_WREN Ú P FSMC_BCR4_WAITEN ñÚ P FSMC_BCR4_EXTMOD èÚ P FSMC_BCR4_ASYNCWAIT Ú P FSMC_BCR4_CBURSTRW 9Ú P FSMC_BTR1_ADDSET öÚ P FSMC_BTR1_ADDSET_0 cÚ P FSMC_BTR1_ADDSET_1 bÚ P FSMC_BTR1_ADDSET_2 aÚ P FSMC_BTR1_ADDSET_3 `Ú P FSMC_BTR1_ADDHLD |
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Ú P FSMC_BTR1_ADDHLD_0 wÚ P FSMC_BTR1_ADDHLD_1 vÚ P FSMC_BTR1_ADDHLD_2 uÚ P FSMC_BTR1_ADDHLD_3 tÚ P FSMC_BTR1_DATAST êÚ P FSMC_BTR1_DATAST_0 WÚ P FSMC_BTR1_DATAST_1 VÚ P FSMC_BTR1_DATAST_2 UÚ P FSMC_BTR1_DATAST_3 TÚ P FSMC_BTR1_BUSTURN vÚ P FSMC_BTR1_BUSTURN_0 ãÚ P FSMC_BTR1_BUSTURN_1 âÚ P FSMC_BTR1_BUSTURN_2 áÚ P FSMC_BTR1_BUSTURN_3 àÚ P FSMC_BTR1_CLKDIV îÚ P FSMC_BTR1_CLKDIV_0 [Ú P FSMC_BTR1_CLKDIV_1 ZÚ P FSMC_BTR1_CLKDIV_2 YÚ P FSMC_BTR1_CLKDIV_3 XÚ P FSMC_BTR1_DATLAT ñÚ P FSMC_BTR1_DATLAT_0 ^Ú P FSMC_BTR1_DATLAT_1 ]Ú P FSMC_BTR1_DATLAT_2 \Ú P FSMC_BTR1_DATLAT_3 [Ú P FSMC_BTR1_ACCMOD Ú P FSMC_BTR1_ACCMOD_0 qÚ P FSMC_BTR1_ACCMOD_1 pÚ P FSMC_BTR2_ADDSET õÚ P FSMC_BTR2_ADDSET_0 bÚ P FSMC_BTR2_ADDSET_1 aÚ P FSMC_BTR2_ADDSET_2 `Ú P FSMC_BTR2_ADDSET_3 _Ú P FSMC_BTR2_ADDHLD Ú P FSMC_BTR2_ADDHLD_0 vÚ P FSMC_BTR2_ADDHLD_1 uÚ P FSMC_BTR2_ADDHLD_2 tÚ P FSMC_BTR2_ADDHLD_3 sÚ P FSMC_BTR2_DATAST éÚ P FSMC_BTR2_DATAST_0 VÚ P FSMC_BTR2_DATAST_1 UÚ P FSMC_BTR2_DATAST_2 TÚ P FSMC_BTR2_DATAST_3 SÚ P FSMC_BTR2_BUSTURN uÚ P FSMC_BTR2_BUSTURN_0 âÚ P FSMC_BTR2_BUSTURN_1 áÚ P FSMC_BTR2_BUSTURN_2 àÚ P FSMC_BTR2_BUSTURN_3 ßÚ P FSMC_BTR2_CLKDIV íÚ P FSMC_BTR2_CLKDIV_0 ZÚ P FSMC_BTR2_CLKDIV_1 YÚ P FSMC_BTR2_CLKDIV_2 XÚ P FSMC_BTR2_CLKDIV_3 WÚ P FSMC_BTR2_DATLAT ðÚ P FSMC_BTR2_DATLAT_0 ]Ú P FSMC_BTR2_DATLAT_1 \Ú P FSMC_BTR2_DATLAT_2 [Ú P FSMC_BTR2_DATLAT_3 ZÚ P FSMC_BTR2_ACCMOD Ú P FSMC_BTR2_ACCMOD_0 pÚ P FSMC_BTR2_ACCMOD_1 oÚ P FSMC_BTR3_ADDSET ôÚ P FSMC_BTR3_ADDSET_0 aÚ P FSMC_BTR3_ADDSET_1 `Ú P FSMC_BTR3_ADDSET_2 _Ú P FSMC_BTR3_ADDSET_3 ^Ú P FSMC_BTR3_ADDHLD Ú P FSMC_BTR3_ADDHLD_0 uÚ P FSMC_BTR3_ADDHLD_1 tÚ P FSMC_BTR3_ADDHLD_2 sÚ P FSMC_BTR3_ADDHLD_3 rÚ P FSMC_BTR3_DATAST èÚ P FSMC_BTR3_DATAST_0 UÚ P FSMC_BTR3_DATAST_1 TÚ P FSMC_BTR3_DATAST_2 SÚ P FSMC_BTR3_DATAST_3 RÚ P FSMC_BTR3_BUSTURN tÚ P FSMC_BTR3_BUSTURN_0 áÚ P FSMC_BTR3_BUSTURN_1 àÚ P FSMC_BTR3_BUSTURN_2 ßÚ P FSMC_BTR3_BUSTURN_3 ÞÚ P FSMC_BTR3_CLKDIV ìÚ P FSMC_BTR3_CLKDIV_0 YÚ P FSMC_BTR3_CLKDIV_1 XÚ P FSMC_BTR3_CLKDIV_2 WÚ P FSMC_BTR3_CLKDIV_3 VÚ P FSMC_BTR3_DATLAT ïÚ P FSMC_BTR3_DATLAT_0 \Ú P FSMC_BTR3_DATLAT_1 [Ú P FSMC_BTR3_DATLAT_2 ZÚ P FSMC_BTR3_DATLAT_3 YÚ P FSMC_BTR3_ACCMOD Ú P FSMC_BTR3_ACCMOD_0 oÚ P FSMC_BTR3_ACCMOD_1 nÚ P FSMC_BTR4_ADDSET óÚ P FSMC_BTR4_ADDSET_0 `Ú P FSMC_BTR4_ADDSET_1 _Ú P FSMC_BTR4_ADDSET_2 ^Ú P FSMC_BTR4_ADDSET_3 ]Ú P FSMC_BTR4_ADDHLD Ú P FSMC_BTR4_ADDHLD_0 tÚ P FSMC_BTR4_ADDHLD_1 sÚ P FSMC_BTR4_ADDHLD_2 rÚ P FSMC_BTR4_ADDHLD_3 qÚ P FSMC_BTR4_DATAST çÚ P FSMC_BTR4_DATAST_0 TÚ P FSMC_BTR4_DATAST_1 SÚ P FSMC_BTR4_DATAST_2 RÚ P FSMC_BTR4_DATAST_3 QÚ P FSMC_BTR4_BUSTURN sÚ P FSMC_BTR4_BUSTURN_0 àÚ P FSMC_BTR4_BUSTURN_1 ßÚ P FSMC_BTR4_BUSTURN_2 ÞÚ P FSMC_BTR4_BUSTURN_3 ÝÚ P FSMC_BTR4_CLKDIV ëÚ P FSMC_BTR4_CLKDIV_0 XÚ P FSMC_BTR4_CLKDIV_1 WÚ P FSMC_BTR4_CLKDIV_2 VÚ P FSMC_BTR4_CLKDIV_3 UÚ P FSMC_BTR4_DATLAT îÚ P FSMC_BTR4_DATLAT_0 [Ú P FSMC_BTR4_DATLAT_1 ZÚ P FSMC_BTR4_DATLAT_2 YÚ P FSMC_BTR4_DATLAT_3 XÚ P FSMC_BTR4_ACCMOD Ú P FSMC_BTR4_ACCMOD_0 nÚ P FSMC_BTR4_ACCMOD_1 mÚ P FSMC_BWTR1_ADDSET Ú P FSMC_BWTR1_ADDSET_0 |
793 |
Ú P FSMC_BTR1_ADDHLD_0 wÚ P FSMC_BTR1_ADDHLD_1 vÚ P FSMC_BTR1_ADDHLD_2 uÚ P FSMC_BTR1_ADDHLD_3 tÚ P FSMC_BTR1_DATAST êÚ P FSMC_BTR1_DATAST_0 WÚ P FSMC_BTR1_DATAST_1 VÚ P FSMC_BTR1_DATAST_2 UÚ P FSMC_BTR1_DATAST_3 TÚ P FSMC_BTR1_BUSTURN vÚ P FSMC_BTR1_BUSTURN_0 ãÚ P FSMC_BTR1_BUSTURN_1 âÚ P FSMC_BTR1_BUSTURN_2 áÚ P FSMC_BTR1_BUSTURN_3 àÚ P FSMC_BTR1_CLKDIV îÚ P FSMC_BTR1_CLKDIV_0 [Ú P FSMC_BTR1_CLKDIV_1 ZÚ P FSMC_BTR1_CLKDIV_2 YÚ P FSMC_BTR1_CLKDIV_3 XÚ P FSMC_BTR1_DATLAT ñÚ P FSMC_BTR1_DATLAT_0 ^Ú P FSMC_BTR1_DATLAT_1 ]Ú P FSMC_BTR1_DATLAT_2 \Ú P FSMC_BTR1_DATLAT_3 [Ú P FSMC_BTR1_ACCMOD Ú P FSMC_BTR1_ACCMOD_0 qÚ P FSMC_BTR1_ACCMOD_1 pÚ P FSMC_BTR2_ADDSET õÚ P FSMC_BTR2_ADDSET_0 bÚ P FSMC_BTR2_ADDSET_1 aÚ P FSMC_BTR2_ADDSET_2 `Ú P FSMC_BTR2_ADDSET_3 _Ú P FSMC_BTR2_ADDHLD Ú P FSMC_BTR2_ADDHLD_0 vÚ P FSMC_BTR2_ADDHLD_1 uÚ P FSMC_BTR2_ADDHLD_2 tÚ P FSMC_BTR2_ADDHLD_3 sÚ P FSMC_BTR2_DATAST éÚ P FSMC_BTR2_DATAST_0 VÚ P FSMC_BTR2_DATAST_1 UÚ P FSMC_BTR2_DATAST_2 TÚ P FSMC_BTR2_DATAST_3 SÚ P FSMC_BTR2_BUSTURN uÚ P FSMC_BTR2_BUSTURN_0 âÚ P FSMC_BTR2_BUSTURN_1 áÚ P FSMC_BTR2_BUSTURN_2 àÚ P FSMC_BTR2_BUSTURN_3 ßÚ P FSMC_BTR2_CLKDIV íÚ P FSMC_BTR2_CLKDIV_0 ZÚ P FSMC_BTR2_CLKDIV_1 YÚ P FSMC_BTR2_CLKDIV_2 XÚ P FSMC_BTR2_CLKDIV_3 WÚ P FSMC_BTR2_DATLAT ðÚ P FSMC_BTR2_DATLAT_0 ]Ú P FSMC_BTR2_DATLAT_1 \Ú P FSMC_BTR2_DATLAT_2 [Ú P FSMC_BTR2_DATLAT_3 ZÚ P FSMC_BTR2_ACCMOD Ú P FSMC_BTR2_ACCMOD_0 pÚ P FSMC_BTR2_ACCMOD_1 oÚ P FSMC_BTR3_ADDSET ôÚ P FSMC_BTR3_ADDSET_0 aÚ P FSMC_BTR3_ADDSET_1 `Ú P FSMC_BTR3_ADDSET_2 _Ú P FSMC_BTR3_ADDSET_3 ^Ú P FSMC_BTR3_ADDHLD Ú P FSMC_BTR3_ADDHLD_0 uÚ P FSMC_BTR3_ADDHLD_1 tÚ P FSMC_BTR3_ADDHLD_2 sÚ P FSMC_BTR3_ADDHLD_3 rÚ P FSMC_BTR3_DATAST èÚ P FSMC_BTR3_DATAST_0 UÚ P FSMC_BTR3_DATAST_1 TÚ P FSMC_BTR3_DATAST_2 SÚ P FSMC_BTR3_DATAST_3 RÚ P FSMC_BTR3_BUSTURN tÚ P FSMC_BTR3_BUSTURN_0 áÚ P FSMC_BTR3_BUSTURN_1 àÚ P FSMC_BTR3_BUSTURN_2 ßÚ P FSMC_BTR3_BUSTURN_3 ÞÚ P FSMC_BTR3_CLKDIV ìÚ P FSMC_BTR3_CLKDIV_0 YÚ P FSMC_BTR3_CLKDIV_1 XÚ P FSMC_BTR3_CLKDIV_2 WÚ P FSMC_BTR3_CLKDIV_3 VÚ P FSMC_BTR3_DATLAT ïÚ P FSMC_BTR3_DATLAT_0 \Ú P FSMC_BTR3_DATLAT_1 [Ú P FSMC_BTR3_DATLAT_2 ZÚ P FSMC_BTR3_DATLAT_3 YÚ P FSMC_BTR3_ACCMOD Ú P FSMC_BTR3_ACCMOD_0 oÚ P FSMC_BTR3_ACCMOD_1 nÚ P FSMC_BTR4_ADDSET óÚ P FSMC_BTR4_ADDSET_0 `Ú P FSMC_BTR4_ADDSET_1 _Ú P FSMC_BTR4_ADDSET_2 ^Ú P FSMC_BTR4_ADDSET_3 ]Ú P FSMC_BTR4_ADDHLD Ú P FSMC_BTR4_ADDHLD_0 tÚ P FSMC_BTR4_ADDHLD_1 sÚ P FSMC_BTR4_ADDHLD_2 rÚ P FSMC_BTR4_ADDHLD_3 qÚ P FSMC_BTR4_DATAST çÚ P FSMC_BTR4_DATAST_0 TÚ P FSMC_BTR4_DATAST_1 SÚ P FSMC_BTR4_DATAST_2 RÚ P FSMC_BTR4_DATAST_3 QÚ P FSMC_BTR4_BUSTURN sÚ P FSMC_BTR4_BUSTURN_0 àÚ P FSMC_BTR4_BUSTURN_1 ßÚ P FSMC_BTR4_BUSTURN_2 ÞÚ P FSMC_BTR4_BUSTURN_3 ÝÚ P FSMC_BTR4_CLKDIV ëÚ P FSMC_BTR4_CLKDIV_0 XÚ P FSMC_BTR4_CLKDIV_1 WÚ P FSMC_BTR4_CLKDIV_2 VÚ P FSMC_BTR4_CLKDIV_3 UÚ P FSMC_BTR4_DATLAT îÚ P FSMC_BTR4_DATLAT_0 [Ú P FSMC_BTR4_DATLAT_1 ZÚ P FSMC_BTR4_DATLAT_2 YÚ P FSMC_BTR4_DATLAT_3 XÚ P FSMC_BTR4_ACCMOD Ú P FSMC_BTR4_ACCMOD_0 nÚ P FSMC_BTR4_ACCMOD_1 mÚ P FSMC_BWTR1_ADDSET Ú P FSMC_BWTR1_ADDSET_0 |
| 794 |
Ú P FSMC_BWTR1_ADDSET_1 Ú P FSMC_BWTR1_ADDSET_2 Ú P FSMC_BWTR1_ADDSET_3 Ú P FSMC_BWTR1_ADDHLD ±Ú P FSMC_BWTR1_ADDHLD_0 Ú P FSMC_BWTR1_ADDHLD_1 Ú P FSMC_BWTR1_ADDHLD_2 Ú P FSMC_BWTR1_ADDHLD_3 Ú P FSMC_BWTR1_DATAST Ú P FSMC_BWTR1_DATAST_0 þÚ P FSMC_BWTR1_DATAST_1 ýÚ P FSMC_BWTR1_DATAST_2 üÚ P FSMC_BWTR1_DATAST_3 ûÚ P FSMC_BWTR1_CLKDIV Ú P FSMC_BWTR1_CLKDIV_0 Ú P FSMC_BWTR1_CLKDIV_1 Ú P FSMC_BWTR1_CLKDIV_2 Ú P FSMC_BWTR1_CLKDIV_3 ÿÚ P FSMC_BWTR1_DATLAT Ú P FSMC_BWTR1_DATLAT_0 Ú P FSMC_BWTR1_DATLAT_1 Ú P FSMC_BWTR1_DATLAT_2 Ú P FSMC_BWTR1_DATLAT_3 Ú P FSMC_BWTR1_ACCMOD «Ú P FSMC_BWTR1_ACCMOD_0 Ú P FSMC_BWTR1_ACCMOD_1 Ú P FSMC_BWTR2_ADDSET Ú P FSMC_BWTR2_ADDSET_0 Ú P FSMC_BWTR2_ADDSET_1 Ú P FSMC_BWTR2_ADDSET_2 Ú P FSMC_BWTR2_ADDSET_3 Ú P FSMC_BWTR2_ADDHLD °Ú P FSMC_BWTR2_ADDHLD_0 Ú P FSMC_BWTR2_ADDHLD_1 Ú P FSMC_BWTR2_ADDHLD_2 Ú P FSMC_BWTR2_ADDHLD_3 Ú P FSMC_BWTR2_DATAST Ú P FSMC_BWTR2_DATAST_0 ýÚ P FSMC_BWTR2_DATAST_1 üÚ P FSMC_BWTR2_DATAST_2 ûÚ P FSMC_BWTR2_DATAST_3 úÚ P FSMC_BWTR2_CLKDIV Ú P FSMC_BWTR2_CLKDIV_0 Ú P FSMC_BWTR2_CLKDIV_1 Ú P FSMC_BWTR2_CLKDIV_2 ÿÚ P FSMC_BWTR2_CLKDIV_3 þÚ P FSMC_BWTR2_DATLAT Ú P FSMC_BWTR2_DATLAT_0 Ú P FSMC_BWTR2_DATLAT_1 Ú P FSMC_BWTR2_DATLAT_2 Ú P FSMC_BWTR2_DATLAT_3 Ú P FSMC_BWTR2_ACCMOD ªÚ P FSMC_BWTR2_ACCMOD_0 Ú P FSMC_BWTR2_ACCMOD_1 Ú P FSMC_BWTR3_ADDSET Ú P FSMC_BWTR3_ADDSET_0 Ú P FSMC_BWTR3_ADDSET_1 Ú P FSMC_BWTR3_ADDSET_2 Ú P FSMC_BWTR3_ADDSET_3 Ú P FSMC_BWTR3_ADDHLD ¯Ú P FSMC_BWTR3_ADDHLD_0 Ú P FSMC_BWTR3_ADDHLD_1 Ú P FSMC_BWTR3_ADDHLD_2 Ú P FSMC_BWTR3_ADDHLD_3 Ú P FSMC_BWTR3_DATAST Ú P FSMC_BWTR3_DATAST_0 üÚ P FSMC_BWTR3_DATAST_1 ûÚ P FSMC_BWTR3_DATAST_2 úÚ P FSMC_BWTR3_DATAST_3 ùÚ P FSMC_BWTR3_CLKDIV Ú P FSMC_BWTR3_CLKDIV_0 Ú P FSMC_BWTR3_CLKDIV_1 ÿÚ P FSMC_BWTR3_CLKDIV_2 þÚ P FSMC_BWTR3_CLKDIV_3 ýÚ P FSMC_BWTR3_DATLAT Ú P FSMC_BWTR3_DATLAT_0 Ú P FSMC_BWTR3_DATLAT_1 Ú P FSMC_BWTR3_DATLAT_2 Ú P FSMC_BWTR3_DATLAT_3 Ú P FSMC_BWTR3_ACCMOD ©Ú P FSMC_BWTR3_ACCMOD_0 Ú P FSMC_BWTR3_ACCMOD_1 Ú P FSMC_BWTR4_ADDSET Ú P FSMC_BWTR4_ADDSET_0 Ú P FSMC_BWTR4_ADDSET_1 Ú P FSMC_BWTR4_ADDSET_2 Ú P FSMC_BWTR4_ADDSET_3 Ú P FSMC_BWTR4_ADDHLD ®Ú P FSMC_BWTR4_ADDHLD_0 Ú P FSMC_BWTR4_ADDHLD_1 Ú P FSMC_BWTR4_ADDHLD_2 Ú P FSMC_BWTR4_ADDHLD_3 Ú P FSMC_BWTR4_DATAST Ú P FSMC_BWTR4_DATAST_0 ûÚ P FSMC_BWTR4_DATAST_1 úÚ P FSMC_BWTR4_DATAST_2 ùÚ P FSMC_BWTR4_DATAST_3 øÚ P FSMC_BWTR4_CLKDIV Ú P FSMC_BWTR4_CLKDIV_0 ÿÚ P FSMC_BWTR4_CLKDIV_1 þÚ P FSMC_BWTR4_CLKDIV_2 ýÚ P FSMC_BWTR4_CLKDIV_3 üÚ P FSMC_BWTR4_DATLAT Ú P FSMC_BWTR4_DATLAT_0 Ú P FSMC_BWTR4_DATLAT_1 Ú P FSMC_BWTR4_DATLAT_2 Ú P FSMC_BWTR4_DATLAT_3 ÿÚ P FSMC_BWTR4_ACCMOD ¨Ú P FSMC_BWTR4_ACCMOD_0 Ú P FSMC_BWTR4_ACCMOD_1 Ú P GPIO_MODER_MODER0 Ú P GPIO_MODER_MODER0_0 Ú P GPIO_MODER_MODER0_1 |
794 |
Ú P FSMC_BWTR1_ADDSET_1 Ú P FSMC_BWTR1_ADDSET_2 Ú P FSMC_BWTR1_ADDSET_3 Ú P FSMC_BWTR1_ADDHLD ±Ú P FSMC_BWTR1_ADDHLD_0 Ú P FSMC_BWTR1_ADDHLD_1 Ú P FSMC_BWTR1_ADDHLD_2 Ú P FSMC_BWTR1_ADDHLD_3 Ú P FSMC_BWTR1_DATAST Ú P FSMC_BWTR1_DATAST_0 þÚ P FSMC_BWTR1_DATAST_1 ýÚ P FSMC_BWTR1_DATAST_2 üÚ P FSMC_BWTR1_DATAST_3 ûÚ P FSMC_BWTR1_CLKDIV Ú P FSMC_BWTR1_CLKDIV_0 Ú P FSMC_BWTR1_CLKDIV_1 Ú P FSMC_BWTR1_CLKDIV_2 Ú P FSMC_BWTR1_CLKDIV_3 ÿÚ P FSMC_BWTR1_DATLAT Ú P FSMC_BWTR1_DATLAT_0 Ú P FSMC_BWTR1_DATLAT_1 Ú P FSMC_BWTR1_DATLAT_2 Ú P FSMC_BWTR1_DATLAT_3 Ú P FSMC_BWTR1_ACCMOD «Ú P FSMC_BWTR1_ACCMOD_0 Ú P FSMC_BWTR1_ACCMOD_1 Ú P FSMC_BWTR2_ADDSET Ú P FSMC_BWTR2_ADDSET_0 Ú P FSMC_BWTR2_ADDSET_1 Ú P FSMC_BWTR2_ADDSET_2 Ú P FSMC_BWTR2_ADDSET_3 Ú P FSMC_BWTR2_ADDHLD °Ú P FSMC_BWTR2_ADDHLD_0 Ú P FSMC_BWTR2_ADDHLD_1 Ú P FSMC_BWTR2_ADDHLD_2 Ú P FSMC_BWTR2_ADDHLD_3 Ú P FSMC_BWTR2_DATAST Ú P FSMC_BWTR2_DATAST_0 ýÚ P FSMC_BWTR2_DATAST_1 üÚ P FSMC_BWTR2_DATAST_2 ûÚ P FSMC_BWTR2_DATAST_3 úÚ P FSMC_BWTR2_CLKDIV Ú P FSMC_BWTR2_CLKDIV_0 Ú P FSMC_BWTR2_CLKDIV_1 Ú P FSMC_BWTR2_CLKDIV_2 ÿÚ P FSMC_BWTR2_CLKDIV_3 þÚ P FSMC_BWTR2_DATLAT Ú P FSMC_BWTR2_DATLAT_0 Ú P FSMC_BWTR2_DATLAT_1 Ú P FSMC_BWTR2_DATLAT_2 Ú P FSMC_BWTR2_DATLAT_3 Ú P FSMC_BWTR2_ACCMOD ªÚ P FSMC_BWTR2_ACCMOD_0 Ú P FSMC_BWTR2_ACCMOD_1 Ú P FSMC_BWTR3_ADDSET Ú P FSMC_BWTR3_ADDSET_0 Ú P FSMC_BWTR3_ADDSET_1 Ú P FSMC_BWTR3_ADDSET_2 Ú P FSMC_BWTR3_ADDSET_3 Ú P FSMC_BWTR3_ADDHLD ¯Ú P FSMC_BWTR3_ADDHLD_0 Ú P FSMC_BWTR3_ADDHLD_1 Ú P FSMC_BWTR3_ADDHLD_2 Ú P FSMC_BWTR3_ADDHLD_3 Ú P FSMC_BWTR3_DATAST Ú P FSMC_BWTR3_DATAST_0 üÚ P FSMC_BWTR3_DATAST_1 ûÚ P FSMC_BWTR3_DATAST_2 úÚ P FSMC_BWTR3_DATAST_3 ùÚ P FSMC_BWTR3_CLKDIV Ú P FSMC_BWTR3_CLKDIV_0 Ú P FSMC_BWTR3_CLKDIV_1 ÿÚ P FSMC_BWTR3_CLKDIV_2 þÚ P FSMC_BWTR3_CLKDIV_3 ýÚ P FSMC_BWTR3_DATLAT Ú P FSMC_BWTR3_DATLAT_0 Ú P FSMC_BWTR3_DATLAT_1 Ú P FSMC_BWTR3_DATLAT_2 Ú P FSMC_BWTR3_DATLAT_3 Ú P FSMC_BWTR3_ACCMOD ©Ú P FSMC_BWTR3_ACCMOD_0 Ú P FSMC_BWTR3_ACCMOD_1 Ú P FSMC_BWTR4_ADDSET Ú P FSMC_BWTR4_ADDSET_0 Ú P FSMC_BWTR4_ADDSET_1 Ú P FSMC_BWTR4_ADDSET_2 Ú P FSMC_BWTR4_ADDSET_3 Ú P FSMC_BWTR4_ADDHLD ®Ú P FSMC_BWTR4_ADDHLD_0 Ú P FSMC_BWTR4_ADDHLD_1 Ú P FSMC_BWTR4_ADDHLD_2 Ú P FSMC_BWTR4_ADDHLD_3 Ú P FSMC_BWTR4_DATAST Ú P FSMC_BWTR4_DATAST_0 ûÚ P FSMC_BWTR4_DATAST_1 úÚ P FSMC_BWTR4_DATAST_2 ùÚ P FSMC_BWTR4_DATAST_3 øÚ P FSMC_BWTR4_CLKDIV Ú P FSMC_BWTR4_CLKDIV_0 ÿÚ P FSMC_BWTR4_CLKDIV_1 þÚ P FSMC_BWTR4_CLKDIV_2 ýÚ P FSMC_BWTR4_CLKDIV_3 üÚ P FSMC_BWTR4_DATLAT Ú P FSMC_BWTR4_DATLAT_0 Ú P FSMC_BWTR4_DATLAT_1 Ú P FSMC_BWTR4_DATLAT_2 Ú P FSMC_BWTR4_DATLAT_3 ÿÚ P FSMC_BWTR4_ACCMOD ¨Ú P FSMC_BWTR4_ACCMOD_0 Ú P FSMC_BWTR4_ACCMOD_1 Ú P GPIO_MODER_MODER0 Ú P GPIO_MODER_MODER0_0 Ú P GPIO_MODER_MODER0_1 |
| 795 |
Ú P GPIO_MODER_MODER1 Ú P GPIO_MODER_MODER1_0 |
795 |
Ú P GPIO_MODER_MODER1 Ú P GPIO_MODER_MODER1_0 |
| 796 |
Ú P GPIO_MODER_MODER1_1 Ú P GPIO_MODER_MODER2 Ú P GPIO_MODER_MODER2_0 Ú P GPIO_MODER_MODER2_1 Ú P GPIO_MODER_MODER3 Ú P GPIO_MODER_MODER3_0 Ú P GPIO_MODER_MODER3_1 Ú P GPIO_MODER_MODER4 Ú P GPIO_MODER_MODER4_0 Ú P GPIO_MODER_MODER4_1 Ú P GPIO_MODER_MODER5 Ú P GPIO_MODER_MODER5_0 Ú P GPIO_MODER_MODER5_1 Ú P GPIO_MODER_MODER6 Ú P GPIO_MODER_MODER6_0 Ú P GPIO_MODER_MODER6_1 Ú P GPIO_MODER_MODER7 Ú P GPIO_MODER_MODER7_0 Ú P GPIO_MODER_MODER7_1 Ú P GPIO_MODER_MODER8 Ú P GPIO_MODER_MODER8_0 Ú P GPIO_MODER_MODER8_1 Ú P GPIO_MODER_MODER9 Ú P GPIO_MODER_MODER9_0 Ú P GPIO_MODER_MODER9_1 Ú P GPIO_MODER_MODER10 kÚ P GPIO_MODER_MODER10_0 ØÚ P GPIO_MODER_MODER10_1 ×Ú P GPIO_MODER_MODER11 jÚ P GPIO_MODER_MODER11_0 ×Ú P GPIO_MODER_MODER11_1 ÖÚ P GPIO_MODER_MODER12 iÚ P GPIO_MODER_MODER12_0 ÖÚ P GPIO_MODER_MODER12_1 ÕÚ P GPIO_MODER_MODER13 hÚ P GPIO_MODER_MODER13_0 ÕÚ P GPIO_MODER_MODER13_1 ÔÚ P GPIO_MODER_MODER14 gÚ P GPIO_MODER_MODER14_0 ÔÚ P GPIO_MODER_MODER14_1 ÓÚ P GPIO_MODER_MODER15 fÚ P GPIO_MODER_MODER15_0 ÓÚ P GPIO_MODER_MODER15_1 ÒÚ P GPIO_OTYPER_OT_0 ©Ú P GPIO_OTYPER_OT_1 ¨Ú P GPIO_OTYPER_OT_2 §Ú P GPIO_OTYPER_OT_3 ¦Ú P GPIO_OTYPER_OT_4 ¥Ú P GPIO_OTYPER_OT_5 ¤Ú P GPIO_OTYPER_OT_6 £Ú P GPIO_OTYPER_OT_7 ¢Ú P GPIO_OTYPER_OT_8 ¡Ú P GPIO_OTYPER_OT_9 Ú P GPIO_OTYPER_OT_10 vÚ P GPIO_OTYPER_OT_11 uÚ P GPIO_OTYPER_OT_12 tÚ P GPIO_OTYPER_OT_13 sÚ P GPIO_OTYPER_OT_14 rÚ P GPIO_OTYPER_OT_15 qÚ P GPIO_OSPEEDER_OSPEEDR0 Ú! P GPIO_OSPEEDER_OSPEEDR0_0 Ú! P GPIO_OSPEEDER_OSPEEDR0_1
Ú P GPIO_OSPEEDER_OSPEEDR1 Ú! P GPIO_OSPEEDER_OSPEEDR1_0
Ú! P GPIO_OSPEEDER_OSPEEDR1_1 Ú P GPIO_OSPEEDER_OSPEEDR2 Ú! P GPIO_OSPEEDER_OSPEEDR2_0 Ú! P GPIO_OSPEEDER_OSPEEDR2_1 Ú P GPIO_OSPEEDER_OSPEEDR3 Ú! P GPIO_OSPEEDER_OSPEEDR3_0 Ú! P GPIO_OSPEEDER_OSPEEDR3_1 Ú P GPIO_OSPEEDER_OSPEEDR4 Ú! P GPIO_OSPEEDER_OSPEEDR4_0 Ú! P GPIO_OSPEEDER_OSPEEDR4_1 Ú P GPIO_OSPEEDER_OSPEEDR5 Ú! P GPIO_OSPEEDER_OSPEEDR5_0 Ú! P GPIO_OSPEEDER_OSPEEDR5_1 Ú P GPIO_OSPEEDER_OSPEEDR6 Ú! P GPIO_OSPEEDER_OSPEEDR6_0 Ú! P GPIO_OSPEEDER_OSPEEDR6_1 Ú P GPIO_OSPEEDER_OSPEEDR7 Ú! P GPIO_OSPEEDER_OSPEEDR7_0 Ú! P GPIO_OSPEEDER_OSPEEDR7_1 ~Ú P GPIO_OSPEEDER_OSPEEDR8 Ú! P GPIO_OSPEEDER_OSPEEDR8_0 ~Ú! P GPIO_OSPEEDER_OSPEEDR8_1 }Ú P GPIO_OSPEEDER_OSPEEDR9 Ú! P GPIO_OSPEEDER_OSPEEDR9_0 }Ú! P GPIO_OSPEEDER_OSPEEDR9_1 |Ú P GPIO_OSPEEDER_OSPEEDR10 æÚ" P GPIO_OSPEEDER_OSPEEDR10_0 SÚ" P GPIO_OSPEEDER_OSPEEDR10_1 RÚ P GPIO_OSPEEDER_OSPEEDR11 åÚ" P GPIO_OSPEEDER_OSPEEDR11_0 RÚ" P GPIO_OSPEEDER_OSPEEDR11_1 QÚ P GPIO_OSPEEDER_OSPEEDR12 äÚ" P GPIO_OSPEEDER_OSPEEDR12_0 QÚ" P GPIO_OSPEEDER_OSPEEDR12_1 PÚ P GPIO_OSPEEDER_OSPEEDR13 ãÚ" P GPIO_OSPEEDER_OSPEEDR13_0 PÚ" P GPIO_OSPEEDER_OSPEEDR13_1 OÚ P GPIO_OSPEEDER_OSPEEDR14 âÚ" P GPIO_OSPEEDER_OSPEEDR14_0 OÚ" P GPIO_OSPEEDER_OSPEEDR14_1 NÚ P GPIO_OSPEEDER_OSPEEDR15 áÚ" P GPIO_OSPEEDER_OSPEEDR15_0 NÚ" P GPIO_OSPEEDER_OSPEEDR15_1 MÚ P GPIO_PUPDR_PUPDR0 vÚ P GPIO_PUPDR_PUPDR0_0 ãÚ P GPIO_PUPDR_PUPDR0_1 âÚ P GPIO_PUPDR_PUPDR1 uÚ P GPIO_PUPDR_PUPDR1_0 âÚ P GPIO_PUPDR_PUPDR1_1 áÚ P GPIO_PUPDR_PUPDR2 tÚ P GPIO_PUPDR_PUPDR2_0 áÚ P GPIO_PUPDR_PUPDR2_1 àÚ P GPIO_PUPDR_PUPDR3 sÚ P GPIO_PUPDR_PUPDR3_0 àÚ P GPIO_PUPDR_PUPDR3_1 ßÚ P GPIO_PUPDR_PUPDR4 rÚ P GPIO_PUPDR_PUPDR4_0 ßÚ P GPIO_PUPDR_PUPDR4_1 ÞÚ P GPIO_PUPDR_PUPDR5 qÚ P GPIO_PUPDR_PUPDR5_0 ÞÚ P GPIO_PUPDR_PUPDR5_1 ÝÚ P GPIO_PUPDR_PUPDR6 pÚ P GPIO_PUPDR_PUPDR6_0 ÝÚ P GPIO_PUPDR_PUPDR6_1 ÜÚ P GPIO_PUPDR_PUPDR7 oÚ P GPIO_PUPDR_PUPDR7_0 ÜÚ P GPIO_PUPDR_PUPDR7_1 ÛÚ P GPIO_PUPDR_PUPDR8 nÚ P GPIO_PUPDR_PUPDR8_0 ÛÚ P GPIO_PUPDR_PUPDR8_1 ÚÚ P GPIO_PUPDR_PUPDR9 mÚ P GPIO_PUPDR_PUPDR9_0 ÚÚ P GPIO_PUPDR_PUPDR9_1 ÙÚ P GPIO_PUPDR_PUPDR10 CÚ P GPIO_PUPDR_PUPDR10_0 °Ú P GPIO_PUPDR_PUPDR10_1 ¯Ú P GPIO_PUPDR_PUPDR11 BÚ P GPIO_PUPDR_PUPDR11_0 ¯Ú P GPIO_PUPDR_PUPDR11_1 ®Ú P GPIO_PUPDR_PUPDR12 AÚ P GPIO_PUPDR_PUPDR12_0 ®Ú P GPIO_PUPDR_PUPDR12_1 Ú P GPIO_PUPDR_PUPDR13 @Ú P GPIO_PUPDR_PUPDR13_0 Ú P GPIO_PUPDR_PUPDR13_1 ¬Ú P GPIO_PUPDR_PUPDR14 ?Ú P GPIO_PUPDR_PUPDR14_0 ¬Ú P GPIO_PUPDR_PUPDR14_1 «Ú P GPIO_PUPDR_PUPDR15 >Ú P GPIO_PUPDR_PUPDR15_0 «Ú P GPIO_PUPDR_PUPDR15_1 ªÚ P GPIO_IDR_IDR_0 uÚ P GPIO_IDR_IDR_1 tÚ P GPIO_IDR_IDR_2 sÚ P GPIO_IDR_IDR_3 rÚ P GPIO_IDR_IDR_4 qÚ P GPIO_IDR_IDR_5 pÚ P GPIO_IDR_IDR_6 oÚ P GPIO_IDR_IDR_7 nÚ P GPIO_IDR_IDR_8 mÚ P GPIO_IDR_IDR_9 lÚ P GPIO_IDR_IDR_10 BÚ P GPIO_IDR_IDR_11 AÚ P GPIO_IDR_IDR_12 @Ú P GPIO_IDR_IDR_13 ?Ú P GPIO_IDR_IDR_14 >Ú P GPIO_IDR_IDR_15 =Ú P GPIO_OTYPER_IDR_0 kÚ P GPIO_OTYPER_IDR_1 jÚ P GPIO_OTYPER_IDR_2 iÚ P GPIO_OTYPER_IDR_3 hÚ P GPIO_OTYPER_IDR_4 gÚ P GPIO_OTYPER_IDR_5 fÚ P GPIO_OTYPER_IDR_6 eÚ P GPIO_OTYPER_IDR_7 dÚ P GPIO_OTYPER_IDR_8 cÚ P GPIO_OTYPER_IDR_9 bÚ P GPIO_OTYPER_IDR_10 8Ú P GPIO_OTYPER_IDR_11 7Ú P GPIO_OTYPER_IDR_12 6Ú P GPIO_OTYPER_IDR_13 5Ú P GPIO_OTYPER_IDR_14 4Ú P GPIO_OTYPER_IDR_15 3Ú P GPIO_ODR_ODR_0 iÚ P GPIO_ODR_ODR_1 hÚ P GPIO_ODR_ODR_2 gÚ P GPIO_ODR_ODR_3 fÚ P GPIO_ODR_ODR_4 eÚ P GPIO_ODR_ODR_5 dÚ P GPIO_ODR_ODR_6 cÚ P GPIO_ODR_ODR_7 bÚ P GPIO_ODR_ODR_8 aÚ P GPIO_ODR_ODR_9 `Ú P GPIO_ODR_ODR_10 6Ú P GPIO_ODR_ODR_11 5Ú P GPIO_ODR_ODR_12 4Ú P GPIO_ODR_ODR_13 3Ú P GPIO_ODR_ODR_14 2Ú P GPIO_ODR_ODR_15 1Ú P GPIO_OTYPER_ODR_0 eÚ P GPIO_OTYPER_ODR_1 dÚ P GPIO_OTYPER_ODR_2 cÚ P GPIO_OTYPER_ODR_3 bÚ P GPIO_OTYPER_ODR_4 aÚ P GPIO_OTYPER_ODR_5 `Ú P GPIO_OTYPER_ODR_6 _Ú P GPIO_OTYPER_ODR_7 ^Ú P GPIO_OTYPER_ODR_8 ]Ú P GPIO_OTYPER_ODR_9 \Ú P GPIO_OTYPER_ODR_10 2Ú P GPIO_OTYPER_ODR_11 1Ú P GPIO_OTYPER_ODR_12 0Ú P GPIO_OTYPER_ODR_13 /Ú P GPIO_OTYPER_ODR_14 .Ú P GPIO_OTYPER_ODR_15 -Ú P GPIO_BSRR_BS_0 eÚ P GPIO_BSRR_BS_1 dÚ P GPIO_BSRR_BS_2 cÚ P GPIO_BSRR_BS_3 bÚ P GPIO_BSRR_BS_4 aÚ P GPIO_BSRR_BS_5 `Ú P GPIO_BSRR_BS_6 _Ú P GPIO_BSRR_BS_7 ^Ú P GPIO_BSRR_BS_8 ]Ú P GPIO_BSRR_BS_9 \Ú P GPIO_BSRR_BS_10 2Ú P GPIO_BSRR_BS_11 1Ú P GPIO_BSRR_BS_12 0Ú P GPIO_BSRR_BS_13 /Ú P GPIO_BSRR_BS_14 .Ú P GPIO_BSRR_BS_15 -Ú P GPIO_BSRR_BR_0 fÚ P GPIO_BSRR_BR_1 eÚ P GPIO_BSRR_BR_2 dÚ P GPIO_BSRR_BR_3 cÚ P GPIO_BSRR_BR_4 bÚ P GPIO_BSRR_BR_5 aÚ P GPIO_BSRR_BR_6 `Ú P GPIO_BSRR_BR_7 _Ú P GPIO_BSRR_BR_8 ^Ú P GPIO_BSRR_BR_9 ]Ú P GPIO_BSRR_BR_10 3Ú P GPIO_BSRR_BR_11 2Ú P GPIO_BSRR_BR_12 1Ú P GPIO_BSRR_BR_13 0Ú P GPIO_BSRR_BR_14 /Ú P GPIO_BSRR_BR_15 .Ú P GPIO_LCKR_LCK0 Ú P GPIO_LCKR_LCK1 Ú P GPIO_LCKR_LCK2 Ú P GPIO_LCKR_LCK3 Ú P GPIO_LCKR_LCK4 Ú P GPIO_LCKR_LCK5 Ú P GPIO_LCKR_LCK6 Ú P GPIO_LCKR_LCK7
Ú P GPIO_LCKR_LCK8 Ú P GPIO_LCKR_LCK9 Ú P GPIO_LCKR_LCK10 YÚ P GPIO_LCKR_LCK11 XÚ P GPIO_LCKR_LCK12 WÚ P GPIO_LCKR_LCK13 VÚ P GPIO_LCKR_LCK14 UÚ P GPIO_LCKR_LCK15 TÚ P GPIO_LCKR_LCKK qÚ P GPIO_AFRL_AFRL0 FÚ P GPIO_AFRL_AFRL1 EÚ P GPIO_AFRL_AFRL2 DÚ P GPIO_AFRL_AFRL3 CÚ P GPIO_AFRL_AFRL4 BÚ P GPIO_AFRL_AFRL5 AÚ P GPIO_AFRL_AFRL6 @Ú P GPIO_AFRL_AFRL7 ?Ú P GPIO_AFRH_AFRH8 FÚ P GPIO_AFRH_AFRH9 EÚ P GPIO_AFRH_AFRH10 Ú P GPIO_AFRH_AFRH11 Ú P GPIO_AFRH_AFRH12 Ú P GPIO_AFRH_AFRH13 Ú P GPIO_AFRH_AFRH14 Ú P GPIO_AFRH_AFRH15 Ú P I2C_CR1_PE àÚ P I2C_CR1_SMBUS åÚ P I2C_CR1_SMBTYPE GÚ P I2C_CR1_ENARP ùÚ P I2C_CR1_ENPEC Ú P
I2C_CR1_ENGC TÚ P I2C_CR1_NOSTRETCH Ú P I2C_CR1_START áÚ P
I2C_CR1_STOP +Ú P I2C_CR1_ACK ¤Ú P I2C_CR1_POS Ú P I2C_CR1_PEC Ú P I2C_CR1_ALERT ÷Ú P I2C_CR1_SWRST ÌÚ P
I2C_CR2_FREQ BÚ P I2C_CR2_FREQ_0 ¯Ú P I2C_CR2_FREQ_1 ®Ú P I2C_CR2_FREQ_2 Ú P I2C_CR2_FREQ_3 ¬Ú P I2C_CR2_FREQ_4 «Ú P I2C_CR2_FREQ_5 ªÚ P I2C_CR2_ITERREN QÚ P I2C_CR2_ITEVTEN KÚ P I2C_CR2_ITBUFEN ]Ú P I2C_CR2_DMAEN Ú P
I2C_CR2_LAST <Ú P I2C_OAR1_ADD1_7 Ú P I2C_OAR1_ADD8_9
Ú P I2C_OAR1_ADD0 )Ú P I2C_OAR1_ADD1 (Ú P I2C_OAR1_ADD2 'Ú P I2C_OAR1_ADD3 &Ú P I2C_OAR1_ADD4 %Ú P I2C_OAR1_ADD5 $Ú P I2C_OAR1_ADD6 #Ú P I2C_OAR1_ADD7 "Ú P I2C_OAR1_ADD8 !Ú P I2C_OAR1_ADD9 Ú P I2C_OAR1_ADDMODE .Ú P I2C_OAR2_ENDUAL dÚ P I2C_OAR2_ADD2 &Ú P |
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Ú P GPIO_MODER_MODER1_1 Ú P GPIO_MODER_MODER2 Ú P GPIO_MODER_MODER2_0 Ú P GPIO_MODER_MODER2_1 Ú P GPIO_MODER_MODER3 Ú P GPIO_MODER_MODER3_0 Ú P GPIO_MODER_MODER3_1 Ú P GPIO_MODER_MODER4 Ú P GPIO_MODER_MODER4_0 Ú P GPIO_MODER_MODER4_1 Ú P GPIO_MODER_MODER5 Ú P GPIO_MODER_MODER5_0 Ú P GPIO_MODER_MODER5_1 Ú P GPIO_MODER_MODER6 Ú P GPIO_MODER_MODER6_0 Ú P GPIO_MODER_MODER6_1 Ú P GPIO_MODER_MODER7 Ú P GPIO_MODER_MODER7_0 Ú P GPIO_MODER_MODER7_1 Ú P GPIO_MODER_MODER8 Ú P GPIO_MODER_MODER8_0 Ú P GPIO_MODER_MODER8_1 Ú P GPIO_MODER_MODER9 Ú P GPIO_MODER_MODER9_0 Ú P GPIO_MODER_MODER9_1 Ú P GPIO_MODER_MODER10 kÚ P GPIO_MODER_MODER10_0 ØÚ P GPIO_MODER_MODER10_1 ×Ú P GPIO_MODER_MODER11 jÚ P GPIO_MODER_MODER11_0 ×Ú P GPIO_MODER_MODER11_1 ÖÚ P GPIO_MODER_MODER12 iÚ P GPIO_MODER_MODER12_0 ÖÚ P GPIO_MODER_MODER12_1 ÕÚ P GPIO_MODER_MODER13 hÚ P GPIO_MODER_MODER13_0 ÕÚ P GPIO_MODER_MODER13_1 ÔÚ P GPIO_MODER_MODER14 gÚ P GPIO_MODER_MODER14_0 ÔÚ P GPIO_MODER_MODER14_1 ÓÚ P GPIO_MODER_MODER15 fÚ P GPIO_MODER_MODER15_0 ÓÚ P GPIO_MODER_MODER15_1 ÒÚ P GPIO_OTYPER_OT_0 ©Ú P GPIO_OTYPER_OT_1 ¨Ú P GPIO_OTYPER_OT_2 §Ú P GPIO_OTYPER_OT_3 ¦Ú P GPIO_OTYPER_OT_4 ¥Ú P GPIO_OTYPER_OT_5 ¤Ú P GPIO_OTYPER_OT_6 £Ú P GPIO_OTYPER_OT_7 ¢Ú P GPIO_OTYPER_OT_8 ¡Ú P GPIO_OTYPER_OT_9 Ú P GPIO_OTYPER_OT_10 vÚ P GPIO_OTYPER_OT_11 uÚ P GPIO_OTYPER_OT_12 tÚ P GPIO_OTYPER_OT_13 sÚ P GPIO_OTYPER_OT_14 rÚ P GPIO_OTYPER_OT_15 qÚ P GPIO_OSPEEDER_OSPEEDR0 Ú! P GPIO_OSPEEDER_OSPEEDR0_0 Ú! P GPIO_OSPEEDER_OSPEEDR0_1
Ú P GPIO_OSPEEDER_OSPEEDR1 Ú! P GPIO_OSPEEDER_OSPEEDR1_0
Ú! P GPIO_OSPEEDER_OSPEEDR1_1 Ú P GPIO_OSPEEDER_OSPEEDR2 Ú! P GPIO_OSPEEDER_OSPEEDR2_0 Ú! P GPIO_OSPEEDER_OSPEEDR2_1 Ú P GPIO_OSPEEDER_OSPEEDR3 Ú! P GPIO_OSPEEDER_OSPEEDR3_0 Ú! P GPIO_OSPEEDER_OSPEEDR3_1 Ú P GPIO_OSPEEDER_OSPEEDR4 Ú! P GPIO_OSPEEDER_OSPEEDR4_0 Ú! P GPIO_OSPEEDER_OSPEEDR4_1 Ú P GPIO_OSPEEDER_OSPEEDR5 Ú! P GPIO_OSPEEDER_OSPEEDR5_0 Ú! P GPIO_OSPEEDER_OSPEEDR5_1 Ú P GPIO_OSPEEDER_OSPEEDR6 Ú! P GPIO_OSPEEDER_OSPEEDR6_0 Ú! P GPIO_OSPEEDER_OSPEEDR6_1 Ú P GPIO_OSPEEDER_OSPEEDR7 Ú! P GPIO_OSPEEDER_OSPEEDR7_0 Ú! P GPIO_OSPEEDER_OSPEEDR7_1 ~Ú P GPIO_OSPEEDER_OSPEEDR8 Ú! P GPIO_OSPEEDER_OSPEEDR8_0 ~Ú! P GPIO_OSPEEDER_OSPEEDR8_1 }Ú P GPIO_OSPEEDER_OSPEEDR9 Ú! P GPIO_OSPEEDER_OSPEEDR9_0 }Ú! P GPIO_OSPEEDER_OSPEEDR9_1 |Ú P GPIO_OSPEEDER_OSPEEDR10 æÚ" P GPIO_OSPEEDER_OSPEEDR10_0 SÚ" P GPIO_OSPEEDER_OSPEEDR10_1 RÚ P GPIO_OSPEEDER_OSPEEDR11 åÚ" P GPIO_OSPEEDER_OSPEEDR11_0 RÚ" P GPIO_OSPEEDER_OSPEEDR11_1 QÚ P GPIO_OSPEEDER_OSPEEDR12 äÚ" P GPIO_OSPEEDER_OSPEEDR12_0 QÚ" P GPIO_OSPEEDER_OSPEEDR12_1 PÚ P GPIO_OSPEEDER_OSPEEDR13 ãÚ" P GPIO_OSPEEDER_OSPEEDR13_0 PÚ" P GPIO_OSPEEDER_OSPEEDR13_1 OÚ P GPIO_OSPEEDER_OSPEEDR14 âÚ" P GPIO_OSPEEDER_OSPEEDR14_0 OÚ" P GPIO_OSPEEDER_OSPEEDR14_1 NÚ P GPIO_OSPEEDER_OSPEEDR15 áÚ" P GPIO_OSPEEDER_OSPEEDR15_0 NÚ" P GPIO_OSPEEDER_OSPEEDR15_1 MÚ P GPIO_PUPDR_PUPDR0 vÚ P GPIO_PUPDR_PUPDR0_0 ãÚ P GPIO_PUPDR_PUPDR0_1 âÚ P GPIO_PUPDR_PUPDR1 uÚ P GPIO_PUPDR_PUPDR1_0 âÚ P GPIO_PUPDR_PUPDR1_1 áÚ P GPIO_PUPDR_PUPDR2 tÚ P GPIO_PUPDR_PUPDR2_0 áÚ P GPIO_PUPDR_PUPDR2_1 àÚ P GPIO_PUPDR_PUPDR3 sÚ P GPIO_PUPDR_PUPDR3_0 àÚ P GPIO_PUPDR_PUPDR3_1 ßÚ P GPIO_PUPDR_PUPDR4 rÚ P GPIO_PUPDR_PUPDR4_0 ßÚ P GPIO_PUPDR_PUPDR4_1 ÞÚ P GPIO_PUPDR_PUPDR5 qÚ P GPIO_PUPDR_PUPDR5_0 ÞÚ P GPIO_PUPDR_PUPDR5_1 ÝÚ P GPIO_PUPDR_PUPDR6 pÚ P GPIO_PUPDR_PUPDR6_0 ÝÚ P GPIO_PUPDR_PUPDR6_1 ÜÚ P GPIO_PUPDR_PUPDR7 oÚ P GPIO_PUPDR_PUPDR7_0 ÜÚ P GPIO_PUPDR_PUPDR7_1 ÛÚ P GPIO_PUPDR_PUPDR8 nÚ P GPIO_PUPDR_PUPDR8_0 ÛÚ P GPIO_PUPDR_PUPDR8_1 ÚÚ P GPIO_PUPDR_PUPDR9 mÚ P GPIO_PUPDR_PUPDR9_0 ÚÚ P GPIO_PUPDR_PUPDR9_1 ÙÚ P GPIO_PUPDR_PUPDR10 CÚ P GPIO_PUPDR_PUPDR10_0 °Ú P GPIO_PUPDR_PUPDR10_1 ¯Ú P GPIO_PUPDR_PUPDR11 BÚ P GPIO_PUPDR_PUPDR11_0 ¯Ú P GPIO_PUPDR_PUPDR11_1 ®Ú P GPIO_PUPDR_PUPDR12 AÚ P GPIO_PUPDR_PUPDR12_0 ®Ú P GPIO_PUPDR_PUPDR12_1 Ú P GPIO_PUPDR_PUPDR13 @Ú P GPIO_PUPDR_PUPDR13_0 Ú P GPIO_PUPDR_PUPDR13_1 ¬Ú P GPIO_PUPDR_PUPDR14 ?Ú P GPIO_PUPDR_PUPDR14_0 ¬Ú P GPIO_PUPDR_PUPDR14_1 «Ú P GPIO_PUPDR_PUPDR15 >Ú P GPIO_PUPDR_PUPDR15_0 «Ú P GPIO_PUPDR_PUPDR15_1 ªÚ P GPIO_IDR_IDR_0 uÚ P GPIO_IDR_IDR_1 tÚ P GPIO_IDR_IDR_2 sÚ P GPIO_IDR_IDR_3 rÚ P GPIO_IDR_IDR_4 qÚ P GPIO_IDR_IDR_5 pÚ P GPIO_IDR_IDR_6 oÚ P GPIO_IDR_IDR_7 nÚ P GPIO_IDR_IDR_8 mÚ P GPIO_IDR_IDR_9 lÚ P GPIO_IDR_IDR_10 BÚ P GPIO_IDR_IDR_11 AÚ P GPIO_IDR_IDR_12 @Ú P GPIO_IDR_IDR_13 ?Ú P GPIO_IDR_IDR_14 >Ú P GPIO_IDR_IDR_15 =Ú P GPIO_OTYPER_IDR_0 kÚ P GPIO_OTYPER_IDR_1 jÚ P GPIO_OTYPER_IDR_2 iÚ P GPIO_OTYPER_IDR_3 hÚ P GPIO_OTYPER_IDR_4 gÚ P GPIO_OTYPER_IDR_5 fÚ P GPIO_OTYPER_IDR_6 eÚ P GPIO_OTYPER_IDR_7 dÚ P GPIO_OTYPER_IDR_8 cÚ P GPIO_OTYPER_IDR_9 bÚ P GPIO_OTYPER_IDR_10 8Ú P GPIO_OTYPER_IDR_11 7Ú P GPIO_OTYPER_IDR_12 6Ú P GPIO_OTYPER_IDR_13 5Ú P GPIO_OTYPER_IDR_14 4Ú P GPIO_OTYPER_IDR_15 3Ú P GPIO_ODR_ODR_0 iÚ P GPIO_ODR_ODR_1 hÚ P GPIO_ODR_ODR_2 gÚ P GPIO_ODR_ODR_3 fÚ P GPIO_ODR_ODR_4 eÚ P GPIO_ODR_ODR_5 dÚ P GPIO_ODR_ODR_6 cÚ P GPIO_ODR_ODR_7 bÚ P GPIO_ODR_ODR_8 aÚ P GPIO_ODR_ODR_9 `Ú P GPIO_ODR_ODR_10 6Ú P GPIO_ODR_ODR_11 5Ú P GPIO_ODR_ODR_12 4Ú P GPIO_ODR_ODR_13 3Ú P GPIO_ODR_ODR_14 2Ú P GPIO_ODR_ODR_15 1Ú P GPIO_OTYPER_ODR_0 eÚ P GPIO_OTYPER_ODR_1 dÚ P GPIO_OTYPER_ODR_2 cÚ P GPIO_OTYPER_ODR_3 bÚ P GPIO_OTYPER_ODR_4 aÚ P GPIO_OTYPER_ODR_5 `Ú P GPIO_OTYPER_ODR_6 _Ú P GPIO_OTYPER_ODR_7 ^Ú P GPIO_OTYPER_ODR_8 ]Ú P GPIO_OTYPER_ODR_9 \Ú P GPIO_OTYPER_ODR_10 2Ú P GPIO_OTYPER_ODR_11 1Ú P GPIO_OTYPER_ODR_12 0Ú P GPIO_OTYPER_ODR_13 /Ú P GPIO_OTYPER_ODR_14 .Ú P GPIO_OTYPER_ODR_15 -Ú P GPIO_BSRR_BS_0 eÚ P GPIO_BSRR_BS_1 dÚ P GPIO_BSRR_BS_2 cÚ P GPIO_BSRR_BS_3 bÚ P GPIO_BSRR_BS_4 aÚ P GPIO_BSRR_BS_5 `Ú P GPIO_BSRR_BS_6 _Ú P GPIO_BSRR_BS_7 ^Ú P GPIO_BSRR_BS_8 ]Ú P GPIO_BSRR_BS_9 \Ú P GPIO_BSRR_BS_10 2Ú P GPIO_BSRR_BS_11 1Ú P GPIO_BSRR_BS_12 0Ú P GPIO_BSRR_BS_13 /Ú P GPIO_BSRR_BS_14 .Ú P GPIO_BSRR_BS_15 -Ú P GPIO_BSRR_BR_0 fÚ P GPIO_BSRR_BR_1 eÚ P GPIO_BSRR_BR_2 dÚ P GPIO_BSRR_BR_3 cÚ P GPIO_BSRR_BR_4 bÚ P GPIO_BSRR_BR_5 aÚ P GPIO_BSRR_BR_6 `Ú P GPIO_BSRR_BR_7 _Ú P GPIO_BSRR_BR_8 ^Ú P GPIO_BSRR_BR_9 ]Ú P GPIO_BSRR_BR_10 3Ú P GPIO_BSRR_BR_11 2Ú P GPIO_BSRR_BR_12 1Ú P GPIO_BSRR_BR_13 0Ú P GPIO_BSRR_BR_14 /Ú P GPIO_BSRR_BR_15 .Ú P GPIO_LCKR_LCK0 Ú P GPIO_LCKR_LCK1 Ú P GPIO_LCKR_LCK2 Ú P GPIO_LCKR_LCK3 Ú P GPIO_LCKR_LCK4 Ú P GPIO_LCKR_LCK5 Ú P GPIO_LCKR_LCK6 Ú P GPIO_LCKR_LCK7
Ú P GPIO_LCKR_LCK8 Ú P GPIO_LCKR_LCK9 Ú P GPIO_LCKR_LCK10 YÚ P GPIO_LCKR_LCK11 XÚ P GPIO_LCKR_LCK12 WÚ P GPIO_LCKR_LCK13 VÚ P GPIO_LCKR_LCK14 UÚ P GPIO_LCKR_LCK15 TÚ P GPIO_LCKR_LCKK qÚ P GPIO_AFRL_AFRL0 FÚ P GPIO_AFRL_AFRL1 EÚ P GPIO_AFRL_AFRL2 DÚ P GPIO_AFRL_AFRL3 CÚ P GPIO_AFRL_AFRL4 BÚ P GPIO_AFRL_AFRL5 AÚ P GPIO_AFRL_AFRL6 @Ú P GPIO_AFRL_AFRL7 ?Ú P GPIO_AFRH_AFRH8 FÚ P GPIO_AFRH_AFRH9 EÚ P GPIO_AFRH_AFRH10 Ú P GPIO_AFRH_AFRH11 Ú P GPIO_AFRH_AFRH12 Ú P GPIO_AFRH_AFRH13 Ú P GPIO_AFRH_AFRH14 Ú P GPIO_AFRH_AFRH15 Ú P I2C_CR1_PE àÚ P I2C_CR1_SMBUS åÚ P I2C_CR1_SMBTYPE GÚ P I2C_CR1_ENARP ùÚ P I2C_CR1_ENPEC Ú P
I2C_CR1_ENGC TÚ P I2C_CR1_NOSTRETCH Ú P I2C_CR1_START áÚ P
I2C_CR1_STOP +Ú P I2C_CR1_ACK ¤Ú P I2C_CR1_POS Ú P I2C_CR1_PEC Ú P I2C_CR1_ALERT ÷Ú P I2C_CR1_SWRST ÌÚ P
I2C_CR2_FREQ BÚ P I2C_CR2_FREQ_0 ¯Ú P I2C_CR2_FREQ_1 ®Ú P I2C_CR2_FREQ_2 Ú P I2C_CR2_FREQ_3 ¬Ú P I2C_CR2_FREQ_4 «Ú P I2C_CR2_FREQ_5 ªÚ P I2C_CR2_ITERREN QÚ P I2C_CR2_ITEVTEN KÚ P I2C_CR2_ITBUFEN ]Ú P I2C_CR2_DMAEN Ú P
I2C_CR2_LAST <Ú P I2C_OAR1_ADD1_7 Ú P I2C_OAR1_ADD8_9
Ú P I2C_OAR1_ADD0 )Ú P I2C_OAR1_ADD1 (Ú P I2C_OAR1_ADD2 'Ú P I2C_OAR1_ADD3 &Ú P I2C_OAR1_ADD4 %Ú P I2C_OAR1_ADD5 $Ú P I2C_OAR1_ADD6 #Ú P I2C_OAR1_ADD7 "Ú P I2C_OAR1_ADD8 !Ú P I2C_OAR1_ADD9 Ú P I2C_OAR1_ADDMODE .Ú P I2C_OAR2_ENDUAL dÚ P I2C_OAR2_ADD2 &Ú P |
| 797 |
I2C_DR_DR Ú P I2C_SR1_SB ÐÚ P
I2C_SR1_ADDR FÚ P I2C_SR1_BTF Ú P I2C_SR1_ADD10 5Ú P I2C_SR1_STOPF ÓÚ P
I2C_SR1_RXNE $Ú P I2C_SR1_TXE rÚ P
I2C_SR1_BERR 6Ú P
I2C_SR1_ARLO 3Ú P I2C_SR1_AF ÞÚ P I2C_SR1_OVR lÚ P I2C_SR1_PECERR Ú P I2C_SR1_TIMEOUT 4Ú P I2C_SR1_SMBALERT ÿÚ P I2C_SR2_MSL vÚ P
I2C_SR2_BUSY Ú P I2C_SR2_TRA {Ú P I2C_SR2_GENCALL dÚ P I2C_SR2_SMBDEFAULT mÚ P I2C_SR2_SMBHOST :Ú P I2C_SR2_DUALF òÚ P I2C_SR2_PEC Ú P I2C_CCR_CCR Ú P
I2C_CCR_DUTY Ú P I2C_CCR_FS ÊÚ P I2C_TRISE_TRISE #Ú P IWDG_KR_KEY FÚ P IWDG_PR_PR Ú P
IWDG_PR_PR_0 ÷Ú P
IWDG_PR_PR_1 öÚ P
IWDG_PR_PR_2 õÚ P IWDG_RLR_RL >Ú P IWDG_SR_PVU ,Ú P IWDG_SR_RVU *Ú P
LCD_CR_LCDEN 'Ú P LCD_CR_VSEL UÚ P LCD_CR_DUTY IÚ P LCD_CR_DUTY_0 ¶Ú P LCD_CR_DUTY_1 µÚ P LCD_CR_DUTY_2 ´Ú P LCD_CR_BIAS pÚ P LCD_CR_BIAS_0 ÝÚ P LCD_CR_BIAS_1 ÜÚ P LCD_CR_MUX_SEG QÚ P LCD_FCR_HD ¿Ú P LCD_FCR_SOFIE ÏÚ P LCD_FCR_UDDIE ÚÚ P LCD_FCR_PON \Ú P LCD_FCR_PON_0 ÉÚ P LCD_FCR_PON_1 ÈÚ P LCD_FCR_PON_2 ÇÚ P
LCD_FCR_DEAD 9Ú P LCD_FCR_DEAD_0 ¦Ú P LCD_FCR_DEAD_1 ¥Ú P LCD_FCR_DEAD_2 ¤Ú P LCD_FCR_CC ÅÚ P
LCD_FCR_CC_0 2Ú P
LCD_FCR_CC_1 1Ú P
LCD_FCR_CC_2 0Ú P LCD_FCR_BLINKF Ú P LCD_FCR_BLINKF_0 úÚ P LCD_FCR_BLINKF_1 ùÚ P LCD_FCR_BLINKF_2 øÚ P LCD_FCR_BLINK ÕÚ P LCD_FCR_BLINK_0 BÚ P LCD_FCR_BLINK_1 AÚ P LCD_FCR_DIV fÚ P LCD_FCR_PS ¨Ú P LCD_SR_ENS Ú P LCD_SR_SOF Ú P LCD_SR_UDR Ú P LCD_SR_UDD ¤Ú P LCD_SR_RDY Ú P
LCD_SR_FCRSR ýÚ P
LCD_CLR_SOFC Ú P
LCD_CLR_UDDC !Ú P LCD_RAM_SEGMENT_DATA ¦Ú P PWR_CR_LPSDSR Ú P PWR_CR_PDDS >Ú P PWR_CR_CWUF 4Ú P PWR_CR_CSBF KÚ P PWR_CR_PVDE :Ú P PWR_CR_PLS |Ú P
PWR_CR_PLS_0 éÚ P
PWR_CR_PLS_1 èÚ P
PWR_CR_PLS_2 çÚ P PWR_CR_PLS_LEV0 üÚ P PWR_CR_PLS_LEV1 ûÚ P PWR_CR_PLS_LEV2 úÚ P PWR_CR_PLS_LEV3 ùÚ P PWR_CR_PLS_LEV4 øÚ P PWR_CR_PLS_LEV5 ÷Ú P PWR_CR_PLS_LEV6 öÚ P PWR_CR_PLS_LEV7 õÚ P PWR_CR_DBP Ú P PWR_CR_ULP zÚ P PWR_CR_FWU yÚ P PWR_CR_VOS sÚ P
PWR_CR_VOS_0 àÚ P
PWR_CR_VOS_1 ßÚ P
PWR_CR_LPRUN ÖÚ P PWR_CSR_WUF $Ú P PWR_CSR_SBF ;Ú P
PWR_CSR_PVDO ÛÚ P PWR_CSR_VREFINTRDYF ³Ú P
PWR_CSR_VOSF ÖÚ P PWR_CSR_REGLPF PÚ P PWR_CSR_EWUP1 Ú P PWR_CSR_EWUP2 Ú P PWR_CSR_EWUP3 Ú P
RCC_CR_HSION Ú P RCC_CR_HSIRDY ³Ú P
RCC_CR_MSION Ú P RCC_CR_MSIRDY ®Ú P
RCC_CR_HSEON Ú P RCC_CR_HSERDY ·Ú P RCC_CR_HSEBYP »Ú P
RCC_CR_PLLON Ú P RCC_CR_PLLRDY ¯Ú P
RCC_CR_CSSON Ú P RCC_CR_RTCPRE ¶Ú P RCC_CR_RTCPRE_0 #Ú P RCC_CR_RTCPRE_1 "Ú P RCC_ICSCR_HSICAL íÚ P RCC_ICSCR_HSITRIM Ú P RCC_ICSCR_MSIRANGE GÚ P RCC_ICSCR_MSIRANGE_0 ´Ú P RCC_ICSCR_MSIRANGE_1 ³Ú P RCC_ICSCR_MSIRANGE_2 ²Ú P RCC_ICSCR_MSIRANGE_3 ±Ú P RCC_ICSCR_MSIRANGE_4 °Ú P RCC_ICSCR_MSIRANGE_5 ¯Ú P RCC_ICSCR_MSIRANGE_6 ®Ú P RCC_ICSCR_MSICAL èÚ P RCC_ICSCR_MSITRIM zÚ P RCC_CFGR_SW SÚ P RCC_CFGR_SW_0 ÀÚ P RCC_CFGR_SW_1 ¿Ú P RCC_CFGR_SW_MSI Ú P RCC_CFGR_SW_HSI Ú P RCC_CFGR_SW_HSE Ú P RCC_CFGR_SW_PLL Ú P
RCC_CFGR_SWS þÚ P RCC_CFGR_SWS_0 kÚ P RCC_CFGR_SWS_1 jÚ P RCC_CFGR_SWS_MSI ®Ú P RCC_CFGR_SWS_HSI ³Ú P RCC_CFGR_SWS_HSE ·Ú P RCC_CFGR_SWS_PLL ¯Ú P RCC_CFGR_HPRE ÊÚ P RCC_CFGR_HPRE_0 7Ú P RCC_CFGR_HPRE_1 6Ú P RCC_CFGR_HPRE_2 5Ú P RCC_CFGR_HPRE_3 4Ú P RCC_CFGR_HPRE_DIV1 MÚ P RCC_CFGR_HPRE_DIV2 LÚ P RCC_CFGR_HPRE_DIV4 JÚ P RCC_CFGR_HPRE_DIV8 FÚ P RCC_CFGR_HPRE_DIV16 Ú P RCC_CFGR_HPRE_DIV64 Ú P RCC_CFGR_HPRE_DIV128 ßÚ P RCC_CFGR_HPRE_DIV256 ÝÚ P RCC_CFGR_HPRE_DIV512 âÚ P RCC_CFGR_PPRE1 Ú P RCC_CFGR_PPRE1_0 üÚ P RCC_CFGR_PPRE1_1 ûÚ P RCC_CFGR_PPRE1_2 úÚ P RCC_CFGR_PPRE1_DIV1 Ú P RCC_CFGR_PPRE1_DIV2 Ú P RCC_CFGR_PPRE1_DIV4 Ú P RCC_CFGR_PPRE1_DIV8 Ú P RCC_CFGR_PPRE1_DIV16 ÚÚ P RCC_CFGR_PPRE2 Ú P RCC_CFGR_PPRE2_0 ûÚ P RCC_CFGR_PPRE2_1 úÚ P RCC_CFGR_PPRE2_2 ùÚ P RCC_CFGR_PPRE2_DIV1 Ú P RCC_CFGR_PPRE2_DIV2 Ú P RCC_CFGR_PPRE2_DIV4 Ú P RCC_CFGR_PPRE2_DIV8 |
797 |
I2C_DR_DR Ú P I2C_SR1_SB ÐÚ P
I2C_SR1_ADDR FÚ P I2C_SR1_BTF Ú P I2C_SR1_ADD10 5Ú P I2C_SR1_STOPF ÓÚ P
I2C_SR1_RXNE $Ú P I2C_SR1_TXE rÚ P
I2C_SR1_BERR 6Ú P
I2C_SR1_ARLO 3Ú P I2C_SR1_AF ÞÚ P I2C_SR1_OVR lÚ P I2C_SR1_PECERR Ú P I2C_SR1_TIMEOUT 4Ú P I2C_SR1_SMBALERT ÿÚ P I2C_SR2_MSL vÚ P
I2C_SR2_BUSY Ú P I2C_SR2_TRA {Ú P I2C_SR2_GENCALL dÚ P I2C_SR2_SMBDEFAULT mÚ P I2C_SR2_SMBHOST :Ú P I2C_SR2_DUALF òÚ P I2C_SR2_PEC Ú P I2C_CCR_CCR Ú P
I2C_CCR_DUTY Ú P I2C_CCR_FS ÊÚ P I2C_TRISE_TRISE #Ú P IWDG_KR_KEY FÚ P IWDG_PR_PR Ú P
IWDG_PR_PR_0 ÷Ú P
IWDG_PR_PR_1 öÚ P
IWDG_PR_PR_2 õÚ P IWDG_RLR_RL >Ú P IWDG_SR_PVU ,Ú P IWDG_SR_RVU *Ú P
LCD_CR_LCDEN 'Ú P LCD_CR_VSEL UÚ P LCD_CR_DUTY IÚ P LCD_CR_DUTY_0 ¶Ú P LCD_CR_DUTY_1 µÚ P LCD_CR_DUTY_2 ´Ú P LCD_CR_BIAS pÚ P LCD_CR_BIAS_0 ÝÚ P LCD_CR_BIAS_1 ÜÚ P LCD_CR_MUX_SEG QÚ P LCD_FCR_HD ¿Ú P LCD_FCR_SOFIE ÏÚ P LCD_FCR_UDDIE ÚÚ P LCD_FCR_PON \Ú P LCD_FCR_PON_0 ÉÚ P LCD_FCR_PON_1 ÈÚ P LCD_FCR_PON_2 ÇÚ P
LCD_FCR_DEAD 9Ú P LCD_FCR_DEAD_0 ¦Ú P LCD_FCR_DEAD_1 ¥Ú P LCD_FCR_DEAD_2 ¤Ú P LCD_FCR_CC ÅÚ P
LCD_FCR_CC_0 2Ú P
LCD_FCR_CC_1 1Ú P
LCD_FCR_CC_2 0Ú P LCD_FCR_BLINKF Ú P LCD_FCR_BLINKF_0 úÚ P LCD_FCR_BLINKF_1 ùÚ P LCD_FCR_BLINKF_2 øÚ P LCD_FCR_BLINK ÕÚ P LCD_FCR_BLINK_0 BÚ P LCD_FCR_BLINK_1 AÚ P LCD_FCR_DIV fÚ P LCD_FCR_PS ¨Ú P LCD_SR_ENS Ú P LCD_SR_SOF Ú P LCD_SR_UDR Ú P LCD_SR_UDD ¤Ú P LCD_SR_RDY Ú P
LCD_SR_FCRSR ýÚ P
LCD_CLR_SOFC Ú P
LCD_CLR_UDDC !Ú P LCD_RAM_SEGMENT_DATA ¦Ú P PWR_CR_LPSDSR Ú P PWR_CR_PDDS >Ú P PWR_CR_CWUF 4Ú P PWR_CR_CSBF KÚ P PWR_CR_PVDE :Ú P PWR_CR_PLS |Ú P
PWR_CR_PLS_0 éÚ P
PWR_CR_PLS_1 èÚ P
PWR_CR_PLS_2 çÚ P PWR_CR_PLS_LEV0 üÚ P PWR_CR_PLS_LEV1 ûÚ P PWR_CR_PLS_LEV2 úÚ P PWR_CR_PLS_LEV3 ùÚ P PWR_CR_PLS_LEV4 øÚ P PWR_CR_PLS_LEV5 ÷Ú P PWR_CR_PLS_LEV6 öÚ P PWR_CR_PLS_LEV7 õÚ P PWR_CR_DBP Ú P PWR_CR_ULP zÚ P PWR_CR_FWU yÚ P PWR_CR_VOS sÚ P
PWR_CR_VOS_0 àÚ P
PWR_CR_VOS_1 ßÚ P
PWR_CR_LPRUN ÖÚ P PWR_CSR_WUF $Ú P PWR_CSR_SBF ;Ú P
PWR_CSR_PVDO ÛÚ P PWR_CSR_VREFINTRDYF ³Ú P
PWR_CSR_VOSF ÖÚ P PWR_CSR_REGLPF PÚ P PWR_CSR_EWUP1 Ú P PWR_CSR_EWUP2 Ú P PWR_CSR_EWUP3 Ú P
RCC_CR_HSION Ú P RCC_CR_HSIRDY ³Ú P
RCC_CR_MSION Ú P RCC_CR_MSIRDY ®Ú P
RCC_CR_HSEON Ú P RCC_CR_HSERDY ·Ú P RCC_CR_HSEBYP »Ú P
RCC_CR_PLLON Ú P RCC_CR_PLLRDY ¯Ú P
RCC_CR_CSSON Ú P RCC_CR_RTCPRE ¶Ú P RCC_CR_RTCPRE_0 #Ú P RCC_CR_RTCPRE_1 "Ú P RCC_ICSCR_HSICAL íÚ P RCC_ICSCR_HSITRIM Ú P RCC_ICSCR_MSIRANGE GÚ P RCC_ICSCR_MSIRANGE_0 ´Ú P RCC_ICSCR_MSIRANGE_1 ³Ú P RCC_ICSCR_MSIRANGE_2 ²Ú P RCC_ICSCR_MSIRANGE_3 ±Ú P RCC_ICSCR_MSIRANGE_4 °Ú P RCC_ICSCR_MSIRANGE_5 ¯Ú P RCC_ICSCR_MSIRANGE_6 ®Ú P RCC_ICSCR_MSICAL èÚ P RCC_ICSCR_MSITRIM zÚ P RCC_CFGR_SW SÚ P RCC_CFGR_SW_0 ÀÚ P RCC_CFGR_SW_1 ¿Ú P RCC_CFGR_SW_MSI Ú P RCC_CFGR_SW_HSI Ú P RCC_CFGR_SW_HSE Ú P RCC_CFGR_SW_PLL Ú P
RCC_CFGR_SWS þÚ P RCC_CFGR_SWS_0 kÚ P RCC_CFGR_SWS_1 jÚ P RCC_CFGR_SWS_MSI ®Ú P RCC_CFGR_SWS_HSI ³Ú P RCC_CFGR_SWS_HSE ·Ú P RCC_CFGR_SWS_PLL ¯Ú P RCC_CFGR_HPRE ÊÚ P RCC_CFGR_HPRE_0 7Ú P RCC_CFGR_HPRE_1 6Ú P RCC_CFGR_HPRE_2 5Ú P RCC_CFGR_HPRE_3 4Ú P RCC_CFGR_HPRE_DIV1 MÚ P RCC_CFGR_HPRE_DIV2 LÚ P RCC_CFGR_HPRE_DIV4 JÚ P RCC_CFGR_HPRE_DIV8 FÚ P RCC_CFGR_HPRE_DIV16 Ú P RCC_CFGR_HPRE_DIV64 Ú P RCC_CFGR_HPRE_DIV128 ßÚ P RCC_CFGR_HPRE_DIV256 ÝÚ P RCC_CFGR_HPRE_DIV512 âÚ P RCC_CFGR_PPRE1 Ú P RCC_CFGR_PPRE1_0 üÚ P RCC_CFGR_PPRE1_1 ûÚ P RCC_CFGR_PPRE1_2 úÚ P RCC_CFGR_PPRE1_DIV1 Ú P RCC_CFGR_PPRE1_DIV2 Ú P RCC_CFGR_PPRE1_DIV4 Ú P RCC_CFGR_PPRE1_DIV8 Ú P RCC_CFGR_PPRE1_DIV16 ÚÚ P RCC_CFGR_PPRE2 Ú P RCC_CFGR_PPRE2_0 ûÚ P RCC_CFGR_PPRE2_1 úÚ P RCC_CFGR_PPRE2_2 ùÚ P RCC_CFGR_PPRE2_DIV1 Ú P RCC_CFGR_PPRE2_DIV2 Ú P RCC_CFGR_PPRE2_DIV4 Ú P RCC_CFGR_PPRE2_DIV8 |
| 798 |
Ú P RCC_CFGR_PPRE2_DIV16 ÙÚ P RCC_CFGR_PLLSRC %Ú P RCC_CFGR_PLLSRC_HSI ÚÚ P RCC_CFGR_PLLSRC_HSE ÞÚ P RCC_CFGR_PLLMUL Ú P RCC_CFGR_PLLMUL_0 Ú P RCC_CFGR_PLLMUL_1 Ú P RCC_CFGR_PLLMUL_2 Ú P RCC_CFGR_PLLMUL_3 Ú P RCC_CFGR_PLLMUL3 êÚ P RCC_CFGR_PLLMUL4 éÚ P RCC_CFGR_PLLMUL6 çÚ P RCC_CFGR_PLLMUL8 åÚ P RCC_CFGR_PLLMUL12 ¸Ú P RCC_CFGR_PLLMUL16 ´Ú P RCC_CFGR_PLLMUL24 µÚ P RCC_CFGR_PLLMUL32 ¶Ú P RCC_CFGR_PLLMUL48 ¯Ú P RCC_CFGR_PLLDIV *Ú P RCC_CFGR_PLLDIV_0 Ú P RCC_CFGR_PLLDIV_1 Ú P RCC_CFGR_PLLDIV1 ÷Ú P RCC_CFGR_PLLDIV2 öÚ P RCC_CFGR_PLLDIV3 õÚ P RCC_CFGR_PLLDIV4 ôÚ P RCC_CFGR_MCOSEL 2Ú P RCC_CFGR_MCOSEL_0 Ú P RCC_CFGR_MCOSEL_1 Ú P RCC_CFGR_MCOSEL_2 Ú P RCC_CFGR_MCO_NOCLOCK ¤Ú P RCC_CFGR_MCO_SYSCLK ÖÚ P RCC_CFGR_MCO_HSI ÑÚ P RCC_CFGR_MCO_MSI ÌÚ P RCC_CFGR_MCO_HSE ÕÚ P RCC_CFGR_MCO_PLL ÍÚ P RCC_CFGR_MCO_LSI ÍÚ P RCC_CFGR_MCO_LSE ÑÚ P RCC_CFGR_MCOPRE /Ú P RCC_CFGR_MCOPRE_0 Ú P RCC_CFGR_MCOPRE_1 Ú P RCC_CFGR_MCOPRE_2 Ú P RCC_CFGR_MCO_DIV1 Ú P RCC_CFGR_MCO_DIV2 Ú P RCC_CFGR_MCO_DIV4 Ú P RCC_CFGR_MCO_DIV8 Ú P RCC_CFGR_MCO_DIV16 gÚ P RCC_CIR_LSIRDYF Ú P RCC_CIR_LSERDYF Ú P RCC_CIR_HSIRDYF Ú P RCC_CIR_HSERDYF $Ú P RCC_CIR_PLLRDYF Ú P RCC_CIR_MSIRDYF Ú P RCC_CIR_LSECSS nÚ P
RCC_CIR_CSSF Ú P RCC_CIR_LSIRDYIE ÒÚ P RCC_CIR_LSERDYIE ÖÚ P RCC_CIR_HSIRDYIE ÖÚ P RCC_CIR_HSERDYIE ÚÚ P RCC_CIR_PLLRDYIE ÒÚ P RCC_CIR_MSIRDYIE ÑÚ P RCC_CIR_LSECSSIE ÜÚ P RCC_CIR_LSIRDYC Ú P RCC_CIR_LSERDYC #Ú P RCC_CIR_HSIRDYC #Ú P RCC_CIR_HSERDYC 'Ú P RCC_CIR_PLLRDYC Ú P RCC_CIR_MSIRDYC Ú P RCC_CIR_LSECSSC )Ú P
RCC_CIR_CSSC Ú P RCC_AHBRSTR_GPIOARST Ú P RCC_AHBRSTR_GPIOBRST Ú P RCC_AHBRSTR_GPIOCRST Ú P RCC_AHBRSTR_GPIODRST Ú P RCC_AHBRSTR_GPIOERST Ú P RCC_AHBRSTR_GPIOHRST Ú P RCC_AHBRSTR_GPIOFRST Ú P RCC_AHBRSTR_GPIOGRST Ú P RCC_AHBRSTR_CRCRST *Ú P RCC_AHBRSTR_FLITFRST Ú P RCC_AHBRSTR_DMA1RST ýÚ P RCC_AHBRSTR_DMA2RST üÚ P RCC_AHBRSTR_AESRST )Ú P RCC_AHBRSTR_FSMCRST ×Ú P RCC_APB2RSTR_SYSCFGRST ñÚ P RCC_APB2RSTR_TIM9RST ¡Ú P RCC_APB2RSTR_TIM10RST wÚ P RCC_APB2RSTR_TIM11RST vÚ P RCC_APB2RSTR_ADC1RST ËÚ P RCC_APB2RSTR_SDIORST Ú P RCC_APB2RSTR_SPI1RST §Ú P RCC_APB2RSTR_USART1RST Ú P RCC_APB1RSTR_TIM2RST ©Ú P RCC_APB1RSTR_TIM3RST ¨Ú P RCC_APB1RSTR_TIM4RST §Ú P RCC_APB1RSTR_TIM5RST ¦Ú P RCC_APB1RSTR_TIM6RST ¥Ú P RCC_APB1RSTR_TIM7RST ¤Ú P RCC_APB1RSTR_LCDRST ôÚ P RCC_APB1RSTR_WWDGRST Ú P RCC_APB1RSTR_SPI2RST §Ú P RCC_APB1RSTR_SPI3RST ¦Ú P RCC_APB1RSTR_USART2RST Ú P RCC_APB1RSTR_USART3RST ÿÚ P RCC_APB1RSTR_UART4RST SÚ P RCC_APB1RSTR_UART5RST RÚ P RCC_APB1RSTR_I2C1RST ÖÚ P RCC_APB1RSTR_I2C2RST ÕÚ P RCC_APB1RSTR_USBRST ÝÚ P RCC_APB1RSTR_PWRRST ÎÚ P RCC_APB1RSTR_DACRST ÿÚ P RCC_APB1RSTR_COMPRST Ú P RCC_AHBENR_GPIOAEN ^Ú P RCC_AHBENR_GPIOBEN ]Ú P RCC_AHBENR_GPIOCEN \Ú P RCC_AHBENR_GPIODEN [Ú P RCC_AHBENR_GPIOEEN ZÚ P RCC_AHBENR_GPIOHEN WÚ P RCC_AHBENR_GPIOFEN YÚ P RCC_AHBENR_GPIOGEN XÚ P RCC_AHBENR_CRCEN úÚ P RCC_AHBENR_FLITFEN YÚ P RCC_AHBENR_DMA1EN ÍÚ P RCC_AHBENR_DMA2EN ÌÚ P RCC_AHBENR_AESEN ùÚ P RCC_AHBENR_FSMCEN §Ú P RCC_APB2ENR_SYSCFGEN ÁÚ P RCC_APB2ENR_TIM9EN qÚ P RCC_APB2ENR_TIM10EN GÚ P RCC_APB2ENR_TIM11EN FÚ P RCC_APB2ENR_ADC1EN Ú P RCC_APB2ENR_SDIOEN eÚ P RCC_APB2ENR_SPI1EN wÚ P RCC_APB2ENR_USART1EN ÐÚ P RCC_APB1ENR_TIM2EN yÚ P RCC_APB1ENR_TIM3EN xÚ P RCC_APB1ENR_TIM4EN wÚ P RCC_APB1ENR_TIM5EN vÚ P RCC_APB1ENR_TIM6EN uÚ P RCC_APB1ENR_TIM7EN tÚ P RCC_APB1ENR_LCDEN ÄÚ P RCC_APB1ENR_WWDGEN \Ú P RCC_APB1ENR_SPI2EN wÚ P RCC_APB1ENR_SPI3EN vÚ P RCC_APB1ENR_USART2EN ÐÚ P RCC_APB1ENR_USART3EN ÏÚ P RCC_APB1ENR_UART4EN #Ú P RCC_APB1ENR_UART5EN "Ú P RCC_APB1ENR_I2C1EN ¦Ú P RCC_APB1ENR_I2C2EN ¥Ú P RCC_APB1ENR_USBEN Ú P RCC_APB1ENR_PWREN Ú P RCC_APB1ENR_DACEN ÏÚ P RCC_APB1ENR_COMPEN fÚ P RCC_AHBLPENR_GPIOALPEN Ú P RCC_AHBLPENR_GPIOBLPEN Ú P RCC_AHBLPENR_GPIOCLPEN Ú P RCC_AHBLPENR_GPIODLPEN Ú P RCC_AHBLPENR_GPIOELPEN Ú P RCC_AHBLPENR_GPIOHLPEN Ú P RCC_AHBLPENR_GPIOFLPEN Ú P RCC_AHBLPENR_GPIOGLPEN Ú P RCC_AHBLPENR_CRCLPEN ºÚ P RCC_AHBLPENR_FLITFLPEN Ú P RCC_AHBLPENR_SRAMLPEN ]Ú P RCC_AHBLPENR_DMA1LPEN Ú P RCC_AHBLPENR_DMA2LPEN Ú P RCC_AHBLPENR_AESLPEN ¹Ú P RCC_AHBLPENR_FSMCLPEN gÚ! P RCC_APB2LPENR_SYSCFGLPEN Ú P RCC_APB2LPENR_TIM9LPEN 1Ú P RCC_APB2LPENR_TIM10LPEN Ú P RCC_APB2LPENR_TIM11LPEN Ú P RCC_APB2LPENR_ADC1LPEN [Ú P RCC_APB2LPENR_SDIOLPEN %Ú P RCC_APB2LPENR_SPI1LPEN 7Ú! P RCC_APB2LPENR_USART1LPEN Ú P RCC_APB1LPENR_TIM2LPEN 9Ú P RCC_APB1LPENR_TIM3LPEN 8Ú P RCC_APB1LPENR_TIM4LPEN 7Ú P RCC_APB1LPENR_TIM5LPEN 6Ú P RCC_APB1LPENR_TIM6LPEN 5Ú P RCC_APB1LPENR_TIM7LPEN 4Ú P RCC_APB1LPENR_LCDLPEN Ú P RCC_APB1LPENR_WWDGLPEN Ú P RCC_APB1LPENR_SPI2LPEN 7Ú P RCC_APB1LPENR_SPI3LPEN 6Ú! P RCC_APB1LPENR_USART2LPEN Ú! P RCC_APB1LPENR_USART3LPEN Ú P RCC_APB1LPENR_UART4LPEN ãÚ P RCC_APB1LPENR_UART5LPEN âÚ P RCC_APB1LPENR_I2C1LPEN fÚ P RCC_APB1LPENR_I2C2LPEN eÚ P RCC_APB1LPENR_USBLPEN mÚ P RCC_APB1LPENR_PWRLPEN ^Ú P RCC_APB1LPENR_DACLPEN Ú P RCC_APB1LPENR_COMPLPEN &Ú P RCC_CSR_LSION ®Ú P RCC_CSR_LSIRDY ZÚ P RCC_CSR_LSEON ²Ú P RCC_CSR_LSERDY ^Ú P RCC_CSR_LSEBYP bÚ P RCC_CSR_LSECSSON ÃÚ P RCC_CSR_LSECSSD Ú P RCC_CSR_RTCSEL dÚ P RCC_CSR_RTCSEL_0 ÑÚ P RCC_CSR_RTCSEL_1 ÐÚ P RCC_CSR_RTCSEL_NOCLOCK ìÚ P RCC_CSR_RTCSEL_LSE Ú P RCC_CSR_RTCSEL_LSI Ú P RCC_CSR_RTCSEL_HSE Ú P RCC_CSR_RTCEN ·Ú P RCC_CSR_RTCRST OÚ P
RCC_CSR_RMVF úÚ P RCC_CSR_OBLRSTF Ú P RCC_CSR_PINRSTF Ú P RCC_CSR_PORRSTF ÿÚ P RCC_CSR_SFTRSTF Ú P RCC_CSR_IWDGRSTF ÃÚ P RCC_CSR_WWDGRSTF µÚ P RCC_CSR_LPWRRSTF ©Ú P |
798 |
Ú P RCC_CFGR_PPRE2_DIV16 ÙÚ P RCC_CFGR_PLLSRC %Ú P RCC_CFGR_PLLSRC_HSI ÚÚ P RCC_CFGR_PLLSRC_HSE ÞÚ P RCC_CFGR_PLLMUL Ú P RCC_CFGR_PLLMUL_0 Ú P RCC_CFGR_PLLMUL_1 Ú P RCC_CFGR_PLLMUL_2 Ú P RCC_CFGR_PLLMUL_3 Ú P RCC_CFGR_PLLMUL3 êÚ P RCC_CFGR_PLLMUL4 éÚ P RCC_CFGR_PLLMUL6 çÚ P RCC_CFGR_PLLMUL8 åÚ P RCC_CFGR_PLLMUL12 ¸Ú P RCC_CFGR_PLLMUL16 ´Ú P RCC_CFGR_PLLMUL24 µÚ P RCC_CFGR_PLLMUL32 ¶Ú P RCC_CFGR_PLLMUL48 ¯Ú P RCC_CFGR_PLLDIV *Ú P RCC_CFGR_PLLDIV_0 Ú P RCC_CFGR_PLLDIV_1 Ú P RCC_CFGR_PLLDIV1 ÷Ú P RCC_CFGR_PLLDIV2 öÚ P RCC_CFGR_PLLDIV3 õÚ P RCC_CFGR_PLLDIV4 ôÚ P RCC_CFGR_MCOSEL 2Ú P RCC_CFGR_MCOSEL_0 Ú P RCC_CFGR_MCOSEL_1 Ú P RCC_CFGR_MCOSEL_2 Ú P RCC_CFGR_MCO_NOCLOCK ¤Ú P RCC_CFGR_MCO_SYSCLK ÖÚ P RCC_CFGR_MCO_HSI ÑÚ P RCC_CFGR_MCO_MSI ÌÚ P RCC_CFGR_MCO_HSE ÕÚ P RCC_CFGR_MCO_PLL ÍÚ P RCC_CFGR_MCO_LSI ÍÚ P RCC_CFGR_MCO_LSE ÑÚ P RCC_CFGR_MCOPRE /Ú P RCC_CFGR_MCOPRE_0 Ú P RCC_CFGR_MCOPRE_1 Ú P RCC_CFGR_MCOPRE_2 Ú P RCC_CFGR_MCO_DIV1 Ú P RCC_CFGR_MCO_DIV2 Ú P RCC_CFGR_MCO_DIV4 Ú P RCC_CFGR_MCO_DIV8 Ú P RCC_CFGR_MCO_DIV16 gÚ P RCC_CIR_LSIRDYF Ú P RCC_CIR_LSERDYF Ú P RCC_CIR_HSIRDYF Ú P RCC_CIR_HSERDYF $Ú P RCC_CIR_PLLRDYF Ú P RCC_CIR_MSIRDYF Ú P RCC_CIR_LSECSS nÚ P
RCC_CIR_CSSF Ú P RCC_CIR_LSIRDYIE ÒÚ P RCC_CIR_LSERDYIE ÖÚ P RCC_CIR_HSIRDYIE ÖÚ P RCC_CIR_HSERDYIE ÚÚ P RCC_CIR_PLLRDYIE ÒÚ P RCC_CIR_MSIRDYIE ÑÚ P RCC_CIR_LSECSSIE ÜÚ P RCC_CIR_LSIRDYC Ú P RCC_CIR_LSERDYC #Ú P RCC_CIR_HSIRDYC #Ú P RCC_CIR_HSERDYC 'Ú P RCC_CIR_PLLRDYC Ú P RCC_CIR_MSIRDYC Ú P RCC_CIR_LSECSSC )Ú P
RCC_CIR_CSSC Ú P RCC_AHBRSTR_GPIOARST Ú P RCC_AHBRSTR_GPIOBRST Ú P RCC_AHBRSTR_GPIOCRST Ú P RCC_AHBRSTR_GPIODRST Ú P RCC_AHBRSTR_GPIOERST Ú P RCC_AHBRSTR_GPIOHRST Ú P RCC_AHBRSTR_GPIOFRST Ú P RCC_AHBRSTR_GPIOGRST Ú P RCC_AHBRSTR_CRCRST *Ú P RCC_AHBRSTR_FLITFRST Ú P RCC_AHBRSTR_DMA1RST ýÚ P RCC_AHBRSTR_DMA2RST üÚ P RCC_AHBRSTR_AESRST )Ú P RCC_AHBRSTR_FSMCRST ×Ú P RCC_APB2RSTR_SYSCFGRST ñÚ P RCC_APB2RSTR_TIM9RST ¡Ú P RCC_APB2RSTR_TIM10RST wÚ P RCC_APB2RSTR_TIM11RST vÚ P RCC_APB2RSTR_ADC1RST ËÚ P RCC_APB2RSTR_SDIORST Ú P RCC_APB2RSTR_SPI1RST §Ú P RCC_APB2RSTR_USART1RST Ú P RCC_APB1RSTR_TIM2RST ©Ú P RCC_APB1RSTR_TIM3RST ¨Ú P RCC_APB1RSTR_TIM4RST §Ú P RCC_APB1RSTR_TIM5RST ¦Ú P RCC_APB1RSTR_TIM6RST ¥Ú P RCC_APB1RSTR_TIM7RST ¤Ú P RCC_APB1RSTR_LCDRST ôÚ P RCC_APB1RSTR_WWDGRST Ú P RCC_APB1RSTR_SPI2RST §Ú P RCC_APB1RSTR_SPI3RST ¦Ú P RCC_APB1RSTR_USART2RST Ú P RCC_APB1RSTR_USART3RST ÿÚ P RCC_APB1RSTR_UART4RST SÚ P RCC_APB1RSTR_UART5RST RÚ P RCC_APB1RSTR_I2C1RST ÖÚ P RCC_APB1RSTR_I2C2RST ÕÚ P RCC_APB1RSTR_USBRST ÝÚ P RCC_APB1RSTR_PWRRST ÎÚ P RCC_APB1RSTR_DACRST ÿÚ P RCC_APB1RSTR_COMPRST Ú P RCC_AHBENR_GPIOAEN ^Ú P RCC_AHBENR_GPIOBEN ]Ú P RCC_AHBENR_GPIOCEN \Ú P RCC_AHBENR_GPIODEN [Ú P RCC_AHBENR_GPIOEEN ZÚ P RCC_AHBENR_GPIOHEN WÚ P RCC_AHBENR_GPIOFEN YÚ P RCC_AHBENR_GPIOGEN XÚ P RCC_AHBENR_CRCEN úÚ P RCC_AHBENR_FLITFEN YÚ P RCC_AHBENR_DMA1EN ÍÚ P RCC_AHBENR_DMA2EN ÌÚ P RCC_AHBENR_AESEN ùÚ P RCC_AHBENR_FSMCEN §Ú P RCC_APB2ENR_SYSCFGEN ÁÚ P RCC_APB2ENR_TIM9EN qÚ P RCC_APB2ENR_TIM10EN GÚ P RCC_APB2ENR_TIM11EN FÚ P RCC_APB2ENR_ADC1EN Ú P RCC_APB2ENR_SDIOEN eÚ P RCC_APB2ENR_SPI1EN wÚ P RCC_APB2ENR_USART1EN ÐÚ P RCC_APB1ENR_TIM2EN yÚ P RCC_APB1ENR_TIM3EN xÚ P RCC_APB1ENR_TIM4EN wÚ P RCC_APB1ENR_TIM5EN vÚ P RCC_APB1ENR_TIM6EN uÚ P RCC_APB1ENR_TIM7EN tÚ P RCC_APB1ENR_LCDEN ÄÚ P RCC_APB1ENR_WWDGEN \Ú P RCC_APB1ENR_SPI2EN wÚ P RCC_APB1ENR_SPI3EN vÚ P RCC_APB1ENR_USART2EN ÐÚ P RCC_APB1ENR_USART3EN ÏÚ P RCC_APB1ENR_UART4EN #Ú P RCC_APB1ENR_UART5EN "Ú P RCC_APB1ENR_I2C1EN ¦Ú P RCC_APB1ENR_I2C2EN ¥Ú P RCC_APB1ENR_USBEN Ú P RCC_APB1ENR_PWREN Ú P RCC_APB1ENR_DACEN ÏÚ P RCC_APB1ENR_COMPEN fÚ P RCC_AHBLPENR_GPIOALPEN Ú P RCC_AHBLPENR_GPIOBLPEN Ú P RCC_AHBLPENR_GPIOCLPEN Ú P RCC_AHBLPENR_GPIODLPEN Ú P RCC_AHBLPENR_GPIOELPEN Ú P RCC_AHBLPENR_GPIOHLPEN Ú P RCC_AHBLPENR_GPIOFLPEN Ú P RCC_AHBLPENR_GPIOGLPEN Ú P RCC_AHBLPENR_CRCLPEN ºÚ P RCC_AHBLPENR_FLITFLPEN Ú P RCC_AHBLPENR_SRAMLPEN ]Ú P RCC_AHBLPENR_DMA1LPEN Ú P RCC_AHBLPENR_DMA2LPEN Ú P RCC_AHBLPENR_AESLPEN ¹Ú P RCC_AHBLPENR_FSMCLPEN gÚ! P RCC_APB2LPENR_SYSCFGLPEN Ú P RCC_APB2LPENR_TIM9LPEN 1Ú P RCC_APB2LPENR_TIM10LPEN Ú P RCC_APB2LPENR_TIM11LPEN Ú P RCC_APB2LPENR_ADC1LPEN [Ú P RCC_APB2LPENR_SDIOLPEN %Ú P RCC_APB2LPENR_SPI1LPEN 7Ú! P RCC_APB2LPENR_USART1LPEN Ú P RCC_APB1LPENR_TIM2LPEN 9Ú P RCC_APB1LPENR_TIM3LPEN 8Ú P RCC_APB1LPENR_TIM4LPEN 7Ú P RCC_APB1LPENR_TIM5LPEN 6Ú P RCC_APB1LPENR_TIM6LPEN 5Ú P RCC_APB1LPENR_TIM7LPEN 4Ú P RCC_APB1LPENR_LCDLPEN Ú P RCC_APB1LPENR_WWDGLPEN Ú P RCC_APB1LPENR_SPI2LPEN 7Ú P RCC_APB1LPENR_SPI3LPEN 6Ú! P RCC_APB1LPENR_USART2LPEN Ú! P RCC_APB1LPENR_USART3LPEN Ú P RCC_APB1LPENR_UART4LPEN ãÚ P RCC_APB1LPENR_UART5LPEN âÚ P RCC_APB1LPENR_I2C1LPEN fÚ P RCC_APB1LPENR_I2C2LPEN eÚ P RCC_APB1LPENR_USBLPEN mÚ P RCC_APB1LPENR_PWRLPEN ^Ú P RCC_APB1LPENR_DACLPEN Ú P RCC_APB1LPENR_COMPLPEN &Ú P RCC_CSR_LSION ®Ú P RCC_CSR_LSIRDY ZÚ P RCC_CSR_LSEON ²Ú P RCC_CSR_LSERDY ^Ú P RCC_CSR_LSEBYP bÚ P RCC_CSR_LSECSSON ÃÚ P RCC_CSR_LSECSSD Ú P RCC_CSR_RTCSEL dÚ P RCC_CSR_RTCSEL_0 ÑÚ P RCC_CSR_RTCSEL_1 ÐÚ P RCC_CSR_RTCSEL_NOCLOCK ìÚ P RCC_CSR_RTCSEL_LSE Ú P RCC_CSR_RTCSEL_LSI Ú P RCC_CSR_RTCSEL_HSE Ú P RCC_CSR_RTCEN ·Ú P RCC_CSR_RTCRST OÚ P
RCC_CSR_RMVF úÚ P RCC_CSR_OBLRSTF Ú P RCC_CSR_PINRSTF Ú P RCC_CSR_PORRSTF ÿÚ P RCC_CSR_SFTRSTF Ú P RCC_CSR_IWDGRSTF ÃÚ P RCC_CSR_WWDGRSTF µÚ P RCC_CSR_LPWRRSTF ©Ú P |
| 799 |
RTC_TR_PM ÏÚ P |
799 |
RTC_TR_PM ÏÚ P |
| 800 |
RTC_TR_HT ÐÚ P RTC_TR_HT_0 =Ú P RTC_TR_HT_1 <Ú P |
800 |
RTC_TR_HT ÐÚ P RTC_TR_HT_0 =Ú P RTC_TR_HT_1 <Ú P |
| 801 |
RTC_TR_HU ÏÚ P RTC_TR_HU_0 <Ú P RTC_TR_HU_1 ;Ú P RTC_TR_HU_2 :Ú P RTC_TR_HU_3 9Ú P RTC_TR_MNT {Ú P
RTC_TR_MNT_0 èÚ P
RTC_TR_MNT_1 çÚ P
RTC_TR_MNT_2 æÚ P RTC_TR_MNU zÚ P
RTC_TR_MNU_0 çÚ P
RTC_TR_MNU_1 æÚ P
RTC_TR_MNU_2 åÚ P
RTC_TR_MNU_3 äÚ P |
801 |
RTC_TR_HU ÏÚ P RTC_TR_HU_0 <Ú P RTC_TR_HU_1 ;Ú P RTC_TR_HU_2 :Ú P RTC_TR_HU_3 9Ú P RTC_TR_MNT {Ú P
RTC_TR_MNT_0 èÚ P
RTC_TR_MNT_1 çÚ P
RTC_TR_MNT_2 æÚ P RTC_TR_MNU zÚ P
RTC_TR_MNU_0 çÚ P
RTC_TR_MNU_1 æÚ P
RTC_TR_MNU_2 åÚ P
RTC_TR_MNU_3 äÚ P |
| 802 |
RTC_TR_ST ÅÚ P RTC_TR_ST_0 2Ú P RTC_TR_ST_1 1Ú P RTC_TR_ST_2 0Ú P |
802 |
RTC_TR_ST ÅÚ P RTC_TR_ST_0 2Ú P RTC_TR_ST_1 1Ú P RTC_TR_ST_2 0Ú P |
| 803 |
RTC_TR_SU ÄÚ P RTC_TR_SU_0 1Ú P RTC_TR_SU_1 0Ú P RTC_TR_SU_2 /Ú P RTC_TR_SU_3 .Ú P |
803 |
RTC_TR_SU ÄÚ P RTC_TR_SU_0 1Ú P RTC_TR_SU_1 0Ú P RTC_TR_SU_2 /Ú P RTC_TR_SU_3 .Ú P |
| 804 |
RTC_DR_YT ÏÚ P RTC_DR_YT_0 <Ú P RTC_DR_YT_1 ;Ú P RTC_DR_YT_2 :Ú P RTC_DR_YT_3 9Ú P |
804 |
RTC_DR_YT ÏÚ P RTC_DR_YT_0 <Ú P RTC_DR_YT_1 ;Ú P RTC_DR_YT_2 :Ú P RTC_DR_YT_3 9Ú P |
| 805 |
RTC_DR_YU ÎÚ P RTC_DR_YU_0 ;Ú P RTC_DR_YU_1 :Ú P RTC_DR_YU_2 9Ú P RTC_DR_YU_3 8Ú P RTC_DR_WDU Ú P
RTC_DR_WDU_0 ÷Ú P
RTC_DR_WDU_1 öÚ P
RTC_DR_WDU_2 õÚ P |
805 |
RTC_DR_YU ÎÚ P RTC_DR_YU_0 ;Ú P RTC_DR_YU_1 :Ú P RTC_DR_YU_2 9Ú P RTC_DR_YU_3 8Ú P RTC_DR_WDU Ú P
RTC_DR_WDU_0 ÷Ú P
RTC_DR_WDU_1 öÚ P
RTC_DR_WDU_2 õÚ P |
| 806 |
RTC_DR_MT ÛÚ P |
806 |
RTC_DR_MT ÛÚ P |
| 807 |
RTC_DR_MU ÚÚ P RTC_DR_MU_0 GÚ P RTC_DR_MU_1 FÚ P RTC_DR_MU_2 EÚ P RTC_DR_MU_3 DÚ P |
807 |
RTC_DR_MU ÚÚ P RTC_DR_MU_0 GÚ P RTC_DR_MU_1 FÚ P RTC_DR_MU_2 EÚ P RTC_DR_MU_3 DÚ P |
| 808 |
RTC_DR_DT äÚ P RTC_DR_DT_0 QÚ P RTC_DR_DT_1 PÚ P |
808 |
RTC_DR_DT äÚ P RTC_DR_DT_0 QÚ P RTC_DR_DT_1 PÚ P |
| 809 |
RTC_DR_DU ãÚ P RTC_DR_DU_0 PÚ P RTC_DR_DU_1 OÚ P RTC_DR_DU_2 NÚ P RTC_DR_DU_3 MÚ P RTC_CR_COE ¤Ú P RTC_CR_OSEL FÚ P RTC_CR_OSEL_0 ³Ú P RTC_CR_OSEL_1 ²Ú P RTC_CR_POL Ú P
RTC_CR_COSEL Ú P RTC_CR_BCK «Ú P
RTC_CR_SUB1H Ú P
RTC_CR_ADD1H 5Ú P RTC_CR_TSIE DÚ P
RTC_CR_WUTIE éÚ P RTC_CR_ALRBIE ÆÚ P RTC_CR_ALRAIE ÇÚ P RTC_CR_TSE Ú P RTC_CR_WUTE 4Ú P
RTC_CR_ALRBE Ú P
RTC_CR_ALRAE Ú P RTC_CR_DCE ¯Ú P RTC_CR_FMT Ú P RTC_CR_BYPSHAD hÚ P RTC_CR_REFCKON kÚ P RTC_CR_TSEDGE ¹Ú P RTC_CR_WUCKSEL UÚ P RTC_CR_WUCKSEL_0 ÂÚ P RTC_CR_WUCKSEL_1 ÁÚ P RTC_CR_WUCKSEL_2 ÀÚ P RTC_ISR_RECALPF Ú P RTC_ISR_TAMP3F oÚ P RTC_ISR_TAMP2F pÚ P RTC_ISR_TAMP1F qÚ P RTC_ISR_TSOVF Ú P RTC_ISR_TSF 3Ú P
RTC_ISR_WUTF ØÚ P RTC_ISR_ALRBF µÚ P RTC_ISR_ALRAF ¶Ú P
RTC_ISR_INIT êÚ P RTC_ISR_INITF ¢Ú P RTC_ISR_RSF 5Ú P RTC_ISR_INITS Ú P
RTC_ISR_SHPF íÚ P RTC_ISR_WUTWF Ú P RTC_ISR_ALRBWF \Ú P RTC_ISR_ALRAWF ]Ú P RTC_PRER_PREDIV_A _Ú P RTC_PRER_PREDIV_S MÚ P
RTC_WUTR_WUT ºÚ P RTC_CALIBR_DCS Ú P RTC_CALIBR_DC ÖÚ P RTC_ALRMAR_MSK4 (Ú P RTC_ALRMAR_WDSEL ÆÚ P RTC_ALRMAR_DT ³Ú P RTC_ALRMAR_DT_0 Ú P RTC_ALRMAR_DT_1 Ú P RTC_ALRMAR_DU ²Ú P RTC_ALRMAR_DU_0 Ú P RTC_ALRMAR_DU_1 Ú P RTC_ALRMAR_DU_2 Ú P RTC_ALRMAR_DU_3 Ú P RTC_ALRMAR_MSK3 )Ú P RTC_ALRMAR_PM ®Ú P RTC_ALRMAR_HT ¯Ú P RTC_ALRMAR_HT_0 Ú P RTC_ALRMAR_HT_1 Ú P RTC_ALRMAR_HU ®Ú P RTC_ALRMAR_HU_0 Ú P RTC_ALRMAR_HU_1 Ú P RTC_ALRMAR_HU_2 Ú P RTC_ALRMAR_HU_3 Ú P RTC_ALRMAR_MSK2 *Ú P RTC_ALRMAR_MNT ZÚ P RTC_ALRMAR_MNT_0 ÇÚ P RTC_ALRMAR_MNT_1 ÆÚ P RTC_ALRMAR_MNT_2 ÅÚ P RTC_ALRMAR_MNU YÚ P RTC_ALRMAR_MNU_0 ÆÚ P RTC_ALRMAR_MNU_1 ÅÚ P RTC_ALRMAR_MNU_2 ÄÚ P RTC_ALRMAR_MNU_3 ÃÚ P RTC_ALRMAR_MSK1 +Ú P RTC_ALRMAR_ST ¤Ú P RTC_ALRMAR_ST_0 Ú P RTC_ALRMAR_ST_1 Ú P RTC_ALRMAR_ST_2 Ú P RTC_ALRMAR_SU £Ú P RTC_ALRMAR_SU_0 Ú P RTC_ALRMAR_SU_1 Ú P RTC_ALRMAR_SU_2 Ú P RTC_ALRMAR_SU_3
Ú P RTC_ALRMBR_MSK4 'Ú P RTC_ALRMBR_WDSEL ÅÚ P RTC_ALRMBR_DT ²Ú P RTC_ALRMBR_DT_0 Ú P RTC_ALRMBR_DT_1 Ú P RTC_ALRMBR_DU ±Ú P RTC_ALRMBR_DU_0 Ú P RTC_ALRMBR_DU_1 Ú P RTC_ALRMBR_DU_2 Ú P RTC_ALRMBR_DU_3 Ú P RTC_ALRMBR_MSK3 (Ú P RTC_ALRMBR_PM Ú P RTC_ALRMBR_HT ®Ú P RTC_ALRMBR_HT_0 Ú P RTC_ALRMBR_HT_1 Ú P RTC_ALRMBR_HU Ú P RTC_ALRMBR_HU_0 Ú P RTC_ALRMBR_HU_1 Ú P RTC_ALRMBR_HU_2 Ú P RTC_ALRMBR_HU_3 Ú P RTC_ALRMBR_MSK2 )Ú P RTC_ALRMBR_MNT YÚ P RTC_ALRMBR_MNT_0 ÆÚ P RTC_ALRMBR_MNT_1 ÅÚ P RTC_ALRMBR_MNT_2 ÄÚ P RTC_ALRMBR_MNU XÚ P RTC_ALRMBR_MNU_0 ÅÚ P RTC_ALRMBR_MNU_1 ÄÚ P RTC_ALRMBR_MNU_2 ÃÚ P RTC_ALRMBR_MNU_3 ÂÚ P RTC_ALRMBR_MSK1 *Ú P RTC_ALRMBR_ST £Ú P RTC_ALRMBR_ST_0 Ú P RTC_ALRMBR_ST_1 Ú P RTC_ALRMBR_ST_2 Ú P RTC_ALRMBR_SU ¢Ú P RTC_ALRMBR_SU_0 Ú P RTC_ALRMBR_SU_1 Ú P RTC_ALRMBR_SU_2
Ú P RTC_ALRMBR_SU_3 Ú P RTC_WPR_KEY ,Ú P RTC_SSR_SS rÚ P RTC_SHIFTR_SUBFS ±Ú P RTC_SHIFTR_ADD1S çÚ P RTC_TSTR_PM $Ú P RTC_TSTR_HT %Ú P RTC_TSTR_HT_0 Ú P RTC_TSTR_HT_1 Ú P RTC_TSTR_HU $Ú P RTC_TSTR_HU_0 Ú P RTC_TSTR_HU_1 Ú P RTC_TSTR_HU_2 Ú P RTC_TSTR_HU_3 Ú P
RTC_TSTR_MNT ÐÚ P RTC_TSTR_MNT_0 =Ú P RTC_TSTR_MNT_1 <Ú P RTC_TSTR_MNT_2 ;Ú P
RTC_TSTR_MNU ÏÚ P RTC_TSTR_MNU_0 <Ú P RTC_TSTR_MNU_1 ;Ú P RTC_TSTR_MNU_2 :Ú P RTC_TSTR_MNU_3 9Ú P RTC_TSTR_ST Ú P RTC_TSTR_ST_0 Ú P RTC_TSTR_ST_1 Ú P RTC_TSTR_ST_2
Ú P RTC_TSTR_SU Ú P RTC_TSTR_SU_0 Ú P RTC_TSTR_SU_1
Ú P RTC_TSTR_SU_2 Ú P RTC_TSTR_SU_3 Ú P
RTC_TSDR_WDU ßÚ P RTC_TSDR_WDU_0 LÚ P RTC_TSDR_WDU_1 KÚ P RTC_TSDR_WDU_2 JÚ P RTC_TSDR_MT 0Ú P RTC_TSDR_MU /Ú P RTC_TSDR_MU_0 Ú P RTC_TSDR_MU_1 Ú P RTC_TSDR_MU_2 Ú P RTC_TSDR_MU_3 Ú P RTC_TSDR_DT 9Ú P RTC_TSDR_DT_0 ¦Ú P RTC_TSDR_DT_1 ¥Ú P RTC_TSDR_DU 8Ú P RTC_TSDR_DU_0 ¥Ú P RTC_TSDR_DU_1 ¤Ú P RTC_TSDR_DU_2 £Ú P RTC_TSDR_DU_3 ¢Ú P
RTC_TSSSR_SS ÇÚ P RTC_CALR_CALP ÈÚ P RTC_CALR_CALW8 Ú P RTC_CALR_CALW16 VÚ P RTC_CALR_CALM ËÚ P RTC_CALR_CALM_0 8Ú P RTC_CALR_CALM_1 7Ú P RTC_CALR_CALM_2 6Ú P RTC_CALR_CALM_3 5Ú P RTC_CALR_CALM_4 4Ú P RTC_CALR_CALM_5 3Ú P RTC_CALR_CALM_6 2Ú P RTC_CALR_CALM_7 1Ú P RTC_CALR_CALM_8 0Ú P RTC_TAFCR_ALARMOUTTYPE áÚ P RTC_TAFCR_TAMPPUDIS ×Ú P RTC_TAFCR_TAMPPRCH 1Ú P RTC_TAFCR_TAMPPRCH_0 Ú P RTC_TAFCR_TAMPPRCH_1 Ú P RTC_TAFCR_TAMPFLT zÚ P RTC_TAFCR_TAMPFLT_0 çÚ P RTC_TAFCR_TAMPFLT_1 æÚ P RTC_TAFCR_TAMPFREQ 0Ú P RTC_TAFCR_TAMPFREQ_0 Ú P RTC_TAFCR_TAMPFREQ_1 Ú P RTC_TAFCR_TAMPFREQ_2 Ú P RTC_TAFCR_TAMPTS »Ú P RTC_TAFCR_TAMP3TRG >Ú P RTC_TAFCR_TAMP3E êÚ P RTC_TAFCR_TAMP2TRG ?Ú P RTC_TAFCR_TAMP2E ëÚ P RTC_TAFCR_TAMPIE ÔÚ P RTC_TAFCR_TAMP1TRG @Ú P RTC_TAFCR_TAMP1E ìÚ P RTC_ALRMASSR_MASKSS ÇÚ P RTC_ALRMASSR_MASKSS_0 4Ú P RTC_ALRMASSR_MASKSS_1 3Ú P RTC_ALRMASSR_MASKSS_2 2Ú P RTC_ALRMASSR_MASKSS_3 1Ú P RTC_ALRMASSR_SS ûÚ P RTC_ALRMBSSR_MASKSS ÆÚ P RTC_ALRMBSSR_MASKSS_0 3Ú P RTC_ALRMBSSR_MASKSS_1 2Ú P RTC_ALRMBSSR_MASKSS_2 1Ú P RTC_ALRMBSSR_MASKSS_3 0Ú P RTC_ALRMBSSR_SS úÚ P |
809 |
RTC_DR_DU ãÚ P RTC_DR_DU_0 PÚ P RTC_DR_DU_1 OÚ P RTC_DR_DU_2 NÚ P RTC_DR_DU_3 MÚ P RTC_CR_COE ¤Ú P RTC_CR_OSEL FÚ P RTC_CR_OSEL_0 ³Ú P RTC_CR_OSEL_1 ²Ú P RTC_CR_POL Ú P
RTC_CR_COSEL Ú P RTC_CR_BCK «Ú P
RTC_CR_SUB1H Ú P
RTC_CR_ADD1H 5Ú P RTC_CR_TSIE DÚ P
RTC_CR_WUTIE éÚ P RTC_CR_ALRBIE ÆÚ P RTC_CR_ALRAIE ÇÚ P RTC_CR_TSE Ú P RTC_CR_WUTE 4Ú P
RTC_CR_ALRBE Ú P
RTC_CR_ALRAE Ú P RTC_CR_DCE ¯Ú P RTC_CR_FMT Ú P RTC_CR_BYPSHAD hÚ P RTC_CR_REFCKON kÚ P RTC_CR_TSEDGE ¹Ú P RTC_CR_WUCKSEL UÚ P RTC_CR_WUCKSEL_0 ÂÚ P RTC_CR_WUCKSEL_1 ÁÚ P RTC_CR_WUCKSEL_2 ÀÚ P RTC_ISR_RECALPF Ú P RTC_ISR_TAMP3F oÚ P RTC_ISR_TAMP2F pÚ P RTC_ISR_TAMP1F qÚ P RTC_ISR_TSOVF Ú P RTC_ISR_TSF 3Ú P
RTC_ISR_WUTF ØÚ P RTC_ISR_ALRBF µÚ P RTC_ISR_ALRAF ¶Ú P
RTC_ISR_INIT êÚ P RTC_ISR_INITF ¢Ú P RTC_ISR_RSF 5Ú P RTC_ISR_INITS Ú P
RTC_ISR_SHPF íÚ P RTC_ISR_WUTWF Ú P RTC_ISR_ALRBWF \Ú P RTC_ISR_ALRAWF ]Ú P RTC_PRER_PREDIV_A _Ú P RTC_PRER_PREDIV_S MÚ P
RTC_WUTR_WUT ºÚ P RTC_CALIBR_DCS Ú P RTC_CALIBR_DC ÖÚ P RTC_ALRMAR_MSK4 (Ú P RTC_ALRMAR_WDSEL ÆÚ P RTC_ALRMAR_DT ³Ú P RTC_ALRMAR_DT_0 Ú P RTC_ALRMAR_DT_1 Ú P RTC_ALRMAR_DU ²Ú P RTC_ALRMAR_DU_0 Ú P RTC_ALRMAR_DU_1 Ú P RTC_ALRMAR_DU_2 Ú P RTC_ALRMAR_DU_3 Ú P RTC_ALRMAR_MSK3 )Ú P RTC_ALRMAR_PM ®Ú P RTC_ALRMAR_HT ¯Ú P RTC_ALRMAR_HT_0 Ú P RTC_ALRMAR_HT_1 Ú P RTC_ALRMAR_HU ®Ú P RTC_ALRMAR_HU_0 Ú P RTC_ALRMAR_HU_1 Ú P RTC_ALRMAR_HU_2 Ú P RTC_ALRMAR_HU_3 Ú P RTC_ALRMAR_MSK2 *Ú P RTC_ALRMAR_MNT ZÚ P RTC_ALRMAR_MNT_0 ÇÚ P RTC_ALRMAR_MNT_1 ÆÚ P RTC_ALRMAR_MNT_2 ÅÚ P RTC_ALRMAR_MNU YÚ P RTC_ALRMAR_MNU_0 ÆÚ P RTC_ALRMAR_MNU_1 ÅÚ P RTC_ALRMAR_MNU_2 ÄÚ P RTC_ALRMAR_MNU_3 ÃÚ P RTC_ALRMAR_MSK1 +Ú P RTC_ALRMAR_ST ¤Ú P RTC_ALRMAR_ST_0 Ú P RTC_ALRMAR_ST_1 Ú P RTC_ALRMAR_ST_2 Ú P RTC_ALRMAR_SU £Ú P RTC_ALRMAR_SU_0 Ú P RTC_ALRMAR_SU_1 Ú P RTC_ALRMAR_SU_2 Ú P RTC_ALRMAR_SU_3
Ú P RTC_ALRMBR_MSK4 'Ú P RTC_ALRMBR_WDSEL ÅÚ P RTC_ALRMBR_DT ²Ú P RTC_ALRMBR_DT_0 Ú P RTC_ALRMBR_DT_1 Ú P RTC_ALRMBR_DU ±Ú P RTC_ALRMBR_DU_0 Ú P RTC_ALRMBR_DU_1 Ú P RTC_ALRMBR_DU_2 Ú P RTC_ALRMBR_DU_3 Ú P RTC_ALRMBR_MSK3 (Ú P RTC_ALRMBR_PM Ú P RTC_ALRMBR_HT ®Ú P RTC_ALRMBR_HT_0 Ú P RTC_ALRMBR_HT_1 Ú P RTC_ALRMBR_HU Ú P RTC_ALRMBR_HU_0 Ú P RTC_ALRMBR_HU_1 Ú P RTC_ALRMBR_HU_2 Ú P RTC_ALRMBR_HU_3 Ú P RTC_ALRMBR_MSK2 )Ú P RTC_ALRMBR_MNT YÚ P RTC_ALRMBR_MNT_0 ÆÚ P RTC_ALRMBR_MNT_1 ÅÚ P RTC_ALRMBR_MNT_2 ÄÚ P RTC_ALRMBR_MNU XÚ P RTC_ALRMBR_MNU_0 ÅÚ P RTC_ALRMBR_MNU_1 ÄÚ P RTC_ALRMBR_MNU_2 ÃÚ P RTC_ALRMBR_MNU_3 ÂÚ P RTC_ALRMBR_MSK1 *Ú P RTC_ALRMBR_ST £Ú P RTC_ALRMBR_ST_0 Ú P RTC_ALRMBR_ST_1 Ú P RTC_ALRMBR_ST_2 Ú P RTC_ALRMBR_SU ¢Ú P RTC_ALRMBR_SU_0 Ú P RTC_ALRMBR_SU_1 Ú P RTC_ALRMBR_SU_2
Ú P RTC_ALRMBR_SU_3 Ú P RTC_WPR_KEY ,Ú P RTC_SSR_SS rÚ P RTC_SHIFTR_SUBFS ±Ú P RTC_SHIFTR_ADD1S çÚ P RTC_TSTR_PM $Ú P RTC_TSTR_HT %Ú P RTC_TSTR_HT_0 Ú P RTC_TSTR_HT_1 Ú P RTC_TSTR_HU $Ú P RTC_TSTR_HU_0 Ú P RTC_TSTR_HU_1 Ú P RTC_TSTR_HU_2 Ú P RTC_TSTR_HU_3 Ú P
RTC_TSTR_MNT ÐÚ P RTC_TSTR_MNT_0 =Ú P RTC_TSTR_MNT_1 <Ú P RTC_TSTR_MNT_2 ;Ú P
RTC_TSTR_MNU ÏÚ P RTC_TSTR_MNU_0 <Ú P RTC_TSTR_MNU_1 ;Ú P RTC_TSTR_MNU_2 :Ú P RTC_TSTR_MNU_3 9Ú P RTC_TSTR_ST Ú P RTC_TSTR_ST_0 Ú P RTC_TSTR_ST_1 Ú P RTC_TSTR_ST_2
Ú P RTC_TSTR_SU Ú P RTC_TSTR_SU_0 Ú P RTC_TSTR_SU_1
Ú P RTC_TSTR_SU_2 Ú P RTC_TSTR_SU_3 Ú P
RTC_TSDR_WDU ßÚ P RTC_TSDR_WDU_0 LÚ P RTC_TSDR_WDU_1 KÚ P RTC_TSDR_WDU_2 JÚ P RTC_TSDR_MT 0Ú P RTC_TSDR_MU /Ú P RTC_TSDR_MU_0 Ú P RTC_TSDR_MU_1 Ú P RTC_TSDR_MU_2 Ú P RTC_TSDR_MU_3 Ú P RTC_TSDR_DT 9Ú P RTC_TSDR_DT_0 ¦Ú P RTC_TSDR_DT_1 ¥Ú P RTC_TSDR_DU 8Ú P RTC_TSDR_DU_0 ¥Ú P RTC_TSDR_DU_1 ¤Ú P RTC_TSDR_DU_2 £Ú P RTC_TSDR_DU_3 ¢Ú P
RTC_TSSSR_SS ÇÚ P RTC_CALR_CALP ÈÚ P RTC_CALR_CALW8 Ú P RTC_CALR_CALW16 VÚ P RTC_CALR_CALM ËÚ P RTC_CALR_CALM_0 8Ú P RTC_CALR_CALM_1 7Ú P RTC_CALR_CALM_2 6Ú P RTC_CALR_CALM_3 5Ú P RTC_CALR_CALM_4 4Ú P RTC_CALR_CALM_5 3Ú P RTC_CALR_CALM_6 2Ú P RTC_CALR_CALM_7 1Ú P RTC_CALR_CALM_8 0Ú P RTC_TAFCR_ALARMOUTTYPE áÚ P RTC_TAFCR_TAMPPUDIS ×Ú P RTC_TAFCR_TAMPPRCH 1Ú P RTC_TAFCR_TAMPPRCH_0 Ú P RTC_TAFCR_TAMPPRCH_1 Ú P RTC_TAFCR_TAMPFLT zÚ P RTC_TAFCR_TAMPFLT_0 çÚ P RTC_TAFCR_TAMPFLT_1 æÚ P RTC_TAFCR_TAMPFREQ 0Ú P RTC_TAFCR_TAMPFREQ_0 Ú P RTC_TAFCR_TAMPFREQ_1 Ú P RTC_TAFCR_TAMPFREQ_2 Ú P RTC_TAFCR_TAMPTS »Ú P RTC_TAFCR_TAMP3TRG >Ú P RTC_TAFCR_TAMP3E êÚ P RTC_TAFCR_TAMP2TRG ?Ú P RTC_TAFCR_TAMP2E ëÚ P RTC_TAFCR_TAMPIE ÔÚ P RTC_TAFCR_TAMP1TRG @Ú P RTC_TAFCR_TAMP1E ìÚ P RTC_ALRMASSR_MASKSS ÇÚ P RTC_ALRMASSR_MASKSS_0 4Ú P RTC_ALRMASSR_MASKSS_1 3Ú P RTC_ALRMASSR_MASKSS_2 2Ú P RTC_ALRMASSR_MASKSS_3 1Ú P RTC_ALRMASSR_SS ûÚ P RTC_ALRMBSSR_MASKSS ÆÚ P RTC_ALRMBSSR_MASKSS_0 3Ú P RTC_ALRMBSSR_MASKSS_1 2Ú P RTC_ALRMBSSR_MASKSS_2 1Ú P RTC_ALRMBSSR_MASKSS_3 0Ú P RTC_ALRMBSSR_SS úÚ P |
| 810 |
RTC_BKP0R Ú P |
810 |
RTC_BKP0R Ú P |
| 811 |
RTC_BKP1R Ú P |
811 |
RTC_BKP1R Ú P |
| 812 |
RTC_BKP2R Ú P |
812 |
RTC_BKP2R Ú P |
| 813 |
RTC_BKP3R Ú P |
813 |
RTC_BKP3R Ú P |
| 814 |
RTC_BKP4R Ú P |
814 |
RTC_BKP4R Ú P |
| 815 |
RTC_BKP5R
Ú P |
815 |
RTC_BKP5R
Ú P |
| 816 |
RTC_BKP6R Ú P |
816 |
RTC_BKP6R Ú P |
| 817 |
RTC_BKP7R Ú P |
817 |
RTC_BKP7R Ú P |
| 818 |
RTC_BKP8R |
818 |
RTC_BKP8R |
| 819 |
Ú P |
819 |
Ú P |
| 820 |
RTC_BKP9R Ú P RTC_BKP10R ßÚ P RTC_BKP11R ÞÚ P RTC_BKP12R ÝÚ P RTC_BKP13R ÜÚ P RTC_BKP14R ÛÚ P RTC_BKP15R ÚÚ P RTC_BKP16R ÙÚ P RTC_BKP17R ØÚ P RTC_BKP18R ×Ú P RTC_BKP19R ÖÚ P RTC_BKP20R ÞÚ P RTC_BKP21R ÝÚ P RTC_BKP22R ÜÚ P RTC_BKP23R ÛÚ P RTC_BKP24R ÚÚ P RTC_BKP25R ÙÚ P RTC_BKP26R ØÚ P RTC_BKP27R ×Ú P RTC_BKP28R ÖÚ P RTC_BKP29R ÕÚ P RTC_BKP30R ÝÚ P RTC_BKP31R ÜÚ P SDIO_POWER_PWRCTRL ÿÚ P SDIO_POWER_PWRCTRL_0 lÚ P SDIO_POWER_PWRCTRL_1 kÚ P SDIO_CLKCR_CLKDIV Ú P SDIO_CLKCR_CLKEN âÚ P SDIO_CLKCR_PWRSAV jÚ P SDIO_CLKCR_BYPASS {Ú P SDIO_CLKCR_WIDBUS Ú P SDIO_CLKCR_WIDBUS_0 ìÚ P SDIO_CLKCR_WIDBUS_1 ëÚ P SDIO_CLKCR_NEGEDGE \Ú P SDIO_CLKCR_HWFC_EN 1Ú P SDIO_ARG_CMDARG 8Ú P SDIO_CMD_CMDINDEX Ú P SDIO_CMD_WAITRESP yÚ P SDIO_CMD_WAITRESP_0 æÚ P SDIO_CMD_WAITRESP_1 åÚ P SDIO_CMD_WAITINT ÊÚ P SDIO_CMD_WAITPEND Ú P SDIO_CMD_CPSMEN &Ú P SDIO_CMD_SDIOSUSPEND Ú P SDIO_CMD_ENCMDCOMPL Ú P SDIO_CMD_NIEN ÆÚ P SDIO_CMD_CEATACMD ¶Ú P SDIO_RESPCMD_RESPCMD Ú P SDIO_RESP0_CARDSTATUS0 Ú P SDIO_RESP1_CARDSTATUS1 Ú P SDIO_RESP2_CARDSTATUS2 Ú P SDIO_RESP3_CARDSTATUS3 Ú P SDIO_RESP4_CARDSTATUS4 Ú P SDIO_DTIMER_DATATIME ¨Ú P SDIO_DLEN_DATALENGTH ·Ú P SDIO_DCTRL_DTEN Ú P SDIO_DCTRL_DTDIR ÎÚ P SDIO_DCTRL_DTMODE Ú P SDIO_DCTRL_DMAEN àÚ P SDIO_DCTRL_DBLOCKSIZE QÚ P SDIO_DCTRL_DBLOCKSIZE_0 ¾Ú P SDIO_DCTRL_DBLOCKSIZE_1 ½Ú P SDIO_DCTRL_DBLOCKSIZE_2 ¼Ú P SDIO_DCTRL_DBLOCKSIZE_3 »Ú P SDIO_DCTRL_RWSTART |
820 |
RTC_BKP9R Ú P RTC_BKP10R ßÚ P RTC_BKP11R ÞÚ P RTC_BKP12R ÝÚ P RTC_BKP13R ÜÚ P RTC_BKP14R ÛÚ P RTC_BKP15R ÚÚ P RTC_BKP16R ÙÚ P RTC_BKP17R ØÚ P RTC_BKP18R ×Ú P RTC_BKP19R ÖÚ P RTC_BKP20R ÞÚ P RTC_BKP21R ÝÚ P RTC_BKP22R ÜÚ P RTC_BKP23R ÛÚ P RTC_BKP24R ÚÚ P RTC_BKP25R ÙÚ P RTC_BKP26R ØÚ P RTC_BKP27R ×Ú P RTC_BKP28R ÖÚ P RTC_BKP29R ÕÚ P RTC_BKP30R ÝÚ P RTC_BKP31R ÜÚ P SDIO_POWER_PWRCTRL ÿÚ P SDIO_POWER_PWRCTRL_0 lÚ P SDIO_POWER_PWRCTRL_1 kÚ P SDIO_CLKCR_CLKDIV Ú P SDIO_CLKCR_CLKEN âÚ P SDIO_CLKCR_PWRSAV jÚ P SDIO_CLKCR_BYPASS {Ú P SDIO_CLKCR_WIDBUS Ú P SDIO_CLKCR_WIDBUS_0 ìÚ P SDIO_CLKCR_WIDBUS_1 ëÚ P SDIO_CLKCR_NEGEDGE \Ú P SDIO_CLKCR_HWFC_EN 1Ú P SDIO_ARG_CMDARG 8Ú P SDIO_CMD_CMDINDEX Ú P SDIO_CMD_WAITRESP yÚ P SDIO_CMD_WAITRESP_0 æÚ P SDIO_CMD_WAITRESP_1 åÚ P SDIO_CMD_WAITINT ÊÚ P SDIO_CMD_WAITPEND Ú P SDIO_CMD_CPSMEN &Ú P SDIO_CMD_SDIOSUSPEND Ú P SDIO_CMD_ENCMDCOMPL Ú P SDIO_CMD_NIEN ÆÚ P SDIO_CMD_CEATACMD ¶Ú P SDIO_RESPCMD_RESPCMD Ú P SDIO_RESP0_CARDSTATUS0 Ú P SDIO_RESP1_CARDSTATUS1 Ú P SDIO_RESP2_CARDSTATUS2 Ú P SDIO_RESP3_CARDSTATUS3 Ú P SDIO_RESP4_CARDSTATUS4 Ú P SDIO_DTIMER_DATATIME ¨Ú P SDIO_DLEN_DATALENGTH ·Ú P SDIO_DCTRL_DTEN Ú P SDIO_DCTRL_DTDIR ÎÚ P SDIO_DCTRL_DTMODE Ú P SDIO_DCTRL_DMAEN àÚ P SDIO_DCTRL_DBLOCKSIZE QÚ P SDIO_DCTRL_DBLOCKSIZE_0 ¾Ú P SDIO_DCTRL_DBLOCKSIZE_1 ½Ú P SDIO_DCTRL_DBLOCKSIZE_2 ¼Ú P SDIO_DCTRL_DBLOCKSIZE_3 »Ú P SDIO_DCTRL_RWSTART |
| 821 |
Ú P SDIO_DCTRL_RWSTOP TÚ P SDIO_DCTRL_RWMOD ¼Ú P SDIO_DCTRL_SDIOEN Ú P SDIO_DCOUNT_DATACOUNT DÚ P SDIO_STA_CCRCFAIL Ú P SDIO_STA_DCRCFAIL Ú P SDIO_STA_CTIMEOUT jÚ P SDIO_STA_DTIMEOUT iÚ P SDIO_STA_TXUNDERR XÚ P SDIO_STA_RXOVERR Ú P SDIO_STA_CMDREND ÙÚ P SDIO_STA_CMDSENT ÈÚ P SDIO_STA_DATAEND åÚ P SDIO_STA_STBITERR eÚ P SDIO_STA_DBCKEND ëÚ P SDIO_STA_CMDACT ,Ú P SDIO_STA_TXACT VÚ P SDIO_STA_RXACT XÚ P SDIO_STA_TXFIFOHE wÚ P SDIO_STA_RXFIFOHF xÚ P SDIO_STA_TXFIFOF ÀÚ P SDIO_STA_RXFIFOF ÂÚ P SDIO_STA_TXFIFOE ÁÚ P SDIO_STA_RXFIFOE ÃÚ P SDIO_STA_TXDAVL Ú P SDIO_STA_RXDAVL Ú P SDIO_STA_SDIOIT Ú P SDIO_STA_CEATAEND Ú P SDIO_ICR_CCRCFAILC bÚ P SDIO_ICR_DCRCFAILC aÚ P SDIO_ICR_CTIMEOUTC /Ú P SDIO_ICR_DTIMEOUTC .Ú P SDIO_ICR_TXUNDERRC Ú P SDIO_ICR_RXOVERRC cÚ P SDIO_ICR_CMDRENDC Ú P SDIO_ICR_CMDSENTC Ú P SDIO_ICR_DATAENDC ªÚ P SDIO_ICR_STBITERRC *Ú P SDIO_ICR_DBCKENDC °Ú P SDIO_ICR_SDIOITC ÑÚ P SDIO_ICR_CEATAENDC dÚ P SDIO_MASK_CCRCFAILIE ÅÚ P SDIO_MASK_DCRCFAILIE ÄÚ P SDIO_MASK_CTIMEOUTIE Ú P SDIO_MASK_DTIMEOUTIE Ú P SDIO_MASK_TXUNDERRIE Ú P SDIO_MASK_RXOVERRIE ÆÚ P SDIO_MASK_CMDRENDIE Ú P SDIO_MASK_CMDSENTIE ðÚ P SDIO_MASK_DATAENDIE
Ú P SDIO_MASK_STBITERRIE Ú P SDIO_MASK_DBCKENDIE Ú P SDIO_MASK_CMDACTIE TÚ P SDIO_MASK_TXACTIE ~Ú P SDIO_MASK_RXACTIE Ú P SDIO_MASK_TXFIFOHEIE Ú P SDIO_MASK_RXFIFOHFIE Ú P SDIO_MASK_TXFIFOFIE èÚ P SDIO_MASK_RXFIFOFIE êÚ P SDIO_MASK_TXFIFOEIE éÚ P SDIO_MASK_RXFIFOEIE ëÚ P SDIO_MASK_TXDAVLIE -Ú P SDIO_MASK_RXDAVLIE /Ú P SDIO_MASK_SDIOITIE 4Ú P SDIO_MASK_CEATAENDIE ÇÚ P SDIO_FIFOCNT_FIFOCOUNT üÚ P SDIO_FIFO_FIFODATA XÚ P
SPI_CR1_CPHA 'Ú P
SPI_CR1_CPOL Ú P
SPI_CR1_MSTR ýÚ P SPI_CR1_BR ³Ú P
SPI_CR1_BR_0 Ú P
SPI_CR1_BR_1 Ú P
SPI_CR1_BR_2 Ú P SPI_CR1_SPE ]Ú P SPI_CR1_LSBFIRST ÒÚ P SPI_CR1_SSI VÚ P SPI_CR1_SSM RÚ P SPI_CR1_RXONLY SÚ P SPI_CR1_DFF uÚ P SPI_CR1_CRCNEXT &Ú P SPI_CR1_CRCEN ÖÚ P SPI_CR1_BIDIOE Ú P SPI_CR1_BIDIMODE þÚ P SPI_CR2_RXDMAEN -Ú P SPI_CR2_TXDMAEN +Ú P
SPI_CR2_SSOE Ú P SPI_CR2_FRF fÚ P SPI_CR2_ERRIE ÉÚ P SPI_CR2_RXNEIE sÚ P SPI_CR2_TXEIE ÁÚ P SPI_SR_RXNE )Ú P SPI_SR_TXE wÚ P SPI_SR_CHSIDE ²Ú P SPI_SR_UDR }Ú P SPI_SR_CRCERR ¡Ú P SPI_SR_MODF @Ú P SPI_SR_OVR qÚ P SPI_SR_BSY zÚ P |
821 |
Ú P SDIO_DCTRL_RWSTOP TÚ P SDIO_DCTRL_RWMOD ¼Ú P SDIO_DCTRL_SDIOEN Ú P SDIO_DCOUNT_DATACOUNT DÚ P SDIO_STA_CCRCFAIL Ú P SDIO_STA_DCRCFAIL Ú P SDIO_STA_CTIMEOUT jÚ P SDIO_STA_DTIMEOUT iÚ P SDIO_STA_TXUNDERR XÚ P SDIO_STA_RXOVERR Ú P SDIO_STA_CMDREND ÙÚ P SDIO_STA_CMDSENT ÈÚ P SDIO_STA_DATAEND åÚ P SDIO_STA_STBITERR eÚ P SDIO_STA_DBCKEND ëÚ P SDIO_STA_CMDACT ,Ú P SDIO_STA_TXACT VÚ P SDIO_STA_RXACT XÚ P SDIO_STA_TXFIFOHE wÚ P SDIO_STA_RXFIFOHF xÚ P SDIO_STA_TXFIFOF ÀÚ P SDIO_STA_RXFIFOF ÂÚ P SDIO_STA_TXFIFOE ÁÚ P SDIO_STA_RXFIFOE ÃÚ P SDIO_STA_TXDAVL Ú P SDIO_STA_RXDAVL Ú P SDIO_STA_SDIOIT Ú P SDIO_STA_CEATAEND Ú P SDIO_ICR_CCRCFAILC bÚ P SDIO_ICR_DCRCFAILC aÚ P SDIO_ICR_CTIMEOUTC /Ú P SDIO_ICR_DTIMEOUTC .Ú P SDIO_ICR_TXUNDERRC Ú P SDIO_ICR_RXOVERRC cÚ P SDIO_ICR_CMDRENDC Ú P SDIO_ICR_CMDSENTC Ú P SDIO_ICR_DATAENDC ªÚ P SDIO_ICR_STBITERRC *Ú P SDIO_ICR_DBCKENDC °Ú P SDIO_ICR_SDIOITC ÑÚ P SDIO_ICR_CEATAENDC dÚ P SDIO_MASK_CCRCFAILIE ÅÚ P SDIO_MASK_DCRCFAILIE ÄÚ P SDIO_MASK_CTIMEOUTIE Ú P SDIO_MASK_DTIMEOUTIE Ú P SDIO_MASK_TXUNDERRIE Ú P SDIO_MASK_RXOVERRIE ÆÚ P SDIO_MASK_CMDRENDIE Ú P SDIO_MASK_CMDSENTIE ðÚ P SDIO_MASK_DATAENDIE
Ú P SDIO_MASK_STBITERRIE Ú P SDIO_MASK_DBCKENDIE Ú P SDIO_MASK_CMDACTIE TÚ P SDIO_MASK_TXACTIE ~Ú P SDIO_MASK_RXACTIE Ú P SDIO_MASK_TXFIFOHEIE Ú P SDIO_MASK_RXFIFOHFIE Ú P SDIO_MASK_TXFIFOFIE èÚ P SDIO_MASK_RXFIFOFIE êÚ P SDIO_MASK_TXFIFOEIE éÚ P SDIO_MASK_RXFIFOEIE ëÚ P SDIO_MASK_TXDAVLIE -Ú P SDIO_MASK_RXDAVLIE /Ú P SDIO_MASK_SDIOITIE 4Ú P SDIO_MASK_CEATAENDIE ÇÚ P SDIO_FIFOCNT_FIFOCOUNT üÚ P SDIO_FIFO_FIFODATA XÚ P
SPI_CR1_CPHA 'Ú P
SPI_CR1_CPOL Ú P
SPI_CR1_MSTR ýÚ P SPI_CR1_BR ³Ú P
SPI_CR1_BR_0 Ú P
SPI_CR1_BR_1 Ú P
SPI_CR1_BR_2 Ú P SPI_CR1_SPE ]Ú P SPI_CR1_LSBFIRST ÒÚ P SPI_CR1_SSI VÚ P SPI_CR1_SSM RÚ P SPI_CR1_RXONLY SÚ P SPI_CR1_DFF uÚ P SPI_CR1_CRCNEXT &Ú P SPI_CR1_CRCEN ÖÚ P SPI_CR1_BIDIOE Ú P SPI_CR1_BIDIMODE þÚ P SPI_CR2_RXDMAEN -Ú P SPI_CR2_TXDMAEN +Ú P
SPI_CR2_SSOE Ú P SPI_CR2_FRF fÚ P SPI_CR2_ERRIE ÉÚ P SPI_CR2_RXNEIE sÚ P SPI_CR2_TXEIE ÁÚ P SPI_SR_RXNE )Ú P SPI_SR_TXE wÚ P SPI_SR_CHSIDE ²Ú P SPI_SR_UDR }Ú P SPI_SR_CRCERR ¡Ú P SPI_SR_MODF @Ú P SPI_SR_OVR qÚ P SPI_SR_BSY zÚ P |
| 822 |
SPI_DR_DR ãÚ P SPI_CRCPR_CRCPOLY iÚ P SPI_RXCRCR_RXCRC «Ú P SPI_TXCRCR_TXCRC §Ú P SPI_I2SCFGR_CHLEN ¥Ú P SPI_I2SCFGR_DATLEN UÚ P SPI_I2SCFGR_DATLEN_0 ÂÚ P SPI_I2SCFGR_DATLEN_1 ÁÚ P SPI_I2SCFGR_CKPOL Ú P SPI_I2SCFGR_I2SSTD TÚ P SPI_I2SCFGR_I2SSTD_0 ÁÚ P SPI_I2SCFGR_I2SSTD_1 ÀÚ P SPI_I2SCFGR_PCMSYNC îÚ P SPI_I2SCFGR_I2SCFG oÚ P SPI_I2SCFGR_I2SCFG_0 ÜÚ P SPI_I2SCFGR_I2SCFG_1 ÛÚ P SPI_I2SCFGR_I2SE þÚ P SPI_I2SCFGR_I2SMOD _Ú P SPI_I2SPR_I2SDIV àÚ P SPI_I2SPR_ODD ÀÚ P SPI_I2SPR_MCKOE $Ú P SYSCFG_MEMRMP_MEM_MODE áÚ! P SYSCFG_MEMRMP_MEM_MODE_0 NÚ! P SYSCFG_MEMRMP_MEM_MODE_1 MÚ P SYSCFG_MEMRMP_BOOT_MODE Ú" P SYSCFG_MEMRMP_BOOT_MODE_0 ÷Ú" P SYSCFG_MEMRMP_BOOT_MODE_1 öÚ P SYSCFG_PMC_USB_PU NÚ P SYSCFG_EXTICR1_EXTI0 ¬Ú P SYSCFG_EXTICR1_EXTI1 «Ú P SYSCFG_EXTICR1_EXTI2 ªÚ P SYSCFG_EXTICR1_EXTI3 ©Ú P SYSCFG_EXTICR1_EXTI0_PA ¶Ú P SYSCFG_EXTICR1_EXTI0_PB µÚ P SYSCFG_EXTICR1_EXTI0_PC ´Ú P SYSCFG_EXTICR1_EXTI0_PD ³Ú P SYSCFG_EXTICR1_EXTI0_PE ²Ú P SYSCFG_EXTICR1_EXTI0_PH ¯Ú P SYSCFG_EXTICR1_EXTI0_PF ±Ú P SYSCFG_EXTICR1_EXTI0_PG °Ú P SYSCFG_EXTICR1_EXTI1_PA µÚ P SYSCFG_EXTICR1_EXTI1_PB ´Ú P SYSCFG_EXTICR1_EXTI1_PC ³Ú P SYSCFG_EXTICR1_EXTI1_PD ²Ú P SYSCFG_EXTICR1_EXTI1_PE ±Ú P SYSCFG_EXTICR1_EXTI1_PH ®Ú P SYSCFG_EXTICR1_EXTI1_PF °Ú P SYSCFG_EXTICR1_EXTI1_PG ¯Ú P SYSCFG_EXTICR1_EXTI2_PA ´Ú P SYSCFG_EXTICR1_EXTI2_PB ³Ú P SYSCFG_EXTICR1_EXTI2_PC ²Ú P SYSCFG_EXTICR1_EXTI2_PD ±Ú P SYSCFG_EXTICR1_EXTI2_PE °Ú P SYSCFG_EXTICR1_EXTI2_PH Ú P SYSCFG_EXTICR1_EXTI2_PF ¯Ú P SYSCFG_EXTICR1_EXTI2_PG ®Ú P SYSCFG_EXTICR1_EXTI3_PA ³Ú P SYSCFG_EXTICR1_EXTI3_PB ²Ú P SYSCFG_EXTICR1_EXTI3_PC ±Ú P SYSCFG_EXTICR1_EXTI3_PD °Ú P SYSCFG_EXTICR1_EXTI3_PE ¯Ú P SYSCFG_EXTICR1_EXTI3_PF ®Ú P SYSCFG_EXTICR1_EXTI3_PG Ú P SYSCFG_EXTICR2_EXTI4 §Ú P SYSCFG_EXTICR2_EXTI5 ¦Ú P SYSCFG_EXTICR2_EXTI6 ¥Ú P SYSCFG_EXTICR2_EXTI7 ¤Ú P SYSCFG_EXTICR2_EXTI4_PA ±Ú P SYSCFG_EXTICR2_EXTI4_PB °Ú P SYSCFG_EXTICR2_EXTI4_PC ¯Ú P SYSCFG_EXTICR2_EXTI4_PD ®Ú P SYSCFG_EXTICR2_EXTI4_PE Ú P SYSCFG_EXTICR2_EXTI4_PF ¬Ú P SYSCFG_EXTICR2_EXTI4_PG «Ú P SYSCFG_EXTICR2_EXTI5_PA °Ú P SYSCFG_EXTICR2_EXTI5_PB ¯Ú P SYSCFG_EXTICR2_EXTI5_PC ®Ú P SYSCFG_EXTICR2_EXTI5_PD Ú P SYSCFG_EXTICR2_EXTI5_PE ¬Ú P SYSCFG_EXTICR2_EXTI5_PF «Ú P SYSCFG_EXTICR2_EXTI5_PG ªÚ P SYSCFG_EXTICR2_EXTI6_PA ¯Ú P SYSCFG_EXTICR2_EXTI6_PB ®Ú P SYSCFG_EXTICR2_EXTI6_PC Ú P SYSCFG_EXTICR2_EXTI6_PD ¬Ú P SYSCFG_EXTICR2_EXTI6_PE «Ú P SYSCFG_EXTICR2_EXTI6_PF ªÚ P SYSCFG_EXTICR2_EXTI6_PG ©Ú P SYSCFG_EXTICR2_EXTI7_PA ®Ú P SYSCFG_EXTICR2_EXTI7_PB Ú P SYSCFG_EXTICR2_EXTI7_PC ¬Ú P SYSCFG_EXTICR2_EXTI7_PD «Ú P SYSCFG_EXTICR2_EXTI7_PE ªÚ P SYSCFG_EXTICR2_EXTI7_PF ©Ú P SYSCFG_EXTICR2_EXTI7_PG ¨Ú P SYSCFG_EXTICR3_EXTI8 ¢Ú P SYSCFG_EXTICR3_EXTI9 ¡Ú P SYSCFG_EXTICR3_EXTI10 wÚ P SYSCFG_EXTICR3_EXTI11 vÚ P SYSCFG_EXTICR3_EXTI8_PA ¬Ú P SYSCFG_EXTICR3_EXTI8_PB «Ú P SYSCFG_EXTICR3_EXTI8_PC ªÚ P SYSCFG_EXTICR3_EXTI8_PD ©Ú P SYSCFG_EXTICR3_EXTI8_PE ¨Ú P SYSCFG_EXTICR3_EXTI8_PF §Ú P SYSCFG_EXTICR3_EXTI8_PG ¦Ú P SYSCFG_EXTICR3_EXTI9_PA «Ú P SYSCFG_EXTICR3_EXTI9_PB ªÚ P SYSCFG_EXTICR3_EXTI9_PC ©Ú P SYSCFG_EXTICR3_EXTI9_PD ¨Ú P SYSCFG_EXTICR3_EXTI9_PE §Ú P SYSCFG_EXTICR3_EXTI9_PF ¦Ú P SYSCFG_EXTICR3_EXTI9_PG ¥Ú! P SYSCFG_EXTICR3_EXTI10_PA Ú! P SYSCFG_EXTICR3_EXTI10_PB Ú! P SYSCFG_EXTICR3_EXTI10_PC Ú! P SYSCFG_EXTICR3_EXTI10_PD ~Ú! P SYSCFG_EXTICR3_EXTI10_PE }Ú! P SYSCFG_EXTICR3_EXTI10_PF |Ú! P SYSCFG_EXTICR3_EXTI10_PG {Ú! P SYSCFG_EXTICR3_EXTI11_PA Ú! P SYSCFG_EXTICR3_EXTI11_PB Ú! P SYSCFG_EXTICR3_EXTI11_PC ~Ú! P SYSCFG_EXTICR3_EXTI11_PD }Ú! P SYSCFG_EXTICR3_EXTI11_PE |Ú! P SYSCFG_EXTICR3_EXTI11_PF {Ú! P SYSCFG_EXTICR3_EXTI11_PG zÚ P SYSCFG_EXTICR4_EXTI12 tÚ P SYSCFG_EXTICR4_EXTI13 sÚ P SYSCFG_EXTICR4_EXTI14 rÚ P SYSCFG_EXTICR4_EXTI15 qÚ! P SYSCFG_EXTICR4_EXTI12_PA ~Ú! P SYSCFG_EXTICR4_EXTI12_PB }Ú! P SYSCFG_EXTICR4_EXTI12_PC |Ú! P SYSCFG_EXTICR4_EXTI12_PD {Ú! P SYSCFG_EXTICR4_EXTI12_PE zÚ! P SYSCFG_EXTICR4_EXTI12_PF yÚ! P SYSCFG_EXTICR4_EXTI12_PG xÚ! P SYSCFG_EXTICR4_EXTI13_PA }Ú! P SYSCFG_EXTICR4_EXTI13_PB |Ú! P SYSCFG_EXTICR4_EXTI13_PC {Ú! P SYSCFG_EXTICR4_EXTI13_PD zÚ! P SYSCFG_EXTICR4_EXTI13_PE yÚ! P SYSCFG_EXTICR4_EXTI13_PF xÚ! P SYSCFG_EXTICR4_EXTI13_PG wÚ! P SYSCFG_EXTICR4_EXTI14_PA |Ú! P SYSCFG_EXTICR4_EXTI14_PB {Ú! P SYSCFG_EXTICR4_EXTI14_PC zÚ! P SYSCFG_EXTICR4_EXTI14_PD yÚ! P SYSCFG_EXTICR4_EXTI14_PE xÚ! P SYSCFG_EXTICR4_EXTI14_PF wÚ! P SYSCFG_EXTICR4_EXTI14_PG vÚ! P SYSCFG_EXTICR4_EXTI15_PA {Ú! P SYSCFG_EXTICR4_EXTI15_PB zÚ! P SYSCFG_EXTICR4_EXTI15_PC yÚ! P SYSCFG_EXTICR4_EXTI15_PD xÚ! P SYSCFG_EXTICR4_EXTI15_PE wÚ! P SYSCFG_EXTICR4_EXTI15_PF vÚ! P SYSCFG_EXTICR4_EXTI15_PG uÚ P RI_ICR_IC1Z gÚ P RI_ICR_IC1Z_0 ÔÚ P RI_ICR_IC1Z_1 ÓÚ P RI_ICR_IC1Z_2 ÒÚ P RI_ICR_IC1Z_3 ÑÚ P RI_ICR_IC2Z fÚ P RI_ICR_IC2Z_0 ÓÚ P RI_ICR_IC2Z_1 ÒÚ P RI_ICR_IC2Z_2 ÑÚ P RI_ICR_IC2Z_3 ÐÚ P RI_ICR_IC3Z eÚ P RI_ICR_IC3Z_0 ÒÚ P RI_ICR_IC3Z_1 ÑÚ P RI_ICR_IC3Z_2 ÐÚ P RI_ICR_IC3Z_3 ÏÚ P RI_ICR_IC4Z dÚ P RI_ICR_IC4Z_0 ÑÚ P RI_ICR_IC4Z_1 ÐÚ P RI_ICR_IC4Z_2 ÏÚ P RI_ICR_IC4Z_3 ÎÚ P RI_ICR_TIM Ú P
RI_ICR_TIM_0 Ú P
RI_ICR_TIM_1 Ú P RI_ICR_IC1 ÃÚ P RI_ICR_IC2 ÂÚ P RI_ICR_IC3 ÁÚ P RI_ICR_IC4 ÀÚ P RI_ASCR1_CH wÚ P RI_ASCR1_CH_0 äÚ P RI_ASCR1_CH_1 ãÚ P RI_ASCR1_CH_2 âÚ P RI_ASCR1_CH_3 áÚ P RI_ASCR1_CH_4 àÚ P RI_ASCR1_CH_5 ßÚ P RI_ASCR1_CH_6 ÞÚ P RI_ASCR1_CH_7 ÝÚ P RI_ASCR1_CH_8 ÜÚ P RI_ASCR1_CH_9 ÛÚ P RI_ASCR1_CH_10 ±Ú P RI_ASCR1_CH_11 °Ú P RI_ASCR1_CH_12 ¯Ú P RI_ASCR1_CH_13 ®Ú P RI_ASCR1_CH_14 Ú P RI_ASCR1_CH_15 ¬Ú P RI_ASCR1_CH_31 ®Ú P RI_ASCR1_CH_18 ©Ú P RI_ASCR1_CH_19 ¨Ú P RI_ASCR1_CH_20 °Ú P RI_ASCR1_CH_21 ¯Ú P RI_ASCR1_CH_22 ®Ú P RI_ASCR1_CH_23 Ú P RI_ASCR1_CH_24 ¬Ú P RI_ASCR1_CH_25 «Ú P RI_ASCR1_VCOMP wÚ P RI_ASCR1_CH_27 ©Ú P RI_ASCR1_CH_28 ¨Ú P RI_ASCR1_CH_29 §Ú P RI_ASCR1_CH_30 ¯Ú P
RI_ASCR1_SCM Ú P RI_ASCR2_GR10_1 oÚ P RI_ASCR2_GR10_2 nÚ P RI_ASCR2_GR10_3 mÚ P RI_ASCR2_GR10_4 lÚ P RI_ASCR2_GR6_1 Ú P RI_ASCR2_GR6_2 Ú P RI_ASCR2_GR5_1 Ú P RI_ASCR2_GR5_2 Ú P RI_ASCR2_GR5_3 Ú P RI_ASCR2_GR4_1 Ú P RI_ASCR2_GR4_2 Ú P RI_ASCR2_GR4_3 Ú P RI_ASCR2_GR4_4 Ú P RI_ASCR2_CH0b àÚ P RI_ASCR2_CH1b ßÚ P RI_ASCR2_CH2b ÞÚ P RI_ASCR2_CH3b ÝÚ P RI_ASCR2_CH6b ÚÚ P RI_ASCR2_CH7b ÙÚ P RI_ASCR2_CH8b ØÚ P RI_ASCR2_CH9b ×Ú P RI_ASCR2_CH10b Ú P RI_ASCR2_CH11b ¬Ú P RI_ASCR2_CH12b «Ú P RI_ASCR2_GR6_3 Ú P RI_ASCR2_GR6_4 Ú P RI_ASCR2_GR5_4 Ú P
RI_HYSCR1_PA Ú P RI_HYSCR1_PA_0 |Ú P RI_HYSCR1_PA_1 {Ú P RI_HYSCR1_PA_2 zÚ P RI_HYSCR1_PA_3 yÚ P RI_HYSCR1_PA_4 xÚ P RI_HYSCR1_PA_5 wÚ P RI_HYSCR1_PA_6 vÚ P RI_HYSCR1_PA_7 uÚ P RI_HYSCR1_PA_8 tÚ P RI_HYSCR1_PA_9 sÚ P RI_HYSCR1_PA_10 IÚ P RI_HYSCR1_PA_11 HÚ P RI_HYSCR1_PA_12 GÚ P RI_HYSCR1_PA_13 FÚ P RI_HYSCR1_PA_14 EÚ P RI_HYSCR1_PA_15 DÚ P
RI_HYSCR1_PB Ú P RI_HYSCR1_PB_0 {Ú P RI_HYSCR1_PB_1 zÚ P RI_HYSCR1_PB_2 yÚ P RI_HYSCR1_PB_3 xÚ P RI_HYSCR1_PB_4 wÚ P RI_HYSCR1_PB_5 vÚ P RI_HYSCR1_PB_6 uÚ P RI_HYSCR1_PB_7 tÚ P RI_HYSCR1_PB_8 sÚ P RI_HYSCR1_PB_9 rÚ P RI_HYSCR1_PB_10 HÚ P RI_HYSCR1_PB_11 GÚ P RI_HYSCR1_PB_12 FÚ P RI_HYSCR1_PB_13 EÚ P RI_HYSCR1_PB_14 DÚ P RI_HYSCR1_PB_15 CÚ P
RI_HYSCR2_PC Ú P RI_HYSCR2_PC_0 yÚ P RI_HYSCR2_PC_1 xÚ P RI_HYSCR2_PC_2 wÚ P RI_HYSCR2_PC_3 vÚ P RI_HYSCR2_PC_4 uÚ P RI_HYSCR2_PC_5 tÚ P RI_HYSCR2_PC_6 sÚ P RI_HYSCR2_PC_7 rÚ P RI_HYSCR2_PC_8 qÚ P RI_HYSCR2_PC_9 pÚ P RI_HYSCR2_PC_10 FÚ P RI_HYSCR2_PC_11 EÚ P RI_HYSCR2_PC_12 DÚ P RI_HYSCR2_PC_13 CÚ P RI_HYSCR2_PC_14 BÚ P RI_HYSCR2_PC_15 AÚ P
RI_HYSCR2_PD Ú P RI_HYSCR2_PD_0 xÚ P RI_HYSCR2_PD_1 wÚ P RI_HYSCR2_PD_2 vÚ P RI_HYSCR2_PD_3 uÚ P RI_HYSCR2_PD_4 tÚ P RI_HYSCR2_PD_5 sÚ P RI_HYSCR2_PD_6 rÚ P RI_HYSCR2_PD_7 qÚ P RI_HYSCR2_PD_8 pÚ P RI_HYSCR2_PD_9 oÚ P RI_HYSCR2_PD_10 EÚ P RI_HYSCR2_PD_11 DÚ P RI_HYSCR2_PD_12 CÚ P RI_HYSCR2_PD_13 BÚ P RI_HYSCR2_PD_14 AÚ P RI_HYSCR2_PD_15 @Ú P
RI_HYSCR2_PE |
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SPI_DR_DR ãÚ P SPI_CRCPR_CRCPOLY iÚ P SPI_RXCRCR_RXCRC «Ú P SPI_TXCRCR_TXCRC §Ú P SPI_I2SCFGR_CHLEN ¥Ú P SPI_I2SCFGR_DATLEN UÚ P SPI_I2SCFGR_DATLEN_0 ÂÚ P SPI_I2SCFGR_DATLEN_1 ÁÚ P SPI_I2SCFGR_CKPOL Ú P SPI_I2SCFGR_I2SSTD TÚ P SPI_I2SCFGR_I2SSTD_0 ÁÚ P SPI_I2SCFGR_I2SSTD_1 ÀÚ P SPI_I2SCFGR_PCMSYNC îÚ P SPI_I2SCFGR_I2SCFG oÚ P SPI_I2SCFGR_I2SCFG_0 ÜÚ P SPI_I2SCFGR_I2SCFG_1 ÛÚ P SPI_I2SCFGR_I2SE þÚ P SPI_I2SCFGR_I2SMOD _Ú P SPI_I2SPR_I2SDIV àÚ P SPI_I2SPR_ODD ÀÚ P SPI_I2SPR_MCKOE $Ú P SYSCFG_MEMRMP_MEM_MODE áÚ! P SYSCFG_MEMRMP_MEM_MODE_0 NÚ! P SYSCFG_MEMRMP_MEM_MODE_1 MÚ P SYSCFG_MEMRMP_BOOT_MODE Ú" P SYSCFG_MEMRMP_BOOT_MODE_0 ÷Ú" P SYSCFG_MEMRMP_BOOT_MODE_1 öÚ P SYSCFG_PMC_USB_PU NÚ P SYSCFG_EXTICR1_EXTI0 ¬Ú P SYSCFG_EXTICR1_EXTI1 «Ú P SYSCFG_EXTICR1_EXTI2 ªÚ P SYSCFG_EXTICR1_EXTI3 ©Ú P SYSCFG_EXTICR1_EXTI0_PA ¶Ú P SYSCFG_EXTICR1_EXTI0_PB µÚ P SYSCFG_EXTICR1_EXTI0_PC ´Ú P SYSCFG_EXTICR1_EXTI0_PD ³Ú P SYSCFG_EXTICR1_EXTI0_PE ²Ú P SYSCFG_EXTICR1_EXTI0_PH ¯Ú P SYSCFG_EXTICR1_EXTI0_PF ±Ú P SYSCFG_EXTICR1_EXTI0_PG °Ú P SYSCFG_EXTICR1_EXTI1_PA µÚ P SYSCFG_EXTICR1_EXTI1_PB ´Ú P SYSCFG_EXTICR1_EXTI1_PC ³Ú P SYSCFG_EXTICR1_EXTI1_PD ²Ú P SYSCFG_EXTICR1_EXTI1_PE ±Ú P SYSCFG_EXTICR1_EXTI1_PH ®Ú P SYSCFG_EXTICR1_EXTI1_PF °Ú P SYSCFG_EXTICR1_EXTI1_PG ¯Ú P SYSCFG_EXTICR1_EXTI2_PA ´Ú P SYSCFG_EXTICR1_EXTI2_PB ³Ú P SYSCFG_EXTICR1_EXTI2_PC ²Ú P SYSCFG_EXTICR1_EXTI2_PD ±Ú P SYSCFG_EXTICR1_EXTI2_PE °Ú P SYSCFG_EXTICR1_EXTI2_PH Ú P SYSCFG_EXTICR1_EXTI2_PF ¯Ú P SYSCFG_EXTICR1_EXTI2_PG ®Ú P SYSCFG_EXTICR1_EXTI3_PA ³Ú P SYSCFG_EXTICR1_EXTI3_PB ²Ú P SYSCFG_EXTICR1_EXTI3_PC ±Ú P SYSCFG_EXTICR1_EXTI3_PD °Ú P SYSCFG_EXTICR1_EXTI3_PE ¯Ú P SYSCFG_EXTICR1_EXTI3_PF ®Ú P SYSCFG_EXTICR1_EXTI3_PG Ú P SYSCFG_EXTICR2_EXTI4 §Ú P SYSCFG_EXTICR2_EXTI5 ¦Ú P SYSCFG_EXTICR2_EXTI6 ¥Ú P SYSCFG_EXTICR2_EXTI7 ¤Ú P SYSCFG_EXTICR2_EXTI4_PA ±Ú P SYSCFG_EXTICR2_EXTI4_PB °Ú P SYSCFG_EXTICR2_EXTI4_PC ¯Ú P SYSCFG_EXTICR2_EXTI4_PD ®Ú P SYSCFG_EXTICR2_EXTI4_PE Ú P SYSCFG_EXTICR2_EXTI4_PF ¬Ú P SYSCFG_EXTICR2_EXTI4_PG «Ú P SYSCFG_EXTICR2_EXTI5_PA °Ú P SYSCFG_EXTICR2_EXTI5_PB ¯Ú P SYSCFG_EXTICR2_EXTI5_PC ®Ú P SYSCFG_EXTICR2_EXTI5_PD Ú P SYSCFG_EXTICR2_EXTI5_PE ¬Ú P SYSCFG_EXTICR2_EXTI5_PF «Ú P SYSCFG_EXTICR2_EXTI5_PG ªÚ P SYSCFG_EXTICR2_EXTI6_PA ¯Ú P SYSCFG_EXTICR2_EXTI6_PB ®Ú P SYSCFG_EXTICR2_EXTI6_PC Ú P SYSCFG_EXTICR2_EXTI6_PD ¬Ú P SYSCFG_EXTICR2_EXTI6_PE «Ú P SYSCFG_EXTICR2_EXTI6_PF ªÚ P SYSCFG_EXTICR2_EXTI6_PG ©Ú P SYSCFG_EXTICR2_EXTI7_PA ®Ú P SYSCFG_EXTICR2_EXTI7_PB Ú P SYSCFG_EXTICR2_EXTI7_PC ¬Ú P SYSCFG_EXTICR2_EXTI7_PD «Ú P SYSCFG_EXTICR2_EXTI7_PE ªÚ P SYSCFG_EXTICR2_EXTI7_PF ©Ú P SYSCFG_EXTICR2_EXTI7_PG ¨Ú P SYSCFG_EXTICR3_EXTI8 ¢Ú P SYSCFG_EXTICR3_EXTI9 ¡Ú P SYSCFG_EXTICR3_EXTI10 wÚ P SYSCFG_EXTICR3_EXTI11 vÚ P SYSCFG_EXTICR3_EXTI8_PA ¬Ú P SYSCFG_EXTICR3_EXTI8_PB «Ú P SYSCFG_EXTICR3_EXTI8_PC ªÚ P SYSCFG_EXTICR3_EXTI8_PD ©Ú P SYSCFG_EXTICR3_EXTI8_PE ¨Ú P SYSCFG_EXTICR3_EXTI8_PF §Ú P SYSCFG_EXTICR3_EXTI8_PG ¦Ú P SYSCFG_EXTICR3_EXTI9_PA «Ú P SYSCFG_EXTICR3_EXTI9_PB ªÚ P SYSCFG_EXTICR3_EXTI9_PC ©Ú P SYSCFG_EXTICR3_EXTI9_PD ¨Ú P SYSCFG_EXTICR3_EXTI9_PE §Ú P SYSCFG_EXTICR3_EXTI9_PF ¦Ú P SYSCFG_EXTICR3_EXTI9_PG ¥Ú! P SYSCFG_EXTICR3_EXTI10_PA Ú! P SYSCFG_EXTICR3_EXTI10_PB Ú! P SYSCFG_EXTICR3_EXTI10_PC Ú! P SYSCFG_EXTICR3_EXTI10_PD ~Ú! P SYSCFG_EXTICR3_EXTI10_PE }Ú! P SYSCFG_EXTICR3_EXTI10_PF |Ú! P SYSCFG_EXTICR3_EXTI10_PG {Ú! P SYSCFG_EXTICR3_EXTI11_PA Ú! P SYSCFG_EXTICR3_EXTI11_PB Ú! P SYSCFG_EXTICR3_EXTI11_PC ~Ú! P SYSCFG_EXTICR3_EXTI11_PD }Ú! P SYSCFG_EXTICR3_EXTI11_PE |Ú! P SYSCFG_EXTICR3_EXTI11_PF {Ú! P SYSCFG_EXTICR3_EXTI11_PG zÚ P SYSCFG_EXTICR4_EXTI12 tÚ P SYSCFG_EXTICR4_EXTI13 sÚ P SYSCFG_EXTICR4_EXTI14 rÚ P SYSCFG_EXTICR4_EXTI15 qÚ! P SYSCFG_EXTICR4_EXTI12_PA ~Ú! P SYSCFG_EXTICR4_EXTI12_PB }Ú! P SYSCFG_EXTICR4_EXTI12_PC |Ú! P SYSCFG_EXTICR4_EXTI12_PD {Ú! P SYSCFG_EXTICR4_EXTI12_PE zÚ! P SYSCFG_EXTICR4_EXTI12_PF yÚ! P SYSCFG_EXTICR4_EXTI12_PG xÚ! P SYSCFG_EXTICR4_EXTI13_PA }Ú! P SYSCFG_EXTICR4_EXTI13_PB |Ú! P SYSCFG_EXTICR4_EXTI13_PC {Ú! P SYSCFG_EXTICR4_EXTI13_PD zÚ! P SYSCFG_EXTICR4_EXTI13_PE yÚ! P SYSCFG_EXTICR4_EXTI13_PF xÚ! P SYSCFG_EXTICR4_EXTI13_PG wÚ! P SYSCFG_EXTICR4_EXTI14_PA |Ú! P SYSCFG_EXTICR4_EXTI14_PB {Ú! P SYSCFG_EXTICR4_EXTI14_PC zÚ! P SYSCFG_EXTICR4_EXTI14_PD yÚ! P SYSCFG_EXTICR4_EXTI14_PE xÚ! P SYSCFG_EXTICR4_EXTI14_PF wÚ! P SYSCFG_EXTICR4_EXTI14_PG vÚ! P SYSCFG_EXTICR4_EXTI15_PA {Ú! P SYSCFG_EXTICR4_EXTI15_PB zÚ! P SYSCFG_EXTICR4_EXTI15_PC yÚ! P SYSCFG_EXTICR4_EXTI15_PD xÚ! P SYSCFG_EXTICR4_EXTI15_PE wÚ! P SYSCFG_EXTICR4_EXTI15_PF vÚ! P SYSCFG_EXTICR4_EXTI15_PG uÚ P RI_ICR_IC1Z gÚ P RI_ICR_IC1Z_0 ÔÚ P RI_ICR_IC1Z_1 ÓÚ P RI_ICR_IC1Z_2 ÒÚ P RI_ICR_IC1Z_3 ÑÚ P RI_ICR_IC2Z fÚ P RI_ICR_IC2Z_0 ÓÚ P RI_ICR_IC2Z_1 ÒÚ P RI_ICR_IC2Z_2 ÑÚ P RI_ICR_IC2Z_3 ÐÚ P RI_ICR_IC3Z eÚ P RI_ICR_IC3Z_0 ÒÚ P RI_ICR_IC3Z_1 ÑÚ P RI_ICR_IC3Z_2 ÐÚ P RI_ICR_IC3Z_3 ÏÚ P RI_ICR_IC4Z dÚ P RI_ICR_IC4Z_0 ÑÚ P RI_ICR_IC4Z_1 ÐÚ P RI_ICR_IC4Z_2 ÏÚ P RI_ICR_IC4Z_3 ÎÚ P RI_ICR_TIM Ú P
RI_ICR_TIM_0 Ú P
RI_ICR_TIM_1 Ú P RI_ICR_IC1 ÃÚ P RI_ICR_IC2 ÂÚ P RI_ICR_IC3 ÁÚ P RI_ICR_IC4 ÀÚ P RI_ASCR1_CH wÚ P RI_ASCR1_CH_0 äÚ P RI_ASCR1_CH_1 ãÚ P RI_ASCR1_CH_2 âÚ P RI_ASCR1_CH_3 áÚ P RI_ASCR1_CH_4 àÚ P RI_ASCR1_CH_5 ßÚ P RI_ASCR1_CH_6 ÞÚ P RI_ASCR1_CH_7 ÝÚ P RI_ASCR1_CH_8 ÜÚ P RI_ASCR1_CH_9 ÛÚ P RI_ASCR1_CH_10 ±Ú P RI_ASCR1_CH_11 °Ú P RI_ASCR1_CH_12 ¯Ú P RI_ASCR1_CH_13 ®Ú P RI_ASCR1_CH_14 Ú P RI_ASCR1_CH_15 ¬Ú P RI_ASCR1_CH_31 ®Ú P RI_ASCR1_CH_18 ©Ú P RI_ASCR1_CH_19 ¨Ú P RI_ASCR1_CH_20 °Ú P RI_ASCR1_CH_21 ¯Ú P RI_ASCR1_CH_22 ®Ú P RI_ASCR1_CH_23 Ú P RI_ASCR1_CH_24 ¬Ú P RI_ASCR1_CH_25 «Ú P RI_ASCR1_VCOMP wÚ P RI_ASCR1_CH_27 ©Ú P RI_ASCR1_CH_28 ¨Ú P RI_ASCR1_CH_29 §Ú P RI_ASCR1_CH_30 ¯Ú P
RI_ASCR1_SCM Ú P RI_ASCR2_GR10_1 oÚ P RI_ASCR2_GR10_2 nÚ P RI_ASCR2_GR10_3 mÚ P RI_ASCR2_GR10_4 lÚ P RI_ASCR2_GR6_1 Ú P RI_ASCR2_GR6_2 Ú P RI_ASCR2_GR5_1 Ú P RI_ASCR2_GR5_2 Ú P RI_ASCR2_GR5_3 Ú P RI_ASCR2_GR4_1 Ú P RI_ASCR2_GR4_2 Ú P RI_ASCR2_GR4_3 Ú P RI_ASCR2_GR4_4 Ú P RI_ASCR2_CH0b àÚ P RI_ASCR2_CH1b ßÚ P RI_ASCR2_CH2b ÞÚ P RI_ASCR2_CH3b ÝÚ P RI_ASCR2_CH6b ÚÚ P RI_ASCR2_CH7b ÙÚ P RI_ASCR2_CH8b ØÚ P RI_ASCR2_CH9b ×Ú P RI_ASCR2_CH10b Ú P RI_ASCR2_CH11b ¬Ú P RI_ASCR2_CH12b «Ú P RI_ASCR2_GR6_3 Ú P RI_ASCR2_GR6_4 Ú P RI_ASCR2_GR5_4 Ú P
RI_HYSCR1_PA Ú P RI_HYSCR1_PA_0 |Ú P RI_HYSCR1_PA_1 {Ú P RI_HYSCR1_PA_2 zÚ P RI_HYSCR1_PA_3 yÚ P RI_HYSCR1_PA_4 xÚ P RI_HYSCR1_PA_5 wÚ P RI_HYSCR1_PA_6 vÚ P RI_HYSCR1_PA_7 uÚ P RI_HYSCR1_PA_8 tÚ P RI_HYSCR1_PA_9 sÚ P RI_HYSCR1_PA_10 IÚ P RI_HYSCR1_PA_11 HÚ P RI_HYSCR1_PA_12 GÚ P RI_HYSCR1_PA_13 FÚ P RI_HYSCR1_PA_14 EÚ P RI_HYSCR1_PA_15 DÚ P
RI_HYSCR1_PB Ú P RI_HYSCR1_PB_0 {Ú P RI_HYSCR1_PB_1 zÚ P RI_HYSCR1_PB_2 yÚ P RI_HYSCR1_PB_3 xÚ P RI_HYSCR1_PB_4 wÚ P RI_HYSCR1_PB_5 vÚ P RI_HYSCR1_PB_6 uÚ P RI_HYSCR1_PB_7 tÚ P RI_HYSCR1_PB_8 sÚ P RI_HYSCR1_PB_9 rÚ P RI_HYSCR1_PB_10 HÚ P RI_HYSCR1_PB_11 GÚ P RI_HYSCR1_PB_12 FÚ P RI_HYSCR1_PB_13 EÚ P RI_HYSCR1_PB_14 DÚ P RI_HYSCR1_PB_15 CÚ P
RI_HYSCR2_PC Ú P RI_HYSCR2_PC_0 yÚ P RI_HYSCR2_PC_1 xÚ P RI_HYSCR2_PC_2 wÚ P RI_HYSCR2_PC_3 vÚ P RI_HYSCR2_PC_4 uÚ P RI_HYSCR2_PC_5 tÚ P RI_HYSCR2_PC_6 sÚ P RI_HYSCR2_PC_7 rÚ P RI_HYSCR2_PC_8 qÚ P RI_HYSCR2_PC_9 pÚ P RI_HYSCR2_PC_10 FÚ P RI_HYSCR2_PC_11 EÚ P RI_HYSCR2_PC_12 DÚ P RI_HYSCR2_PC_13 CÚ P RI_HYSCR2_PC_14 BÚ P RI_HYSCR2_PC_15 AÚ P
RI_HYSCR2_PD Ú P RI_HYSCR2_PD_0 xÚ P RI_HYSCR2_PD_1 wÚ P RI_HYSCR2_PD_2 vÚ P RI_HYSCR2_PD_3 uÚ P RI_HYSCR2_PD_4 tÚ P RI_HYSCR2_PD_5 sÚ P RI_HYSCR2_PD_6 rÚ P RI_HYSCR2_PD_7 qÚ P RI_HYSCR2_PD_8 pÚ P RI_HYSCR2_PD_9 oÚ P RI_HYSCR2_PD_10 EÚ P RI_HYSCR2_PD_11 DÚ P RI_HYSCR2_PD_12 CÚ P RI_HYSCR2_PD_13 BÚ P RI_HYSCR2_PD_14 AÚ P RI_HYSCR2_PD_15 @Ú P
RI_HYSCR2_PE |
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Ú P RI_HYSCR2_PE_0 wÚ P RI_HYSCR2_PE_1 vÚ P RI_HYSCR2_PE_2 uÚ P RI_HYSCR2_PE_3 tÚ P RI_HYSCR2_PE_4 sÚ P RI_HYSCR2_PE_5 rÚ P RI_HYSCR2_PE_6 qÚ P RI_HYSCR2_PE_7 pÚ P RI_HYSCR2_PE_8 oÚ P RI_HYSCR2_PE_9 nÚ P RI_HYSCR2_PE_10 DÚ P RI_HYSCR2_PE_11 CÚ P RI_HYSCR2_PE_12 BÚ P RI_HYSCR2_PE_13 AÚ P RI_HYSCR2_PE_14 @Ú P RI_HYSCR2_PE_15 ?Ú P
RI_HYSCR3_PF Ú P RI_HYSCR3_PF_0 uÚ P RI_HYSCR3_PF_1 tÚ P RI_HYSCR3_PF_2 sÚ P RI_HYSCR3_PF_3 rÚ P RI_HYSCR3_PF_4 qÚ P RI_HYSCR3_PF_5 pÚ P RI_HYSCR3_PF_6 oÚ P RI_HYSCR3_PF_7 nÚ P RI_HYSCR3_PF_8 mÚ P RI_HYSCR3_PF_9 lÚ P RI_HYSCR3_PF_10 BÚ P RI_HYSCR3_PF_11 AÚ P RI_HYSCR3_PF_12 @Ú P RI_HYSCR3_PF_13 ?Ú P RI_HYSCR3_PF_14 >Ú P RI_HYSCR3_PF_15 =Ú P
RI_HYSCR4_PG Ú P RI_HYSCR4_PG_0 sÚ P RI_HYSCR4_PG_1 rÚ P RI_HYSCR4_PG_2 qÚ P RI_HYSCR4_PG_3 pÚ P RI_HYSCR4_PG_4 oÚ P RI_HYSCR4_PG_5 nÚ P RI_HYSCR4_PG_6 mÚ P RI_HYSCR4_PG_7 lÚ P RI_HYSCR4_PG_8 kÚ P RI_HYSCR4_PG_9 jÚ P RI_HYSCR4_PG_10 @Ú P RI_HYSCR4_PG_11 ?Ú P RI_HYSCR4_PG_12 >Ú P RI_HYSCR4_PG_13 =Ú P RI_HYSCR4_PG_14 <Ú P RI_HYSCR4_PG_15 ;Ú P TIM_CR1_CEN qÚ P
TIM_CR1_UDIS Ú P TIM_CR1_URS MÚ P TIM_CR1_OPM [Ú P TIM_CR1_DIR hÚ P TIM_CR1_CMS dÚ P TIM_CR1_CMS_0 ÑÚ P TIM_CR1_CMS_1 ÐÚ P
TIM_CR1_ARPE Ú P TIM_CR1_CKD uÚ P TIM_CR1_CKD_0 âÚ P TIM_CR1_CKD_1 áÚ P
TIM_CR2_CCDS 'Ú P TIM_CR2_MMS YÚ P TIM_CR2_MMS_0 ÆÚ P TIM_CR2_MMS_1 ÅÚ P TIM_CR2_MMS_2 ÄÚ P
TIM_CR2_TI1S #Ú P
TIM_SMCR_SMS ãÚ P TIM_SMCR_SMS_0 PÚ P TIM_SMCR_SMS_1 OÚ P TIM_SMCR_SMS_2 NÚ P TIM_SMCR_OCCS ¬Ú P TIM_SMCR_TS 1Ú P TIM_SMCR_TS_0 Ú P TIM_SMCR_TS_1 Ú P TIM_SMCR_TS_2 Ú P
TIM_SMCR_MSM éÚ P
TIM_SMCR_ETF ÷Ú P TIM_SMCR_ETF_0 dÚ P TIM_SMCR_ETF_1 cÚ P TIM_SMCR_ETF_2 bÚ P TIM_SMCR_ETF_3 aÚ P TIM_SMCR_ETPS Ú P TIM_SMCR_ETPS_0 Ú P TIM_SMCR_ETPS_1 Ú P
TIM_SMCR_ECE Ú P
TIM_SMCR_ETP íÚ P
TIM_DIER_UIE Ú P TIM_DIER_CC1IE Ú P TIM_DIER_CC2IE Ú P TIM_DIER_CC3IE Ú P TIM_DIER_CC4IE Ú P
TIM_DIER_TIE Ú P
TIM_DIER_UDE Ú P TIM_DIER_CC1DE £Ú P TIM_DIER_CC2DE ¢Ú P TIM_DIER_CC3DE ¡Ú P TIM_DIER_CC4DE Ú P
TIM_DIER_TDE |
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Ú P RI_HYSCR2_PE_0 wÚ P RI_HYSCR2_PE_1 vÚ P RI_HYSCR2_PE_2 uÚ P RI_HYSCR2_PE_3 tÚ P RI_HYSCR2_PE_4 sÚ P RI_HYSCR2_PE_5 rÚ P RI_HYSCR2_PE_6 qÚ P RI_HYSCR2_PE_7 pÚ P RI_HYSCR2_PE_8 oÚ P RI_HYSCR2_PE_9 nÚ P RI_HYSCR2_PE_10 DÚ P RI_HYSCR2_PE_11 CÚ P RI_HYSCR2_PE_12 BÚ P RI_HYSCR2_PE_13 AÚ P RI_HYSCR2_PE_14 @Ú P RI_HYSCR2_PE_15 ?Ú P
RI_HYSCR3_PF Ú P RI_HYSCR3_PF_0 uÚ P RI_HYSCR3_PF_1 tÚ P RI_HYSCR3_PF_2 sÚ P RI_HYSCR3_PF_3 rÚ P RI_HYSCR3_PF_4 qÚ P RI_HYSCR3_PF_5 pÚ P RI_HYSCR3_PF_6 oÚ P RI_HYSCR3_PF_7 nÚ P RI_HYSCR3_PF_8 mÚ P RI_HYSCR3_PF_9 lÚ P RI_HYSCR3_PF_10 BÚ P RI_HYSCR3_PF_11 AÚ P RI_HYSCR3_PF_12 @Ú P RI_HYSCR3_PF_13 ?Ú P RI_HYSCR3_PF_14 >Ú P RI_HYSCR3_PF_15 =Ú P
RI_HYSCR4_PG Ú P RI_HYSCR4_PG_0 sÚ P RI_HYSCR4_PG_1 rÚ P RI_HYSCR4_PG_2 qÚ P RI_HYSCR4_PG_3 pÚ P RI_HYSCR4_PG_4 oÚ P RI_HYSCR4_PG_5 nÚ P RI_HYSCR4_PG_6 mÚ P RI_HYSCR4_PG_7 lÚ P RI_HYSCR4_PG_8 kÚ P RI_HYSCR4_PG_9 jÚ P RI_HYSCR4_PG_10 @Ú P RI_HYSCR4_PG_11 ?Ú P RI_HYSCR4_PG_12 >Ú P RI_HYSCR4_PG_13 =Ú P RI_HYSCR4_PG_14 <Ú P RI_HYSCR4_PG_15 ;Ú P TIM_CR1_CEN qÚ P
TIM_CR1_UDIS Ú P TIM_CR1_URS MÚ P TIM_CR1_OPM [Ú P TIM_CR1_DIR hÚ P TIM_CR1_CMS dÚ P TIM_CR1_CMS_0 ÑÚ P TIM_CR1_CMS_1 ÐÚ P
TIM_CR1_ARPE Ú P TIM_CR1_CKD uÚ P TIM_CR1_CKD_0 âÚ P TIM_CR1_CKD_1 áÚ P
TIM_CR2_CCDS 'Ú P TIM_CR2_MMS YÚ P TIM_CR2_MMS_0 ÆÚ P TIM_CR2_MMS_1 ÅÚ P TIM_CR2_MMS_2 ÄÚ P
TIM_CR2_TI1S #Ú P
TIM_SMCR_SMS ãÚ P TIM_SMCR_SMS_0 PÚ P TIM_SMCR_SMS_1 OÚ P TIM_SMCR_SMS_2 NÚ P TIM_SMCR_OCCS ¬Ú P TIM_SMCR_TS 1Ú P TIM_SMCR_TS_0 Ú P TIM_SMCR_TS_1 Ú P TIM_SMCR_TS_2 Ú P
TIM_SMCR_MSM éÚ P
TIM_SMCR_ETF ÷Ú P TIM_SMCR_ETF_0 dÚ P TIM_SMCR_ETF_1 cÚ P TIM_SMCR_ETF_2 bÚ P TIM_SMCR_ETF_3 aÚ P TIM_SMCR_ETPS Ú P TIM_SMCR_ETPS_0 Ú P TIM_SMCR_ETPS_1 Ú P
TIM_SMCR_ECE Ú P
TIM_SMCR_ETP íÚ P
TIM_DIER_UIE Ú P TIM_DIER_CC1IE Ú P TIM_DIER_CC2IE Ú P TIM_DIER_CC3IE Ú P TIM_DIER_CC4IE Ú P
TIM_DIER_TIE Ú P
TIM_DIER_UDE Ú P TIM_DIER_CC1DE £Ú P TIM_DIER_CC2DE ¢Ú P TIM_DIER_CC3DE ¡Ú P TIM_DIER_CC4DE Ú P
TIM_DIER_TDE |
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Ú P TIM_SR_UIF Ú P
TIM_SR_CC1IF Ú P
TIM_SR_CC2IF Ú P
TIM_SR_CC3IF Ú P
TIM_SR_CC4IF Ú P TIM_SR_TIF Ú P
TIM_SR_CC1OF Ú P
TIM_SR_CC2OF Ú P
TIM_SR_CC3OF Ú P
TIM_SR_CC4OF Ú P TIM_EGR_UG Ú P
TIM_EGR_CC1G /Ú P
TIM_EGR_CC2G .Ú P
TIM_EGR_CC3G -Ú P
TIM_EGR_CC4G ,Ú P TIM_EGR_TG Ú P TIM_CCMR1_CC1S §Ú P TIM_CCMR1_CC1S_0 Ú P TIM_CCMR1_CC1S_1 Ú P TIM_CCMR1_OC1FE aÚ P TIM_CCMR1_OC1PE WÚ P TIM_CCMR1_OC1M ¡Ú P TIM_CCMR1_OC1M_0 Ú P TIM_CCMR1_OC1M_1
Ú P TIM_CCMR1_OC1M_2 Ú P TIM_CCMR1_OC1CE dÚ P TIM_CCMR1_CC2S ¦Ú P TIM_CCMR1_CC2S_0 Ú P TIM_CCMR1_CC2S_1 Ú P TIM_CCMR1_OC2FE `Ú P TIM_CCMR1_OC2PE VÚ P TIM_CCMR1_OC2M Ú P TIM_CCMR1_OC2M_0
Ú P TIM_CCMR1_OC2M_1 Ú P TIM_CCMR1_OC2M_2 Ú P TIM_CCMR1_OC2CE cÚ P TIM_CCMR1_IC1PSC |
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Ú P TIM_SR_UIF Ú P
TIM_SR_CC1IF Ú P
TIM_SR_CC2IF Ú P
TIM_SR_CC3IF Ú P
TIM_SR_CC4IF Ú P TIM_SR_TIF Ú P
TIM_SR_CC1OF Ú P
TIM_SR_CC2OF Ú P
TIM_SR_CC3OF Ú P
TIM_SR_CC4OF Ú P TIM_EGR_UG Ú P
TIM_EGR_CC1G /Ú P
TIM_EGR_CC2G .Ú P
TIM_EGR_CC3G -Ú P
TIM_EGR_CC4G ,Ú P TIM_EGR_TG Ú P TIM_CCMR1_CC1S §Ú P TIM_CCMR1_CC1S_0 Ú P TIM_CCMR1_CC1S_1 Ú P TIM_CCMR1_OC1FE aÚ P TIM_CCMR1_OC1PE WÚ P TIM_CCMR1_OC1M ¡Ú P TIM_CCMR1_OC1M_0 Ú P TIM_CCMR1_OC1M_1
Ú P TIM_CCMR1_OC1M_2 Ú P TIM_CCMR1_OC1CE dÚ P TIM_CCMR1_CC2S ¦Ú P TIM_CCMR1_CC2S_0 Ú P TIM_CCMR1_CC2S_1 Ú P TIM_CCMR1_OC2FE `Ú P TIM_CCMR1_OC2PE VÚ P TIM_CCMR1_OC2M Ú P TIM_CCMR1_OC2M_0
Ú P TIM_CCMR1_OC2M_1 Ú P TIM_CCMR1_OC2M_2 Ú P TIM_CCMR1_OC2CE cÚ P TIM_CCMR1_IC1PSC |
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Ú P TIM_CCMR1_IC1PSC_0 wÚ P TIM_CCMR1_IC1PSC_1 vÚ P TIM_CCMR1_IC1F ®Ú P TIM_CCMR1_IC1F_0 Ú P TIM_CCMR1_IC1F_1 Ú P TIM_CCMR1_IC1F_2 Ú P TIM_CCMR1_IC1F_3 Ú P TIM_CCMR1_IC2PSC Ú P TIM_CCMR1_IC2PSC_0 vÚ P TIM_CCMR1_IC2PSC_1 uÚ P TIM_CCMR1_IC2F Ú P TIM_CCMR1_IC2F_0 Ú P TIM_CCMR1_IC2F_1 Ú P TIM_CCMR1_IC2F_2 Ú P TIM_CCMR1_IC2F_3 Ú P TIM_CCMR2_CC3S ¤Ú P TIM_CCMR2_CC3S_0 Ú P TIM_CCMR2_CC3S_1 Ú P TIM_CCMR2_OC3FE ^Ú P TIM_CCMR2_OC3PE TÚ P TIM_CCMR2_OC3M Ú P TIM_CCMR2_OC3M_0 Ú P TIM_CCMR2_OC3M_1 |
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Ú P TIM_CCMR1_IC1PSC_0 wÚ P TIM_CCMR1_IC1PSC_1 vÚ P TIM_CCMR1_IC1F ®Ú P TIM_CCMR1_IC1F_0 Ú P TIM_CCMR1_IC1F_1 Ú P TIM_CCMR1_IC1F_2 Ú P TIM_CCMR1_IC1F_3 Ú P TIM_CCMR1_IC2PSC Ú P TIM_CCMR1_IC2PSC_0 vÚ P TIM_CCMR1_IC2PSC_1 uÚ P TIM_CCMR1_IC2F Ú P TIM_CCMR1_IC2F_0 Ú P TIM_CCMR1_IC2F_1 Ú P TIM_CCMR1_IC2F_2 Ú P TIM_CCMR1_IC2F_3 Ú P TIM_CCMR2_CC3S ¤Ú P TIM_CCMR2_CC3S_0 Ú P TIM_CCMR2_CC3S_1 Ú P TIM_CCMR2_OC3FE ^Ú P TIM_CCMR2_OC3PE TÚ P TIM_CCMR2_OC3M Ú P TIM_CCMR2_OC3M_0 Ú P TIM_CCMR2_OC3M_1 |
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Ú P TIM_CCMR2_OC3M_2 Ú P TIM_CCMR2_OC3CE aÚ P TIM_CCMR2_CC4S £Ú P TIM_CCMR2_CC4S_0 Ú P TIM_CCMR2_CC4S_1 Ú P TIM_CCMR2_OC4FE ]Ú P TIM_CCMR2_OC4PE SÚ P TIM_CCMR2_OC4M Ú P TIM_CCMR2_OC4M_0 |
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Ú P TIM_CCMR2_OC3M_2 Ú P TIM_CCMR2_OC3CE aÚ P TIM_CCMR2_CC4S £Ú P TIM_CCMR2_CC4S_0 Ú P TIM_CCMR2_CC4S_1 Ú P TIM_CCMR2_OC4FE ]Ú P TIM_CCMR2_OC4PE SÚ P TIM_CCMR2_OC4M Ú P TIM_CCMR2_OC4M_0 |
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Ú P TIM_CCMR2_OC4M_1 Ú P TIM_CCMR2_OC4M_2 Ú P TIM_CCMR2_OC4CE `Ú P TIM_CCMR2_IC3PSC Ú P TIM_CCMR2_IC3PSC_0 tÚ P TIM_CCMR2_IC3PSC_1 sÚ P TIM_CCMR2_IC3F «Ú P TIM_CCMR2_IC3F_0 Ú P TIM_CCMR2_IC3F_1 Ú P TIM_CCMR2_IC3F_2 Ú P TIM_CCMR2_IC3F_3 Ú P TIM_CCMR2_IC4PSC Ú P TIM_CCMR2_IC4PSC_0 sÚ P TIM_CCMR2_IC4PSC_1 rÚ P TIM_CCMR2_IC4F ªÚ P TIM_CCMR2_IC4F_0 Ú P TIM_CCMR2_IC4F_1 Ú P TIM_CCMR2_IC4F_2 Ú P TIM_CCMR2_IC4F_3 Ú P TIM_CCER_CC1E ðÚ P TIM_CCER_CC1P åÚ P TIM_CCER_CC1NP Ú P TIM_CCER_CC2E ïÚ P TIM_CCER_CC2P äÚ P TIM_CCER_CC2NP Ú P TIM_CCER_CC3E îÚ P TIM_CCER_CC3P ãÚ P TIM_CCER_CC3NP Ú P TIM_CCER_CC4E íÚ P TIM_CCER_CC4P âÚ P TIM_CCER_CC4NP Ú P TIM_CNT_CNT CÚ P TIM_PSC_PSC AÚ P TIM_ARR_ARR CÚ P TIM_CCR1_CCR1 ÷Ú P TIM_CCR2_CCR2 õÚ P TIM_CCR3_CCR3 óÚ P TIM_CCR4_CCR4 ñÚ P TIM_DCR_DBA mÚ P TIM_DCR_DBA_0 ÚÚ P TIM_DCR_DBA_1 ÙÚ P TIM_DCR_DBA_2 ØÚ P TIM_DCR_DBA_3 ×Ú P TIM_DCR_DBA_4 ÖÚ P TIM_DCR_DBL bÚ P TIM_DCR_DBL_0 ÏÚ P TIM_DCR_DBL_1 ÎÚ P TIM_DCR_DBL_2 ÍÚ P TIM_DCR_DBL_3 ÌÚ P TIM_DCR_DBL_4 ËÚ P TIM_DMAR_DMAB ÑÚ P TIM_OR_TI1RMP «Ú P TIM_OR_TI1RMP_0 Ú P TIM_OR_TI1RMP_1 Ú P USART_SR_PE .Ú P USART_SR_FE 8Ú P USART_SR_NE 0Ú P
USART_SR_ORE ÛÚ P USART_SR_IDLE ¡Ú P USART_SR_RXNE Ú P USART_SR_TC ,Ú P
USART_SR_TXE ÐÚ P
USART_SR_LBD ïÚ P
USART_SR_CTS ×Ú P USART_DR_DR <Ú P USART_BRR_DIV_FRACTION ÔÚ P USART_BRR_DIV_MANTISSA ÊÚ P USART_CR1_SBK ¾Ú P USART_CR1_RWU Ú P
USART_CR1_RE Ú P
USART_CR1_TE Ú P USART_CR1_IDLEIE ìÚ P USART_CR1_RXNEIE ÍÚ P USART_CR1_TCIE wÚ P USART_CR1_TXEIE Ú P USART_CR1_PEIE yÚ P
USART_CR1_PS ýÚ P USART_CR1_PCE ÆÚ P USART_CR1_WAKE tÚ P USART_CR1_M UÚ P
USART_CR1_UE Ú P USART_CR1_OVER8 &Ú P USART_CR2_ADD ÔÚ P USART_CR2_LBDL }Ú P USART_CR2_LBDIE 9Ú P USART_CR2_LBCL ~Ú P USART_CR2_CPHA Ú P USART_CR2_CPOL mÚ P USART_CR2_CLKEN ,Ú P USART_CR2_STOP UÚ P USART_CR2_STOP_0 ÂÚ P USART_CR2_STOP_1 ÁÚ P USART_CR2_LINEN #Ú P USART_CR3_EIE ÉÚ P USART_CR3_IREN lÚ P USART_CR3_IRLP cÚ P USART_CR3_HDSEL (Ú P USART_CR3_NACK }Ú P USART_CR3_SCEN qÚ P USART_CR3_DMAR vÚ P USART_CR3_DMAT tÚ P USART_CR3_RTSE \Ú P USART_CR3_CTSE kÚ P USART_CR3_CTSIE Ú P USART_CR3_ONEBIT ÕÚ P USART_GTPR_PSC ?Ú P USART_GTPR_PSC_0 ¬Ú P USART_GTPR_PSC_1 «Ú P USART_GTPR_PSC_2 ªÚ P USART_GTPR_PSC_3 ©Ú P USART_GTPR_PSC_4 ¨Ú P USART_GTPR_PSC_5 §Ú P USART_GTPR_PSC_6 ¦Ú P USART_GTPR_PSC_7 ¥Ú P USART_GTPR_GT Ú P USB_EP0R_EA pÚ P USB_EP0R_STAT_TX ¥Ú P USB_EP0R_STAT_TX_0 Ú P USB_EP0R_STAT_TX_1 Ú P USB_EP0R_DTOG_TX ³Ú P USB_EP0R_CTR_TX úÚ P USB_EP0R_EP_KIND ÒÚ P USB_EP0R_EP_TYPE ¶Ú P USB_EP0R_EP_TYPE_0 #Ú P USB_EP0R_EP_TYPE_1 "Ú P USB_EP0R_SETUP _Ú P USB_EP0R_STAT_RX §Ú P USB_EP0R_STAT_RX_0 Ú P USB_EP0R_STAT_RX_1 Ú P USB_EP0R_DTOG_RX µÚ P USB_EP0R_CTR_RX üÚ P USB_EP1R_EA oÚ P USB_EP1R_STAT_TX ¤Ú P USB_EP1R_STAT_TX_0 Ú P USB_EP1R_STAT_TX_1 Ú P USB_EP1R_DTOG_TX ²Ú P USB_EP1R_CTR_TX ùÚ P USB_EP1R_EP_KIND ÑÚ P USB_EP1R_EP_TYPE µÚ P USB_EP1R_EP_TYPE_0 "Ú P USB_EP1R_EP_TYPE_1 !Ú P USB_EP1R_SETUP ^Ú P USB_EP1R_STAT_RX ¦Ú P USB_EP1R_STAT_RX_0 Ú P USB_EP1R_STAT_RX_1 Ú P USB_EP1R_DTOG_RX ´Ú P USB_EP1R_CTR_RX ûÚ P USB_EP2R_EA nÚ P USB_EP2R_STAT_TX £Ú P USB_EP2R_STAT_TX_0 Ú P USB_EP2R_STAT_TX_1 Ú P USB_EP2R_DTOG_TX ±Ú P USB_EP2R_CTR_TX øÚ P USB_EP2R_EP_KIND ÐÚ P USB_EP2R_EP_TYPE ´Ú P USB_EP2R_EP_TYPE_0 !Ú P USB_EP2R_EP_TYPE_1 Ú P USB_EP2R_SETUP ]Ú P USB_EP2R_STAT_RX ¥Ú P USB_EP2R_STAT_RX_0 Ú P USB_EP2R_STAT_RX_1 Ú P USB_EP2R_DTOG_RX ³Ú P USB_EP2R_CTR_RX úÚ P USB_EP3R_EA mÚ P USB_EP3R_STAT_TX ¢Ú P USB_EP3R_STAT_TX_0 Ú P USB_EP3R_STAT_TX_1 Ú P USB_EP3R_DTOG_TX °Ú P USB_EP3R_CTR_TX ÷Ú P USB_EP3R_EP_KIND ÏÚ P USB_EP3R_EP_TYPE ³Ú P USB_EP3R_EP_TYPE_0 Ú P USB_EP3R_EP_TYPE_1 Ú P USB_EP3R_SETUP \Ú P USB_EP3R_STAT_RX ¤Ú P USB_EP3R_STAT_RX_0 Ú P USB_EP3R_STAT_RX_1 Ú P USB_EP3R_DTOG_RX ²Ú P USB_EP3R_CTR_RX ùÚ P USB_EP4R_EA lÚ P USB_EP4R_STAT_TX ¡Ú P USB_EP4R_STAT_TX_0 Ú P USB_EP4R_STAT_TX_1
Ú P USB_EP4R_DTOG_TX ¯Ú P USB_EP4R_CTR_TX öÚ P USB_EP4R_EP_KIND ÎÚ P USB_EP4R_EP_TYPE ²Ú P USB_EP4R_EP_TYPE_0 Ú P USB_EP4R_EP_TYPE_1 Ú P USB_EP4R_SETUP [Ú P USB_EP4R_STAT_RX £Ú P USB_EP4R_STAT_RX_0 Ú P USB_EP4R_STAT_RX_1 Ú P USB_EP4R_DTOG_RX ±Ú P USB_EP4R_CTR_RX øÚ P USB_EP5R_EA kÚ P USB_EP5R_STAT_TX Ú P USB_EP5R_STAT_TX_0
Ú P USB_EP5R_STAT_TX_1 Ú P USB_EP5R_DTOG_TX ®Ú P USB_EP5R_CTR_TX õÚ P USB_EP5R_EP_KIND ÍÚ P USB_EP5R_EP_TYPE ±Ú P USB_EP5R_EP_TYPE_0 Ú P USB_EP5R_EP_TYPE_1 Ú P USB_EP5R_SETUP ZÚ P USB_EP5R_STAT_RX ¢Ú P USB_EP5R_STAT_RX_0 Ú P USB_EP5R_STAT_RX_1 Ú P USB_EP5R_DTOG_RX °Ú P USB_EP5R_CTR_RX ÷Ú P USB_EP6R_EA jÚ P USB_EP6R_STAT_TX Ú P USB_EP6R_STAT_TX_0 Ú P USB_EP6R_STAT_TX_1 Ú P USB_EP6R_DTOG_TX Ú P USB_EP6R_CTR_TX ôÚ P USB_EP6R_EP_KIND ÌÚ P USB_EP6R_EP_TYPE °Ú P USB_EP6R_EP_TYPE_0 Ú P USB_EP6R_EP_TYPE_1 Ú P USB_EP6R_SETUP YÚ P USB_EP6R_STAT_RX ¡Ú P USB_EP6R_STAT_RX_0 Ú P USB_EP6R_STAT_RX_1
Ú P USB_EP6R_DTOG_RX ¯Ú P USB_EP6R_CTR_RX öÚ P USB_EP7R_EA iÚ P USB_EP7R_STAT_TX Ú P USB_EP7R_STAT_TX_0 Ú P USB_EP7R_STAT_TX_1 |
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Ú P TIM_CCMR2_OC4M_1 Ú P TIM_CCMR2_OC4M_2 Ú P TIM_CCMR2_OC4CE `Ú P TIM_CCMR2_IC3PSC Ú P TIM_CCMR2_IC3PSC_0 tÚ P TIM_CCMR2_IC3PSC_1 sÚ P TIM_CCMR2_IC3F «Ú P TIM_CCMR2_IC3F_0 Ú P TIM_CCMR2_IC3F_1 Ú P TIM_CCMR2_IC3F_2 Ú P TIM_CCMR2_IC3F_3 Ú P TIM_CCMR2_IC4PSC Ú P TIM_CCMR2_IC4PSC_0 sÚ P TIM_CCMR2_IC4PSC_1 rÚ P TIM_CCMR2_IC4F ªÚ P TIM_CCMR2_IC4F_0 Ú P TIM_CCMR2_IC4F_1 Ú P TIM_CCMR2_IC4F_2 Ú P TIM_CCMR2_IC4F_3 Ú P TIM_CCER_CC1E ðÚ P TIM_CCER_CC1P åÚ P TIM_CCER_CC1NP Ú P TIM_CCER_CC2E ïÚ P TIM_CCER_CC2P äÚ P TIM_CCER_CC2NP Ú P TIM_CCER_CC3E îÚ P TIM_CCER_CC3P ãÚ P TIM_CCER_CC3NP Ú P TIM_CCER_CC4E íÚ P TIM_CCER_CC4P âÚ P TIM_CCER_CC4NP Ú P TIM_CNT_CNT CÚ P TIM_PSC_PSC AÚ P TIM_ARR_ARR CÚ P TIM_CCR1_CCR1 ÷Ú P TIM_CCR2_CCR2 õÚ P TIM_CCR3_CCR3 óÚ P TIM_CCR4_CCR4 ñÚ P TIM_DCR_DBA mÚ P TIM_DCR_DBA_0 ÚÚ P TIM_DCR_DBA_1 ÙÚ P TIM_DCR_DBA_2 ØÚ P TIM_DCR_DBA_3 ×Ú P TIM_DCR_DBA_4 ÖÚ P TIM_DCR_DBL bÚ P TIM_DCR_DBL_0 ÏÚ P TIM_DCR_DBL_1 ÎÚ P TIM_DCR_DBL_2 ÍÚ P TIM_DCR_DBL_3 ÌÚ P TIM_DCR_DBL_4 ËÚ P TIM_DMAR_DMAB ÑÚ P TIM_OR_TI1RMP «Ú P TIM_OR_TI1RMP_0 Ú P TIM_OR_TI1RMP_1 Ú P USART_SR_PE .Ú P USART_SR_FE 8Ú P USART_SR_NE 0Ú P
USART_SR_ORE ÛÚ P USART_SR_IDLE ¡Ú P USART_SR_RXNE Ú P USART_SR_TC ,Ú P
USART_SR_TXE ÐÚ P
USART_SR_LBD ïÚ P
USART_SR_CTS ×Ú P USART_DR_DR <Ú P USART_BRR_DIV_FRACTION ÔÚ P USART_BRR_DIV_MANTISSA ÊÚ P USART_CR1_SBK ¾Ú P USART_CR1_RWU Ú P
USART_CR1_RE Ú P
USART_CR1_TE Ú P USART_CR1_IDLEIE ìÚ P USART_CR1_RXNEIE ÍÚ P USART_CR1_TCIE wÚ P USART_CR1_TXEIE Ú P USART_CR1_PEIE yÚ P
USART_CR1_PS ýÚ P USART_CR1_PCE ÆÚ P USART_CR1_WAKE tÚ P USART_CR1_M UÚ P
USART_CR1_UE Ú P USART_CR1_OVER8 &Ú P USART_CR2_ADD ÔÚ P USART_CR2_LBDL }Ú P USART_CR2_LBDIE 9Ú P USART_CR2_LBCL ~Ú P USART_CR2_CPHA Ú P USART_CR2_CPOL mÚ P USART_CR2_CLKEN ,Ú P USART_CR2_STOP UÚ P USART_CR2_STOP_0 ÂÚ P USART_CR2_STOP_1 ÁÚ P USART_CR2_LINEN #Ú P USART_CR3_EIE ÉÚ P USART_CR3_IREN lÚ P USART_CR3_IRLP cÚ P USART_CR3_HDSEL (Ú P USART_CR3_NACK }Ú P USART_CR3_SCEN qÚ P USART_CR3_DMAR vÚ P USART_CR3_DMAT tÚ P USART_CR3_RTSE \Ú P USART_CR3_CTSE kÚ P USART_CR3_CTSIE Ú P USART_CR3_ONEBIT ÕÚ P USART_GTPR_PSC ?Ú P USART_GTPR_PSC_0 ¬Ú P USART_GTPR_PSC_1 «Ú P USART_GTPR_PSC_2 ªÚ P USART_GTPR_PSC_3 ©Ú P USART_GTPR_PSC_4 ¨Ú P USART_GTPR_PSC_5 §Ú P USART_GTPR_PSC_6 ¦Ú P USART_GTPR_PSC_7 ¥Ú P USART_GTPR_GT Ú P USB_EP0R_EA pÚ P USB_EP0R_STAT_TX ¥Ú P USB_EP0R_STAT_TX_0 Ú P USB_EP0R_STAT_TX_1 Ú P USB_EP0R_DTOG_TX ³Ú P USB_EP0R_CTR_TX úÚ P USB_EP0R_EP_KIND ÒÚ P USB_EP0R_EP_TYPE ¶Ú P USB_EP0R_EP_TYPE_0 #Ú P USB_EP0R_EP_TYPE_1 "Ú P USB_EP0R_SETUP _Ú P USB_EP0R_STAT_RX §Ú P USB_EP0R_STAT_RX_0 Ú P USB_EP0R_STAT_RX_1 Ú P USB_EP0R_DTOG_RX µÚ P USB_EP0R_CTR_RX üÚ P USB_EP1R_EA oÚ P USB_EP1R_STAT_TX ¤Ú P USB_EP1R_STAT_TX_0 Ú P USB_EP1R_STAT_TX_1 Ú P USB_EP1R_DTOG_TX ²Ú P USB_EP1R_CTR_TX ùÚ P USB_EP1R_EP_KIND ÑÚ P USB_EP1R_EP_TYPE µÚ P USB_EP1R_EP_TYPE_0 "Ú P USB_EP1R_EP_TYPE_1 !Ú P USB_EP1R_SETUP ^Ú P USB_EP1R_STAT_RX ¦Ú P USB_EP1R_STAT_RX_0 Ú P USB_EP1R_STAT_RX_1 Ú P USB_EP1R_DTOG_RX ´Ú P USB_EP1R_CTR_RX ûÚ P USB_EP2R_EA nÚ P USB_EP2R_STAT_TX £Ú P USB_EP2R_STAT_TX_0 Ú P USB_EP2R_STAT_TX_1 Ú P USB_EP2R_DTOG_TX ±Ú P USB_EP2R_CTR_TX øÚ P USB_EP2R_EP_KIND ÐÚ P USB_EP2R_EP_TYPE ´Ú P USB_EP2R_EP_TYPE_0 !Ú P USB_EP2R_EP_TYPE_1 Ú P USB_EP2R_SETUP ]Ú P USB_EP2R_STAT_RX ¥Ú P USB_EP2R_STAT_RX_0 Ú P USB_EP2R_STAT_RX_1 Ú P USB_EP2R_DTOG_RX ³Ú P USB_EP2R_CTR_RX úÚ P USB_EP3R_EA mÚ P USB_EP3R_STAT_TX ¢Ú P USB_EP3R_STAT_TX_0 Ú P USB_EP3R_STAT_TX_1 Ú P USB_EP3R_DTOG_TX °Ú P USB_EP3R_CTR_TX ÷Ú P USB_EP3R_EP_KIND ÏÚ P USB_EP3R_EP_TYPE ³Ú P USB_EP3R_EP_TYPE_0 Ú P USB_EP3R_EP_TYPE_1 Ú P USB_EP3R_SETUP \Ú P USB_EP3R_STAT_RX ¤Ú P USB_EP3R_STAT_RX_0 Ú P USB_EP3R_STAT_RX_1 Ú P USB_EP3R_DTOG_RX ²Ú P USB_EP3R_CTR_RX ùÚ P USB_EP4R_EA lÚ P USB_EP4R_STAT_TX ¡Ú P USB_EP4R_STAT_TX_0 Ú P USB_EP4R_STAT_TX_1
Ú P USB_EP4R_DTOG_TX ¯Ú P USB_EP4R_CTR_TX öÚ P USB_EP4R_EP_KIND ÎÚ P USB_EP4R_EP_TYPE ²Ú P USB_EP4R_EP_TYPE_0 Ú P USB_EP4R_EP_TYPE_1 Ú P USB_EP4R_SETUP [Ú P USB_EP4R_STAT_RX £Ú P USB_EP4R_STAT_RX_0 Ú P USB_EP4R_STAT_RX_1 Ú P USB_EP4R_DTOG_RX ±Ú P USB_EP4R_CTR_RX øÚ P USB_EP5R_EA kÚ P USB_EP5R_STAT_TX Ú P USB_EP5R_STAT_TX_0
Ú P USB_EP5R_STAT_TX_1 Ú P USB_EP5R_DTOG_TX ®Ú P USB_EP5R_CTR_TX õÚ P USB_EP5R_EP_KIND ÍÚ P USB_EP5R_EP_TYPE ±Ú P USB_EP5R_EP_TYPE_0 Ú P USB_EP5R_EP_TYPE_1 Ú P USB_EP5R_SETUP ZÚ P USB_EP5R_STAT_RX ¢Ú P USB_EP5R_STAT_RX_0 Ú P USB_EP5R_STAT_RX_1 Ú P USB_EP5R_DTOG_RX °Ú P USB_EP5R_CTR_RX ÷Ú P USB_EP6R_EA jÚ P USB_EP6R_STAT_TX Ú P USB_EP6R_STAT_TX_0 Ú P USB_EP6R_STAT_TX_1 Ú P USB_EP6R_DTOG_TX Ú P USB_EP6R_CTR_TX ôÚ P USB_EP6R_EP_KIND ÌÚ P USB_EP6R_EP_TYPE °Ú P USB_EP6R_EP_TYPE_0 Ú P USB_EP6R_EP_TYPE_1 Ú P USB_EP6R_SETUP YÚ P USB_EP6R_STAT_RX ¡Ú P USB_EP6R_STAT_RX_0 Ú P USB_EP6R_STAT_RX_1
Ú P USB_EP6R_DTOG_RX ¯Ú P USB_EP6R_CTR_RX öÚ P USB_EP7R_EA iÚ P USB_EP7R_STAT_TX Ú P USB_EP7R_STAT_TX_0 Ú P USB_EP7R_STAT_TX_1 |
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Ú P USB_EP7R_DTOG_TX ¬Ú P USB_EP7R_CTR_TX óÚ P USB_EP7R_EP_KIND ËÚ P USB_EP7R_EP_TYPE ¯Ú P USB_EP7R_EP_TYPE_0 Ú P USB_EP7R_EP_TYPE_1 Ú P USB_EP7R_SETUP XÚ P USB_EP7R_STAT_RX Ú P USB_EP7R_STAT_RX_0
Ú P USB_EP7R_STAT_RX_1 Ú P USB_EP7R_DTOG_RX ®Ú P USB_EP7R_CTR_RX õÚ P USB_CNTR_FRES ¢Ú P USB_CNTR_PDWN Ú P USB_CNTR_LP_MODE ¬Ú P USB_CNTR_FSUSP ?Ú P USB_CNTR_RESUME ýÚ P USB_CNTR_ESOFM VÚ P USB_CNTR_SOFM Ú P USB_CNTR_RESETM þÚ P USB_CNTR_SUSPM 8Ú P USB_CNTR_WKUPM <Ú P USB_CNTR_ERRM Ú P USB_CNTR_PMAOVRM ªÚ P USB_CNTR_CTRM Ú P USB_ISTR_EP_ID DÚ P
USB_ISTR_DIR êÚ P USB_ISTR_ESOF Ú P
USB_ISTR_SOF áÚ P USB_ISTR_RESET BÚ P USB_ISTR_SUSP |Ú P USB_ISTR_WKUP Ú P
USB_ISTR_ERR àÚ P USB_ISTR_PMAOVR îÚ P
USB_ISTR_CTR àÚ P USB_FNR_FN Ú P
USB_FNR_LSOF ñÚ P USB_FNR_LCK MÚ P
USB_FNR_RXDM êÚ P
USB_FNR_RXDP çÚ P USB_DADDR_ADD áÚ P USB_DADDR_ADD0 ¯Ú P USB_DADDR_ADD1 ®Ú P USB_DADDR_ADD2 Ú P USB_DADDR_ADD3 ¬Ú P USB_DADDR_ADD4 «Ú P USB_DADDR_ADD5 ªÚ P USB_DADDR_ADD6 ©Ú P
USB_DADDR_EF !Ú P USB_BTABLE_BTABLE Ú P USB_ADDR0_TX_ADDR0_TX MÚ P USB_ADDR1_TX_ADDR1_TX KÚ P USB_ADDR2_TX_ADDR2_TX IÚ P USB_ADDR3_TX_ADDR3_TX GÚ P USB_ADDR4_TX_ADDR4_TX EÚ P USB_ADDR5_TX_ADDR5_TX CÚ P USB_ADDR6_TX_ADDR6_TX AÚ P USB_ADDR7_TX_ADDR7_TX ?Ú P USB_COUNT0_TX_COUNT0_TX mÚ P USB_COUNT1_TX_COUNT1_TX kÚ P USB_COUNT2_TX_COUNT2_TX iÚ P USB_COUNT3_TX_COUNT3_TX gÚ P USB_COUNT4_TX_COUNT4_TX eÚ P USB_COUNT5_TX_COUNT5_TX cÚ P USB_COUNT6_TX_COUNT6_TX aÚ P USB_COUNT7_TX_COUNT7_TX _Ú$ P USB_COUNT0_TX_0_COUNT0_TX_0 GÚ$ P USB_COUNT0_TX_1_COUNT0_TX_1 EÚ$ P USB_COUNT1_TX_0_COUNT1_TX_0 EÚ$ P USB_COUNT1_TX_1_COUNT1_TX_1 CÚ$ P USB_COUNT2_TX_0_COUNT2_TX_0 CÚ$ P USB_COUNT2_TX_1_COUNT2_TX_1 AÚ$ P USB_COUNT3_TX_0_COUNT3_TX_0 AÚ$ P USB_COUNT3_TX_1_COUNT3_TX_1 ?Ú$ P USB_COUNT4_TX_0_COUNT4_TX_0 ?Ú$ P USB_COUNT4_TX_1_COUNT4_TX_1 =Ú$ P USB_COUNT5_TX_0_COUNT5_TX_0 =Ú$ P USB_COUNT5_TX_1_COUNT5_TX_1 ;Ú$ P USB_COUNT6_TX_0_COUNT6_TX_0 ;Ú$ P USB_COUNT6_TX_1_COUNT6_TX_1 9Ú$ P USB_COUNT7_TX_0_COUNT7_TX_0 9Ú$ P USB_COUNT7_TX_1_COUNT7_TX_1 7Ú P USB_ADDR0_RX_ADDR0_RX QÚ P USB_ADDR1_RX_ADDR1_RX OÚ P USB_ADDR2_RX_ADDR2_RX MÚ P USB_ADDR3_RX_ADDR3_RX KÚ P USB_ADDR4_RX_ADDR4_RX IÚ P USB_ADDR5_RX_ADDR5_RX GÚ P USB_ADDR6_RX_ADDR6_RX EÚ P USB_ADDR7_RX_ADDR7_RX CÚ P USB_COUNT0_RX_COUNT0_RX qÚ P USB_COUNT0_RX_NUM_BLOCK yÚ" P USB_COUNT0_RX_NUM_BLOCK_0 æÚ" P USB_COUNT0_RX_NUM_BLOCK_1 åÚ" P USB_COUNT0_RX_NUM_BLOCK_2 äÚ" P USB_COUNT0_RX_NUM_BLOCK_3 ãÚ" P USB_COUNT0_RX_NUM_BLOCK_4 âÚ P USB_COUNT0_RX_BLSIZE pÚ P USB_COUNT1_RX_COUNT1_RX oÚ P USB_COUNT1_RX_NUM_BLOCK xÚ" P USB_COUNT1_RX_NUM_BLOCK_0 åÚ" P USB_COUNT1_RX_NUM_BLOCK_1 äÚ" P USB_COUNT1_RX_NUM_BLOCK_2 ãÚ" P USB_COUNT1_RX_NUM_BLOCK_3 âÚ" P USB_COUNT1_RX_NUM_BLOCK_4 áÚ P USB_COUNT1_RX_BLSIZE oÚ P USB_COUNT2_RX_COUNT2_RX mÚ P USB_COUNT2_RX_NUM_BLOCK wÚ" P USB_COUNT2_RX_NUM_BLOCK_0 äÚ" P USB_COUNT2_RX_NUM_BLOCK_1 ãÚ" P USB_COUNT2_RX_NUM_BLOCK_2 âÚ" P USB_COUNT2_RX_NUM_BLOCK_3 áÚ" P USB_COUNT2_RX_NUM_BLOCK_4 àÚ P USB_COUNT2_RX_BLSIZE nÚ P USB_COUNT3_RX_COUNT3_RX kÚ P USB_COUNT3_RX_NUM_BLOCK vÚ" P USB_COUNT3_RX_NUM_BLOCK_0 ãÚ" P USB_COUNT3_RX_NUM_BLOCK_1 âÚ" P USB_COUNT3_RX_NUM_BLOCK_2 áÚ" P USB_COUNT3_RX_NUM_BLOCK_3 àÚ" P USB_COUNT3_RX_NUM_BLOCK_4 ßÚ P USB_COUNT3_RX_BLSIZE mÚ P USB_COUNT4_RX_COUNT4_RX iÚ P USB_COUNT4_RX_NUM_BLOCK uÚ" P USB_COUNT4_RX_NUM_BLOCK_0 âÚ" P USB_COUNT4_RX_NUM_BLOCK_1 áÚ" P USB_COUNT4_RX_NUM_BLOCK_2 àÚ" P USB_COUNT4_RX_NUM_BLOCK_3 ßÚ" P USB_COUNT4_RX_NUM_BLOCK_4 ÞÚ P USB_COUNT4_RX_BLSIZE lÚ P USB_COUNT5_RX_COUNT5_RX gÚ P USB_COUNT5_RX_NUM_BLOCK tÚ" P USB_COUNT5_RX_NUM_BLOCK_0 áÚ" P USB_COUNT5_RX_NUM_BLOCK_1 àÚ" P USB_COUNT5_RX_NUM_BLOCK_2 ßÚ" P USB_COUNT5_RX_NUM_BLOCK_3 ÞÚ" P USB_COUNT5_RX_NUM_BLOCK_4 ÝÚ P USB_COUNT5_RX_BLSIZE kÚ P USB_COUNT6_RX_COUNT6_RX eÚ P USB_COUNT6_RX_NUM_BLOCK sÚ" P USB_COUNT6_RX_NUM_BLOCK_0 àÚ" P USB_COUNT6_RX_NUM_BLOCK_1 ßÚ" P USB_COUNT6_RX_NUM_BLOCK_2 ÞÚ" P USB_COUNT6_RX_NUM_BLOCK_3 ÝÚ" P USB_COUNT6_RX_NUM_BLOCK_4 ÜÚ P USB_COUNT6_RX_BLSIZE jÚ P USB_COUNT7_RX_COUNT7_RX cÚ P USB_COUNT7_RX_NUM_BLOCK rÚ" P USB_COUNT7_RX_NUM_BLOCK_0 ßÚ" P USB_COUNT7_RX_NUM_BLOCK_1 ÞÚ" P USB_COUNT7_RX_NUM_BLOCK_2 ÝÚ" P USB_COUNT7_RX_NUM_BLOCK_3 ÜÚ" P USB_COUNT7_RX_NUM_BLOCK_4 ÛÚ P USB_COUNT7_RX_BLSIZE iÚ$ P USB_COUNT0_RX_0_COUNT0_RX_0 KÚ$ P USB_COUNT0_RX_0_NUM_BLOCK_0 SÚ& P USB_COUNT0_RX_0_NUM_BLOCK_0_0 ÀÚ& P USB_COUNT0_RX_0_NUM_BLOCK_0_1 ¿Ú& P USB_COUNT0_RX_0_NUM_BLOCK_0_2 ¾Ú& P USB_COUNT0_RX_0_NUM_BLOCK_0_3 ½Ú& P USB_COUNT0_RX_0_NUM_BLOCK_0_4 ¼Ú! P USB_COUNT0_RX_0_BLSIZE_0 JÚ$ P USB_COUNT0_RX_1_COUNT0_RX_1 IÚ$ P USB_COUNT0_RX_1_NUM_BLOCK_1 QÚ& P USB_COUNT0_RX_1_NUM_BLOCK_1_0 ¾Ú& P USB_COUNT0_RX_1_NUM_BLOCK_1_1 ½Ú& P USB_COUNT0_RX_1_NUM_BLOCK_1_2 ¼Ú& P USB_COUNT0_RX_1_NUM_BLOCK_1_3 »Ú& P USB_COUNT0_RX_1_NUM_BLOCK_1_4 ºÚ! P USB_COUNT0_RX_1_BLSIZE_1 HÚ$ P USB_COUNT1_RX_0_COUNT1_RX_0 IÚ$ P USB_COUNT1_RX_0_NUM_BLOCK_0 RÚ& P USB_COUNT1_RX_0_NUM_BLOCK_0_0 ¿Ú& P USB_COUNT1_RX_0_NUM_BLOCK_0_1 ¾Ú& P USB_COUNT1_RX_0_NUM_BLOCK_0_2 ½Ú& P USB_COUNT1_RX_0_NUM_BLOCK_0_3 ¼Ú& P USB_COUNT1_RX_0_NUM_BLOCK_0_4 »Ú! P USB_COUNT1_RX_0_BLSIZE_0 IÚ$ P USB_COUNT1_RX_1_COUNT1_RX_1 GÚ$ P USB_COUNT1_RX_1_NUM_BLOCK_1 PÚ& P USB_COUNT1_RX_1_NUM_BLOCK_1_0 ½Ú& P USB_COUNT1_RX_1_NUM_BLOCK_1_1 ¼Ú& P USB_COUNT1_RX_1_NUM_BLOCK_1_2 »Ú& P USB_COUNT1_RX_1_NUM_BLOCK_1_3 ºÚ& P USB_COUNT1_RX_1_NUM_BLOCK_1_4 ¹Ú! P USB_COUNT1_RX_1_BLSIZE_1 GÚ$ P USB_COUNT2_RX_0_COUNT2_RX_0 GÚ$ P USB_COUNT2_RX_0_NUM_BLOCK_0 QÚ& P USB_COUNT2_RX_0_NUM_BLOCK_0_0 ¾Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_1 ½Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_2 ¼Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_3 »Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_4 ºÚ! P USB_COUNT2_RX_0_BLSIZE_0 HÚ$ P USB_COUNT2_RX_1_COUNT2_RX_1 EÚ$ P USB_COUNT2_RX_1_NUM_BLOCK_1 OÚ& P USB_COUNT2_RX_1_NUM_BLOCK_1_0 ¼Ú& P USB_COUNT2_RX_1_NUM_BLOCK_1_1 »Ú& P USB_COUNT2_RX_1_NUM_BLOCK_1_2 ºÚ& P USB_COUNT2_RX_1_NUM_BLOCK_1_3 ¹Ú& P USB_COUNT2_RX_1_NUM_BLOCK_1_4 ¸Ú! P USB_COUNT2_RX_1_BLSIZE_1 FÚ$ P USB_COUNT3_RX_0_COUNT3_RX_0 EÚ$ P USB_COUNT3_RX_0_NUM_BLOCK_0 PÚ& P USB_COUNT3_RX_0_NUM_BLOCK_0_0 ½Ú& P USB_COUNT3_RX_0_NUM_BLOCK_0_1 ¼Ú& P USB_COUNT3_RX_0_NUM_BLOCK_0_2 »Ú& P USB_COUNT3_RX_0_NUM_BLOCK_0_3 ºÚ& P USB_COUNT3_RX_0_NUM_BLOCK_0_4 ¹Ú! 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828 |
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USB_FNR_RXDM êÚ P
USB_FNR_RXDP çÚ P USB_DADDR_ADD áÚ P USB_DADDR_ADD0 ¯Ú P USB_DADDR_ADD1 ®Ú P USB_DADDR_ADD2 Ú P USB_DADDR_ADD3 ¬Ú P USB_DADDR_ADD4 «Ú P USB_DADDR_ADD5 ªÚ P USB_DADDR_ADD6 ©Ú P
USB_DADDR_EF !Ú P USB_BTABLE_BTABLE Ú P USB_ADDR0_TX_ADDR0_TX MÚ P USB_ADDR1_TX_ADDR1_TX KÚ P USB_ADDR2_TX_ADDR2_TX IÚ P USB_ADDR3_TX_ADDR3_TX GÚ P USB_ADDR4_TX_ADDR4_TX EÚ P USB_ADDR5_TX_ADDR5_TX CÚ P USB_ADDR6_TX_ADDR6_TX AÚ P USB_ADDR7_TX_ADDR7_TX ?Ú P USB_COUNT0_TX_COUNT0_TX mÚ P USB_COUNT1_TX_COUNT1_TX kÚ P USB_COUNT2_TX_COUNT2_TX iÚ P USB_COUNT3_TX_COUNT3_TX gÚ P USB_COUNT4_TX_COUNT4_TX eÚ P USB_COUNT5_TX_COUNT5_TX cÚ P USB_COUNT6_TX_COUNT6_TX aÚ P USB_COUNT7_TX_COUNT7_TX _Ú$ P USB_COUNT0_TX_0_COUNT0_TX_0 GÚ$ P USB_COUNT0_TX_1_COUNT0_TX_1 EÚ$ P USB_COUNT1_TX_0_COUNT1_TX_0 EÚ$ P USB_COUNT1_TX_1_COUNT1_TX_1 CÚ$ P USB_COUNT2_TX_0_COUNT2_TX_0 CÚ$ P USB_COUNT2_TX_1_COUNT2_TX_1 AÚ$ P USB_COUNT3_TX_0_COUNT3_TX_0 AÚ$ P USB_COUNT3_TX_1_COUNT3_TX_1 ?Ú$ P USB_COUNT4_TX_0_COUNT4_TX_0 ?Ú$ P USB_COUNT4_TX_1_COUNT4_TX_1 =Ú$ P USB_COUNT5_TX_0_COUNT5_TX_0 =Ú$ P USB_COUNT5_TX_1_COUNT5_TX_1 ;Ú$ P USB_COUNT6_TX_0_COUNT6_TX_0 ;Ú$ P USB_COUNT6_TX_1_COUNT6_TX_1 9Ú$ P USB_COUNT7_TX_0_COUNT7_TX_0 9Ú$ P USB_COUNT7_TX_1_COUNT7_TX_1 7Ú P USB_ADDR0_RX_ADDR0_RX QÚ P USB_ADDR1_RX_ADDR1_RX OÚ P USB_ADDR2_RX_ADDR2_RX MÚ P USB_ADDR3_RX_ADDR3_RX KÚ P USB_ADDR4_RX_ADDR4_RX IÚ P USB_ADDR5_RX_ADDR5_RX GÚ P USB_ADDR6_RX_ADDR6_RX EÚ P USB_ADDR7_RX_ADDR7_RX CÚ P USB_COUNT0_RX_COUNT0_RX qÚ P USB_COUNT0_RX_NUM_BLOCK yÚ" P USB_COUNT0_RX_NUM_BLOCK_0 æÚ" P USB_COUNT0_RX_NUM_BLOCK_1 åÚ" P USB_COUNT0_RX_NUM_BLOCK_2 äÚ" P USB_COUNT0_RX_NUM_BLOCK_3 ãÚ" P USB_COUNT0_RX_NUM_BLOCK_4 âÚ P USB_COUNT0_RX_BLSIZE pÚ P USB_COUNT1_RX_COUNT1_RX oÚ P USB_COUNT1_RX_NUM_BLOCK xÚ" P USB_COUNT1_RX_NUM_BLOCK_0 åÚ" P USB_COUNT1_RX_NUM_BLOCK_1 äÚ" P USB_COUNT1_RX_NUM_BLOCK_2 ãÚ" P USB_COUNT1_RX_NUM_BLOCK_3 âÚ" P USB_COUNT1_RX_NUM_BLOCK_4 áÚ P USB_COUNT1_RX_BLSIZE oÚ P USB_COUNT2_RX_COUNT2_RX mÚ P USB_COUNT2_RX_NUM_BLOCK wÚ" P USB_COUNT2_RX_NUM_BLOCK_0 äÚ" P USB_COUNT2_RX_NUM_BLOCK_1 ãÚ" P USB_COUNT2_RX_NUM_BLOCK_2 âÚ" P USB_COUNT2_RX_NUM_BLOCK_3 áÚ" P USB_COUNT2_RX_NUM_BLOCK_4 àÚ P USB_COUNT2_RX_BLSIZE nÚ P USB_COUNT3_RX_COUNT3_RX kÚ P USB_COUNT3_RX_NUM_BLOCK vÚ" P USB_COUNT3_RX_NUM_BLOCK_0 ãÚ" P USB_COUNT3_RX_NUM_BLOCK_1 âÚ" P USB_COUNT3_RX_NUM_BLOCK_2 áÚ" P USB_COUNT3_RX_NUM_BLOCK_3 àÚ" P USB_COUNT3_RX_NUM_BLOCK_4 ßÚ P USB_COUNT3_RX_BLSIZE mÚ P USB_COUNT4_RX_COUNT4_RX iÚ P USB_COUNT4_RX_NUM_BLOCK uÚ" P USB_COUNT4_RX_NUM_BLOCK_0 âÚ" P USB_COUNT4_RX_NUM_BLOCK_1 áÚ" P USB_COUNT4_RX_NUM_BLOCK_2 àÚ" P USB_COUNT4_RX_NUM_BLOCK_3 ßÚ" P USB_COUNT4_RX_NUM_BLOCK_4 ÞÚ P USB_COUNT4_RX_BLSIZE lÚ P USB_COUNT5_RX_COUNT5_RX gÚ P USB_COUNT5_RX_NUM_BLOCK tÚ" P USB_COUNT5_RX_NUM_BLOCK_0 áÚ" P USB_COUNT5_RX_NUM_BLOCK_1 àÚ" P USB_COUNT5_RX_NUM_BLOCK_2 ßÚ" P USB_COUNT5_RX_NUM_BLOCK_3 ÞÚ" P USB_COUNT5_RX_NUM_BLOCK_4 ÝÚ P USB_COUNT5_RX_BLSIZE kÚ P USB_COUNT6_RX_COUNT6_RX eÚ P USB_COUNT6_RX_NUM_BLOCK sÚ" P USB_COUNT6_RX_NUM_BLOCK_0 àÚ" P USB_COUNT6_RX_NUM_BLOCK_1 ßÚ" P USB_COUNT6_RX_NUM_BLOCK_2 ÞÚ" P USB_COUNT6_RX_NUM_BLOCK_3 ÝÚ" P USB_COUNT6_RX_NUM_BLOCK_4 ÜÚ P USB_COUNT6_RX_BLSIZE jÚ P USB_COUNT7_RX_COUNT7_RX cÚ P USB_COUNT7_RX_NUM_BLOCK rÚ" P USB_COUNT7_RX_NUM_BLOCK_0 ßÚ" P USB_COUNT7_RX_NUM_BLOCK_1 ÞÚ" P USB_COUNT7_RX_NUM_BLOCK_2 ÝÚ" P USB_COUNT7_RX_NUM_BLOCK_3 ÜÚ" P USB_COUNT7_RX_NUM_BLOCK_4 ÛÚ P USB_COUNT7_RX_BLSIZE iÚ$ P USB_COUNT0_RX_0_COUNT0_RX_0 KÚ$ P USB_COUNT0_RX_0_NUM_BLOCK_0 SÚ& P USB_COUNT0_RX_0_NUM_BLOCK_0_0 ÀÚ& P USB_COUNT0_RX_0_NUM_BLOCK_0_1 ¿Ú& P USB_COUNT0_RX_0_NUM_BLOCK_0_2 ¾Ú& P USB_COUNT0_RX_0_NUM_BLOCK_0_3 ½Ú& P USB_COUNT0_RX_0_NUM_BLOCK_0_4 ¼Ú! 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P USB_COUNT1_RX_1_BLSIZE_1 GÚ$ P USB_COUNT2_RX_0_COUNT2_RX_0 GÚ$ P USB_COUNT2_RX_0_NUM_BLOCK_0 QÚ& P USB_COUNT2_RX_0_NUM_BLOCK_0_0 ¾Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_1 ½Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_2 ¼Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_3 »Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_4 ºÚ! P USB_COUNT2_RX_0_BLSIZE_0 HÚ$ P USB_COUNT2_RX_1_COUNT2_RX_1 EÚ$ P USB_COUNT2_RX_1_NUM_BLOCK_1 OÚ& P USB_COUNT2_RX_1_NUM_BLOCK_1_0 ¼Ú& P USB_COUNT2_RX_1_NUM_BLOCK_1_1 »Ú& P USB_COUNT2_RX_1_NUM_BLOCK_1_2 ºÚ& P USB_COUNT2_RX_1_NUM_BLOCK_1_3 ¹Ú& P USB_COUNT2_RX_1_NUM_BLOCK_1_4 ¸Ú! P USB_COUNT2_RX_1_BLSIZE_1 FÚ$ P USB_COUNT3_RX_0_COUNT3_RX_0 EÚ$ P USB_COUNT3_RX_0_NUM_BLOCK_0 PÚ& P USB_COUNT3_RX_0_NUM_BLOCK_0_0 ½Ú& P USB_COUNT3_RX_0_NUM_BLOCK_0_1 ¼Ú& P USB_COUNT3_RX_0_NUM_BLOCK_0_2 »Ú& P USB_COUNT3_RX_0_NUM_BLOCK_0_3 ºÚ& P USB_COUNT3_RX_0_NUM_BLOCK_0_4 ¹Ú! P USB_COUNT3_RX_0_BLSIZE_0 GÚ$ P USB_COUNT3_RX_1_COUNT3_RX_1 CÚ$ P USB_COUNT3_RX_1_NUM_BLOCK_1 NÚ& P USB_COUNT3_RX_1_NUM_BLOCK_1_0 »Ú& P USB_COUNT3_RX_1_NUM_BLOCK_1_1 ºÚ& P USB_COUNT3_RX_1_NUM_BLOCK_1_2 ¹Ú& P USB_COUNT3_RX_1_NUM_BLOCK_1_3 ¸Ú& P USB_COUNT3_RX_1_NUM_BLOCK_1_4 ·Ú! P USB_COUNT3_RX_1_BLSIZE_1 EÚ$ P USB_COUNT4_RX_0_COUNT4_RX_0 CÚ$ P USB_COUNT4_RX_0_NUM_BLOCK_0 OÚ& P USB_COUNT4_RX_0_NUM_BLOCK_0_0 ¼Ú& P USB_COUNT4_RX_0_NUM_BLOCK_0_1 »Ú& P USB_COUNT4_RX_0_NUM_BLOCK_0_2 ºÚ& P USB_COUNT4_RX_0_NUM_BLOCK_0_3 ¹Ú& P USB_COUNT4_RX_0_NUM_BLOCK_0_4 ¸Ú! P USB_COUNT4_RX_0_BLSIZE_0 FÚ$ P USB_COUNT4_RX_1_COUNT4_RX_1 AÚ$ P USB_COUNT4_RX_1_NUM_BLOCK_1 MÚ& P USB_COUNT4_RX_1_NUM_BLOCK_1_0 ºÚ& P USB_COUNT4_RX_1_NUM_BLOCK_1_1 ¹Ú& P USB_COUNT4_RX_1_NUM_BLOCK_1_2 ¸Ú& P USB_COUNT4_RX_1_NUM_BLOCK_1_3 ·Ú& P USB_COUNT4_RX_1_NUM_BLOCK_1_4 ¶Ú! P USB_COUNT4_RX_1_BLSIZE_1 DÚ$ P USB_COUNT5_RX_0_COUNT5_RX_0 AÚ$ P USB_COUNT5_RX_0_NUM_BLOCK_0 NÚ& P USB_COUNT5_RX_0_NUM_BLOCK_0_0 »Ú& P USB_COUNT5_RX_0_NUM_BLOCK_0_1 ºÚ& P USB_COUNT5_RX_0_NUM_BLOCK_0_2 ¹Ú& P USB_COUNT5_RX_0_NUM_BLOCK_0_3 ¸Ú& P USB_COUNT5_RX_0_NUM_BLOCK_0_4 ·Ú! P USB_COUNT5_RX_0_BLSIZE_0 EÚ$ P USB_COUNT5_RX_1_COUNT5_RX_1 ?Ú$ P USB_COUNT5_RX_1_NUM_BLOCK_1 LÚ& P USB_COUNT5_RX_1_NUM_BLOCK_1_0 ¹Ú& P USB_COUNT5_RX_1_NUM_BLOCK_1_1 ¸Ú& P USB_COUNT5_RX_1_NUM_BLOCK_1_2 ·Ú& P USB_COUNT5_RX_1_NUM_BLOCK_1_3 ¶Ú& P USB_COUNT5_RX_1_NUM_BLOCK_1_4 µÚ! P USB_COUNT5_RX_1_BLSIZE_1 CÚ$ P USB_COUNT6_RX_0_COUNT6_RX_0 ?Ú$ P USB_COUNT6_RX_0_NUM_BLOCK_0 MÚ& P USB_COUNT6_RX_0_NUM_BLOCK_0_0 ºÚ& P USB_COUNT6_RX_0_NUM_BLOCK_0_1 ¹Ú& P USB_COUNT6_RX_0_NUM_BLOCK_0_2 ¸Ú& P USB_COUNT6_RX_0_NUM_BLOCK_0_3 ·Ú& P USB_COUNT6_RX_0_NUM_BLOCK_0_4 ¶Ú! P USB_COUNT6_RX_0_BLSIZE_0 DÚ$ P USB_COUNT6_RX_1_COUNT6_RX_1 =Ú$ P USB_COUNT6_RX_1_NUM_BLOCK_1 KÚ& P USB_COUNT6_RX_1_NUM_BLOCK_1_0 ¸Ú& P USB_COUNT6_RX_1_NUM_BLOCK_1_1 ·Ú& P USB_COUNT6_RX_1_NUM_BLOCK_1_2 ¶Ú& P USB_COUNT6_RX_1_NUM_BLOCK_1_3 µÚ& P USB_COUNT6_RX_1_NUM_BLOCK_1_4 ´Ú! P USB_COUNT6_RX_1_BLSIZE_1 BÚ$ P USB_COUNT7_RX_0_COUNT7_RX_0 =Ú$ P USB_COUNT7_RX_0_NUM_BLOCK_0 LÚ& P USB_COUNT7_RX_0_NUM_BLOCK_0_0 ¹Ú& P USB_COUNT7_RX_0_NUM_BLOCK_0_1 ¸Ú& P USB_COUNT7_RX_0_NUM_BLOCK_0_2 ·Ú& P USB_COUNT7_RX_0_NUM_BLOCK_0_3 ¶Ú& P USB_COUNT7_RX_0_NUM_BLOCK_0_4 µÚ! P USB_COUNT7_RX_0_BLSIZE_0 CÚ$ P USB_COUNT7_RX_1_COUNT7_RX_1 ;Ú$ P USB_COUNT7_RX_1_NUM_BLOCK_1 JÚ& P USB_COUNT7_RX_1_NUM_BLOCK_1_0 ·Ú& P USB_COUNT7_RX_1_NUM_BLOCK_1_1 ¶Ú& P USB_COUNT7_RX_1_NUM_BLOCK_1_2 µÚ& P USB_COUNT7_RX_1_NUM_BLOCK_1_3 ´Ú& P USB_COUNT7_RX_1_NUM_BLOCK_1_4 ³Ú! P USB_COUNT7_RX_1_BLSIZE_1 AÚ P |
| 829 |
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WWDG_CR_WDGA Ú P WWDG_CFR_W Ú P WWDG_CFR_W0 \Ú P WWDG_CFR_W1 [Ú P WWDG_CFR_W2 ZÚ P WWDG_CFR_W3 YÚ P WWDG_CFR_W4 XÚ P WWDG_CFR_W5 WÚ P WWDG_CFR_W6 VÚ P WWDG_CFR_WDGTB eÚ P WWDG_CFR_WDGTB0 3Ú P WWDG_CFR_WDGTB1 2Ú P
WWDG_CFR_EWI üÚ P
WWDG_SR_EWIF ìÚ P SysTick_CTRL_ENABLE AÚ P SysTick_CTRL_TICKINT ÐÚ P SysTick_CTRL_CLKSOURCE 7Ú P SysTick_CTRL_COUNTFLAG ?Ú P SysTick_LOAD_RELOAD FÚ P SysTick_VAL_CURRENT Ú P SysTick_CALIB_TENMS ;Ú P SysTick_CALIB_SKEW Ú P SysTick_CALIB_NOREF HÚ P NVIC_ISER_SETENA ÊÚ P NVIC_ISER_SETENA_0 7Ú P NVIC_ISER_SETENA_1 6Ú P NVIC_ISER_SETENA_2 5Ú P NVIC_ISER_SETENA_3 4Ú P NVIC_ISER_SETENA_4 3Ú P NVIC_ISER_SETENA_5 2Ú P NVIC_ISER_SETENA_6 1Ú P NVIC_ISER_SETENA_7 0Ú P NVIC_ISER_SETENA_8 /Ú P NVIC_ISER_SETENA_9 .Ú P NVIC_ISER_SETENA_10 Ú P NVIC_ISER_SETENA_11 Ú P NVIC_ISER_SETENA_12 Ú P NVIC_ISER_SETENA_13 Ú P NVIC_ISER_SETENA_14 Ú P NVIC_ISER_SETENA_15 ÿÚ P NVIC_ISER_SETENA_16 þÚ P NVIC_ISER_SETENA_17 ýÚ P NVIC_ISER_SETENA_18 üÚ P NVIC_ISER_SETENA_19 ûÚ P NVIC_ISER_SETENA_20 Ú P NVIC_ISER_SETENA_21 Ú P NVIC_ISER_SETENA_22 Ú P NVIC_ISER_SETENA_23 Ú P NVIC_ISER_SETENA_24 ÿÚ P NVIC_ISER_SETENA_25 þÚ P NVIC_ISER_SETENA_26 ýÚ P NVIC_ISER_SETENA_27 üÚ P NVIC_ISER_SETENA_28 ûÚ P NVIC_ISER_SETENA_29 úÚ P NVIC_ISER_SETENA_30 Ú P NVIC_ISER_SETENA_31 Ú P NVIC_ICER_CLRENA åÚ P NVIC_ICER_CLRENA_0 RÚ P NVIC_ICER_CLRENA_1 QÚ P NVIC_ICER_CLRENA_2 PÚ P NVIC_ICER_CLRENA_3 OÚ P NVIC_ICER_CLRENA_4 NÚ P NVIC_ICER_CLRENA_5 MÚ P NVIC_ICER_CLRENA_6 LÚ P NVIC_ICER_CLRENA_7 KÚ P NVIC_ICER_CLRENA_8 JÚ P NVIC_ICER_CLRENA_9 IÚ P NVIC_ICER_CLRENA_10 Ú P NVIC_ICER_CLRENA_11 Ú P NVIC_ICER_CLRENA_12 Ú P NVIC_ICER_CLRENA_13 Ú P NVIC_ICER_CLRENA_14 Ú P NVIC_ICER_CLRENA_15 Ú P NVIC_ICER_CLRENA_16 Ú P NVIC_ICER_CLRENA_17 Ú P NVIC_ICER_CLRENA_18 Ú P NVIC_ICER_CLRENA_19 Ú P NVIC_ICER_CLRENA_20 Ú P NVIC_ICER_CLRENA_21 Ú P NVIC_ICER_CLRENA_22 Ú P NVIC_ICER_CLRENA_23 Ú P NVIC_ICER_CLRENA_24 Ú P NVIC_ICER_CLRENA_25 Ú P NVIC_ICER_CLRENA_26 Ú P NVIC_ICER_CLRENA_27 Ú P NVIC_ICER_CLRENA_28 Ú P NVIC_ICER_CLRENA_29 Ú P NVIC_ICER_CLRENA_30 Ú P NVIC_ICER_CLRENA_31 Ú P NVIC_ISPR_SETPEND jÚ P NVIC_ISPR_SETPEND_0 ×Ú P NVIC_ISPR_SETPEND_1 ÖÚ P NVIC_ISPR_SETPEND_2 ÕÚ P NVIC_ISPR_SETPEND_3 ÔÚ P NVIC_ISPR_SETPEND_4 ÓÚ P NVIC_ISPR_SETPEND_5 ÒÚ P NVIC_ISPR_SETPEND_6 ÑÚ P NVIC_ISPR_SETPEND_7 ÐÚ P NVIC_ISPR_SETPEND_8 ÏÚ P NVIC_ISPR_SETPEND_9 ÎÚ P NVIC_ISPR_SETPEND_10 ¤Ú P NVIC_ISPR_SETPEND_11 £Ú P NVIC_ISPR_SETPEND_12 ¢Ú P NVIC_ISPR_SETPEND_13 ¡Ú P NVIC_ISPR_SETPEND_14 Ú P NVIC_ISPR_SETPEND_15 Ú P NVIC_ISPR_SETPEND_16 Ú P NVIC_ISPR_SETPEND_17 Ú P NVIC_ISPR_SETPEND_18 Ú P NVIC_ISPR_SETPEND_19 Ú P NVIC_ISPR_SETPEND_20 £Ú P NVIC_ISPR_SETPEND_21 ¢Ú P NVIC_ISPR_SETPEND_22 ¡Ú P NVIC_ISPR_SETPEND_23 Ú P NVIC_ISPR_SETPEND_24 Ú P NVIC_ISPR_SETPEND_25 Ú P NVIC_ISPR_SETPEND_26 Ú P NVIC_ISPR_SETPEND_27 Ú P NVIC_ISPR_SETPEND_28 Ú P NVIC_ISPR_SETPEND_29 Ú P NVIC_ISPR_SETPEND_30 ¢Ú P NVIC_ISPR_SETPEND_31 ¡Ú P NVIC_ICPR_CLRPEND
Ú P NVIC_ICPR_CLRPEND_0 òÚ P NVIC_ICPR_CLRPEND_1 ñÚ P NVIC_ICPR_CLRPEND_2 ðÚ P NVIC_ICPR_CLRPEND_3 ïÚ P NVIC_ICPR_CLRPEND_4 îÚ P NVIC_ICPR_CLRPEND_5 íÚ P NVIC_ICPR_CLRPEND_6 ìÚ P NVIC_ICPR_CLRPEND_7 ëÚ P NVIC_ICPR_CLRPEND_8 êÚ P NVIC_ICPR_CLRPEND_9 éÚ P NVIC_ICPR_CLRPEND_10 ¿Ú P NVIC_ICPR_CLRPEND_11 ¾Ú P NVIC_ICPR_CLRPEND_12 ½Ú P NVIC_ICPR_CLRPEND_13 ¼Ú P NVIC_ICPR_CLRPEND_14 »Ú P NVIC_ICPR_CLRPEND_15 ºÚ P NVIC_ICPR_CLRPEND_16 ¹Ú P NVIC_ICPR_CLRPEND_17 ¸Ú P NVIC_ICPR_CLRPEND_18 ·Ú P NVIC_ICPR_CLRPEND_19 ¶Ú P NVIC_ICPR_CLRPEND_20 ¾Ú P NVIC_ICPR_CLRPEND_21 ½Ú P NVIC_ICPR_CLRPEND_22 ¼Ú P NVIC_ICPR_CLRPEND_23 »Ú P NVIC_ICPR_CLRPEND_24 ºÚ P NVIC_ICPR_CLRPEND_25 ¹Ú P NVIC_ICPR_CLRPEND_26 ¸Ú P NVIC_ICPR_CLRPEND_27 ·Ú P NVIC_ICPR_CLRPEND_28 ¶Ú P NVIC_ICPR_CLRPEND_29 µÚ P NVIC_ICPR_CLRPEND_30 ½Ú P NVIC_ICPR_CLRPEND_31 ¼Ú P NVIC_IABR_ACTIVE ãÚ P NVIC_IABR_ACTIVE_0 PÚ P NVIC_IABR_ACTIVE_1 OÚ P NVIC_IABR_ACTIVE_2 NÚ P NVIC_IABR_ACTIVE_3 MÚ P NVIC_IABR_ACTIVE_4 LÚ P NVIC_IABR_ACTIVE_5 KÚ P NVIC_IABR_ACTIVE_6 JÚ P NVIC_IABR_ACTIVE_7 IÚ P NVIC_IABR_ACTIVE_8 HÚ P NVIC_IABR_ACTIVE_9 GÚ P NVIC_IABR_ACTIVE_10 Ú P NVIC_IABR_ACTIVE_11 Ú P NVIC_IABR_ACTIVE_12 Ú P NVIC_IABR_ACTIVE_13 Ú P NVIC_IABR_ACTIVE_14 Ú P NVIC_IABR_ACTIVE_15 Ú P NVIC_IABR_ACTIVE_16 Ú P NVIC_IABR_ACTIVE_17 Ú P NVIC_IABR_ACTIVE_18 Ú P NVIC_IABR_ACTIVE_19 Ú P NVIC_IABR_ACTIVE_20 Ú P NVIC_IABR_ACTIVE_21 Ú P NVIC_IABR_ACTIVE_22 Ú P NVIC_IABR_ACTIVE_23 Ú P NVIC_IABR_ACTIVE_24 Ú P NVIC_IABR_ACTIVE_25 Ú P NVIC_IABR_ACTIVE_26 Ú P NVIC_IABR_ACTIVE_27 Ú P NVIC_IABR_ACTIVE_28 Ú P NVIC_IABR_ACTIVE_29 Ú P NVIC_IABR_ACTIVE_30 Ú P NVIC_IABR_ACTIVE_31 Ú P NVIC_IPR0_PRI_0 *Ú P NVIC_IPR0_PRI_1 )Ú P NVIC_IPR0_PRI_2 (Ú P NVIC_IPR0_PRI_3 'Ú P NVIC_IPR1_PRI_4 %Ú P NVIC_IPR1_PRI_5 $Ú P NVIC_IPR1_PRI_6 #Ú P NVIC_IPR1_PRI_7 "Ú P NVIC_IPR2_PRI_8 Ú P NVIC_IPR2_PRI_9 Ú P NVIC_IPR2_PRI_10 õÚ P NVIC_IPR2_PRI_11 ôÚ P NVIC_IPR3_PRI_12 òÚ P NVIC_IPR3_PRI_13 ñÚ P NVIC_IPR3_PRI_14 ðÚ P NVIC_IPR3_PRI_15 ïÚ P NVIC_IPR4_PRI_16 íÚ P NVIC_IPR4_PRI_17 ìÚ P NVIC_IPR4_PRI_18 ëÚ P NVIC_IPR4_PRI_19 êÚ P NVIC_IPR5_PRI_20 ñÚ P NVIC_IPR5_PRI_21 ðÚ P NVIC_IPR5_PRI_22 ïÚ P NVIC_IPR5_PRI_23 îÚ P NVIC_IPR6_PRI_24 ìÚ P NVIC_IPR6_PRI_25 ëÚ P NVIC_IPR6_PRI_26 êÚ P NVIC_IPR6_PRI_27 éÚ P NVIC_IPR7_PRI_28 çÚ P NVIC_IPR7_PRI_29 æÚ P NVIC_IPR7_PRI_30 îÚ P NVIC_IPR7_PRI_31 íÚ P SCB_CPUID_REVISION -Ú P SCB_CPUID_PARTNO ÌÚ P SCB_CPUID_Constant RÚ P SCB_CPUID_VARIANT Ú P SCB_CPUID_IMPLEMENTER TÚ P SCB_ICSR_VECTACTIVE ðÚ P SCB_ICSR_RETTOBASE 7Ú P SCB_ICSR_VECTPENDING ¥Ú P SCB_ICSR_ISRPENDING ëÚ P SCB_ICSR_ISRPREEMPT ÓÚ P SCB_ICSR_PENDSTCLR 1Ú P SCB_ICSR_PENDSTSET &Ú P SCB_ICSR_PENDSVCLR /Ú P SCB_ICSR_PENDSVSET $Ú P SCB_ICSR_NMIPENDSET çÚ P SCB_VTOR_TBLOFF Ú P SCB_VTOR_TBLBASE ÍÚ P SCB_AIRCR_VECTRESET éÚ P SCB_AIRCR_VECTCLRACTIVE ÇÚ P SCB_AIRCR_SYSRESETREQ 0Ú P SCB_AIRCR_PRIGROUP (Ú P SCB_AIRCR_PRIGROUP_0 Ú P SCB_AIRCR_PRIGROUP_1 Ú P SCB_AIRCR_PRIGROUP_2 Ú P SCB_AIRCR_PRIGROUP0 öÚ P SCB_AIRCR_PRIGROUP1 õÚ P SCB_AIRCR_PRIGROUP2 ôÚ P SCB_AIRCR_PRIGROUP3 óÚ P SCB_AIRCR_PRIGROUP4 òÚ P SCB_AIRCR_PRIGROUP5 ñÚ P SCB_AIRCR_PRIGROUP6 ðÚ P SCB_AIRCR_PRIGROUP7 ïÚ P SCB_AIRCR_ENDIANESS Ú P SCB_AIRCR_VECTKEY Ú P SCB_SCR_SLEEPONEXIT ×Ú P SCB_SCR_SLEEPDEEP Ú P SCB_SCR_SEVONPEND yÚ P SCB_CCR_NONBASETHRDENA %Ú P SCB_CCR_USERSETMPEND Ú P SCB_CCR_UNALIGN_TRP ÔÚ P SCB_CCR_DIV_0_TRP tÚ P SCB_CCR_BFHFNMIGN ¬Ú P SCB_CCR_STKALIGN àÚ P SCB_SHPR_PRI_N DÚ P SCB_SHPR_PRI_N1 Ú P SCB_SHPR_PRI_N2 Ú P SCB_SHPR_PRI_N3 Ú P SCB_SHCSR_MEMFAULTACT UÚ P SCB_SHCSR_BUSFAULTACT JÚ P SCB_SHCSR_USGFAULTACT EÚ P SCB_SHCSR_SVCALLACT ïÚ P SCB_SHCSR_MONITORACT Ú P SCB_SHCSR_PENDSVACT äÚ P SCB_SHCSR_SYSTICKACT Ú! P SCB_SHCSR_USGFAULTPENDED gÚ! P SCB_SHCSR_MEMFAULTPENDED wÚ! P SCB_SHCSR_BUSFAULTPENDED lÚ P SCB_SHCSR_SVCALLPENDED Ú P SCB_SHCSR_MEMFAULTENA YÚ P SCB_SHCSR_BUSFAULTENA NÚ P SCB_SHCSR_USGFAULTENA IÚ P SCB_CFSR_IACCVIOL Ú P SCB_CFSR_DACCVIOL Ú P SCB_CFSR_MUNSTKERR Ú P SCB_CFSR_MSTKERR ¿Ú P SCB_CFSR_MMARVALID FÚ P SCB_CFSR_IBUSERR ËÚ P SCB_CFSR_PRECISERR 4Ú P SCB_CFSR_IMPRECISERR Ú P SCB_CFSR_UNSTKERR gÚ P SCB_CFSR_STKERR Ú P SCB_CFSR_BFARVALID XÚ P SCB_CFSR_UNDEFINSTR ßÚ P SCB_CFSR_INVSTATE wÚ P SCB_CFSR_INVPC kÚ P SCB_CFSR_NOCP ½Ú P SCB_CFSR_UNALIGNED LÚ P SCB_CFSR_DIVBYZERO %Ú P SCB_HFSR_VECTTBL ÎÚ P SCB_HFSR_FORCED 1Ú P SCB_HFSR_DEBUGEVT Ú P SCB_DFSR_HALTED 6Ú P SCB_DFSR_BKPT »Ú P SCB_DFSR_DWTTRAP ÀÚ P SCB_DFSR_VCATCH /Ú P SCB_DFSR_EXTERNAL Ú P SCB_MMFAR_ADDRESS Ú P SCB_BFAR_ADDRESS ôÚ P SCB_AFSR_IMPDEF 6Ú P USE_STDPERIPH_DRIVER wÚ P SET_BIT Ú P |
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WWDG_CR_T ÙÚ P WWDG_CR_T0 §Ú P WWDG_CR_T1 ¦Ú P WWDG_CR_T2 ¥Ú P WWDG_CR_T3 ¤Ú P WWDG_CR_T4 £Ú P WWDG_CR_T5 ¢Ú P WWDG_CR_T6 ¡Ú P
WWDG_CR_WDGA Ú P WWDG_CFR_W Ú P WWDG_CFR_W0 \Ú P WWDG_CFR_W1 [Ú P WWDG_CFR_W2 ZÚ P WWDG_CFR_W3 YÚ P WWDG_CFR_W4 XÚ P WWDG_CFR_W5 WÚ P WWDG_CFR_W6 VÚ P WWDG_CFR_WDGTB eÚ P WWDG_CFR_WDGTB0 3Ú P WWDG_CFR_WDGTB1 2Ú P
WWDG_CFR_EWI üÚ P
WWDG_SR_EWIF ìÚ P SysTick_CTRL_ENABLE AÚ P SysTick_CTRL_TICKINT ÐÚ P SysTick_CTRL_CLKSOURCE 7Ú P SysTick_CTRL_COUNTFLAG ?Ú P SysTick_LOAD_RELOAD FÚ P SysTick_VAL_CURRENT Ú P SysTick_CALIB_TENMS ;Ú P SysTick_CALIB_SKEW Ú P SysTick_CALIB_NOREF HÚ P NVIC_ISER_SETENA ÊÚ P NVIC_ISER_SETENA_0 7Ú P NVIC_ISER_SETENA_1 6Ú P NVIC_ISER_SETENA_2 5Ú P NVIC_ISER_SETENA_3 4Ú P NVIC_ISER_SETENA_4 3Ú P NVIC_ISER_SETENA_5 2Ú P NVIC_ISER_SETENA_6 1Ú P NVIC_ISER_SETENA_7 0Ú P NVIC_ISER_SETENA_8 /Ú P NVIC_ISER_SETENA_9 .Ú P NVIC_ISER_SETENA_10 Ú P NVIC_ISER_SETENA_11 Ú P NVIC_ISER_SETENA_12 Ú P NVIC_ISER_SETENA_13 Ú P NVIC_ISER_SETENA_14 Ú P NVIC_ISER_SETENA_15 ÿÚ P NVIC_ISER_SETENA_16 þÚ P NVIC_ISER_SETENA_17 ýÚ P NVIC_ISER_SETENA_18 üÚ P NVIC_ISER_SETENA_19 ûÚ P NVIC_ISER_SETENA_20 Ú P NVIC_ISER_SETENA_21 Ú P NVIC_ISER_SETENA_22 Ú P NVIC_ISER_SETENA_23 Ú P NVIC_ISER_SETENA_24 ÿÚ P NVIC_ISER_SETENA_25 þÚ P NVIC_ISER_SETENA_26 ýÚ P NVIC_ISER_SETENA_27 üÚ P NVIC_ISER_SETENA_28 ûÚ P NVIC_ISER_SETENA_29 úÚ P NVIC_ISER_SETENA_30 Ú P NVIC_ISER_SETENA_31 Ú P NVIC_ICER_CLRENA åÚ P NVIC_ICER_CLRENA_0 RÚ P NVIC_ICER_CLRENA_1 QÚ P NVIC_ICER_CLRENA_2 PÚ P NVIC_ICER_CLRENA_3 OÚ P NVIC_ICER_CLRENA_4 NÚ P NVIC_ICER_CLRENA_5 MÚ P NVIC_ICER_CLRENA_6 LÚ P NVIC_ICER_CLRENA_7 KÚ P NVIC_ICER_CLRENA_8 JÚ P NVIC_ICER_CLRENA_9 IÚ P NVIC_ICER_CLRENA_10 Ú P NVIC_ICER_CLRENA_11 Ú P NVIC_ICER_CLRENA_12 Ú P NVIC_ICER_CLRENA_13 Ú P NVIC_ICER_CLRENA_14 Ú P NVIC_ICER_CLRENA_15 Ú P NVIC_ICER_CLRENA_16 Ú P NVIC_ICER_CLRENA_17 Ú P NVIC_ICER_CLRENA_18 Ú P NVIC_ICER_CLRENA_19 Ú P NVIC_ICER_CLRENA_20 Ú P NVIC_ICER_CLRENA_21 Ú P NVIC_ICER_CLRENA_22 Ú P NVIC_ICER_CLRENA_23 Ú P NVIC_ICER_CLRENA_24 Ú P NVIC_ICER_CLRENA_25 Ú P NVIC_ICER_CLRENA_26 Ú P NVIC_ICER_CLRENA_27 Ú P NVIC_ICER_CLRENA_28 Ú P NVIC_ICER_CLRENA_29 Ú P NVIC_ICER_CLRENA_30 Ú P NVIC_ICER_CLRENA_31 Ú P NVIC_ISPR_SETPEND jÚ P NVIC_ISPR_SETPEND_0 ×Ú P NVIC_ISPR_SETPEND_1 ÖÚ P NVIC_ISPR_SETPEND_2 ÕÚ P NVIC_ISPR_SETPEND_3 ÔÚ P NVIC_ISPR_SETPEND_4 ÓÚ P NVIC_ISPR_SETPEND_5 ÒÚ P NVIC_ISPR_SETPEND_6 ÑÚ P NVIC_ISPR_SETPEND_7 ÐÚ P NVIC_ISPR_SETPEND_8 ÏÚ P NVIC_ISPR_SETPEND_9 ÎÚ P NVIC_ISPR_SETPEND_10 ¤Ú P NVIC_ISPR_SETPEND_11 £Ú P NVIC_ISPR_SETPEND_12 ¢Ú P NVIC_ISPR_SETPEND_13 ¡Ú P NVIC_ISPR_SETPEND_14 Ú P NVIC_ISPR_SETPEND_15 Ú P NVIC_ISPR_SETPEND_16 Ú P NVIC_ISPR_SETPEND_17 Ú P NVIC_ISPR_SETPEND_18 Ú P NVIC_ISPR_SETPEND_19 Ú P NVIC_ISPR_SETPEND_20 £Ú P NVIC_ISPR_SETPEND_21 ¢Ú P NVIC_ISPR_SETPEND_22 ¡Ú P NVIC_ISPR_SETPEND_23 Ú P NVIC_ISPR_SETPEND_24 Ú P NVIC_ISPR_SETPEND_25 Ú P NVIC_ISPR_SETPEND_26 Ú P NVIC_ISPR_SETPEND_27 Ú P NVIC_ISPR_SETPEND_28 Ú P NVIC_ISPR_SETPEND_29 Ú P NVIC_ISPR_SETPEND_30 ¢Ú P NVIC_ISPR_SETPEND_31 ¡Ú P NVIC_ICPR_CLRPEND
Ú P NVIC_ICPR_CLRPEND_0 òÚ P NVIC_ICPR_CLRPEND_1 ñÚ P NVIC_ICPR_CLRPEND_2 ðÚ P NVIC_ICPR_CLRPEND_3 ïÚ P NVIC_ICPR_CLRPEND_4 îÚ P NVIC_ICPR_CLRPEND_5 íÚ P NVIC_ICPR_CLRPEND_6 ìÚ P NVIC_ICPR_CLRPEND_7 ëÚ P NVIC_ICPR_CLRPEND_8 êÚ P NVIC_ICPR_CLRPEND_9 éÚ P NVIC_ICPR_CLRPEND_10 ¿Ú P NVIC_ICPR_CLRPEND_11 ¾Ú P NVIC_ICPR_CLRPEND_12 ½Ú P NVIC_ICPR_CLRPEND_13 ¼Ú P NVIC_ICPR_CLRPEND_14 »Ú P NVIC_ICPR_CLRPEND_15 ºÚ P NVIC_ICPR_CLRPEND_16 ¹Ú P NVIC_ICPR_CLRPEND_17 ¸Ú P NVIC_ICPR_CLRPEND_18 ·Ú P NVIC_ICPR_CLRPEND_19 ¶Ú P NVIC_ICPR_CLRPEND_20 ¾Ú P NVIC_ICPR_CLRPEND_21 ½Ú P NVIC_ICPR_CLRPEND_22 ¼Ú P NVIC_ICPR_CLRPEND_23 »Ú P NVIC_ICPR_CLRPEND_24 ºÚ P NVIC_ICPR_CLRPEND_25 ¹Ú P NVIC_ICPR_CLRPEND_26 ¸Ú P NVIC_ICPR_CLRPEND_27 ·Ú P NVIC_ICPR_CLRPEND_28 ¶Ú P NVIC_ICPR_CLRPEND_29 µÚ P NVIC_ICPR_CLRPEND_30 ½Ú P NVIC_ICPR_CLRPEND_31 ¼Ú P NVIC_IABR_ACTIVE ãÚ P NVIC_IABR_ACTIVE_0 PÚ P NVIC_IABR_ACTIVE_1 OÚ P NVIC_IABR_ACTIVE_2 NÚ P NVIC_IABR_ACTIVE_3 MÚ P NVIC_IABR_ACTIVE_4 LÚ P NVIC_IABR_ACTIVE_5 KÚ P NVIC_IABR_ACTIVE_6 JÚ P NVIC_IABR_ACTIVE_7 IÚ P NVIC_IABR_ACTIVE_8 HÚ P NVIC_IABR_ACTIVE_9 GÚ P NVIC_IABR_ACTIVE_10 Ú P NVIC_IABR_ACTIVE_11 Ú P NVIC_IABR_ACTIVE_12 Ú P NVIC_IABR_ACTIVE_13 Ú P NVIC_IABR_ACTIVE_14 Ú P NVIC_IABR_ACTIVE_15 Ú P NVIC_IABR_ACTIVE_16 Ú P NVIC_IABR_ACTIVE_17 Ú P NVIC_IABR_ACTIVE_18 Ú P NVIC_IABR_ACTIVE_19 Ú P NVIC_IABR_ACTIVE_20 Ú P NVIC_IABR_ACTIVE_21 Ú P NVIC_IABR_ACTIVE_22 Ú P NVIC_IABR_ACTIVE_23 Ú P NVIC_IABR_ACTIVE_24 Ú P NVIC_IABR_ACTIVE_25 Ú P NVIC_IABR_ACTIVE_26 Ú P NVIC_IABR_ACTIVE_27 Ú P NVIC_IABR_ACTIVE_28 Ú P NVIC_IABR_ACTIVE_29 Ú P NVIC_IABR_ACTIVE_30 Ú P NVIC_IABR_ACTIVE_31 Ú P NVIC_IPR0_PRI_0 *Ú P NVIC_IPR0_PRI_1 )Ú P NVIC_IPR0_PRI_2 (Ú P NVIC_IPR0_PRI_3 'Ú P NVIC_IPR1_PRI_4 %Ú P NVIC_IPR1_PRI_5 $Ú P NVIC_IPR1_PRI_6 #Ú P NVIC_IPR1_PRI_7 "Ú P NVIC_IPR2_PRI_8 Ú P NVIC_IPR2_PRI_9 Ú P NVIC_IPR2_PRI_10 õÚ P NVIC_IPR2_PRI_11 ôÚ P NVIC_IPR3_PRI_12 òÚ P NVIC_IPR3_PRI_13 ñÚ P NVIC_IPR3_PRI_14 ðÚ P NVIC_IPR3_PRI_15 ïÚ P NVIC_IPR4_PRI_16 íÚ P NVIC_IPR4_PRI_17 ìÚ P NVIC_IPR4_PRI_18 ëÚ P NVIC_IPR4_PRI_19 êÚ P NVIC_IPR5_PRI_20 ñÚ P NVIC_IPR5_PRI_21 ðÚ P NVIC_IPR5_PRI_22 ïÚ P NVIC_IPR5_PRI_23 îÚ P NVIC_IPR6_PRI_24 ìÚ P NVIC_IPR6_PRI_25 ëÚ P NVIC_IPR6_PRI_26 êÚ P NVIC_IPR6_PRI_27 éÚ P NVIC_IPR7_PRI_28 çÚ P NVIC_IPR7_PRI_29 æÚ P NVIC_IPR7_PRI_30 îÚ P NVIC_IPR7_PRI_31 íÚ P SCB_CPUID_REVISION -Ú P SCB_CPUID_PARTNO ÌÚ P SCB_CPUID_Constant RÚ P SCB_CPUID_VARIANT Ú P SCB_CPUID_IMPLEMENTER TÚ P SCB_ICSR_VECTACTIVE ðÚ P SCB_ICSR_RETTOBASE 7Ú P SCB_ICSR_VECTPENDING ¥Ú P SCB_ICSR_ISRPENDING ëÚ P SCB_ICSR_ISRPREEMPT ÓÚ P SCB_ICSR_PENDSTCLR 1Ú P SCB_ICSR_PENDSTSET &Ú P SCB_ICSR_PENDSVCLR /Ú P SCB_ICSR_PENDSVSET $Ú P SCB_ICSR_NMIPENDSET çÚ P SCB_VTOR_TBLOFF Ú P SCB_VTOR_TBLBASE ÍÚ P SCB_AIRCR_VECTRESET éÚ P SCB_AIRCR_VECTCLRACTIVE ÇÚ P SCB_AIRCR_SYSRESETREQ 0Ú P SCB_AIRCR_PRIGROUP (Ú P SCB_AIRCR_PRIGROUP_0 Ú P SCB_AIRCR_PRIGROUP_1 Ú P SCB_AIRCR_PRIGROUP_2 Ú P SCB_AIRCR_PRIGROUP0 öÚ P SCB_AIRCR_PRIGROUP1 õÚ P SCB_AIRCR_PRIGROUP2 ôÚ P SCB_AIRCR_PRIGROUP3 óÚ P SCB_AIRCR_PRIGROUP4 òÚ P SCB_AIRCR_PRIGROUP5 ñÚ P SCB_AIRCR_PRIGROUP6 ðÚ P SCB_AIRCR_PRIGROUP7 ïÚ P SCB_AIRCR_ENDIANESS Ú P SCB_AIRCR_VECTKEY Ú P SCB_SCR_SLEEPONEXIT ×Ú P SCB_SCR_SLEEPDEEP Ú P SCB_SCR_SEVONPEND yÚ P SCB_CCR_NONBASETHRDENA %Ú P SCB_CCR_USERSETMPEND Ú P SCB_CCR_UNALIGN_TRP ÔÚ P SCB_CCR_DIV_0_TRP tÚ P SCB_CCR_BFHFNMIGN ¬Ú P SCB_CCR_STKALIGN àÚ P SCB_SHPR_PRI_N DÚ P SCB_SHPR_PRI_N1 Ú P SCB_SHPR_PRI_N2 Ú P SCB_SHPR_PRI_N3 Ú P SCB_SHCSR_MEMFAULTACT UÚ P SCB_SHCSR_BUSFAULTACT JÚ P SCB_SHCSR_USGFAULTACT EÚ P SCB_SHCSR_SVCALLACT ïÚ P SCB_SHCSR_MONITORACT Ú P SCB_SHCSR_PENDSVACT äÚ P SCB_SHCSR_SYSTICKACT Ú! P SCB_SHCSR_USGFAULTPENDED gÚ! P SCB_SHCSR_MEMFAULTPENDED wÚ! P SCB_SHCSR_BUSFAULTPENDED lÚ P SCB_SHCSR_SVCALLPENDED Ú P SCB_SHCSR_MEMFAULTENA YÚ P SCB_SHCSR_BUSFAULTENA NÚ P SCB_SHCSR_USGFAULTENA IÚ P SCB_CFSR_IACCVIOL Ú P SCB_CFSR_DACCVIOL Ú P SCB_CFSR_MUNSTKERR Ú P SCB_CFSR_MSTKERR ¿Ú P SCB_CFSR_MMARVALID FÚ P SCB_CFSR_IBUSERR ËÚ P SCB_CFSR_PRECISERR 4Ú P SCB_CFSR_IMPRECISERR Ú P SCB_CFSR_UNSTKERR gÚ P SCB_CFSR_STKERR Ú P SCB_CFSR_BFARVALID XÚ P SCB_CFSR_UNDEFINSTR ßÚ P SCB_CFSR_INVSTATE wÚ P SCB_CFSR_INVPC kÚ P SCB_CFSR_NOCP ½Ú P SCB_CFSR_UNALIGNED LÚ P SCB_CFSR_DIVBYZERO %Ú P SCB_HFSR_VECTTBL ÎÚ P SCB_HFSR_FORCED 1Ú P SCB_HFSR_DEBUGEVT Ú P SCB_DFSR_HALTED 6Ú P SCB_DFSR_BKPT »Ú P SCB_DFSR_DWTTRAP ÀÚ P SCB_DFSR_VCATCH /Ú P SCB_DFSR_EXTERNAL Ú P SCB_MMFAR_ADDRESS Ú P SCB_BFAR_ADDRESS ôÚ P SCB_AFSR_IMPDEF 6Ú P USE_STDPERIPH_DRIVER wÚ P SET_BIT Ú P |
| 830 |
CLEAR_BIT Ú P READ_BIT aÚ P |
830 |
CLEAR_BIT Ú P READ_BIT aÚ P |
| 831 |
CLEAR_REG Ú P |
831 |
CLEAR_REG Ú P |
| 832 |
WRITE_REG ñÚ P READ_REG bÚ P MODIFY_REG ²Ú 8 |
832 |
WRITE_REG ñÚ P READ_REG bÚ P MODIFY_REG ²Ú 8 |
| 833 |
<unnamed> QÚ " ®3CR1 Ú " ®3_resvd0 %Ú " ®3CR2 Ú " ®3_resvd1 $Ú " ®3SMCR ©Ú " ®3_resvd2 #Ú " ®3DIER ºÚ " ®3_resvd3 "Ú
" ®3SR =Ú " ®3_resvd4 !Ú " ®3EGR Ú " ®3_resvd5 Ú " ®3CCMR1 Ú " ®3_resvd6 Ú " ®3CCMR2
Ú " ®3_resvd7 Ú " ®3CCER ÁÚ " ®3_resvd8 Ú |
833 |
<unnamed> QÚ " ®3CR1 Ú " ®3_resvd0 %Ú " ®3CR2 Ú " ®3_resvd1 $Ú " ®3SMCR ©Ú " ®3_resvd2 #Ú " ®3DIER ºÚ " ®3_resvd3 "Ú
" ®3SR =Ú " ®3_resvd4 !Ú " ®3EGR Ú " ®3_resvd5 Ú " ®3CCMR1 Ú " ®3_resvd6 Ú " ®3CCMR2
Ú " ®3_resvd7 Ú " ®3CCER ÁÚ " ®3_resvd8 Ú |
| 834 |
" ®3CNT ýÚ " ®3PSC úÚ " ®3_resvd9 Ú |
834 |
" ®3CNT ýÚ " ®3PSC úÚ " ®3_resvd9 Ú |
| 835 |
" ®3ARR ýÚ " ®3RCR ùÚ " ®3 _resvd10 òÚ <" ®3CCR ÌÚ " ®3BDTR ²Ú " ®3 _resvd11 ñÚ " ®3DCR Ú " ®3 _resvd12 ðÚ " ®3DMAR ºÚ " ®3 _resvd13 ïÚ
" ®3OR AÚ " ®3 _resvd14 îÚ stm32_tim_t ¶Ú P STM32_TIM1 äÚ P STM32_TIM2 ãÚ P STM32_TIM3 âÚ P STM32_TIM4 áÚ P STM32_TIM5 àÚ P STM32_TIM6 ßÚ P STM32_TIM7 ÞÚ P STM32_TIM8 ÝÚ P STM32_TIM9 ÜÚ P STM32_TIM10 ²Ú P STM32_TIM11 ±Ú P STM32_TIM12 °Ú P STM32_TIM13 ¯Ú P STM32_TIM14 ®Ú P HAL_IMPLEMENTS_COUNTERS Ú P PLATFORM_NAME ÌÚ P
STM32_HSICLK =Ú P
STM32_LSICLK 9Ú P STM32_VOS_MASK tÚ P STM32_VOS_1P8 éÚ P STM32_VOS_1P5 ìÚ P STM32_VOS_1P2 ïÚ P STM32_PLS_MASK }Ú P STM32_PLS_LEV0 Ú P STM32_PLS_LEV1 Ú P STM32_PLS_LEV2 Ú P STM32_PLS_LEV3 Ú P STM32_PLS_LEV4 Ú P STM32_PLS_LEV5 Ú P STM32_PLS_LEV6 Ú P STM32_PLS_LEV7 Ú P STM32_RTCPRE_MASK Ú P STM32_RTCPRE_DIV2 Ú P STM32_RTCPRE_DIV4 «Ú P STM32_RTCPRE_DIV8 §Ú P STM32_RTCPRE_DIV16 vÚ P
STM32_SW_MSI Ú P
STM32_SW_HSI Ú P
STM32_SW_HSE Ú P
STM32_SW_PLL |
835 |
" ®3ARR ýÚ " ®3RCR ùÚ " ®3 _resvd10 òÚ <" ®3CCR ÌÚ " ®3BDTR ²Ú " ®3 _resvd11 ñÚ " ®3DCR Ú " ®3 _resvd12 ðÚ " ®3DMAR ºÚ " ®3 _resvd13 ïÚ
" ®3OR AÚ " ®3 _resvd14 îÚ stm32_tim_t ¶Ú P STM32_TIM1 äÚ P STM32_TIM2 ãÚ P STM32_TIM3 âÚ P STM32_TIM4 áÚ P STM32_TIM5 àÚ P STM32_TIM6 ßÚ P STM32_TIM7 ÞÚ P STM32_TIM8 ÝÚ P STM32_TIM9 ÜÚ P STM32_TIM10 ²Ú P STM32_TIM11 ±Ú P STM32_TIM12 °Ú P STM32_TIM13 ¯Ú P STM32_TIM14 ®Ú P HAL_IMPLEMENTS_COUNTERS Ú P PLATFORM_NAME ÌÚ P
STM32_HSICLK =Ú P
STM32_LSICLK 9Ú P STM32_VOS_MASK tÚ P STM32_VOS_1P8 éÚ P STM32_VOS_1P5 ìÚ P STM32_VOS_1P2 ïÚ P STM32_PLS_MASK }Ú P STM32_PLS_LEV0 Ú P STM32_PLS_LEV1 Ú P STM32_PLS_LEV2 Ú P STM32_PLS_LEV3 Ú P STM32_PLS_LEV4 Ú P STM32_PLS_LEV5 Ú P STM32_PLS_LEV6 Ú P STM32_PLS_LEV7 Ú P STM32_RTCPRE_MASK Ú P STM32_RTCPRE_DIV2 Ú P STM32_RTCPRE_DIV4 «Ú P STM32_RTCPRE_DIV8 §Ú P STM32_RTCPRE_DIV16 vÚ P
STM32_SW_MSI Ú P
STM32_SW_HSI Ú P
STM32_SW_HSE Ú P
STM32_SW_PLL |
| 836 |
Ú P STM32_HPRE_DIV1 SÚ P STM32_HPRE_DIV2 RÚ P STM32_HPRE_DIV4 PÚ P STM32_HPRE_DIV8 LÚ P STM32_HPRE_DIV16 Ú P STM32_HPRE_DIV64 Ú P STM32_HPRE_DIV128 åÚ P STM32_HPRE_DIV256 ãÚ P STM32_HPRE_DIV512 èÚ P STM32_PPRE1_DIV1 Ú P STM32_PPRE1_DIV2 Ú P STM32_PPRE1_DIV4 Ú P STM32_PPRE1_DIV8 Ú P STM32_PPRE1_DIV16 àÚ P STM32_PPRE2_DIV1 Ú P STM32_PPRE2_DIV2 Ú P STM32_PPRE2_DIV4 Ú P STM32_PPRE2_DIV8 Ú P STM32_PPRE2_DIV16 ßÚ P STM32_PLLSRC_HSI àÚ P STM32_PLLSRC_HSE äÚ P STM32_MCOSEL_NOCLOCK ÀÚ P STM32_MCOSEL_SYSCLK òÚ P STM32_MCOSEL_HSI íÚ P STM32_MCOSEL_MSI èÚ P STM32_MCOSEL_HSE ñÚ P STM32_MCOSEL_PLL éÚ P STM32_MCOSEL_LSI éÚ P STM32_MCOSEL_LSE íÚ P STM32_MCOPRE_DIV1 ¸Ú P STM32_MCOPRE_DIV2 ·Ú P STM32_MCOPRE_DIV4 µÚ P STM32_MCOPRE_DIV8 ±Ú P STM32_MCOPRE_DIV16 Ú P STM32_MSIRANGE_MASK Ú P STM32_MSIRANGE_64K
Ú P STM32_MSIRANGE_128K RÚ P STM32_MSIRANGE_256K PÚ P STM32_MSIRANGE_512K UÚ P STM32_MSIRANGE_1M ¾Ú P STM32_MSIRANGE_2M ½Ú P STM32_MSIRANGE_4M »Ú P STM32_RTCSEL_MASK Ú P STM32_RTCSEL_NOCLOCK ¶Ú P STM32_RTCSEL_LSE ãÚ P STM32_RTCSEL_LSI ßÚ P STM32_RTCSEL_HSEDIV þÚ P STM32_HAS_ADC1 ÃÚ P STM32_HAS_ADC2 ÂÚ P STM32_HAS_ADC3 ÁÚ P STM32_HAS_ADC4 ÀÚ P STM32_HAS_CAN1 ¹Ú P STM32_HAS_CAN2 ¸Ú P STM32_CAN_MAX_FILTERS ZÚ P STM32_HAS_DAC öÚ P STM32_ADVANCED_DMA Ú P STM32_HAS_DMA1 ¹Ú P STM32_HAS_DMA2 ¸Ú P STM32_HAS_ETH ÝÚ P STM32_EXTI_NUM_CHANNELS ±Ú P STM32_HAS_GPIOA JÚ P STM32_HAS_GPIOB IÚ P STM32_HAS_GPIOC HÚ P STM32_HAS_GPIOD GÚ P STM32_HAS_GPIOE FÚ P STM32_HAS_GPIOF EÚ P STM32_HAS_GPIOG DÚ P STM32_HAS_GPIOH CÚ P STM32_HAS_GPIOI BÚ P STM32_HAS_I2C1 ÍÚ P STM32_I2C1_RX_DMA_MSK vÚ P STM32_I2C1_RX_DMA_CHN Ú P STM32_I2C1_TX_DMA_MSK tÚ P STM32_I2C1_TX_DMA_CHN Ú P STM32_HAS_I2C2 ÌÚ P STM32_I2C2_RX_DMA_MSK uÚ P STM32_I2C2_RX_DMA_CHN Ú P STM32_I2C2_TX_DMA_MSK sÚ P STM32_I2C2_TX_DMA_CHN
Ú P STM32_HAS_I2C3 ËÚ P STM32_I2C3_RX_DMA_MSK tÚ P STM32_I2C3_RX_DMA_CHN Ú P STM32_I2C3_TX_DMA_MSK rÚ P STM32_I2C3_TX_DMA_CHN Ú P STM32_HAS_RTC ÕÚ! P STM32_RTC_HAS_SUBSECONDS gÚ P STM32_RTC_IS_CALENDAR lÚ P STM32_HAS_SDIO Ú P STM32_HAS_SPI1 Ú P STM32_SPI1_RX_DMA_MSK HÚ P STM32_SPI1_RX_DMA_CHN ZÚ P STM32_SPI1_TX_DMA_MSK FÚ P STM32_SPI1_TX_DMA_CHN XÚ P STM32_HAS_SPI2 Ú P STM32_SPI2_RX_DMA_MSK GÚ P STM32_SPI2_RX_DMA_CHN YÚ P STM32_SPI2_TX_DMA_MSK EÚ P STM32_SPI2_TX_DMA_CHN WÚ P STM32_HAS_SPI3 Ú P STM32_SPI3_RX_DMA_MSK FÚ P STM32_SPI3_RX_DMA_CHN XÚ P STM32_SPI3_TX_DMA_MSK DÚ P STM32_SPI3_TX_DMA_CHN VÚ P STM32_HAS_TIM1 ¡Ú P STM32_HAS_TIM2 Ú P STM32_HAS_TIM3 Ú P STM32_HAS_TIM4 Ú P STM32_HAS_TIM5 Ú P STM32_HAS_TIM6 Ú P STM32_HAS_TIM7 Ú P STM32_HAS_TIM8 Ú P STM32_HAS_TIM9 Ú P STM32_HAS_TIM10 oÚ P STM32_HAS_TIM11 nÚ P STM32_HAS_TIM12 mÚ P STM32_HAS_TIM13 lÚ P STM32_HAS_TIM14 kÚ P STM32_HAS_TIM15 jÚ P STM32_HAS_TIM16 iÚ P STM32_HAS_TIM17 hÚ P STM32_HAS_TIM18 gÚ P STM32_HAS_TIM19 fÚ P STM32_HAS_USART1 øÚ P STM32_USART1_RX_DMA_MSK ¡Ú P STM32_USART1_RX_DMA_CHN ³Ú P STM32_USART1_TX_DMA_MSK Ú P STM32_USART1_TX_DMA_CHN ±Ú P STM32_HAS_USART2 ÷Ú P STM32_USART2_RX_DMA_MSK Ú P STM32_USART2_RX_DMA_CHN ²Ú P STM32_USART2_TX_DMA_MSK Ú P STM32_USART2_TX_DMA_CHN °Ú P STM32_HAS_USART3 öÚ P STM32_USART3_RX_DMA_MSK Ú P STM32_USART3_RX_DMA_CHN ±Ú P STM32_USART3_TX_DMA_MSK Ú P STM32_USART3_TX_DMA_CHN ¯Ú P STM32_HAS_UART4 JÚ P STM32_UART4_RX_DMA_MSK óÚ P STM32_UART4_RX_DMA_CHN Ú P STM32_UART4_TX_DMA_MSK ñÚ P STM32_UART4_TX_DMA_CHN Ú P STM32_HAS_UART5 IÚ P STM32_UART5_RX_DMA_MSK òÚ P STM32_UART5_RX_DMA_CHN Ú P STM32_UART5_TX_DMA_MSK ðÚ P STM32_UART5_TX_DMA_CHN Ú P STM32_HAS_USART6 óÚ P STM32_USART6_RX_DMA_MSK Ú P STM32_USART6_RX_DMA_CHN ®Ú P STM32_USART6_TX_DMA_MSK Ú P STM32_USART6_TX_DMA_CHN ¬Ú P STM32_HAS_USB ÔÚ P STM32_HAS_OTG1 ¡Ú P STM32_HAS_OTG2 Ú P WWDG_IRQHandler kÚ P PVD_IRQHandler ¼Ú P TAMPER_STAMP_IRQHandler çÚ P RTC_WKUP_IRQHandler
Ú P FLASH_IRQHandler 4Ú P RCC_IRQHandler ÎÚ P EXTI0_IRQHandler 8Ú P EXTI1_IRQHandler 7Ú P EXTI2_IRQHandler 6Ú P EXTI3_IRQHandler 5Ú P EXTI4_IRQHandler 4Ú P DMA1_Ch1_IRQHandler ^Ú P DMA1_Ch2_IRQHandler ]Ú P DMA1_Ch3_IRQHandler \Ú P DMA1_Ch4_IRQHandler [Ú P DMA1_Ch5_IRQHandler ZÚ P DMA1_Ch6_IRQHandler YÚ P DMA1_Ch7_IRQHandler XÚ P ADC1_IRQHandler «Ú P USB_HP_IRQHandler ¿Ú P USB_LP_IRQHandler »Ú P DAC_IRQHandler ÞÚ P COMP_IRQHandler uÚ P EXTI9_5_IRQHandler Ú P TIM9_IRQHandler Ú P TIM10_IRQHandler WÚ P TIM11_IRQHandler VÚ P LCD_IRQHandler ÓÚ P TIM2_IRQHandler Ú P TIM3_IRQHandler Ú P TIM4_IRQHandler Ú P I2C1_EV_IRQHandler µÚ P I2C1_ER_IRQHandler ¹Ú P I2C2_EV_IRQHandler ´Ú P I2C2_ER_IRQHandler ¸Ú P SPI1_IRQHandler Ú P SPI2_IRQHandler Ú P USART1_IRQHandler àÚ P USART2_IRQHandler ßÚ P USART3_IRQHandler ÞÚ P EXTI15_10_IRQHandler :Ú P RTC_Alarm_IRQHandler eÚ P USB_FS_WKUP_IRQHandler Ú P TIM6_IRQHandler Ú P TIM7_IRQHandler Ú P STM32_HSECLK_MAX ôÚ P STM32_SYSCLK_MAX ÕÚ P STM32_PLLVCO_MAX ÞÚ P STM32_PLLVCO_MIN àÚ P STM32_PCLK1_MAX UÚ P STM32_PCLK2_MAX TÚ P STM32_0WS_THRESHOLD Ú P STM32_HSI_AVAILABLE )Ú P STM32_ACTIVATE_PLL WÚ P
STM32_PLLMUL %Ú P
STM32_PLLDIV 0Ú P STM32_PLLCLKIN Ú P
STM32_PLLVCO +Ú P STM32_PLLCLKOUT ;Ú P
STM32_MSICLK 8Ú P
STM32_SYSCLK "Ú P STM32_HCLK ÝÚ P STM32_PCLK1 ¢Ú P STM32_PCLK2 ¡Ú P STM_MCODIVCLK ÂÚ P STM_MCOCLK «Ú P STM32_HSEDIVCLK XÚ P STM_RTCCLK ¡Ú P
STM32_ADCCLK YÚ P
STM32_USBCLK 7Ú P STM32_TIMCLK1 Ú P STM32_TIMCLK2 Ú P STM32_FLASHBITS1 "Ú P STM32_FLASHBITS2 !Ú halclock_t ÙÚ halrtcnt_t ºÚ" P hal_lld_get_counter_value OÚ& P hal_lld_get_counter_frequency Ú P _STM32_ISR_H_ ¦Ú P STM32_TIM2_HANDLER vÚ P STM32_TIM3_HANDLER uÚ P STM32_TIM4_HANDLER tÚ P STM32_TIM2_NUMBER Ú P STM32_TIM3_NUMBER ¬Ú P STM32_TIM4_NUMBER «Ú P STM32_USART1_HANDLER ÎÚ P STM32_USART2_HANDLER ÍÚ P STM32_USART3_HANDLER ÌÚ P STM32_USART1_NUMBER Ú P STM32_USART2_NUMBER Ú P STM32_USART3_NUMBER Ú P STM32_USB1_HP_HANDLER zÚ P STM32_USB1_LP_HANDLER vÚ P STM32_USB1_HP_NUMBER ±Ú P STM32_USB1_LP_NUMBER Ú P _STM32_DMA_H_ ÂÚ P STM32_DMA_STREAMS ¡Ú P STM32_DMA_ISR_MASK EÚ P STM32_DMA_GETCHANNEL áÚ$ P STM32_DMA_IS_VALID_PRIORITY `Ú P STM32_DMA_STREAM_ID Ú P STM32_DMA_STREAM_ID_MSK ²Ú P STM32_DMA_IS_VALID_ID aÚ P STM32_DMA_STREAM öÚ P STM32_DMA1_STREAM1 Ú P STM32_DMA1_STREAM2 Ú P STM32_DMA1_STREAM3 Ú P STM32_DMA1_STREAM4 Ú P STM32_DMA1_STREAM5 Ú P STM32_DMA1_STREAM6 Ú P STM32_DMA1_STREAM7 Ú P STM32_DMA_CR_EN =Ú P STM32_DMA_CR_TEIE ¥Ú P STM32_DMA_CR_HTIE ¢Ú P STM32_DMA_CR_TCIE §Ú P STM32_DMA_CR_DIR_MASK ZÚ P STM32_DMA_CR_DIR_P2M ¹Ú P STM32_DMA_CR_DIR_M2P ¹Ú P STM32_DMA_CR_DIR_M2M ¼Ú P STM32_DMA_CR_CIRC «Ú P STM32_DMA_CR_PINC ¢Ú P STM32_DMA_CR_MINC ¥Ú P STM32_DMA_CR_PSIZE_MASK ªÚ P STM32_DMA_CR_PSIZE_BYTE ¢Ú! P STM32_DMA_CR_PSIZE_HWORD PÚ P STM32_DMA_CR_PSIZE_WORD Ú P STM32_DMA_CR_MSIZE_MASK Ú P STM32_DMA_CR_MSIZE_BYTE ¥Ú! P STM32_DMA_CR_MSIZE_HWORD SÚ P STM32_DMA_CR_MSIZE_WORD Ú P STM32_DMA_CR_SIZE_MASK üÚ P STM32_DMA_CR_PL_MASK Ú P STM32_DMA_CR_PL 4Ú P STM32_DMA_CR_DMEIE fÚ P STM32_DMA_CR_CHSEL_MASK ÆÚ P STM32_DMA_CR_CHSEL [Ú P STM32_DMA_ISR_FEIF WÚ P STM32_DMA_ISR_DMEIF |
836 |
Ú P STM32_HPRE_DIV1 SÚ P STM32_HPRE_DIV2 RÚ P STM32_HPRE_DIV4 PÚ P STM32_HPRE_DIV8 LÚ P STM32_HPRE_DIV16 Ú P STM32_HPRE_DIV64 Ú P STM32_HPRE_DIV128 åÚ P STM32_HPRE_DIV256 ãÚ P STM32_HPRE_DIV512 èÚ P STM32_PPRE1_DIV1 Ú P STM32_PPRE1_DIV2 Ú P STM32_PPRE1_DIV4 Ú P STM32_PPRE1_DIV8 Ú P STM32_PPRE1_DIV16 àÚ P STM32_PPRE2_DIV1 Ú P STM32_PPRE2_DIV2 Ú P STM32_PPRE2_DIV4 Ú P STM32_PPRE2_DIV8 Ú P STM32_PPRE2_DIV16 ßÚ P STM32_PLLSRC_HSI àÚ P STM32_PLLSRC_HSE äÚ P STM32_MCOSEL_NOCLOCK ÀÚ P STM32_MCOSEL_SYSCLK òÚ P STM32_MCOSEL_HSI íÚ P STM32_MCOSEL_MSI èÚ P STM32_MCOSEL_HSE ñÚ P STM32_MCOSEL_PLL éÚ P STM32_MCOSEL_LSI éÚ P STM32_MCOSEL_LSE íÚ P STM32_MCOPRE_DIV1 ¸Ú P STM32_MCOPRE_DIV2 ·Ú P STM32_MCOPRE_DIV4 µÚ P STM32_MCOPRE_DIV8 ±Ú P STM32_MCOPRE_DIV16 Ú P STM32_MSIRANGE_MASK Ú P STM32_MSIRANGE_64K
Ú P STM32_MSIRANGE_128K RÚ P STM32_MSIRANGE_256K PÚ P STM32_MSIRANGE_512K UÚ P STM32_MSIRANGE_1M ¾Ú P STM32_MSIRANGE_2M ½Ú P STM32_MSIRANGE_4M »Ú P STM32_RTCSEL_MASK Ú P STM32_RTCSEL_NOCLOCK ¶Ú P STM32_RTCSEL_LSE ãÚ P STM32_RTCSEL_LSI ßÚ P STM32_RTCSEL_HSEDIV þÚ P STM32_HAS_ADC1 ÃÚ P STM32_HAS_ADC2 ÂÚ P STM32_HAS_ADC3 ÁÚ P STM32_HAS_ADC4 ÀÚ P STM32_HAS_CAN1 ¹Ú P STM32_HAS_CAN2 ¸Ú P STM32_CAN_MAX_FILTERS ZÚ P STM32_HAS_DAC öÚ P STM32_ADVANCED_DMA Ú P STM32_HAS_DMA1 ¹Ú P STM32_HAS_DMA2 ¸Ú P STM32_HAS_ETH ÝÚ P STM32_EXTI_NUM_CHANNELS ±Ú P STM32_HAS_GPIOA JÚ P STM32_HAS_GPIOB IÚ P STM32_HAS_GPIOC HÚ P STM32_HAS_GPIOD GÚ P STM32_HAS_GPIOE FÚ P STM32_HAS_GPIOF EÚ P STM32_HAS_GPIOG DÚ P STM32_HAS_GPIOH CÚ P STM32_HAS_GPIOI BÚ P STM32_HAS_I2C1 ÍÚ P STM32_I2C1_RX_DMA_MSK vÚ P STM32_I2C1_RX_DMA_CHN Ú P STM32_I2C1_TX_DMA_MSK tÚ P STM32_I2C1_TX_DMA_CHN Ú P STM32_HAS_I2C2 ÌÚ P STM32_I2C2_RX_DMA_MSK uÚ P STM32_I2C2_RX_DMA_CHN Ú P STM32_I2C2_TX_DMA_MSK sÚ P STM32_I2C2_TX_DMA_CHN
Ú P STM32_HAS_I2C3 ËÚ P STM32_I2C3_RX_DMA_MSK tÚ P STM32_I2C3_RX_DMA_CHN Ú P STM32_I2C3_TX_DMA_MSK rÚ P STM32_I2C3_TX_DMA_CHN Ú P STM32_HAS_RTC ÕÚ! P STM32_RTC_HAS_SUBSECONDS gÚ P STM32_RTC_IS_CALENDAR lÚ P STM32_HAS_SDIO Ú P STM32_HAS_SPI1 Ú P STM32_SPI1_RX_DMA_MSK HÚ P STM32_SPI1_RX_DMA_CHN ZÚ P STM32_SPI1_TX_DMA_MSK FÚ P STM32_SPI1_TX_DMA_CHN XÚ P STM32_HAS_SPI2 Ú P STM32_SPI2_RX_DMA_MSK GÚ P STM32_SPI2_RX_DMA_CHN YÚ P STM32_SPI2_TX_DMA_MSK EÚ P STM32_SPI2_TX_DMA_CHN WÚ P STM32_HAS_SPI3 Ú P STM32_SPI3_RX_DMA_MSK FÚ P STM32_SPI3_RX_DMA_CHN XÚ P STM32_SPI3_TX_DMA_MSK DÚ P STM32_SPI3_TX_DMA_CHN VÚ P STM32_HAS_TIM1 ¡Ú P STM32_HAS_TIM2 Ú P STM32_HAS_TIM3 Ú P STM32_HAS_TIM4 Ú P STM32_HAS_TIM5 Ú P STM32_HAS_TIM6 Ú P STM32_HAS_TIM7 Ú P STM32_HAS_TIM8 Ú P STM32_HAS_TIM9 Ú P STM32_HAS_TIM10 oÚ P STM32_HAS_TIM11 nÚ P STM32_HAS_TIM12 mÚ P STM32_HAS_TIM13 lÚ P STM32_HAS_TIM14 kÚ P STM32_HAS_TIM15 jÚ P STM32_HAS_TIM16 iÚ P STM32_HAS_TIM17 hÚ P STM32_HAS_TIM18 gÚ P STM32_HAS_TIM19 fÚ P STM32_HAS_USART1 øÚ P STM32_USART1_RX_DMA_MSK ¡Ú P STM32_USART1_RX_DMA_CHN ³Ú P STM32_USART1_TX_DMA_MSK Ú P STM32_USART1_TX_DMA_CHN ±Ú P STM32_HAS_USART2 ÷Ú P STM32_USART2_RX_DMA_MSK Ú P STM32_USART2_RX_DMA_CHN ²Ú P STM32_USART2_TX_DMA_MSK Ú P STM32_USART2_TX_DMA_CHN °Ú P STM32_HAS_USART3 öÚ P STM32_USART3_RX_DMA_MSK Ú P STM32_USART3_RX_DMA_CHN ±Ú P STM32_USART3_TX_DMA_MSK Ú P STM32_USART3_TX_DMA_CHN ¯Ú P STM32_HAS_UART4 JÚ P STM32_UART4_RX_DMA_MSK óÚ P STM32_UART4_RX_DMA_CHN Ú P STM32_UART4_TX_DMA_MSK ñÚ P STM32_UART4_TX_DMA_CHN Ú P STM32_HAS_UART5 IÚ P STM32_UART5_RX_DMA_MSK òÚ P STM32_UART5_RX_DMA_CHN Ú P STM32_UART5_TX_DMA_MSK ðÚ P STM32_UART5_TX_DMA_CHN Ú P STM32_HAS_USART6 óÚ P STM32_USART6_RX_DMA_MSK Ú P STM32_USART6_RX_DMA_CHN ®Ú P STM32_USART6_TX_DMA_MSK Ú P STM32_USART6_TX_DMA_CHN ¬Ú P STM32_HAS_USB ÔÚ P STM32_HAS_OTG1 ¡Ú P STM32_HAS_OTG2 Ú P WWDG_IRQHandler kÚ P PVD_IRQHandler ¼Ú P TAMPER_STAMP_IRQHandler çÚ P RTC_WKUP_IRQHandler
Ú P FLASH_IRQHandler 4Ú P RCC_IRQHandler ÎÚ P EXTI0_IRQHandler 8Ú P EXTI1_IRQHandler 7Ú P EXTI2_IRQHandler 6Ú P EXTI3_IRQHandler 5Ú P EXTI4_IRQHandler 4Ú P DMA1_Ch1_IRQHandler ^Ú P DMA1_Ch2_IRQHandler ]Ú P DMA1_Ch3_IRQHandler \Ú P DMA1_Ch4_IRQHandler [Ú P DMA1_Ch5_IRQHandler ZÚ P DMA1_Ch6_IRQHandler YÚ P DMA1_Ch7_IRQHandler XÚ P ADC1_IRQHandler «Ú P USB_HP_IRQHandler ¿Ú P USB_LP_IRQHandler »Ú P DAC_IRQHandler ÞÚ P COMP_IRQHandler uÚ P EXTI9_5_IRQHandler Ú P TIM9_IRQHandler Ú P TIM10_IRQHandler WÚ P TIM11_IRQHandler VÚ P LCD_IRQHandler ÓÚ P TIM2_IRQHandler Ú P TIM3_IRQHandler Ú P TIM4_IRQHandler Ú P I2C1_EV_IRQHandler µÚ P I2C1_ER_IRQHandler ¹Ú P I2C2_EV_IRQHandler ´Ú P I2C2_ER_IRQHandler ¸Ú P SPI1_IRQHandler Ú P SPI2_IRQHandler Ú P USART1_IRQHandler àÚ P USART2_IRQHandler ßÚ P USART3_IRQHandler ÞÚ P EXTI15_10_IRQHandler :Ú P RTC_Alarm_IRQHandler eÚ P USB_FS_WKUP_IRQHandler Ú P TIM6_IRQHandler Ú P TIM7_IRQHandler Ú P STM32_HSECLK_MAX ôÚ P STM32_SYSCLK_MAX ÕÚ P STM32_PLLVCO_MAX ÞÚ P STM32_PLLVCO_MIN àÚ P STM32_PCLK1_MAX UÚ P STM32_PCLK2_MAX TÚ P STM32_0WS_THRESHOLD Ú P STM32_HSI_AVAILABLE )Ú P STM32_ACTIVATE_PLL WÚ P
STM32_PLLMUL %Ú P
STM32_PLLDIV 0Ú P STM32_PLLCLKIN Ú P
STM32_PLLVCO +Ú P STM32_PLLCLKOUT ;Ú P
STM32_MSICLK 8Ú P
STM32_SYSCLK "Ú P STM32_HCLK ÝÚ P STM32_PCLK1 ¢Ú P STM32_PCLK2 ¡Ú P STM_MCODIVCLK ÂÚ P STM_MCOCLK «Ú P STM32_HSEDIVCLK XÚ P STM_RTCCLK ¡Ú P
STM32_ADCCLK YÚ P
STM32_USBCLK 7Ú P STM32_TIMCLK1 Ú P STM32_TIMCLK2 Ú P STM32_FLASHBITS1 "Ú P STM32_FLASHBITS2 !Ú halclock_t ÙÚ halrtcnt_t ºÚ" P hal_lld_get_counter_value OÚ& P hal_lld_get_counter_frequency Ú P _STM32_ISR_H_ ¦Ú P STM32_TIM2_HANDLER vÚ P STM32_TIM3_HANDLER uÚ P STM32_TIM4_HANDLER tÚ P STM32_TIM2_NUMBER Ú P STM32_TIM3_NUMBER ¬Ú P STM32_TIM4_NUMBER «Ú P STM32_USART1_HANDLER ÎÚ P STM32_USART2_HANDLER ÍÚ P STM32_USART3_HANDLER ÌÚ P STM32_USART1_NUMBER Ú P STM32_USART2_NUMBER Ú P STM32_USART3_NUMBER Ú P STM32_USB1_HP_HANDLER zÚ P STM32_USB1_LP_HANDLER vÚ P STM32_USB1_HP_NUMBER ±Ú P STM32_USB1_LP_NUMBER Ú P _STM32_DMA_H_ ÂÚ P STM32_DMA_STREAMS ¡Ú P STM32_DMA_ISR_MASK EÚ P STM32_DMA_GETCHANNEL áÚ$ P STM32_DMA_IS_VALID_PRIORITY `Ú P STM32_DMA_STREAM_ID Ú P STM32_DMA_STREAM_ID_MSK ²Ú P STM32_DMA_IS_VALID_ID aÚ P STM32_DMA_STREAM öÚ P STM32_DMA1_STREAM1 Ú P STM32_DMA1_STREAM2 Ú P STM32_DMA1_STREAM3 Ú P STM32_DMA1_STREAM4 Ú P STM32_DMA1_STREAM5 Ú P STM32_DMA1_STREAM6 Ú P STM32_DMA1_STREAM7 Ú P STM32_DMA_CR_EN =Ú P STM32_DMA_CR_TEIE ¥Ú P STM32_DMA_CR_HTIE ¢Ú P STM32_DMA_CR_TCIE §Ú P STM32_DMA_CR_DIR_MASK ZÚ P STM32_DMA_CR_DIR_P2M ¹Ú P STM32_DMA_CR_DIR_M2P ¹Ú P STM32_DMA_CR_DIR_M2M ¼Ú P STM32_DMA_CR_CIRC «Ú P STM32_DMA_CR_PINC ¢Ú P STM32_DMA_CR_MINC ¥Ú P STM32_DMA_CR_PSIZE_MASK ªÚ P STM32_DMA_CR_PSIZE_BYTE ¢Ú! P STM32_DMA_CR_PSIZE_HWORD PÚ P STM32_DMA_CR_PSIZE_WORD Ú P STM32_DMA_CR_MSIZE_MASK Ú P STM32_DMA_CR_MSIZE_BYTE ¥Ú! P STM32_DMA_CR_MSIZE_HWORD SÚ P STM32_DMA_CR_MSIZE_WORD Ú P STM32_DMA_CR_SIZE_MASK üÚ P STM32_DMA_CR_PL_MASK Ú P STM32_DMA_CR_PL 4Ú P STM32_DMA_CR_DMEIE fÚ P STM32_DMA_CR_CHSEL_MASK ÆÚ P STM32_DMA_CR_CHSEL [Ú P STM32_DMA_ISR_FEIF WÚ P STM32_DMA_ISR_DMEIF |
| 837 |
Ú P STM32_DMA_ISR_TEIF IÚ P STM32_DMA_ISR_HTIF FÚ P STM32_DMA_ISR_TCIF KÚ 8 |
837 |
Ú P STM32_DMA_ISR_TEIF IÚ P STM32_DMA_ISR_HTIF FÚ P STM32_DMA_ISR_TCIF KÚ 8 |
| 838 |
<unnamed> QÚ " ¡6channel ýÚ " ¡6ifcr 8Ú " ¡6ishift fÚ " ¡6 |
838 |
<unnamed> QÚ " ¡6channel ýÚ " ¡6ifcr 8Ú " ¡6ishift fÚ " ¡6 |
| 839 |
selfindex %Ú " ¡6vector ZÚ stm32_dma_stream_t ÕÚ stm32_dmaisr_t zÚ P dmaStreamSetPeripheral ÉÚ P dmaStreamSetMemory0 2Ú$ P dmaStreamSetTransactionSize ªÚ$ P dmaStreamGetTransactionSize ¶Ú P dmaStreamSetMode \Ú P dmaStreamEnable ÈÚ P dmaStreamDisable YÚ P dmaStreamClearInterrupt KÚ P dmaStartMemCopy ³Ú P dmaWaitCompletion ÈÚ < T_stm32_dma_streams NÚ dmaInit Ú , dmastp <Ú , |
839 |
selfindex %Ú " ¡6vector ZÚ stm32_dma_stream_t ÕÚ stm32_dmaisr_t zÚ P dmaStreamSetPeripheral ÉÚ P dmaStreamSetMemory0 2Ú$ P dmaStreamSetTransactionSize ªÚ$ P dmaStreamGetTransactionSize ¶Ú P dmaStreamSetMode \Ú P dmaStreamEnable ÈÚ P dmaStreamDisable YÚ P dmaStreamClearInterrupt KÚ P dmaStartMemCopy ³Ú P dmaWaitCompletion ÈÚ < T_stm32_dma_streams NÚ dmaInit Ú , dmastp <Ú , |
| 840 |
priority MÚ
, func Ú , param ¶Ú dmaStreamAllocate Ú , dmastp <Ú dmaStreamRelease iÚ P _STM32_RCC_ gÚ P rccEnableAPB1 .Ú P rccDisableAPB1 ¿Ú P
rccResetAPB1 tÚ P rccEnableAPB2 -Ú P rccDisableAPB2 ¾Ú P
rccResetAPB2 sÚ P
rccEnableAHB iÚ P rccDisableAHB úÚ P rccResetAHB ¯Ú P rccEnableADC1 9Ú P rccDisableADC1 ÊÚ P
rccResetADC1 Ú P rccEnableDMA1 /Ú P rccDisableDMA1 ÀÚ P
rccResetDMA1 uÚ P rccEnablePWRInterface Ú P rccDisablePWRInterface )Ú P rccResetPWRInterface ÞÚ P rccEnableI2C1 CÚ P rccDisableI2C1 ÔÚ P
rccResetI2C1 Ú P rccEnableI2C2 BÚ P rccDisableI2C2 ÓÚ P
rccResetI2C2 Ú P rccEnableSPI1 Ú P rccDisableSPI1 ¦Ú P
rccResetSPI1 [Ú P rccEnableSPI2 Ú P rccDisableSPI2 ¥Ú P
rccResetSPI2 ZÚ P rccEnableTIM2 Ú P rccDisableTIM2 §Ú P
rccResetTIM2 \Ú P rccEnableTIM3 Ú P rccDisableTIM3 ¦Ú P
rccResetTIM3 [Ú P rccEnableTIM4 Ú P rccDisableTIM4 ¥Ú P
rccResetTIM4 ZÚ P rccEnableUSART1 nÚ P rccDisableUSART1 ÿÚ P rccResetUSART1 ´Ú P rccEnableUSART2 mÚ P rccDisableUSART2 þÚ P rccResetUSART2 ³Ú P rccEnableUSART3 lÚ P rccDisableUSART3 ýÚ P rccResetUSART3 ²Ú P
rccEnableUSB JÚ P rccDisableUSB ÛÚ P rccResetUSB Ú
hal_lld_init íÚ stm32_clock_init Ú P _IO_CHANNEL_H_ ZÚ P _base_channel_methods Ú P _base_channel_data |Ú 8 BaseChannelVMT ~Ú " õ6write [Ú " õ6read ìÚ " õ6put 1Ú " õ6get JÚ " õ6putt »Ú " õ6gett ÔÚ " õ6writet åÚ " õ6readt vÚ 8 |
840 |
priority MÚ
, func Ú , param ¶Ú dmaStreamAllocate Ú , dmastp <Ú dmaStreamRelease iÚ P _STM32_RCC_ gÚ P rccEnableAPB1 .Ú P rccDisableAPB1 ¿Ú P
rccResetAPB1 tÚ P rccEnableAPB2 -Ú P rccDisableAPB2 ¾Ú P
rccResetAPB2 sÚ P
rccEnableAHB iÚ P rccDisableAHB úÚ P rccResetAHB ¯Ú P rccEnableADC1 9Ú P rccDisableADC1 ÊÚ P
rccResetADC1 Ú P rccEnableDMA1 /Ú P rccDisableDMA1 ÀÚ P
rccResetDMA1 uÚ P rccEnablePWRInterface Ú P rccDisablePWRInterface )Ú P rccResetPWRInterface ÞÚ P rccEnableI2C1 CÚ P rccDisableI2C1 ÔÚ P
rccResetI2C1 Ú P rccEnableI2C2 BÚ P rccDisableI2C2 ÓÚ P
rccResetI2C2 Ú P rccEnableSPI1 Ú P rccDisableSPI1 ¦Ú P
rccResetSPI1 [Ú P rccEnableSPI2 Ú P rccDisableSPI2 ¥Ú P
rccResetSPI2 ZÚ P rccEnableTIM2 Ú P rccDisableTIM2 §Ú P
rccResetTIM2 \Ú P rccEnableTIM3 Ú P rccDisableTIM3 ¦Ú P
rccResetTIM3 [Ú P rccEnableTIM4 Ú P rccDisableTIM4 ¥Ú P
rccResetTIM4 ZÚ P rccEnableUSART1 nÚ P rccDisableUSART1 ÿÚ P rccResetUSART1 ´Ú P rccEnableUSART2 mÚ P rccDisableUSART2 þÚ P rccResetUSART2 ³Ú P rccEnableUSART3 lÚ P rccDisableUSART3 ýÚ P rccResetUSART3 ²Ú P
rccEnableUSB JÚ P rccDisableUSB ÛÚ P rccResetUSB Ú
hal_lld_init íÚ stm32_clock_init Ú P _IO_CHANNEL_H_ ZÚ P _base_channel_methods Ú P _base_channel_data |Ú 8 BaseChannelVMT ~Ú " õ6write [Ú " õ6read ìÚ " õ6put 1Ú " õ6get JÚ " õ6putt »Ú " õ6gett ÔÚ " õ6writet åÚ " õ6readt vÚ 8 |
| 841 |
<unnamed> QÚ " þ6vmt *Ú BaseChannel ·Ú P chnPutTimeout XÚ P chnGetTimeout qÚ P chnWrite wÚ P chnWriteTimeout Ú P chnRead Ú P chnReadTimeout Ú P
CHN_NO_ERROR õÚ P CHN_CONNECTED æÚ P CHN_DISCONNECTED Ú P CHN_INPUT_AVAILABLE ýÚ P CHN_OUTPUT_EMPTY Ú P CHN_TRANSMISSION_END Ú+ P #_base_asynchronous_channel_methods wÚ( P _base_asynchronous_channel_data ×Ú# 8 BaseAsynchronousChannelVMT ZÚ " 7write ÀÚ " 7read QÚ " 7put Ú " 7get ¯Ú " 7putt Ú " 7gett 9Ú " 7writet JÚ " 7readt ÛÚ 8 |
841 |
<unnamed> QÚ " þ6vmt *Ú BaseChannel ·Ú P chnPutTimeout XÚ P chnGetTimeout qÚ P chnWrite wÚ P chnWriteTimeout Ú P chnRead Ú P chnReadTimeout Ú P
CHN_NO_ERROR õÚ P CHN_CONNECTED æÚ P CHN_DISCONNECTED Ú P CHN_INPUT_AVAILABLE ýÚ P CHN_OUTPUT_EMPTY Ú P CHN_TRANSMISSION_END Ú+ P #_base_asynchronous_channel_methods wÚ( P _base_asynchronous_channel_data ×Ú# 8 BaseAsynchronousChannelVMT ZÚ " 7write ÀÚ " 7read QÚ " 7put Ú " 7get ¯Ú " 7putt Ú " 7gett 9Ú " 7writet JÚ " 7readt ÛÚ 8 |
| 842 |
<unnamed> QÚ " 7vmt Ú " 7event ¼Ú BaseAsynchronousChannel Ú P chnGetEventSource ÝÚ P
chnAddFlagsI ;Ú P
_IO_BLOCK_H_ ìÚ BLK_UNINIT ÚÚ BLK_STOP oÚ BLK_ACTIVE õÚ BLK_CONNECTING ÁÚ BLK_DISCONNECTING ÛÚ |
842 |
<unnamed> QÚ " 7vmt Ú " 7event ¼Ú BaseAsynchronousChannel Ú P chnGetEventSource ÝÚ P
chnAddFlagsI ;Ú P
_IO_BLOCK_H_ ìÚ BLK_UNINIT ÚÚ BLK_STOP oÚ BLK_ACTIVE õÚ BLK_CONNECTING ÁÚ BLK_DISCONNECTING ÛÚ |
| 843 |
BLK_READY >Ú BLK_READING µÚ BLK_WRITING Ú BLK_SYNCING Ú blkstate_t ÀÚ 8 |
843 |
BLK_READY >Ú BLK_READING µÚ BLK_WRITING Ú BLK_SYNCING Ú blkstate_t ÀÚ 8 |
| 844 |
<unnamed> QÚ |
844 |
<unnamed> QÚ |
| 845 |
" ©7 blk_size Ú |
845 |
" ©7 blk_size Ú |
| 846 |
" ©7blk_num óÚ BlockDeviceInfo Ú# P _base_block_device_methods Ú P _base_block_device_data qÚ 8 BaseBlockDeviceVMT ôÚ " ¯7 is_inserted &Ú " ¯7
is_protected ¸Ú " ¯7connect ÝÚ " ¯7 disconnect Ú " ¯7read 1Ú " ¯7write Ú " ¯7sync Ú " ¯7 get_info zÚ 8 |
846 |
" ©7blk_num óÚ BlockDeviceInfo Ú# P _base_block_device_methods Ú P _base_block_device_data qÚ 8 BaseBlockDeviceVMT ôÚ " ¯7 is_inserted &Ú " ¯7
is_protected ¸Ú " ¯7connect ÝÚ " ¯7 disconnect Ú " ¯7read 1Ú " ¯7write Ú " ¯7sync Ú " ¯7 get_info zÚ 8 |
| 847 |
<unnamed> QÚ " ¸7vmt oÚ "" ¸7state Ú BaseBlockDevice -Ú P blkGetDriverState ãÚ P blkIsTransferring ¿Ú P blkIsInserted ~Ú P blkIsWriteProtected ûÚ P blkConnect ´Ú P blkDisconnect nÚ P blkRead Ú P blkWrite wÚ P blkSync çÚ P blkGetInfo ÒÚ P |
847 |
<unnamed> QÚ " ¸7vmt oÚ "" ¸7state Ú BaseBlockDevice -Ú P blkGetDriverState ãÚ P blkIsTransferring ¿Ú P blkIsInserted ~Ú P blkIsWriteProtected ûÚ P blkConnect ´Ú P blkDisconnect nÚ P blkRead Ú P blkWrite wÚ P blkSync çÚ P blkGetInfo ÒÚ P |
| 848 |
_MMCSD_H_ àÚ P _TM_H_ ¹Ú 8 TimeMeasurement Ú TimeMeasurement ÎÚ " È7start Ú " È7stop îÚ |
848 |
_MMCSD_H_ àÚ P _TM_H_ ¹Ú 8 TimeMeasurement Ú TimeMeasurement ÎÚ " È7start Ú " È7stop îÚ |
| 849 |
" È7last Ú |
849 |
" È7last Ú |
| 850 |
" È7worst Ú |
850 |
" È7worst Ú |
| 851 |
" È7best Ú P tmStartMeasurement 2Ú P tmStopMeasurement Ú tmInit gÚ , tmp zÚ
tmObjectInit Ú P _PAL_H_ {Ú P PAL_MODE_RESET lÚ P PAL_MODE_UNCONNECTED Ú P PAL_MODE_INPUT _Ú P PAL_MODE_INPUT_PULLUP Ú P PAL_MODE_INPUT_PULLDOWN yÚ P PAL_MODE_INPUT_ANALOG @Ú! P PAL_MODE_OUTPUT_PUSHPULL Ú" P PAL_MODE_OUTPUT_OPENDRAIN éÚ P PAL_LOW Ú P PAL_HIGH _Ú P _PAL_LLD_H_ 8Ú P PAL_STM32_MODE_MASK Ú P PAL_STM32_MODE_INPUT Ú P PAL_STM32_MODE_OUTPUT 8Ú! P PAL_STM32_MODE_ALTERNATE Ú P PAL_STM32_MODE_ANALOG wÚ P PAL_STM32_OTYPE_MASK Ú! P PAL_STM32_OTYPE_PUSHPULL :Ú" P PAL_STM32_OTYPE_OPENDRAIN Ú P PAL_STM32_OSPEED_MASK bÚ P PAL_STM32_OSPEED_LOWEST ¬Ú P PAL_STM32_OSPEED_MID1 Ú P PAL_STM32_OSPEED_MID2 Ú! P PAL_STM32_OSPEED_HIGHEST |Ú P PAL_STM32_PUDR_MASK ëÚ P PAL_STM32_PUDR_FLOATING »Ú P PAL_STM32_PUDR_PULLUP 1Ú P PAL_STM32_PUDR_PULLDOWN Ú! P PAL_STM32_ALTERNATE_MASK |Ú P PAL_STM32_ALTERNATE Ú P PAL_MODE_ALTERNATE GÚ 8 |
851 |
" È7best Ú P tmStartMeasurement 2Ú P tmStopMeasurement Ú tmInit gÚ , tmp zÚ
tmObjectInit Ú P _PAL_H_ {Ú P PAL_MODE_RESET lÚ P PAL_MODE_UNCONNECTED Ú P PAL_MODE_INPUT _Ú P PAL_MODE_INPUT_PULLUP Ú P PAL_MODE_INPUT_PULLDOWN yÚ P PAL_MODE_INPUT_ANALOG @Ú! P PAL_MODE_OUTPUT_PUSHPULL Ú" P PAL_MODE_OUTPUT_OPENDRAIN éÚ P PAL_LOW Ú P PAL_HIGH _Ú P _PAL_LLD_H_ 8Ú P PAL_STM32_MODE_MASK Ú P PAL_STM32_MODE_INPUT Ú P PAL_STM32_MODE_OUTPUT 8Ú! P PAL_STM32_MODE_ALTERNATE Ú P PAL_STM32_MODE_ANALOG wÚ P PAL_STM32_OTYPE_MASK Ú! P PAL_STM32_OTYPE_PUSHPULL :Ú" P PAL_STM32_OTYPE_OPENDRAIN Ú P PAL_STM32_OSPEED_MASK bÚ P PAL_STM32_OSPEED_LOWEST ¬Ú P PAL_STM32_OSPEED_MID1 Ú P PAL_STM32_OSPEED_MID2 Ú! P PAL_STM32_OSPEED_HIGHEST |Ú P PAL_STM32_PUDR_MASK ëÚ P PAL_STM32_PUDR_FLOATING »Ú P PAL_STM32_PUDR_PULLUP 1Ú P PAL_STM32_PUDR_PULLDOWN Ú! P PAL_STM32_ALTERNATE_MASK |Ú P PAL_STM32_ALTERNATE Ú P PAL_MODE_ALTERNATE GÚ 8 |
| 852 |
<unnamed> QÚ |
852 |
<unnamed> QÚ |
| 853 |
" ô7MODER Ú |
853 |
" ô7MODER Ú |
| 854 |
" ô7OTYPER ¯Ú |
854 |
" ô7OTYPER ¯Ú |
| 855 |
" ô7OSPEEDR ~Ú |
855 |
" ô7OSPEEDR ~Ú |
| 856 |
" ô7PUPDR Ú |
856 |
" ô7PUPDR Ú |
| 857 |
" ô7IDR ¹Ú |
857 |
" ô7IDR ¹Ú |
| 858 |
" ô7ODR ³Ú 8 |
858 |
" ô7ODR ³Ú 8 |
| 859 |
<unnamed> SÚ |
859 |
<unnamed> SÚ |
| 860 |
" û7W >Ú 8 |
860 |
" û7W >Ú 8 |
| 861 |
<unnamed> QÚ " ý7set AÚ " ý7clear Ú " û7H ;Ú " ô7BSRR MÚ |
861 |
<unnamed> QÚ " ý7set AÚ " ý7clear Ú " û7H ;Ú " ô7BSRR MÚ |
| 862 |
" ô7LCKR jÚ |
862 |
" ô7LCKR jÚ |
| 863 |
" ô7AFRL qÚ |
863 |
" ô7AFRL qÚ |
| 864 |
" ô7AFRH uÚ
GPIO_TypeDef ªÚ 8 |
864 |
" ô7AFRH uÚ
GPIO_TypeDef ªÚ 8 |
| 865 |
<unnamed> QÚ |
865 |
<unnamed> QÚ |
| 866 |
" 8moder êÚ |
866 |
" 8moder êÚ |
| 867 |
" 8otyper \Ú |
867 |
" 8otyper \Ú |
| 868 |
" 8ospeedr Ú |
868 |
" 8ospeedr Ú |
| 869 |
" 8pupdr ÖÚ |
869 |
" 8pupdr ÖÚ |
| 870 |
" 8odr ÀÚ |
870 |
" 8odr ÀÚ |
| 871 |
" 8afrl ^Ú |
871 |
" 8afrl ^Ú |
| 872 |
" 8afrh bÚ stm32_gpio_setup_t ³Ú 8 |
872 |
" 8afrh bÚ stm32_gpio_setup_t ³Ú 8 |
| 873 |
<unnamed> QÚ " 8PAData ÁÚ " 8PBData ÀÚ " 8PCData ¿Ú " 8PDData ¾Ú " 8PEData ½Ú " 8PHData ºÚ |
873 |
<unnamed> QÚ " 8PAData ÁÚ " 8PBData ÀÚ " 8PCData ¿Ú " 8PDData ¾Ú " 8PEData ½Ú " 8PHData ºÚ |
| 874 |
PALConfig ¼Ú P PAL_IOPORTS_WIDTH ^Ú P PAL_WHOLE_PORT PÚ
ioportmask_t ÍÚ iomode_t ¡Ú ioportid_t °Ú P IOPORT1 ¯Ú P IOPORT2 ®Ú P IOPORT3 Ú P IOPORT4 ¬Ú P IOPORT5 «Ú P IOPORT8 ¨Ú P
pal_lld_init ÈÚ P pal_lld_readport Ú P pal_lld_readlatch ÊÚ P pal_lld_writeport Ú P pal_lld_setport eÚ P pal_lld_clearport ¦Ú P pal_lld_writegroup Ú P pal_lld_setgroupmode NÚ P pal_lld_writepad Ú ¨pal_default_config ÉÚ , config OÚ _pal_lld_init Ú
, port Ú
, |
874 |
PALConfig ¼Ú P PAL_IOPORTS_WIDTH ^Ú P PAL_WHOLE_PORT PÚ
ioportmask_t ÍÚ iomode_t ¡Ú ioportid_t °Ú P IOPORT1 ¯Ú P IOPORT2 ®Ú P IOPORT3 Ú P IOPORT4 ¬Ú P IOPORT5 «Ú P IOPORT8 ¨Ú P
pal_lld_init ÈÚ P pal_lld_readport Ú P pal_lld_readlatch ÊÚ P pal_lld_writeport Ú P pal_lld_setport eÚ P pal_lld_clearport ¦Ú P pal_lld_writegroup Ú P pal_lld_setgroupmode NÚ P pal_lld_writepad Ú ¨pal_default_config ÉÚ , config OÚ _pal_lld_init Ú
, port Ú
, |
| 875 |
mask +Ú
, |
875 |
mask +Ú
, |
| 876 |
mode 2Ú _pal_lld_setgroupmode |
876 |
mode 2Ú _pal_lld_setgroupmode |
| 877 |
Ú 8 |
877 |
Ú 8 |
| 878 |
<unnamed> QÚ " ²8portid 3Ú |
878 |
<unnamed> QÚ " ²8portid 3Ú |
| 879 |
" ²8mask +Ú |
879 |
" ²8mask +Ú |
| 880 |
" ²8offset LÚ IOBus 5Ú P
PAL_PORT_BIT ôÚ P PAL_GROUP_MASK [Ú P _IOBUS_DATA [Ú P IOBUS_DECL ¾Ú P palInit ìÚ P palReadPort WÚ P
palReadLatch Ú P
palWritePort ÆÚ P palSetPort ©Ú P
palClearPort êÚ P palTogglePort mÚ P
palReadGroup íÚ P palWriteGroup \Ú P palSetGroupMode ²Ú P palReadPad éÚ P palWritePad XÚ P |
880 |
" ²8offset LÚ IOBus 5Ú P
PAL_PORT_BIT ôÚ P PAL_GROUP_MASK [Ú P _IOBUS_DATA [Ú P IOBUS_DECL ¾Ú P palInit ìÚ P palReadPort WÚ P
palReadLatch Ú P
palWritePort ÆÚ P palSetPort ©Ú P
palClearPort êÚ P palTogglePort mÚ P
palReadGroup íÚ P palWriteGroup \Ú P palSetGroupMode ²Ú P palReadPad éÚ P palWritePad XÚ P |
| 881 |
palSetPad ;Ú P palClearPad |Ú P
palTogglePad ÿÚ P palSetPadMode ®Ú , bus Ú palReadBus ñÚ , bus Ú
, |
881 |
palSetPad ;Ú P palClearPad |Ú P
palTogglePad ÿÚ P palSetPadMode ®Ú , bus Ú palReadBus ñÚ , bus Ú
, |
| 882 |
bits %Ú palWriteBus `Ú , bus Ú
, |
882 |
bits %Ú palWriteBus `Ú , bus Ú
, |
| 883 |
mode 2Ú palSetBusMode ¶Ú P _ADC_H_ Ú ADC_UNINIT ëÚ ADC_STOP Ú |
883 |
mode 2Ú palSetBusMode ¶Ú P _ADC_H_ Ú P _CAN_H_ Ú P _EXT_H_ gÚ P _GPT_H_ mÚ GPT_UNINIT ÈÚ GPT_STOP ]Ú |
| 884 |
ADC_READY OÚ ADC_ACTIVE Ú
ADC_COMPLETE eÚ |
884 |
GPT_READY ,Ú GPT_CONTINUOUS Ú GPT_ONESHOT }Ú gptstate_t ®Ú 8 |
| 885 |
ADC_ERROR :Ú adcstate_t ÑÚ P _ADC_LLD_H_ MÚ P ADC_CR2_EXTSEL_SRC >Ú P ADC_CCR_ADCPRE_DIV1 %Ú P ADC_CCR_ADCPRE_DIV2 $Ú P ADC_CCR_ADCPRE_DIV4 "Ú P ADC_CHANNEL_IN0 gÚ P ADC_CHANNEL_IN1 fÚ P ADC_CHANNEL_IN2 eÚ P ADC_CHANNEL_IN3 dÚ P ADC_CHANNEL_IN4 cÚ P ADC_CHANNEL_IN5 bÚ P ADC_CHANNEL_IN6 aÚ P ADC_CHANNEL_IN7 `Ú P ADC_CHANNEL_IN8 _Ú P ADC_CHANNEL_IN9 ^Ú P ADC_CHANNEL_IN10 4Ú P ADC_CHANNEL_IN11 3Ú P ADC_CHANNEL_IN12 2Ú P ADC_CHANNEL_IN13 1Ú P ADC_CHANNEL_IN14 0Ú P ADC_CHANNEL_IN15 /Ú P ADC_CHANNEL_SENSOR NÚ P ADC_CHANNEL_VREFINT Ú P ADC_CHANNEL_IN18 ,Ú P ADC_CHANNEL_IN19 +Ú P ADC_CHANNEL_IN20 3Ú P ADC_CHANNEL_IN21 2Ú P ADC_CHANNEL_IN22 1Ú P ADC_CHANNEL_IN23 0Ú P ADC_CHANNEL_IN24 /Ú P ADC_CHANNEL_IN25 .Ú P
ADC_SAMPLE_4 7Ú P
ADC_SAMPLE_9 2Ú P ADC_SAMPLE_16 Ú P ADC_SAMPLE_24 Ú P ADC_SAMPLE_48 ýÚ P ADC_SAMPLE_96 úÚ P ADC_SAMPLE_192 ËÚ P ADC_SAMPLE_384 ÈÚ P STM32_ADC_ADCPRE Ú P STM32_DMA_REQUIRED ]Ú adcsample_t nÚ adc_channels_num_t Ú ADC_ERR_DMAFAILURE Ú ADC_ERR_OVERFLOW úÚ adcerror_t ÈÚ 8 |
885 |
GPTDriver \Ú |
| 886 |
ADCDriver Ú |
886 |
GPTDriver Ú gptcallback_t Ú P _GPT_LLD_H_ *Ú P STM32_GPT_USE_TIM1 >Ú P STM32_GPT_USE_TIM5 :Ú P STM32_GPT_USE_TIM6 9Ú P STM32_GPT_USE_TIM7 8Ú P STM32_GPT_USE_TIM8 7Ú P STM32_GPT_USE_TIM9 6Ú P STM32_GPT_USE_TIM11 Ú P STM32_GPT_USE_TIM12 |
| 887 |
ADCDriver »Ú adccallback_t ¿Ú adcerrorcallback_t Ú 8 |
887 |
Ú P STM32_GPT_USE_TIM14 Ú$ P STM32_GPT_TIM1_IRQ_PRIORITY LÚ$ P STM32_GPT_TIM5_IRQ_PRIORITY HÚ$ P STM32_GPT_TIM6_IRQ_PRIORITY GÚ$ P STM32_GPT_TIM7_IRQ_PRIORITY FÚ$ P STM32_GPT_TIM8_IRQ_PRIORITY EÚ$ P STM32_GPT_TIM9_IRQ_PRIORITY DÚ% P STM32_GPT_TIM11_IRQ_PRIORITY Ú% P STM32_GPT_TIM12_IRQ_PRIORITY Ú% P STM32_GPT_TIM14_IRQ_PRIORITY Ú |
| 888 |
<unnamed> QÚ " 9 circular ¥Ú " 9
num_channels îÚ " 9end_cb Ú " 9 error_cb Ú |
888 |
gptfreq_t #Ú gptcnt_t Ú 8 |
| 889 |
" 9cr1 ÷Ú |
889 |
<unnamed> QÚ |
| 890 |
" 9cr2 öÚ |
890 |
" õ8 |
| 891 |
" 9smpr1 Ú |
891 |
frequency ¸Ú " õ8 callback QÚ |
| 892 |
" 9smpr2 Ú |
892 |
GPTConfig ®Ú "" Ý8state tÚ " Ý8config $Ú |
| 893 |
" 9smpr3 Ú |
893 |
" Ý8clock Ú " Ý8tim VÚ P gpt_lld_change_interval .Ú GPTD2 rÚ
gpt_lld_init ×Ú
, gptp Ú gpt_lld_start [Ú
, gptp Ú
gpt_lld_stop ÅÚ
, gptp Ú , period NÚ gpt_lld_start_timer ÏÚ
, gptp Ú gpt_lld_stop_timer 9Ú
, gptp Ú , interval hÚ gpt_lld_polled_delay Ú P gptChangeIntervalI Ú gptInit ûÚ
, gptp Ú gptObjectInit Ú
, gptp Ú , config OÚ gptStart Ú
, gptp Ú gptStop éÚ
, gptp Ú , interval hÚ gptStartContinuous 4Ú
, gptp Ú , interval hÚ gptStartContinuousI éÚ
, gptp Ú , interval hÚ gptChangeInterval ðÚ
, gptp Ú , interval hÚ gptStartOneShot ±Ú
, gptp Ú , interval hÚ gptStartOneShotI fÚ
, gptp Ú
gptStopTimer ÞÚ
, gptp Ú gptStopTimerI Ú
, gptp Ú , interval hÚ gptPolledDelay 2Ú P _I2C_H_ Ú P _ICU_H_ wÚ P _MAC_H_ Ú P _PWM_H_ dÚ P _RTC_H_ oÚ P _SERIAL_H_ Ú P SD_PARITY_ERROR õÚ P SD_FRAMING_ERROR ÈÚ P SD_OVERRUN_ERROR Ú P SD_NOISE_ERROR RÚ P SD_BREAK_DETECTED Ú |
| 894 |
" 9sqr1 tÚ |
894 |
SD_UNINIT Ú SD_STOP ³Ú SD_READY Ú |
| 895 |
" 9sqr2 sÚ |
895 |
sdstate_t $Ú 8
SerialDriver áÚ
SerialDriver Ú P _SERIAL_LLD_H_ OÚ P STM32_SERIAL_USE_UART4 Ú P STM32_SERIAL_USE_UART5 Ú P STM32_SERIAL_USE_USART6 µÚ$ P STM32_SERIAL_UART4_PRIORITY mÚ$ P STM32_SERIAL_UART5_PRIORITY lÚ% P STM32_SERIAL_USART6_PRIORITY Ú 8 |
| 896 |
" 9sqr3 rÚ |
896 |
<unnamed> QÚ |
| 897 |
" 9sqr4 qÚ |
897 |
" Ã9 sc_speed wÚ " Ã9sc_cr1 Ú " Ã9sc_cr2 Ú " Ã9sc_cr3 Ú
SerialConfig 3Ú P _serial_driver_data âÚ P USART_CR2_STOP1_BITS Ú P USART_CR2_STOP0P5_BITS ÿÚ P USART_CR2_STOP2_BITS Ú P USART_CR2_STOP1P5_BITS þÚ SD1 Ú SD2 Ú sd_lld_init MÚ , sdp Ú , config OÚ
sd_lld_start ÑÚ , sdp Ú sd_lld_stop ;Ú P _serial_driver_methods Ú 8 SerialDriverVMT äÚ " ×9write vÚ " ×9read Ú " ×9put LÚ " ×9get eÚ " ×9putt ÖÚ " ×9gett ïÚ " ×9writet Ú " ×9readt Ú " º9vmt kÚ " º9event Ú "" º9state Ú " $º9iqueue |
| 898 |
" 9sqr5 pÚ ADCConversionGroup âÚ 8 |
898 |
Ú " $º9oqueue Ú
<" º9ib ÉÚ
<" º9ob ÃÚ " º9usart Ú P sdPutWouldBlock §Ú P sdGetWouldBlock ÀÚ P sdPut ±Ú P
sdPutTimeout ¼Ú P sdGet ÊÚ P
sdGetTimeout ÕÚ P sdWrite ÛÚ P sdWriteTimeout æÚ P sdAsynchronousWrite ·Ú P sdRead lÚ P sdReadTimeout wÚ P sdAsynchronousRead HÚ sdInit qÚ , sdp Ú , inotify ÁÚ , onotify »Ú
sdObjectInit Ú , sdp Ú , config OÚ sdStart õÚ , sdp Ú sdStop _Ú , sdp Ú |
| 899 |
<unnamed> QÚ |
899 |
, b Ú sdIncomingDataI üÚ , sdp Ú sdRequestDataI IÚ P _SDC_H_ ~Ú P _SPI_H_ lÚ P _UART_H_ Ú P _USB_H_ nÚ P _MMC_SPI_H_ (Ú P _SERIAL_USB_H_ AÚ P S2RTT BÚ P MS2RTT óÚ P US2RTT ëÚ P RTT2S BÚ P RTT2MS óÚ P RTT2US ëÚ P halGetCounterValue uÚ P halGetCounterFrequency ¸Ú halInit Ú , |
| 900 |
" 9dummy ½Ú |
900 |
start §Ú , |
| 901 |
ADCConfig ÑÚ "" 9state ÇÚ " 9config wÚ " 9samples öÚ |
901 |
end ¢Ú halIsCounterWithin Ú , |
| 902 |
" 9depth èÚ " 9grpp 8Ú " 9thread uÚ " 9mutex ¬Ú " 9adc ËÚ " 9dmastp dÚ |
902 |
ticks ·Ú halPolledDelay HÚ , |
| 903 |
" 9dmamode "Ú P ADC_SQR1_NUM_CH &Ú P ADC_SQR5_SQ1_N |Ú P ADC_SQR5_SQ2_N {Ú P ADC_SQR5_SQ3_N zÚ P ADC_SQR5_SQ4_N yÚ P ADC_SQR5_SQ5_N xÚ P ADC_SQR5_SQ6_N wÚ P ADC_SQR4_SQ7_N wÚ P ADC_SQR4_SQ8_N vÚ P ADC_SQR4_SQ9_N uÚ P ADC_SQR4_SQ10_N KÚ P ADC_SQR4_SQ11_N JÚ P ADC_SQR4_SQ12_N IÚ P ADC_SQR3_SQ13_N IÚ P ADC_SQR3_SQ14_N HÚ P ADC_SQR3_SQ15_N GÚ P ADC_SQR3_SQ16_N FÚ P ADC_SQR3_SQ17_N EÚ P ADC_SQR3_SQ18_N DÚ P ADC_SQR2_SQ19_N DÚ P ADC_SQR2_SQ20_N LÚ P ADC_SQR2_SQ21_N KÚ P ADC_SQR2_SQ22_N JÚ P ADC_SQR2_SQ23_N IÚ P ADC_SQR2_SQ24_N HÚ P ADC_SQR1_SQ25_N HÚ P ADC_SQR1_SQ26_N GÚ P ADC_SQR1_SQ27_N FÚ P ADC_SMPR3_SMP_AN0 Ú P ADC_SMPR3_SMP_AN1 Ú P ADC_SMPR3_SMP_AN2 Ú P ADC_SMPR3_SMP_AN3 Ú P ADC_SMPR3_SMP_AN4 Ú P ADC_SMPR3_SMP_AN5 Ú P ADC_SMPR3_SMP_AN6 Ú P ADC_SMPR3_SMP_AN7 Ú P ADC_SMPR3_SMP_AN8 Ú P ADC_SMPR3_SMP_AN9 Ú P ADC_SMPR2_SMP_AN10 nÚ P ADC_SMPR2_SMP_AN11 mÚ P ADC_SMPR2_SMP_AN12 lÚ P ADC_SMPR2_SMP_AN13 kÚ P ADC_SMPR2_SMP_AN14 jÚ P ADC_SMPR2_SMP_AN15 iÚ P ADC_SMPR2_SMP_SENSOR Ú P ADC_SMPR2_SMP_VREF +Ú P ADC_SMPR2_SMP_AN18 fÚ P ADC_SMPR2_SMP_AN19 eÚ P ADC_SMPR1_SMP_AN20 nÚ P ADC_SMPR1_SMP_AN21 mÚ P ADC_SMPR1_SMP_AN22 lÚ P ADC_SMPR1_SMP_AN23 kÚ P ADC_SMPR1_SMP_AN24 jÚ P ADC_SMPR1_SMP_AN25 iÚ 4ADCD1 rÚ
adc_lld_init úÚ
, adcp 1Ú adc_lld_start ~Ú
, adcp 1Ú
adc_lld_stop èÚ
, adcp 1Ú! adc_lld_start_conversion ÃÚ
, adcp 1Ú adc_lld_stop_conversion -Ú adcSTM32EnableTSVREFE ×Ú adcSTM32DisableTSVREFE hÚ P
_adc_reset_i âÚ P
_adc_reset_s ØÚ P _adc_wakeup_isr Ú P _adc_timeout_isr Ú P _adc_isr_half_code Ú P _adc_isr_full_code gÚ P _adc_isr_error_code îÚ adcInit Ú
, adcp 1Ú adcObjectInit »Ú
, adcp 1Ú , config OÚ adcStart ¢Ú
, adcp 1Ú adcStop Ú
, adcp 1Ú
, grpp Ú , samples ÎÚ , |
903 |
" :start ·Ú , |
| 904 |
depth ÀÚ adcStartConversion hÚ
, adcp 1Ú
, grpp Ú , samples ÎÚ , |
904 |
" :end ²Ú |
| 905 |
depth ÀÚ adcStartConversionI Ú
, adcp 1Ú adcStopConversion ÒÚ
, adcp 1Ú adcStopConversionI Ú
, adcp 1Ú
, grpp Ú , samples ÎÚ , |
905 |
" :now ¹Ú , |
| 906 |
depth ÀÚ adcConvert ËÚ
, adcp 1Ú adcAcquireBus ²Ú
, adcp 1Ú adcReleaseBus »Ú P _CAN_H_ Ú P _EXT_H_ gÚ P _GPT_H_ mÚ GPT_UNINIT ÈÚ GPT_STOP ]Ú |
906 |
" :ticks ÅÚ |
| 907 |
GPT_READY ,Ú GPT_CONTINUOUS Ú GPT_ONESHOT }Ú gptstate_t ®Ú 8 |
907 |
" :start ÙÚ |
| 908 |
GPTDriver \Ú |
908 |
" :timeout üÛ ! 7Û & ×Û + ÑÛ 4 ÇÛ 9 ÁÛ > »ÛK H % |
| 909 |
GPTDriver Ú gptcallback_t Ú P _GPT_LLD_H_ *Ú P STM32_GPT_USE_TIM1 >Ú P STM32_GPT_USE_TIM5 :Ú P STM32_GPT_USE_TIM6 9Ú P STM32_GPT_USE_TIM7 8Ú P STM32_GPT_USE_TIM8 7Ú P STM32_GPT_USE_TIM9 6Ú P STM32_GPT_USE_TIM11 Ú P STM32_GPT_USE_TIM12 |
909 |
|
| 910 |
Ú P STM32_GPT_USE_TIM14 Ú$ P STM32_GPT_TIM1_IRQ_PRIORITY LÚ$ P STM32_GPT_TIM5_IRQ_PRIORITY HÚ$ P STM32_GPT_TIM6_IRQ_PRIORITY GÚ$ P STM32_GPT_TIM7_IRQ_PRIORITY FÚ$ P STM32_GPT_TIM8_IRQ_PRIORITY EÚ$ P STM32_GPT_TIM9_IRQ_PRIORITY DÚ% P STM32_GPT_TIM11_IRQ_PRIORITY Ú% P STM32_GPT_TIM12_IRQ_PRIORITY Ú% P STM32_GPT_TIM14_IRQ_PRIORITY Ú |
910 |
Ï |
| 911 |
gptfreq_t #Ú gptcnt_t Ú 8 |
911 |
õ |
| 912 |
<unnamed> QÚ |
912 |
|
| 913 |
" ³: |
913 |
ý |
| 914 |
frequency øÚ " ³: callback Ú |
914 |
|
| 915 |
GPTConfig ®Ú "" :state ´Ú " :config dÚ |
915 |
´ |
| 916 |
" :clock ÞÚ " :tim Ú P gpt_lld_change_interval .Ú GPTD2 rÚ
gpt_lld_init ×Ú
, gptp Ú gpt_lld_start [Ú
, gptp Ú
gpt_lld_stop ÅÚ
, gptp Ú , period NÚ gpt_lld_start_timer ÏÚ
, gptp Ú gpt_lld_stop_timer 9Ú
, gptp Ú , interval hÚ gpt_lld_polled_delay Ú P gptChangeIntervalI Ú gptInit ûÚ
, gptp Ú gptObjectInit Ú
, gptp Ú , config OÚ gptStart Ú
, gptp Ú gptStop éÚ
, gptp Ú , interval hÚ gptStartContinuous 4Ú
, gptp Ú , interval hÚ gptStartContinuousI éÚ
, gptp Ú , interval hÚ gptChangeInterval ðÚ
, gptp Ú , interval hÚ gptStartOneShot ±Ú
, gptp Ú , interval hÚ gptStartOneShotI fÚ
, gptp Ú
gptStopTimer ÞÚ
, gptp Ú gptStopTimerI Ú
, gptp Ú , interval hÚ gptPolledDelay 2Ú P _I2C_H_ Ú P _ICU_H_ wÚ P _MAC_H_ Ú P _PWM_H_ dÚ P PWM_OUTPUT_MASK ÞÚ P PWM_OUTPUT_DISABLED ÊÚ P PWM_OUTPUT_ACTIVE_HIGH ÁÚ P PWM_OUTPUT_ACTIVE_LOW ñÚ PWM_UNINIT ¿Ú PWM_STOP TÚ |
916 |
Á |
| 917 |
PWM_READY #Ú pwmstate_t ¥Ú 8 |
917 |
Ó |
| 918 |
PWMDriver SÚ |
918 |
ã $%OiHÛL ä ! ! O f ¬ Ñ Ú é í%%ºÛM %©0"0"3È3Ì3Ô3£3ª3¸4 5 6 8ï8ï8÷8ûîÛR 8ÿ8ÿ888888888888 8 8¡úÛR 8¡8¢8¢8£8£8¤8¤8¨8²8·8¼8Á8Æ8Ë8Ð8ÕåÛO 8Ú8ß8·8¿8Ã8Ç8Ë8Ï8Ó8×8Û8ß8ã9$: ; ÛP < =$??????£?£?¨?¨?©?©?·?¼?ÁZÛG ?Æ????@ A B C D E FGFJFMFSFV'Û& FYF\FbFeFhFkFnFqFtWÛE O k(] 86 #(=#µµºÃ´ÛE à %E %))D ^cw¥ÛI ®´¾ÄÏÏó %%(((48 ?ÛL \ ! %ÿ%%¤%¬.Ê1 2 3 3Ä3Ð333?ÛP 333±7 8 8ó8ó8÷8û8888888» ÛM > >R>R? ??????§?§??²??!WÛ !ÊFAFDFPF_F{Û Y Û |
| 919 |
PWMDriver Ú pwmcallback_t Ú P _PWM_LLD_H_ !Ú P
PWM_CHANNELS Ú& P PWM_COMPLEMENTARY_OUTPUT_MASK Ú* P "PWM_COMPLEMENTARY_OUTPUT_DISABLED oÚ- P %PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH fÚ, P $PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW Ú P STM32_PWM_USE_ADVANCED Ú P STM32_PWM_USE_TIM1 5Ú P STM32_PWM_USE_TIM5 1Ú P STM32_PWM_USE_TIM8 .Ú P STM32_PWM_USE_TIM9 -Ú$ P STM32_PWM_TIM1_IRQ_PRIORITY CÚ$ P STM32_PWM_TIM5_IRQ_PRIORITY ?Ú$ P STM32_PWM_TIM8_IRQ_PRIORITY <Ú$ P STM32_PWM_TIM9_IRQ_PRIORITY ;Ú |
919 |
c Û 3Û , ÆÛ
; ¬ÖðÛ J ¦Û [ $ßÛ p kµÃ !Û ]^c \¿Û ®ó%¶Û 6%)NÛ ¤ DÛ |
| 920 |
pwmmode_t #Ú
pwmchannel_t éÚ pwmcnt_t
Ú 8 |
920 |
° 8kÛ º ()DÄ®Û |
| 921 |
<unnamed> QÚ |
921 |
Æ #eÛ |
| 922 |
" ;mode WÚ " ; callback ¹Ú PWMChannelConfig ÞÚ 8 |
922 |
Ò =>Û Ü #¥¾.Ê>RÛ è µºÃúÛ ó ´áÛ ÿ áÛ |
| 923 |
<unnamed> QÚ |
923 |
Û >RqÛ E%Û ® (4×Û !¼ %OrÛ "Ç Ï(8HÛ #Ô wÏ %(6Û $è ! O Ú´Û %ó ìÛ &ÿ ¬¾Û ' f éÛ ( |
| 924 |
" ; |
924 |
ãi !÷Û )¤ ä¨Û *± üÛ + Õ×!Û ,Î Û -Ü ñÛ .æ æÛ /ð ÛÛ 0û ÏÛ |
| 925 |
frequency Ú " ;period oÚ " ; callback µÚ <" ; channels VÚ " ;cr2 ñÚ |
925 |
1 >sÛ 2 Û 3 Û 4 IÛ 5
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1479 |
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1480 |
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"Û º'Ü |
1481 |
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1484 |
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#'£ rÛ #'¤ pÛ #'¥ nÛ #'¨ jÛ #'© hÛ #'ª fÛ #'« dÛ #'¬ bÛ #' `Û #'® ^Û #'¯ \Û #'± YÛ #'² WÛ #'³ UÛ #'µ RÛ #'¶ PÛ #'· NÛ #'¸ LÛ #'» HÛ #'¼ FÛ #'½ DÛ #'¾ BÛ #'¿ @Û #'À >Û #'Â ;Û #'Ã 9Û #'Ä 7Û #'Ì .Û ¡#'Í ,Û ¢#'Ï )Û £#'Ð 'Û ¤#'Ò $Û ¥#'Ó "Û ¦#'Ô Û §#'Ö Û ¨#'× Û ©#'Ø Û ª#'Ú Û «#'Û Û ¬#'Ü Û #'ß Û ®#'à Û ¯#'â Û °#'ã Û ±#'ä Û ²#'å Û ³#'æ Û ´#'ç ÿÛ µ#'è ýÛ ¶#'é ûÛ ·#'ê ùÛ ¸#'ë ÷Û ¹#'î óÛ º#'ï ñÛ »#'ð ïÛ ¼#'ó ëÛ ½#'ô éÛ ¾#'õ çÛ ¿#'ö åÛ À#'ø âÛ Á#'ù àÛ Â#'ú ÞÛ Ã#'ý ÚÛ Ä#'þ ØÛ Å#'ÿ ÖÛ Æ#' SÛ Ç#' PÛ È#' NÛ É#' LÛ Ê#'
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| 1485 |
Û ¾'á |
1485 |
Û ç#'¬ Û è#'® Û é#'¯ Û ê#'² ýÛ ë#'³ ûÛ ì#'´ ùÛ í#'µ ÷Û î#'¶ õÛ ï#'¹ ñÛ ð#'º ïÛ ñ#'» íÛ ò#'¼ ëÛ ó#'½ éÛ ô#'¾ çÛ õ#'¿ åÛ ö#'À ãÛ ÷#'Á áÛ ø#'Ä ÝÛ ù#'Å ÛÛ ú#'Æ ÙÛ û#'Ê ÔÛ ü#'Ë ÒÛ ý#'Ì ÐÛ þ#'Í ÎÛ ÿ#'Ð ÊÛ $'Ñ GÛ $'Ò EÛ $'Ó CÛ $'Ö ?Û $'× =Û
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| 1486 |
Û ¿'â |
1486 |
Û $'õ Û $'ö Û $'÷ Û $'ø Û $'ù ÿÛ ¡$'ú ýÛ ¢$'û ûÛ £$'ý øÛ ¤$'þ öÛ ¥$'ÿ ôÛ ¦$' qÛ §$' oÛ ¨$' mÛ ©$' kÛ ª$' iÛ «$' dÛ ¬$' bÛ $' `Û ®$' ^Û ¯$' \Û °$' ZÛ ±$' XÛ ²$' VÛ ³$' TÛ ´$' RÛ µ$' PÛ ¶$' NÛ ·$' LÛ ¸$' JÛ ¹$' FÛ º$' DÛ »$' BÛ ¼$' @Û ½$' >Û ¾$' <Û ¿$' :Û À$' 8Û Á$'¢ 4Û Â$'£ 2Û Ã$'¤ 0Û Ä$'¥ .Û Å$'¦ ,Û Æ$'§ *Û Ç$'¨ (Û È$'© &Û É$'ª $Û Ê$'« "Û Ë$'¬ Û Ì$' Û Í$'® Û Î$'¯ Û Ï$'° Û Ð$'± Û Ñ$'² Û Ò$'³ Û Ó$'´ Û Ô$'µ Û Õ$'¸ |
| 1487 |
Û À'ã |
1487 |
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| 1488 |
Û Á'ä |
1488 |
Û %'ÿ Û %'
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| 1489 |
Û Â'æ |
1489 |
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| 1490 |
Û Ã'ç |
1490 |
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| 1491 |
Û Ä'è |
1491 |
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| 1492 |
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1492 |
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Û Å'é |
1493 |
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| 1495 |
Û Ç'ë |
1495 |
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Û È'í |
1496 |
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| 1497 |
Û É'î |
1497 |
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| 1498 |
ÿÛ Ê'ï |
1498 |
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1499 |
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1500 |
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1501 |
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1502 |
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1503 |
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1504 |
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1505 |
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1506 |
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1507 |
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1508 |
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1509 |
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1510 |
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1511 |
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1512 |
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1513 |
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1515 |
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1517 |
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1518 |
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1519 |
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1520 |
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1526 |
¯9=!=" ÕÛ |
| 1527 |
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% Û ì*'% Û í*'% Û î*'% Û ï*'% Û ð*'% Û ñ*'% Û ò*'% |
1527 |
°9> > ÚÛ ±9>* Û ²9>+ «Û ³9>, ©Û ´9>- §Û µ9>. ¥Û ¶9>^ tÛ ·9>_ rÛ ¸9>` pÛ ¹9>a >&Û º9>f> #Û3 »9>f ???¥?¦>±>²>³>´>µÛ |
| 1528 |
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1528 |
¼9?? ÔÛ ½9?K ??¨?¼?ÐÛ ¾9?T ??©?Á?¹Û ¿9?] ?£?©?Æ?£Û À9?y ?½ËÛ Á9? ?Â¼Û Â9? ?Ç¯Û Ã9?× ëÛ Ä9?Û æÛ Å9?à àÛ Æ9?ä ÛÛ Ç9?è ÖÛ È9?é ?¥>²ðÛ É9?î >Û Ê9?
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| 1529 |
Û Ò/'£, Û Ó/'¤, Û Ô/'¥, Û Õ/'¦, Û Ö/'§, ÿÛ ×/'¨, ýÛ Ø/'ª, úÛ Ù/', öÛ Ú/'¯, óÛ Û/'°, ñÛ Ü/'±, ïÛ Ý/'², íÛ Þ/'³, ëÛ ß/'´, éÛ à/'¶, æÛ á/'¹, âÛ â/'», ßÛ ã/'¼, ÝÛ ä/'½, ÛÛ å/'¾, ÙÛ æ/'¿, ×Û ç/'À, ÕÛ è/'Â, ÒÛ é/'Ç, ÌÛ ê/'É, ÉÛ ë/'Ê, ÇÛ ì/'Ë, ÅÛ í/'Ì, ÃÛ î/'Í, ÁÛ ï/'Î, ¿Û ð/'Ð, ¼Û ñ/'Ó, ¸Û ò/'Õ, µÛ ó/'Ö, ³Û ô/'×, ±Û õ/'Ø, ¯Û ö/'Ù, Û ÷/'Ú, «Û ø/'Ü, ¨Û ù/'ß, ¤Û ú/'á, ¡Û û/'â, Û ü/'ã, Û ý/'ä, Û þ/'å, Û ÿ/'æ, Û 0'è, Û 0'ë, Û 0'í, Û 0'î, |
1529 |
Ö9>m >v Û ×9>u >õÛ Ø9>v :Û Ù9>v 9Û Ú9>v 8Û Û9>v 7Û Ü9>v 6Û Ý9>v 5Û Þ9>v 4Û ß9>v 3Û à9> $Û á9> "Û â9> !Û ã9> Û ä9> Û å9> Û æ9> Û ç9> Û è9> Û é9>¦ ÷Û ê9>² êÛ ë9>¾ ÝÛ ì9>Ê ÐÛ í9>Ö ÃÛ î9>â ¶Û ï9>ð §Û ð9>ý Û ñ9> |
| 1530 |
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1530 |
Û ò9> ûÛ ó9>¥ íÛ ô9>°F`TÛ õ9>±}Û ö9>±|Û ÷9>±{Û ø9>±zÛ ù9>²xÛ ú9>²wÛ û9>²vÛ ü9>³tÛ ý9>³sÛ þ9>´qÛ ÿ9>´pÛ :>´îÛ :>µìÛ :>µëÛ |
| 1531 |
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1531 |
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| 1532 |
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1533 |
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1536 |
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¬7/> /bÛ |
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7/C /bÛ |
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®7/Z /lqÛ |
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¯7/a /kjÛ °7/b Û ±7/b Û ²7/b
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Æ70 0 ÞÛ |
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| 1548 |
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| 1552 |
Û ù73 Û ú73 Û û73 Û ü73 Û ý73 Û þ73 þÛ ÿ73 üÛ 83 yÛ 83 wÛ 83 uÛ 83 sÛ 83 qÛ
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| 1553 |
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| 1555 |
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| 1556 |
:7 7 Û |
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| 1558 |
:99 ýÛ :90 9ï99¨9·ÌÛ :9T 9ÿ9¡9¼9ÇqÛ ¡:9] 99¡9Á9ËÙÛ ¢:9f 99¢9Æ9ÏÁÛ £:9o 99¢9Ë9ÓªÛ ¤:9x 99£9Ð9×Û ¥:9 99£9Õ9ÛyÛ ¦:9 99¤9Ú9ßaÛ §:9 99¤9ß9ãJÛ ¨:9 9©ÞÛ ©:9¶ 9½Û ª:9½ 9Â Û «:9Ä 9ÇÛ ¬:9Ë 9ÌÛ :9Ò 9ÑyÛ ®:9Ù 9ÖlÛ ¯:9à 9Û_Û °:9ç 9àRÛ ±:9ë 9ü0Û) ²:9ð 9í9ï8k8l8m8n8o8rÛ ³:9ö àÛ ´:9ü ÙÛ µ:9 RÛ ¶:9 98i×Û ·:9 EÛ ¸:9 @Û ¹:9 7Û º:9 2Û »:9° Û ¼:9¼®Û ½:9êÛ ¾:9ë}Û ¿:9ë|Û À:9ìzÛ Á:9ìyÛ Â:9íwÛ Ã:9ívÛ Ä:9íuÛ Å:9îsÛ Æ:9îrÛ Ç:9ïpÛ È:9ïoÛ É:9ïnÛ Ê:8\ gÛ Ë:8gHQÛÛ Ì:8h÷Û Í:8höÛ Î:8iôÛ Ï:8ióÛ Ð:8iòÛ Ñ:8jðÛ Ò:8jïÛ Ó:8kíÛ Ô:8kìÛ Õ:8këÛ Ö:8léÛ ×:8lèÛ Ø:8lçÛ Ù:8måÛ Ú:8mäÛ Û:8mãÛ Ü:8náÛ Ý:8nàÛ Þ:8nßÛ ß:8oÝÛ à:8oÜÛ á:8oÛÛ â:8pÙÛ ã:8pØÛ ä:8qÖÛ å:8qÕÛ æ:8rÓÛ ç:8rÒÛ è:8rÑÛ |
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| 1559 |
é::!:" Û |
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| 1560 |
ê:; ; ¥Û |
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| 1561 |
ë:< < ¤Û |
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| 1562 |
ì:= = Û í:=- nÛ î:=2 hÛ ï:=7 bÛ ð:=< \Û ñ:=O HÛ ò:=P FÛ ó:=Q DÛ ô:=R >ëÛ õ:=W>ç ÛA ö:=W =^>·>Ê>Ë>Ì>Ï=ì=í=î=ï=ð=ó Û ÷:=^ >·>Ð Û |
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| 1563 |
ø:>> Û ù:>% >ÔÏÛ ú:>+ bÛ û:>1 [Û ü:>: QÛ ý:>C GÛ þ:>T >ð>ÛßÛ ÿ:>] >Í>é>ð>ô>ª Û ;> >Ý>ë>>ºbÛ% ;> >á>ë>ì>ð>>¾åÛ ;> >å>>ÂäÛ ;> >õÛ ;>¶ >ûÛ
;>½ >îÛ ;>Å >àÛ ;> >±çÛ ;>£ >Í>Ï=ñ=óÂÛ ;>¨ >Ê>ó>Î=ï=ò Û ;> LÛ ;>± GÛ ;>· @Û ;>¹ >Ô£Û ;>¾ 7Û ;>Ä 0Û ;>Ê )Û ;>Ð "Û ;>Ô Û ;>Ú Û ;>â >ï=í§Û ;>ë Û ;>ï þÛ ;>ó ùÛ ;>û ðÛ ;>ÿ ëÛ ;> RÛ ;>¢ EÛ ;>·ÍÛ ;>ÉºÛ ;>Ê¸Û ;>Ê·Û ;>ËµÛ ¡;>Ë´Û ¢;>Ì²Û £;>Í°Û ¤;>Î®Û ¥;>Ì¯Û ¦;>Ï«Û §;>ÏªÛ ¨;>Ï©Û ©;=x fÛ ª;= RÛ «;= AÛ ¬;=° )Û ;=Ã Û ®;=Ô Û ¯;=à öÛ °;=ëH]^Û ±;=ìÛ ²;=ì
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| 1564 |
Â;?!?" ¼Û |
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| 1565 |
Ã;@ @ ÁÛ Ä;@* Û Å;@+ Û Æ;@, Û Ç;@- Û È;@. Û É;@^ ]Û Ê;@_ [Û Ë;@` YÛ Ì;@a @
Û Í;@f@ |
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| 1566 |
Û3 Î;@f AAA¥A¦@±@²@³@´@µYÛ |
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| 1567 |
Ï;AA »Û Ð;AK AA¨A¼A±Û Ñ;AT AA©AÁAÛ Ò;A] A£A©AÆAÛ Ó;Ay A½²Û Ô;A AÂ£Û Õ;A AÇÛ Ö;A× ÔÛ ×;AÛ ÏÛ Ø;Aà ÉÛ Ù;Aä ÄÛ Ú;Aè ¿Û Û;Aé A¥@²ÕÛ Ü;Aî @mÛ Ý;A
Û Þ;A Û ß;A Û à;A Û á;A®Û â;AªÛ ã;A¤Û ä;A¥Û å;A¥Û æ;A¥Û ç;A¦Û è;A¦Û |
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| 1568 |
é;@m @vóÛ ê;@u @ÜÛ ë;@v #Û ì;@v "Û í;@v !Û î;@v Û ï;@v Û ð;@v Û ñ;@v Û ò;@v Û ó;@
Û ô;@ Û õ;@ |
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| 1569 |
Û ö;@ Û ÷;@ Û ø;@ Û ù;@ Û ú;@ Û û;@ îÛ ü;@¦ àÛ ý;@² ÓÛ þ;@¾ ÆÛ ÿ;@Ê ¹Û <@Ö +Û <@â Û <@ð Û <@ý Û <@ rÛ
<@ cÛ <@¥ UÛ <@°H`ºÛ <@±åÛ <@±äÛ <@±ãÛ <@±âÛ <@²àÛ <@²ßÛ <@²ÞÛ <@³ÜÛ <@³ÛÛ <@´ÙÛ <@´ØÛ <@´×Û <@µÕÛ <@µÔÛ |
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| 1570 |
<B B éÛ |
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| 1571 |
<C C æÛ |
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| 1572 |
<D D ãÛ |
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| 1573 |
<E E àÛ |
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| 1574 |
<F F ÝÛ |
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| 1575 |
<G G ÚÛ <!f Û <!r Û <!~ Û <! wÛ <! kÛ ¡<! _Û ¢<!² H¨H»KÛ £<!¾ ?Û ¤<!ÉH= )Û ¥<!ËÎÛ ¦<!ËÍÛ §<!ËH§ H½,Û ¨<!ÌÊÛ ©<!ÌHº ¢Û ª<H§ HªHªH«?Û «<H§ HªHªH«>Û ¬<H¨ HªHªH«H«CÛ <Hº H¼Û ®<H» H¼H½ûÛ ¯<H¼ H½Ø " |
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