Rev 3224 Rev 3229
1 # Board: www.mlab.cz S3AN01A 1 # Board: www.mlab.cz S3AN01A
2 # Device: XC3S50AN-4C 2 # Device: XC3S50AN-4C
3 # Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes 3 # Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes
4 # Main Clock (Embedded 100MHz board oscillator) 4 # Main Clock (Embedded 100MHz board oscillator)
5 NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33; 5 NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33;
6 #NET "CLK100MHz" LOC = P125 | IOSTANDARD = LVCMOS33; 6 #NET "CLK100MHz" LOC = P125 | IOSTANDARD = LVCMOS33;
7   7  
8 NET "CLK100MHz" TNM_NET = CLK100MHz; 8 NET "CLK100MHz" TNM_NET = CLK100MHz;
9 TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%; 9 TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;
10   10  
11 NET "LO_CLOCK" TNM_NET = LO_CLOCK; 11 NET "LO_CLOCK" TNM_NET = LO_CLOCK;
12 TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.2 ns HIGH 50%; 12 TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.2 ns HIGH 50%;
13   13  
14 # For DCM connection across the whole chip 14 # For DCM connection across the whole chip
15 NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE; 15 NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;
16 NET "PS2_CLK2" CLOCK_DEDICATED_ROUTE = FALSE; 16 NET "PS2_CLK2" CLOCK_DEDICATED_ROUTE = FALSE;
17   17  
18 # Mode signals 18 # Mode signals
19 NET "M[0]" LOC = P38 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 19 NET "M[0]" LOC = P38 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
20 NET "M[1]" LOC = P37 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M1 and M2 for boot from external SPI Flash Memory 20 NET "M[1]" LOC = P37 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M1 and M2 for boot from external SPI Flash Memory
21 NET "M[2]" LOC = P39 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M2 for boot from internal Flash memory 21 NET "M[2]" LOC = P39 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M2 for boot from internal Flash memory
22 # SPI Flash Vendor Mode Select (for external SPI boot Flash) 22 # SPI Flash Vendor Mode Select (for external SPI boot Flash)
23 NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 23 NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
24 NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 24 NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
25 NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 25 NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
26   26  
27 # DIP Switches (positive signals with pull-down) 27 # DIP Switches (positive signals with pull-down)
28 NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 28 NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
29 NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 29 NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
30 NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 30 NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
31 NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 31 NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
32 NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 32 NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
33 NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 33 NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
34 NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 34 NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
35 NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 35 NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
36   36  
37 # Push Buttons (positive signals with pull-down) 37 # Push Buttons (positive signals with pull-down)
38 NET "PB[0]" LOC = P121 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 38 NET "PB[0]" LOC = P121 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
39 NET "PB[1]" LOC = P120 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 39 NET "PB[1]" LOC = P120 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
40 NET "PB[2]" LOC = P117 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 40 NET "PB[2]" LOC = P117 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
41 NET "PB[3]" LOC = P116 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 41 NET "PB[3]" LOC = P116 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
42   42  
43 # LED String (positive output signals) 43 # LED String (positive output signals)
44 NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33; 44 NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33;
45 NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33; 45 NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33;
46 NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33; 46 NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33;
47 NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33; 47 NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33;
48 NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33; 48 NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33;
49 NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33; 49 NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33;
50 NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33; 50 NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33;
51 NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33; 51 NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33;
52   52  
53 # LED Display Output Signals (negative, multiplexed) 53 # LED Display Output Signals (negative, multiplexed)
54 NET "LD_A_n" LOC = P15 |IOSTANDARD = LVCMOS33; 54 NET "LD_A_n" LOC = P15 |IOSTANDARD = LVCMOS33;
55 NET "LD_B_n" LOC = P30 |IOSTANDARD = LVCMOS33; 55 NET "LD_B_n" LOC = P30 |IOSTANDARD = LVCMOS33;
56 NET "LD_C_n" LOC = P21 |IOSTANDARD = LVCMOS33; 56 NET "LD_C_n" LOC = P21 |IOSTANDARD = LVCMOS33;
57 NET "LD_D_n" LOC = P19 |IOSTANDARD = LVCMOS33; 57 NET "LD_D_n" LOC = P19 |IOSTANDARD = LVCMOS33;
58 NET "LD_E_n" LOC = P18 |IOSTANDARD = LVCMOS33; 58 NET "LD_E_n" LOC = P18 |IOSTANDARD = LVCMOS33;
59 NET "LD_F_n" LOC = P16 |IOSTANDARD = LVCMOS33; 59 NET "LD_F_n" LOC = P16 |IOSTANDARD = LVCMOS33;
60 NET "LD_G_n" LOC = P24 |IOSTANDARD = LVCMOS33; 60 NET "LD_G_n" LOC = P24 |IOSTANDARD = LVCMOS33;
61 NET "LD_DP_n" LOC = P20 |IOSTANDARD = LVCMOS33; 61 NET "LD_DP_n" LOC = P20 |IOSTANDARD = LVCMOS33;
62   62  
63 NET "LD_0_n" LOC = P25 |IOSTANDARD = LVCMOS33; 63 NET "LD_0_n" LOC = P25 |IOSTANDARD = LVCMOS33;
64 NET "LD_1_n" LOC = P31 |IOSTANDARD = LVCMOS33; 64 NET "LD_1_n" LOC = P31 |IOSTANDARD = LVCMOS33;
65 NET "LD_2_n" LOC = P32 |IOSTANDARD = LVCMOS33; 65 NET "LD_2_n" LOC = P32 |IOSTANDARD = LVCMOS33;
66 NET "LD_3_n" LOC = P13 |IOSTANDARD = LVCMOS33; # !!! Connect U1.13 with U1.33 66 NET "LD_3_n" LOC = P13 |IOSTANDARD = LVCMOS33; # !!! Connect U1.13 with U1.33
67 NET "LD_4_n" LOC = P27 |IOSTANDARD = LVCMOS33; 67 NET "LD_4_n" LOC = P27 |IOSTANDARD = LVCMOS33;
68 NET "LD_5_n" LOC = P29 |IOSTANDARD = LVCMOS33; 68 NET "LD_5_n" LOC = P29 |IOSTANDARD = LVCMOS33;
69 NET "LD_6_n" LOC = P28 |IOSTANDARD = LVCMOS33; 69 NET "LD_6_n" LOC = P28 |IOSTANDARD = LVCMOS33;
70 NET "LD_7_n" LOC = P12 |IOSTANDARD = LVCMOS33; # !!! Connect U1.12 with U1.35 70 NET "LD_7_n" LOC = P12 |IOSTANDARD = LVCMOS33; # !!! Connect U1.12 with U1.35
71 # VGA Analog Display Connection (outputs) 71 # VGA Analog Display Connection (outputs)
72 NET "VGA_R[0]" LOC = P3 |IOSTANDARD = LVCMOS33; 72 NET "VGA_R[0]" LOC = P3 |IOSTANDARD = LVCMOS33;
73 NET "VGA_R[1]" LOC = P4 |IOSTANDARD = LVCMOS33; 73 NET "VGA_R[1]" LOC = P4 |IOSTANDARD = LVCMOS33;
74 NET "VGA_G[0]" LOC = P5 |IOSTANDARD = LVCMOS33; 74 NET "VGA_G[0]" LOC = P5 |IOSTANDARD = LVCMOS33;
75 NET "VGA_G[1]" LOC = P6 |IOSTANDARD = LVCMOS33; 75 NET "VGA_G[1]" LOC = P6 |IOSTANDARD = LVCMOS33;
76 NET "VGA_B[0]" LOC = P7 |IOSTANDARD = LVCMOS33; 76 NET "VGA_B[0]" LOC = P7 |IOSTANDARD = LVCMOS33;
77 NET "VGA_B[1]" LOC = P8 |IOSTANDARD = LVCMOS33; 77 NET "VGA_B[1]" LOC = P8 |IOSTANDARD = LVCMOS33;
78 NET "VGA_VS" LOC = P10 |IOSTANDARD = LVCMOS33; 78 NET "VGA_VS" LOC = P10 |IOSTANDARD = LVCMOS33;
79 NET "VGA_HS" LOC = P11 |IOSTANDARD = LVCMOS33; 79 NET "VGA_HS" LOC = P11 |IOSTANDARD = LVCMOS33;
80   80  
81 # Bank 1 Port (input for tests, pull-up) 81 # Bank 1 Port (input for tests, pull-up)
82 NET "B[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 82 NET "B[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
83 NET "B[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 83 NET "B[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
84 NET "B[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 84 NET "B[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
85 NET "B[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 85 NET "B[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
86 NET "B[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 86 NET "B[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
87 NET "B[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 87 NET "B[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
88 NET "B[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 88 NET "B[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
89 NET "B[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 89 NET "B[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
90 NET "B[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 90 NET "B[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
91 NET "B[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 91 NET "B[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
92 NET "B[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 92 NET "B[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
93 NET "B[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 93 NET "B[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
94 NET "B[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 94 NET "B[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
95 NET "B[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 95 NET "B[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
96 NET "B[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 96 NET "B[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
97 NET "B[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 97 NET "B[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
98 NET "B[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 98 NET "B[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
99 NET "B[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 99 NET "B[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
100 NET "B[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 100 NET "B[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
101 NET "B[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 101 NET "B[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
102 NET "B[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 102 NET "B[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
103 NET "B[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 103 NET "B[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
104 NET "B[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 104 NET "B[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
105 NET "B[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 105 NET "B[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
106 NET "B[24]" LOC = P97 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Connected with B[23] on PCB 106 NET "B[24]" LOC = P97 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Connected with B[23] on PCB
107 # PS/2 Bidirectional Port (open collector, J31 and J32) 107 # PS/2 Bidirectional Port (open collector, J31 and J32)
108 #NET "PS2_CLK1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # S3AN01A PCB Design has bug so these pins 108 #NET "PS2_CLK1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # S3AN01A PCB Design has bug so these pins
109 #NET "PS2_DATA1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # will be assinged after PCB redesign 109 #NET "PS2_DATA1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # will be assinged after PCB redesign
110 NET "PS2_CLK2" LOC = P42 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 110 NET "PS2_CLK2" LOC = P42 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
111 NET "PS2_DATA2" LOC = P58 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 111 NET "PS2_DATA2" LOC = P58 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
112   112  
113 # Diferencial Signals on 4 pin header (J7) 113 # Diferencial Signals on 4 pin header (J7)
114 NET "DIF1P" LOC = P110 |IOSTANDARD = LVCMOS33 ; 114 NET "DIF1P" LOC = P110 |IOSTANDARD = LVCMOS33 ;
115 NET "DIF1N" LOC = P111 |IOSTANDARD = LVCMOS33 ; 115 NET "DIF1N" LOC = P111 |IOSTANDARD = LVCMOS33 ;
116 NET "DIF2P" LOC = P112 |IOSTANDARD = LVCMOS33 ; 116 NET "DIF2P" LOC = P112 |IOSTANDARD = LVCMOS33 ;
117 NET "DIF2N" LOC = P113 |IOSTANDARD = LVCMOS33 ; 117 NET "DIF2N" LOC = P113 |IOSTANDARD = LVCMOS33 ;
118   118  
119 # I2C Signals (on connector J30) 119 # I2C Signals (on connector J30)
120 NET "I2C_SCL" LOC = P115 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 120 NET "I2C_SCL" LOC = P115 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
121 NET "I2C_SDA" LOC = P114 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 121 NET "I2C_SDA" LOC = P114 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
122   122  
123 # Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) 123 # Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
124 NET "SD1AP" LOC = P54 |IOSTANDARD = LVPECL_33; 124 NET "SD1AP" LOC = P54 |IOSTANDARD = LVPECL_33;
125 NET "SD1AN" LOC = P55 |IOSTANDARD = LVPECL_33; 125 NET "SD1AN" LOC = P55 |IOSTANDARD = LVPECL_33;
126 NET "SD1BP" LOC = P59 |IOSTANDARD = LVCMOS33 ; 126 NET "SD1BP" LOC = P59 |IOSTANDARD = LVCMOS33 ;
127 NET "SD1BN" LOC = P57 |IOSTANDARD = LVCMOS33 ; 127 NET "SD1BN" LOC = P57 |IOSTANDARD = LVCMOS33 ;
128 NET "SD2AP" LOC = P124 |IOSTANDARD = LVDS_33 ; 128 NET "SD2AP" LOC = P124 |IOSTANDARD = LVDS_33 ;
129 NET "SD2AN" LOC = P126 |IOSTANDARD = LVDS_33 ; 129 NET "SD2AN" LOC = P126 |IOSTANDARD = LVDS_33 ;
130 NET "SD2BP" LOC = P131 |IOSTANDARD = LVCMOS33 ; 130 NET "SD2BP" LOC = P131 |IOSTANDARD = LVCMOS33 ;
131 NET "SD2BN" LOC = P129 |IOSTANDARD = LVCMOS33 ; 131 NET "SD2BN" LOC = P129 |IOSTANDARD = LVCMOS33 ;
132   132  
133 # SPI Memory Interface 133 # SPI Memory Interface
134 NET "SPI_CS_n" LOC = P41 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 134 NET "SPI_CS_n" LOC = P41 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
135 NET "SPI_DO" LOC = P71 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 135 NET "SPI_DO" LOC = P71 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
136 NET "SPI_DI" LOC = P62 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 136 NET "SPI_DI" LOC = P62 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
137 NET "SPI_CLK" LOC = P72 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 137 NET "SPI_CLK" LOC = P72 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
138 NET "SPI_WP_n" LOC = P70 |IOSTANDARD = LVCMOS33 |PULLUP = YES; 138 NET "SPI_WP_n" LOC = P70 |IOSTANDARD = LVCMOS33 |PULLUP = YES;
139   139  
140 # Analog In Out 140 # Analog In Out
141 NET "ANA_OUTD" LOC = P67 |IOSTANDARD = LVCMOS33; 141 NET "ANA_OUTD" LOC = P67 |IOSTANDARD = LVCMOS33;
142 NET "ANA_REFD" LOC = P68 |IOSTANDARD = LVCMOS33; 142 NET "ANA_REFD" LOC = P68 |IOSTANDARD = LVCMOS33;
143 NET "ANA_IND" LOC = P69 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; 143 NET "ANA_IND" LOC = P69 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;
144   144  
145 /* 145 /*
146 # Used Signals (test points) 146 # Used Signals (test points)
147 NET "TPS1" LOC = P53 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; 147 NET "TPS1" LOC = P53 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
148 NET "TPS2" LOC = P125 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; 148 NET "TPS2" LOC = P125 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
149 NET "TPS3" LOC = P127 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; 149 NET "TPS3" LOC = P127 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
150 NET "TPS4" LOC = P130 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; 150 NET "TPS4" LOC = P130 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
151 NET "TPS5" LOC = P141 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; 151 NET "TPS5" LOC = P141 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
152 NET "TPS6" LOC = P123 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; 152 NET "TPS6" LOC = P123 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;
153 NET "XXX1" LOC = P33 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only 153 NET "XXX1" LOC = P33 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only
154 NET "XXX2" LOC = P35 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only 154 NET "XXX2" LOC = P35 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only
155 */ 155 */