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| 1 | //////////////////////////////////////////////////////////////////////////// |
1 | //////////////////////////////////////////////////////////////////////////// |
| 2 | // //// |
2 | // //// |
| 3 | // DEFINICE REGISTRU PROCESORU PIC16F877 //// |
3 | // DEFINICE REGISTRU PROCESORU PIC16F877 //// |
| 4 | // //// |
4 | // //// |
| 5 | //////////////////////////////////////////////////////////////////////////// |
5 | //////////////////////////////////////////////////////////////////////////// |
| 6 | // //// |
6 | // //// |
| 7 | // PEFI S.ICZ a.s 2002 //// |
7 | // PEFI S.ICZ a.s 2002 //// |
| 8 | // //// |
8 | // //// |
| 9 | // Verze 1.0 //// |
9 | // Verze 1.0 //// |
| 10 | // //// |
10 | // //// |
| 11 | //////////////////////////////////////////////////////////////////////////// |
11 | //////////////////////////////////////////////////////////////////////////// |
| 12 | |
12 | |
| 13 | |
13 | |
| 14 | |
14 | |
| 15 | // registry v bance 0 |
15 | // registry v bance 0 |
| 16 | #define INDF 0x00 |
16 | #define INDF 0x00 |
| 17 | #define TMR0 0x01 |
17 | #define TMR0 0x01 |
| 18 | #define PCL 0x02 |
18 | #define PCL 0x02 |
| 19 | #define STATUS 0x03 |
19 | #define STATUS 0x03 |
| 20 | #define FSR 0x04 |
20 | #define FSR 0x04 |
| 21 | #define PORTA 0x05 |
21 | #define PORTA 0x05 |
| 22 | #define PORTB 0x06 |
22 | #define PORTB 0x06 |
| 23 | #define PORTC 0x07 |
23 | #define PORTC 0x07 |
| 24 | #define PORTD 0x08 |
24 | #define PORTD 0x08 |
| 25 | #define PORTE 0x09 |
25 | #define PORTE 0x09 |
| 26 | #define PCLATH 0x0A |
26 | #define PCLATH 0x0A |
| 27 | #define INTCON 0x0B |
27 | #define INTCON 0x0B |
| 28 | #define PIR1 0x0C |
28 | #define PIR1 0x0C |
| 29 | #define PIR2 0x0D |
29 | #define PIR2 0x0D |
| 30 | #define TMR1L 0x0E |
30 | #define TMR1L 0x0E |
| 31 | #define TMR1H 0x0F |
31 | #define TMR1H 0x0F |
| 32 | #define T1CON 0x10 |
32 | #define T1CON 0x10 |
| 33 | #define TMR2 0x11 |
33 | #define TMR2 0x11 |
| 34 | #define T2CON 0x12 |
34 | #define T2CON 0x12 |
| 35 | #define SSPBUF 0x13 |
35 | #define SSPBUF 0x13 |
| 36 | #define SSPCON 0x14 |
36 | #define SSPCON 0x14 |
| 37 | #define CCPR1L 0x15 |
37 | #define CCPR1L 0x15 |
| 38 | #define CCPR1H 0x16 |
38 | #define CCPR1H 0x16 |
| 39 | #define CCP1CON 0x17 |
39 | #define CCP1CON 0x17 |
| 40 | #define RCSTA 0x18 |
40 | #define RCSTA 0x18 |
| 41 | #define TXREG 0x19 |
41 | #define TXREG 0x19 |
| 42 | #define RCREG 0x1A |
42 | #define RCREG 0x1A |
| 43 | #define CCPR2L 0x1B |
43 | #define CCPR2L 0x1B |
| 44 | #define CCPR2H 0x1C |
44 | #define CCPR2H 0x1C |
| 45 | #define CCP2CON 0x1D |
45 | #define CCP2CON 0x1D |
| 46 | #define ADRESH 0x1E |
46 | #define ADRESH 0x1E |
| 47 | #define ADCON0 0x1F |
47 | #define ADCON0 0x1F |
| 48 | |
48 | |
| 49 | // registry v bance 1 |
49 | // registry v bance 1 |
| 50 | #define OPTION 0x81 |
50 | #define OPTION 0x81 |
| 51 | #define TRISA 0x85 |
51 | #define TRISA 0x85 |
| 52 | #define TRISB 0x86 |
52 | #define TRISB 0x86 |
| 53 | #define TRISC 0x87 |
53 | #define TRISC 0x87 |
| 54 | #define TRISD 0x88 |
54 | #define TRISD 0x88 |
| 55 | #define TRISE 0x89 |
55 | #define TRISE 0x89 |
| 56 | #define PIE1 0x8C |
56 | #define PIE1 0x8C |
| 57 | #define PIE2 0x8D |
57 | #define PIE2 0x8D |
| 58 | #define PCON 0x8E |
58 | #define PCON 0x8E |
| 59 | #define SSPCON2 0x91 |
59 | #define SSPCON2 0x91 |
| 60 | #define PR2 0x92 |
60 | #define PR2 0x92 |
| 61 | #define SSPADD 0x93 |
61 | #define SSPADD 0x93 |
| 62 | #define SSPSTAT 0x94 |
62 | #define SSPSTAT 0x94 |
| 63 | #define TXSTA 0x98 |
63 | #define TXSTA 0x98 |
| 64 | #define SPBRG 0x99 |
64 | #define SPBRG 0x99 |
| 65 | #define ADRESL 0x9E |
65 | #define ADRESL 0x9E |
| 66 | #define ADCON1 0x9F |
66 | #define ADCON1 0x9F |
| 67 | |
67 | |
| 68 | // registry v bance 2 |
68 | // registry v bance 2 |
| 69 | #define EEDATA 0x10C |
69 | #define EEDATA 0x10C |
| 70 | #define EEADR 0x10D |
70 | #define EEADR 0x10D |
| 71 | #define EEDATH 0x10E |
71 | #define EEDATH 0x10E |
| 72 | #define EEADRH 0x10F |
72 | #define EEADRH 0x10F |
| 73 | |
73 | |
| 74 | // registry v bance 3 |
74 | // registry v bance 3 |
| 75 | #define EECON1 0x18C |
75 | #define EECON1 0x18C |
| 76 | #define EECON2 0x18D |
76 | #define EECON2 0x18D |
| 77 | |
77 | |
| 78 | // bity v registru STATUS |
78 | // bity v registru STATUS |
| 79 | #define _IRP 7 |
79 | #define _IRP 7 |
| 80 | #define _RP1 6 |
80 | #define _RP1 6 |
| 81 | #define _RP0 5 |
81 | #define _RP0 5 |
| 82 | #define _NOT_TO 4 |
82 | #define _NOT_TO 4 |
| 83 | #define _NOT_PD 3 |
83 | #define _NOT_PD 3 |
| 84 | #define _Z 2 |
84 | #define _Z 2 |
| 85 | #define _DC 1 |
85 | #define _DC 1 |
| 86 | #define _C 0 |
86 | #define _C 0 |
| 87 | |
87 | |
| 88 | // bity v registru INTCON |
88 | // bity v registru INTCON |
| 89 | #define _GIE 7 |
89 | #define _GIE 7 |
| 90 | #define _PEIE 6 |
90 | #define _PEIE 6 |
| 91 | #define _T0IE 5 |
91 | #define _T0IE 5 |
| 92 | #define _INTE 4 |
92 | #define _INTE 4 |
| 93 | #define _RBIE 3 |
93 | #define _RBIE 3 |
| 94 | #define _T0IF 2 |
94 | #define _T0IF 2 |
| 95 | #define _INTF 1 |
95 | #define _INTF 1 |
| 96 | #define _RBIF 0 |
96 | #define _RBIF 0 |
| 97 | |
97 | |
| 98 | // bity v registru PIR1 |
98 | // bity v registru PIR1 |
| 99 | #define _PSPIF 7 |
99 | #define _PSPIF 7 |
| 100 | #define _ADIF 6 |
100 | #define _ADIF 6 |
| 101 | #define _RCIF 5 |
101 | #define _RCIF 5 |
| 102 | #define _TXIF 4 |
102 | #define _TXIF 4 |
| 103 | #define _SSPIF 3 |
103 | #define _SSPIF 3 |
| 104 | #define _CCP1IF 2 |
104 | #define _CCP1IF 2 |
| 105 | #define _TMR2IF 1 |
105 | #define _TMR2IF 1 |
| 106 | #define _TMR1IF 0 |
106 | #define _TMR1IF 0 |
| 107 | |
107 | |
| 108 | // bity v registru PIR2 |
108 | // bity v registru PIR2 |
| 109 | #define _EEIF 4 |
109 | #define _EEIF 4 |
| 110 | #define _BCLIF 3 |
110 | #define _BCLIF 3 |
| 111 | #define _CCP2IF 0 |
111 | #define _CCP2IF 0 |
| 112 | |
112 | |
| 113 | // bity v registru T1CON |
113 | // bity v registru T1CON |
| 114 | #define _T1CKPS1 5 |
114 | #define _T1CKPS1 5 |
| 115 | #define _T1CKPS0 4 |
115 | #define _T1CKPS0 4 |
| 116 | #define _T1OSCEN 3 |
116 | #define _T1OSCEN 3 |
| 117 | #define _NOT_T1SYNC 2 |
117 | #define _NOT_T1SYNC 2 |
| 118 | #define _T1SYNC 2 |
118 | #define _T1SYNC 2 |
| 119 | #define _TMR1CS 1 |
119 | #define _TMR1CS 1 |
| 120 | #define _TMR1ON 0 |
120 | #define _TMR1ON 0 |
| 121 | |
121 | |
| 122 | // bity v registru T2CON |
122 | // bity v registru T2CON |
| 123 | #define _TOUTPS3 6 |
123 | #define _TOUTPS3 6 |
| 124 | #define _TOUTPS2 5 |
124 | #define _TOUTPS2 5 |
| 125 | #define _TOUTPS1 4 |
125 | #define _TOUTPS1 4 |
| 126 | #define _TOUTPS0 3 |
126 | #define _TOUTPS0 3 |
| 127 | #define _TMR2ON 2 |
127 | #define _TMR2ON 2 |
| 128 | #define _T2CKPS1 1 |
128 | #define _T2CKPS1 1 |
| 129 | #define _T2CKPS0 0 |
129 | #define _T2CKPS0 0 |
| 130 | |
130 | |
| 131 | // bity v registru SSPCON |
131 | // bity v registru SSPCON |
| 132 | #define _WCOL 7 |
132 | #define _WCOL 7 |
| 133 | #define _SSPOV 6 |
133 | #define _SSPOV 6 |
| 134 | #define _SSPEN 5 |
134 | #define _SSPEN 5 |
| 135 | #define _CKP 4 |
135 | #define _CKP 4 |
| 136 | #define _SSPM3 3 |
136 | #define _SSPM3 3 |
| 137 | #define _SSPM2 2 |
137 | #define _SSPM2 2 |
| 138 | #define _SSPM1 1 |
138 | #define _SSPM1 1 |
| 139 | #define _SSPM0 0 |
139 | #define _SSPM0 0 |
| 140 | |
140 | |
| 141 | // bity v registru CCP1CON |
141 | // bity v registru CCP1CON |
| 142 | #define _CCP1X 5 |
142 | #define _CCP1X 5 |
| 143 | #define _CCP1Y 4 |
143 | #define _CCP1Y 4 |
| 144 | #define _CCP1M3 3 |
144 | #define _CCP1M3 3 |
| 145 | #define _CCP1M2 2 |
145 | #define _CCP1M2 2 |
| 146 | #define _CCP1M1 1 |
146 | #define _CCP1M1 1 |
| 147 | #define _CCP1M0 0 |
147 | #define _CCP1M0 0 |
| 148 | |
148 | |
| 149 | // bity v registru RCSTA |
149 | // bity v registru RCSTA |
| 150 | #define _SPEN 7 |
150 | #define _SPEN 7 |
| 151 | #define _RX9 6 |
151 | #define _RX9 6 |
| 152 | #define _SREN 5 |
152 | #define _SREN 5 |
| 153 | #define _CREN 4 |
153 | #define _CREN 4 |
| 154 | #define _ADDEN 3 |
154 | #define _ADDEN 3 |
| 155 | #define _FERR 2 |
155 | #define _FERR 2 |
| 156 | #define _OERR 1 |
156 | #define _OERR 1 |
| 157 | #define _RX9D 0 |
157 | #define _RX9D 0 |
| 158 | |
158 | |
| 159 | // bity registru CCP2CON |
159 | // bity registru CCP2CON |
| 160 | #define _CCP2X 5 |
160 | #define _CCP2X 5 |
| 161 | #define _CCP2Y 4 |
161 | #define _CCP2Y 4 |
| 162 | #define _CCP2M3 3 |
162 | #define _CCP2M3 3 |
| 163 | #define _CCP2M2 2 |
163 | #define _CCP2M2 2 |
| 164 | #define _CCP2M1 1 |
164 | #define _CCP2M1 1 |
| 165 | #define _CCP2M0 0 |
165 | #define _CCP2M0 0 |
| 166 | |
166 | |
| 167 | // bity v registru ADCON0 |
167 | // bity v registru ADCON0 |
| 168 | #define _ADCS1 7 |
168 | #define _ADCS1 7 |
| 169 | #define _ADCS0 6 |
169 | #define _ADCS0 6 |
| 170 | #define _CHS2 5 |
170 | #define _CHS2 5 |
| 171 | #define _CHS1 4 |
171 | #define _CHS1 4 |
| 172 | #define _CHS0 3 |
172 | #define _CHS0 3 |
| 173 | #define _GO 2 |
173 | #define _GO 2 |
| 174 | #define _NOT_DONE 2 |
174 | #define _NOT_DONE 2 |
| 175 | #define _GO_DONE 2 |
175 | #define _GO_DONE 2 |
| 176 | #define _ADON 0 |
176 | #define _ADON 0 |
| 177 | |
177 | |
| 178 | // bity v registru OPTION |
178 | // bity v registru OPTION |
| 179 | #define _NOT_RBPU 7 |
179 | #define _NOT_RBPU 7 |
| 180 | #define _INTEDG 6 |
180 | #define _INTEDG 6 |
| 181 | #define _T0CS 5 |
181 | #define _T0CS 5 |
| 182 | #define _T0SE 4 |
182 | #define _T0SE 4 |
| 183 | #define _PSA 3 |
183 | #define _PSA 3 |
| 184 | #define _PS2 2 |
184 | #define _PS2 2 |
| 185 | #define _PS1 1 |
185 | #define _PS1 1 |
| 186 | #define _PS0 0 |
186 | #define _PS0 0 |
| 187 | |
187 | |
| 188 | // bity v registru TRISE |
188 | // bity v registru TRISE |
| 189 | #define _IBF 7 |
189 | #define _IBF 7 |
| 190 | #define _OBF 6 |
190 | #define _OBF 6 |
| 191 | #define _IBOV 5 |
191 | #define _IBOV 5 |
| 192 | #define _PSPMODE 4 |
192 | #define _PSPMODE 4 |
| 193 | #define _TRISE2 2 |
193 | #define _TRISE2 2 |
| 194 | #define _TRISE1 1 |
194 | #define _TRISE1 1 |
| 195 | #define _TRISE0 0 |
195 | #define _TRISE0 0 |
| 196 | |
196 | |
| 197 | // bity v registru PIE1 |
197 | // bity v registru PIE1 |
| 198 | #define _PSPIE 7 |
198 | #define _PSPIE 7 |
| 199 | #define _ADIE 6 |
199 | #define _ADIE 6 |
| 200 | #define _RCIE 5 |
200 | #define _RCIE 5 |
| 201 | #define _TXIE 4 |
201 | #define _TXIE 4 |
| 202 | #define _SSPIE 3 |
202 | #define _SSPIE 3 |
| 203 | #define _CCP1IE 2 |
203 | #define _CCP1IE 2 |
| 204 | #define _TMR2IE 1 |
204 | #define _TMR2IE 1 |
| 205 | #define _TMR1IE 0 |
205 | #define _TMR1IE 0 |
| 206 | |
206 | |
| 207 | // bity v registru PIE2 |
207 | // bity v registru PIE2 |
| 208 | #define _EEIE 4 |
208 | #define _EEIE 4 |
| 209 | #define _BCLIE 3 |
209 | #define _BCLIE 3 |
| 210 | #define _CCP2IE 0 |
210 | #define _CCP2IE 0 |
| 211 | |
211 | |
| 212 | // bity v registru PCON |
212 | // bity v registru PCON |
| 213 | #define _NOT_POR 1 |
213 | #define _NOT_POR 1 |
| 214 | #define _NOT_BOR 0 |
214 | #define _NOT_BOR 0 |
| 215 | |
215 | |
| 216 | // bity v registu |
216 | // bity v registu |
| 217 | #define _GCEN 7 |
217 | #define _GCEN 7 |
| 218 | #define _ACKSTAT 6 |
218 | #define _ACKSTAT 6 |
| 219 | #define _ACKDT 5 |
219 | #define _ACKDT 5 |
| 220 | #define _ACKEN 4 |
220 | #define _ACKEN 4 |
| 221 | #define _RCEN 3 |
221 | #define _RCEN 3 |
| 222 | #define _PEN 2 |
222 | #define _PEN 2 |
| 223 | #define _RSEN 1 |
223 | #define _RSEN 1 |
| 224 | #define _SEN 0 |
224 | #define _SEN 0 |
| 225 | |
225 | |
| 226 | //bity v registru SSPSTAT |
226 | //bity v registru SSPSTAT |
| 227 | #define _SMP 7 |
227 | #define _SMP 7 |
| 228 | #define _CKE 6 |
228 | #define _CKE 6 |
| 229 | #define _D 5 |
229 | #define _D 5 |
| 230 | #define _I2C_DATA 5 |
230 | #define _I2C_DATA 5 |
| 231 | #define _NOT_A 5 |
231 | #define _NOT_A 5 |
| 232 | #define _NOT_ADDRESS 5 |
232 | #define _NOT_ADDRESS 5 |
| 233 | #define _D_A 5 |
233 | #define _D_A 5 |
| 234 | #define _DATA_ADDRESS 5 |
234 | #define _DATA_ADDRESS 5 |
| 235 | #define _P 4 |
235 | #define _P 4 |
| 236 | #define _I2C_STOP 4 |
236 | #define _I2C_STOP 4 |
| 237 | #define _S 3 |
237 | #define _S 3 |
| 238 | #define _I2C_START 3 |
238 | #define _I2C_START 3 |
| 239 | #define _R 2 |
239 | #define _R 2 |
| 240 | #define _I2C_READ 2 |
240 | #define _I2C_READ 2 |
| 241 | #define _NOT_W 2 |
241 | #define _NOT_W 2 |
| 242 | #define _NOT_WRITE 2 |
242 | #define _NOT_WRITE 2 |
| 243 | #define _R_W 2 |
243 | #define _R_W 2 |
| 244 | #define _READ_WRITE 2 |
244 | #define _READ_WRITE 2 |
| 245 | #define _UA 1 |
245 | #define _UA 1 |
| 246 | #define _BF 0 |
246 | #define _BF 0 |
| 247 | |
247 | |
| 248 | // bity v registru TXSTA |
248 | // bity v registru TXSTA |
| 249 | #define CSRC 7 |
249 | #define CSRC 7 |
| 250 | #define TX9 6 |
250 | #define TX9 6 |
| 251 | #define TXEN 5 |
251 | #define TXEN 5 |
| 252 | #define SYNC 4 |
252 | #define SYNC 4 |
| 253 | #define BRGH 2 |
253 | #define BRGH 2 |
| 254 | #define TRMT 2 |
254 | #define TRMT 2 |
| 255 | #define TX9D 0 |
255 | #define TX9D 0 |
| 256 | |
256 | |
| 257 | // bity v registru ADCON1 |
257 | // bity v registru ADCON1 |
| 258 | #define _ADFM 7 |
258 | #define _ADFM 7 |
| 259 | #define _PCFG3 3 |
259 | #define _PCFG3 3 |
| 260 | #define _PCFG2 2 |
260 | #define _PCFG2 2 |
| 261 | #define _PCFG1 2 |
261 | #define _PCFG1 2 |
| 262 | #define _PCFG0 0 |
262 | #define _PCFG0 0 |
| 263 | |
263 | |
| 264 | // bity v registru EECON1 |
264 | // bity v registru EECON1 |
| 265 | #define _EEPGD 7 |
265 | #define _EEPGD 7 |
| 266 | #define _WRERR 3 |
266 | #define _WRERR 3 |
| 267 | #define _WREN 2 |
267 | #define _WREN 2 |
| 268 | #define _WR 1 |
268 | #define _WR 1 |
| 269 | #define _RD 0 |
269 | #define _RD 0 |
| 270 | |
270 | |
| 271 | // masky pro nastaveni orientace I/O pinu |
271 | // masky pro nastaveni orientace I/O pinu |
| 272 | #define PIN0_IN 0x01 |
272 | #define PIN0_IN 0x01 |
| 273 | #define PIN1_IN 0x02 |
273 | #define PIN1_IN 0x02 |
| 274 | #define PIN2_IN 0x04 |
274 | #define PIN2_IN 0x04 |
| 275 | #define PIN3_IN 0x08 |
275 | #define PIN3_IN 0x08 |
| 276 | #define PIN4_IN 0x10 |
276 | #define PIN4_IN 0x10 |
| 277 | #define PIN5_IN 0x20 |
277 | #define PIN5_IN 0x20 |
| 278 | #define PIN6_IN 0x40 |
278 | #define PIN6_IN 0x40 |
| 279 | #define PIN7_IN 0x80 |
279 | #define PIN7_IN 0x80 |
| 280 | |
280 | |
| 281 | #define PIN0_OUT ~0x01 |
281 | #define PIN0_OUT ~0x01 |
| 282 | #define PIN1_OUT ~0x02 |
282 | #define PIN1_OUT ~0x02 |
| 283 | #define PIN2_OUT ~0x04 |
283 | #define PIN2_OUT ~0x04 |
| 284 | #define PIN3_OUT ~0x08 |
284 | #define PIN3_OUT ~0x08 |
| 285 | #define PIN4_OUT ~0x10 |
285 | #define PIN4_OUT ~0x10 |
| 286 | #define PIN5_OUT ~0x20 |
286 | #define PIN5_OUT ~0x20 |
| 287 | #define PIN6_OUT ~0x40 |
287 | #define PIN6_OUT ~0x40 |
| 288 | #define PIN7_OUT ~0x80 |
288 | #define PIN7_OUT ~0x80 |