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-- Company: www.mlab.cz |
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-- Company: www.mlab.cz |
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-- Based on code written by MIHO. |
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-- Based on code written by MIHO. |
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-- |
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-- |
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-- HW Design Name: S3AN01A |
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-- HW Design Name: S3AN01A |
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-- Project Name: gtime |
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-- Project Name: gtime |
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-- Target Devices: XC3S50AN-4 |
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-- Target Devices: XC3S50AN-4 |
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-- Tool versions: ISE 13.3 |
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-- Tool versions: ISE 13.3 |
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-- Description: Time and frequency synchronisation for RDMS01A. |
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-- Description: Time and frequency synchronisation for RDMS01A. |
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-- |
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-- |
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-- Dependencies: CLKGEN01B, GPS01A |
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-- Dependencies: CLKGEN01B, GPS01A |
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-- |
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-- |
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-- Version: $Id: PulseGen.vhd 2534 2012-09-02 13:40:37Z kakl $ |
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-- Version: $Id: PulseGen.vhd 2534 2012-09-02 13:40:37Z kakl $ |
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-- |
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-- |
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---------------------------------------------------------------------------------- |
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---------------------------------------------------------------------------------- |
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|
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|
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library IEEE; |
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library IEEE; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.numeric_std.ALL; |
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use IEEE.numeric_std.ALL; |
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use WORK.PS2_pkg.ALL; |
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|
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|
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|
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library UNISIM; |
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library UNISIM; |
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use UNISIM.vcomponents.all; |
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use UNISIM.vcomponents.all; |
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|
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|
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entity gtime is |
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entity gtime is |
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generic ( |
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generic ( |
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-- Top Value for 100MHz Clock Counter |
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-- Top Value for 100MHz Clock Counter |
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--!!!KAKL MAXCOUNT: integer := 30_000_000; |
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--!!!KAKL MAXCOUNT: integer := 30_000_000; |
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MAXCOUNT: integer := 3_000_000; |
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MAXCOUNT: integer := 3_000_000; |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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); |
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); |
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port ( |
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port ( |
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-- Main Clock |
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-- Main Clock |
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CLK100MHz: in std_logic; |
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CLK100MHz: in std_logic; |
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|
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|
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-- Mode Signals (usualy not used) |
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-- Mode Signals (usualy not used) |
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M: in std_logic_vector(2 downto 0); |
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M: in std_logic_vector(2 downto 0); |
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VS: in std_logic_vector(2 downto 0); |
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VS: in std_logic_vector(2 downto 0); |
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|
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|
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-- Dipswitch Inputs |
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-- Dipswitch Inputs |
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DIPSW: in std_logic_vector(7 downto 0); |
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DIPSW: in std_logic_vector(7 downto 0); |
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|
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|
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-- Push Buttons |
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-- Push Buttons |
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PB: in std_logic_vector(3 downto 0); |
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PB: in std_logic_vector(3 downto 0); |
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|
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|
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-- LED Bar Outputs |
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-- LED Bar Outputs |
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LED: out std_logic_vector(7 downto 0); |
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LED: out std_logic_vector(7 downto 0); |
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|
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|
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-- LED Display (8 digit with 7 segments and ddecimal point) |
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-- LED Display (8 digit with 7 segments and ddecimal point) |
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LD_A_n: out std_logic; |
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LD_A_n: out std_logic; |
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LD_B_n: out std_logic; |
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LD_B_n: out std_logic; |
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LD_C_n: out std_logic; |
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LD_C_n: out std_logic; |
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LD_D_n: out std_logic; |
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LD_D_n: out std_logic; |
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LD_E_n: out std_logic; |
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LD_E_n: out std_logic; |
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LD_F_n: out std_logic; |
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LD_F_n: out std_logic; |
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LD_G_n: out std_logic; |
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LD_G_n: out std_logic; |
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LD_DP_n: out std_logic; |
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LD_DP_n: out std_logic; |
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LD_0_n: out std_logic; |
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LD_0_n: out std_logic; |
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LD_1_n: out std_logic; |
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LD_1_n: out std_logic; |
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LD_2_n: out std_logic; |
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LD_2_n: out std_logic; |
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LD_3_n: out std_logic; |
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LD_3_n: out std_logic; |
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LD_4_n: out std_logic; |
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LD_4_n: out std_logic; |
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LD_5_n: out std_logic; |
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LD_5_n: out std_logic; |
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LD_6_n: out std_logic; |
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LD_6_n: out std_logic; |
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LD_7_n: out std_logic; |
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LD_7_n: out std_logic; |
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|
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|
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-- VGA Video Out Port |
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-- VGA Video Out Port |
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VGA_R: out std_logic_vector(1 downto 0); |
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VGA_R: out std_logic_vector(1 downto 0); |
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VGA_G: out std_logic_vector(1 downto 0); |
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VGA_G: out std_logic_vector(1 downto 0); |
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VGA_B: out std_logic_vector(1 downto 0); |
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VGA_B: out std_logic_vector(1 downto 0); |
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VGA_VS: out std_logic; |
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VGA_VS: out std_logic; |
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VGA_HS: out std_logic; |
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VGA_HS: out std_logic; |
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|
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|
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-- Bank 1 Pins - Inputs for this Test |
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-- Bank 1 Pins - Inputs for this Test |
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B: inout std_logic_vector(24 downto 0); |
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B: inout std_logic_vector(24 downto 0); |
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|
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|
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-- PS/2 Bidirectional Port (open collector, J31 and J32) |
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-- PS/2 Bidirectional Port (open collector, J31 and J32) |
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-- PS2_CLK1: inout std_logic; |
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-- PS2_CLK1: inout std_logic; |
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-- PS2_DATA1: inout std_logic; |
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-- PS2_DATA1: inout std_logic; |
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PS2_CLK2: inout std_logic; |
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PS2_CLK2: inout std_logic; |
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PS2_DATA2: inout std_logic; |
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PS2_DATA2: inout std_logic; |
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|
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|
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-- Diferencial Signals on 4 pin header (J7) |
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-- Diferencial Signals on 4 pin header (J7) |
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DIF1P: inout std_logic; |
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DIF1P: inout std_logic; |
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DIF1N: inout std_logic; |
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DIF1N: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2N: inout std_logic; |
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DIF2N: inout std_logic; |
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|
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|
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|
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|
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-- I2C Signals (on connector J30) |
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-- I2C Signals (on connector J30) |
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I2C_SCL: inout std_logic; |
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I2C_SCL: inout std_logic; |
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I2C_SDA: inout std_logic; |
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I2C_SDA: inout std_logic; |
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|
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|
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-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
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-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
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SD1AP: inout std_logic; |
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SD1AP: inout std_logic; |
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SD1AN: inout std_logic; |
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SD1AN: inout std_logic; |
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SD1BP: inout std_logic; |
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SD1BP: inout std_logic; |
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SD1BN: inout std_logic; |
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SD1BN: inout std_logic; |
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SD2AP: inout std_logic; |
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SD2AP: inout std_logic; |
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SD2AN: inout std_logic; |
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SD2AN: inout std_logic; |
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SD2BP: inout std_logic; |
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SD2BP: inout std_logic; |
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SD2BN: inout std_logic; |
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SD2BN: inout std_logic; |
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|
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|
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-- Analog In Out |
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-- Analog In Out |
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ANA_OUTD: out std_logic; |
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ANA_OUTD: out std_logic; |
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ANA_REFD: out std_logic; |
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ANA_REFD: out std_logic; |
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ANA_IND: in std_logic; |
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ANA_IND: in std_logic; |
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|
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|
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-- SPI Memory Interface |
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-- SPI Memory Interface |
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SPI_CS_n: inout std_logic; |
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SPI_CS_n: inout std_logic; |
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SPI_DO: inout std_logic; |
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SPI_DO: inout std_logic; |
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SPI_DI: inout std_logic; |
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SPI_DI: inout std_logic; |
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SPI_CLK: inout std_logic; |
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SPI_CLK: inout std_logic; |
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SPI_WP_n: inout std_logic |
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SPI_WP_n: inout std_logic |
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); |
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); |
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end entity gtime; |
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end entity gtime; |
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|
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|
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|
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|
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architecture gtime_a of gtime is |
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architecture gtime_a of gtime is |
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|
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|
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function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is |
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function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is |
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variable i : integer:=0; |
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variable i : integer:=0; |
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variable mybcd : std_logic_vector(11 downto 0) := (others => '0'); |
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variable mybcd : std_logic_vector(11 downto 0) := (others => '0'); |
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variable bint : std_logic_vector(7 downto 0) := bin; |
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variable bint : std_logic_vector(7 downto 0) := bin; |
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begin |
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begin |
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for i in 0 to 7 loop -- repeating 8 times. |
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for i in 0 to 7 loop -- repeating 8 times. |
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mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits. |
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mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits. |
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mybcd(0) := bint(7); |
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mybcd(0) := bint(7); |
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bint(7 downto 1) := bint(6 downto 0); |
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bint(7 downto 1) := bint(6 downto 0); |
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bint(0) :='0'; |
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bint(0) :='0'; |
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|
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|
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|
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|
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if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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end if; |
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end if; |
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end loop; |
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end loop; |
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|
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|
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return mybcd; |
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return mybcd; |
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end to_bcd; |
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end to_bcd; |
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|
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|
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|
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|
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-- O1: ____|^^^^^^^|______ |
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|
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-- O2: _________|^^|______ |
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|
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-- t1 t2 |
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|
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-- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz |
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|
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|
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|
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signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2 |
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|
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signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2 |
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|
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signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer |
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|
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signal O1: std_logic := '0'; -- Output 1 |
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|
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signal O2: std_logic := '0'; -- Output 2 |
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|
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signal CTburst: unsigned(15 downto 0) := X"0000"; -- Pulse counter |
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|
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|
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|
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-- LED Demo Signals |
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-- LED Demo Signals |
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-- ---------------- |
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-- ---------------- |
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|
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|
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signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary) |
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signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary) |
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signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) |
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signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) |
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|
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|
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signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) |
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signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) |
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|
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|
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-- LED Display |
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-- LED Display |
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-- ----------- |
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-- ----------- |
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|
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|
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signal Number: std_logic_vector(32 downto 0); -- LED Display Input |
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signal Number: std_logic_vector(32 downto 0); -- LED Display Input |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal Enable: std_logic; |
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signal Enable: std_logic; |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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|
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|
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-- PS/2 Port |
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|
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-- --------- |
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|
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|
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|
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-- Interface Signals |
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|
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signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code |
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|
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signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
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|
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signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock) |
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|
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signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code |
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|
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|
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|
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-- Result |
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|
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signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory) |
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|
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|
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|
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-- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese |
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|
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|
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|
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-- VGA Demo Signals |
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|
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-- ---------------- |
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|
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|
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|
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signal CLK: std_logic; -- Main Clock - global distribution network |
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|
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signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG |
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|
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signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network |
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|
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signal VGA_Blank: boolean; -- Blank |
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|
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signal VGA_Hsync: boolean; -- Horisontal Synchronisation |
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|
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signal VGA_Vsync: boolean; -- Vertical Synchronisation |
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|
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|
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|
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signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter |
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|
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signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter |
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|
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|
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|
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signal PinState: std_logic; -- For IB1 Port Test |
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|
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signal Red: std_logic_vector(1 downto 0); |
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|
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signal Green: std_logic_vector(1 downto 0); |
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|
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signal Blue: std_logic_vector(1 downto 0); |
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|
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|
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|
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-- ADDA |
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|
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signal ADDA_DataIn: std_logic_vector(7 downto 0); |
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|
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|
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|
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|
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|
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signal LO_CLOCK: std_logic; |
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signal LO_CLOCK: std_logic; |
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|
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|
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|
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signal Decko: std_logic; |
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|
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signal Disp: std_logic := '0'; |
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|
172 |
|
218 |
begin |
173 |
begin |
219 |
|
174 |
|
220 |
-- Basic LED Blinking Test |
175 |
-- Basic LED Blinking Test |
221 |
-- ======================= |
176 |
-- ======================= |
222 |
|
177 |
|
223 |
-- LED Bar Counter |
178 |
-- LED Bar Counter |
224 |
--!!!KAKL process (CLK100MHz) |
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|
225 |
process (LO_CLOCK) |
179 |
process (LO_CLOCK) |
226 |
begin |
180 |
begin |
227 |
-- if rising_edge(CLK100MHz) then |
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|
228 |
if DIPSW(0)='1' then |
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|
229 |
if rising_edge(LO_CLOCK) then |
181 |
if rising_edge(LO_CLOCK) then |
230 |
if Counter < MAXCOUNT-1 then |
182 |
if Counter < MAXCOUNT-1 then |
231 |
Counter <= Counter + 1; |
183 |
Counter <= Counter + 1; |
232 |
else |
184 |
else |
233 |
Counter <= (others => '0'); |
185 |
Counter <= (others => '0'); |
234 |
Bar <= Bar + 1; |
186 |
Bar <= Bar + 1; |
235 |
end if; |
187 |
end if; |
236 |
end if; |
188 |
end if; |
237 |
end if; |
- |
|
238 |
end process; |
189 |
end process; |
239 |
|
190 |
|
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|
191 |
process (LO_CLOCK) |
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|
192 |
begin |
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|
193 |
if rising_edge(LO_CLOCK) then |
- |
|
194 |
Decko <= DIPSW(0); |
- |
|
195 |
end if; |
- |
|
196 |
end process; |
- |
|
197 |
|
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|
198 |
|
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|
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process (LO_CLOCK) |
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|
200 |
begin |
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|
201 |
if rising_edge(LO_CLOCK) then |
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|
202 |
if Decko = '1' then |
- |
|
203 |
if Disp = '0' then |
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|
204 |
Number(3 downto 0) <= std_logic_vector(Bar(3 downto 0)); |
- |
|
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Number(7 downto 4) <= std_logic_vector(Bar(7 downto 4)); |
- |
|
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Number(15 downto 8) <= (others=>'0'); |
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|
207 |
Number(19 downto 16) <= (others=>'0'); |
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|
208 |
Number(31 downto 20) <= (others=>'0'); --to_bcd(std_logic_vector(T1)); |
- |
|
209 |
Disp <= '1'; |
- |
|
210 |
end if; |
- |
|
211 |
else |
- |
|
212 |
Disp <= '0'; |
- |
|
213 |
end if; |
- |
|
214 |
end if; |
- |
|
215 |
end process; |
- |
|
216 |
|
240 |
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter |
217 |
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter |
241 |
|
218 |
|
242 |
FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity |
219 |
-- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity |
243 |
|
220 |
|
244 |
-- LED Display (multiplexed) |
221 |
-- LED Display (multiplexed) |
245 |
-- ========================= |
222 |
-- ========================= |
246 |
|
223 |
|
247 |
-- Connect LED Display Output Ports (negative outputs) |
224 |
-- Connect LED Display Output Ports (negative outputs) |
248 |
LD_A_n <= not (Segments(0) and Enable); |
225 |
LD_A_n <= not (Segments(0) and Enable); |
249 |
LD_B_n <= not (Segments(1) and Enable); |
226 |
LD_B_n <= not (Segments(1) and Enable); |
250 |
LD_C_n <= not (Segments(2) and Enable); |
227 |
LD_C_n <= not (Segments(2) and Enable); |
251 |
LD_D_n <= not (Segments(3) and Enable); |
228 |
LD_D_n <= not (Segments(3) and Enable); |
252 |
LD_E_n <= not (Segments(4) and Enable); |
229 |
LD_E_n <= not (Segments(4) and Enable); |
253 |
LD_F_n <= not (Segments(5) and Enable); |
230 |
LD_F_n <= not (Segments(5) and Enable); |
254 |
LD_G_n <= not (Segments(6) and Enable); |
231 |
LD_G_n <= not (Segments(6) and Enable); |
255 |
LD_DP_n <= not (Segments(7) and Enable); |
232 |
LD_DP_n <= not (Segments(7) and Enable); |
256 |
|
233 |
|
257 |
LD_0_n <= not Digits(0); |
234 |
LD_0_n <= not Digits(0); |
258 |
LD_1_n <= not Digits(1); |
235 |
LD_1_n <= not Digits(1); |
259 |
LD_2_n <= not Digits(2); |
236 |
LD_2_n <= not Digits(2); |
260 |
LD_3_n <= not Digits(3); |
237 |
LD_3_n <= not Digits(3); |
261 |
LD_4_n <= not Digits(4); |
238 |
LD_4_n <= not Digits(4); |
262 |
LD_5_n <= not Digits(5); |
239 |
LD_5_n <= not Digits(5); |
263 |
LD_6_n <= not Digits(6); |
240 |
LD_6_n <= not Digits(6); |
264 |
LD_7_n <= not Digits(7); |
241 |
LD_7_n <= not Digits(7); |
265 |
|
242 |
|
266 |
-- Time Multiplex |
243 |
-- Time Multiplex |
267 |
process (CLK100MHz) |
244 |
process (CLK100MHz) |
268 |
begin |
245 |
begin |
269 |
if rising_edge(CLK100MHz) then |
246 |
if rising_edge(CLK100MHz) then |
270 |
if MuxCounter < MUXCOUNT-1 then |
247 |
if MuxCounter < MUXCOUNT-1 then |
271 |
MuxCounter <= MuxCounter + 1; |
248 |
MuxCounter <= MuxCounter + 1; |
272 |
else |
249 |
else |
273 |
MuxCounter <= (others => '0'); |
250 |
MuxCounter <= (others => '0'); |
274 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
251 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
275 |
Enable <= '0'; |
252 |
Enable <= '0'; |
276 |
end if; |
253 |
end if; |
277 |
if MuxCounter > (MUXCOUNT-4) then |
254 |
if MuxCounter > (MUXCOUNT-4) then |
278 |
Enable <= '1'; |
255 |
Enable <= '1'; |
279 |
end if; |
256 |
end if; |
280 |
end if; |
257 |
end if; |
281 |
end process; |
258 |
end process; |
282 |
|
259 |
|
283 |
-- BCD to 7 Segmet Decoder |
260 |
-- HEX to 7 Segmet Decoder |
284 |
-- -- A |
261 |
-- -- A |
285 |
-- | | F B |
262 |
-- | | F B |
286 |
-- -- G |
263 |
-- -- G |
287 |
-- | | E C |
264 |
-- | | E C |
288 |
-- -- D H |
265 |
-- -- D H |
289 |
-- ABCDEFGH |
266 |
-- ABCDEFGH |
290 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
267 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
291 |
"01100000" when Code="0001" else -- Digit 1 |
268 |
"01100000" when Code="0001" else -- Digit 1 |
292 |
"11011010" when Code="0010" else -- Digit 2 |
269 |
"11011010" when Code="0010" else -- Digit 2 |
293 |
"11110010" when Code="0011" else -- Digit 3 |
270 |
"11110010" when Code="0011" else -- Digit 3 |
294 |
"01100110" when Code="0100" else -- Digit 4 |
271 |
"01100110" when Code="0100" else -- Digit 4 |
295 |
"10110110" when Code="0101" else -- Digit 5 |
272 |
"10110110" when Code="0101" else -- Digit 5 |
296 |
"10111110" when Code="0110" else -- Digit 6 |
273 |
"10111110" when Code="0110" else -- Digit 6 |
297 |
"11100000" when Code="0111" else -- Digit 7 |
274 |
"11100000" when Code="0111" else -- Digit 7 |
298 |
"11111110" when Code="1000" else -- Digit 8 |
275 |
"11111110" when Code="1000" else -- Digit 8 |
299 |
"11110110" when Code="1001" else -- Digit 9 |
276 |
"11110110" when Code="1001" else -- Digit 9 |
300 |
"11101110" when Code="1010" else -- Digit A |
277 |
"11101110" when Code="1010" else -- Digit A |
301 |
"00111110" when Code="1011" else -- Digit b |
278 |
"00111110" when Code="1011" else -- Digit b |
302 |
"10011100" when Code="1100" else -- Digit C |
279 |
"10011100" when Code="1100" else -- Digit C |
303 |
"01111010" when Code="1101" else -- Digit d |
280 |
"01111010" when Code="1101" else -- Digit d |
304 |
"10011110" when Code="1110" else -- Digit E |
281 |
"10011110" when Code="1110" else -- Digit E |
305 |
"10001110" when Code="1111" else -- Digit F |
282 |
"10001110" when Code="1111" else -- Digit F |
306 |
"00000000"; |
283 |
"00000000"; |
307 |
|
284 |
|
308 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
285 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
309 |
Number( 7 downto 4) when Digits="00000010" else |
286 |
Number( 7 downto 4) when Digits="00000010" else |
310 |
Number(11 downto 8) when Digits="00000100" else |
287 |
Number(11 downto 8) when Digits="00000100" else |
311 |
Number(15 downto 12) when Digits="00001000" else |
288 |
Number(15 downto 12) when Digits="00001000" else |
312 |
Number(19 downto 16) when Digits="00010000" else |
289 |
Number(19 downto 16) when Digits="00010000" else |
313 |
Number(23 downto 20) when Digits="00100000" else |
290 |
Number(23 downto 20) when Digits="00100000" else |
314 |
Number(27 downto 24) when Digits="01000000" else |
291 |
Number(27 downto 24) when Digits="01000000" else |
315 |
Number(31 downto 28) when Digits="10000000" else |
292 |
Number(31 downto 28) when Digits="10000000" else |
316 |
"0000"; |
293 |
"0000"; |
317 |
|
294 |
|
318 |
-- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0 |
- |
|
319 |
-- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1 |
- |
|
320 |
-- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2 |
- |
|
321 |
-- "11111111"; |
- |
|
322 |
|
- |
|
323 |
-- Number(31 downto 28) <= Key(3 downto 0); |
- |
|
324 |
|
- |
|
325 |
-- Number( 7 downto 0) <= std_logic_vector(BAR); |
- |
|
326 |
-- Number(31 downto 24) <= DIPSW; |
- |
|
327 |
|
- |
|
328 |
-- PS/2 Port |
- |
|
329 |
-- ========= |
- |
|
330 |
|
- |
|
331 |
-- Instantiate PS/2 Keyboard Interface Handler |
- |
|
332 |
PS2_Keyboard: PS2 generic map( |
- |
|
333 |
CLKFREQ => 100_000_000 |
- |
|
334 |
) |
- |
|
335 |
port map( |
- |
|
336 |
-- Main Clock |
- |
|
337 |
Clk => CLK100MHz, |
- |
|
338 |
|
- |
|
339 |
-- PS/2 Port |
- |
|
340 |
PS2_Clk => PS2_CLK2, |
- |
|
341 |
PS2_Data => PS2_DATA2, |
- |
|
342 |
|
- |
|
343 |
-- Result - valid when PS2_Valid |
- |
|
344 |
PS2_Code => PS2_Code, |
- |
|
345 |
PS2_Attribs => PS2_Attribs, |
- |
|
346 |
PS2_Valid => PS2_Valid, |
- |
|
347 |
|
- |
|
348 |
-- Immediate State of Shifts |
- |
|
349 |
PS2_Shifts => PS2_Shifts |
- |
|
350 |
); -- PS2 |
- |
|
351 |
|
295 |
|
352 |
process (CLK100MHz) |
296 |
-- Display on 7seg. |
353 |
begin |
- |
|
354 |
if rising_edge(CLK100MHz) then |
- |
|
355 |
if PS2_Valid and PS2_Attribs(7)='0' then |
297 |
-- Number(3 downto 0) <= (others=>'0'); |
356 |
-- Valid Scan Code with no Break Attribute |
298 |
-- Number(15 downto 4) <= (others=>'1'); --to_bcd(std_logic_vector(T2)); |
357 |
PS2_Result( 7 downto 0) <= PS2_Code; |
- |
|
358 |
PS2_Result(15 downto 8) <= PS2_Attribs; |
299 |
-- Number(19 downto 16) <= (others=>'0'); |
359 |
end if; |
- |
|
360 |
|
- |
|
361 |
if PS2_Valid and PS2_Attribs(7)='0' then |
- |
|
362 |
if PS2_Code = X"74" and T1<2000 then T1<=T1+1; end if; |
300 |
-- Number(31 downto 20) <= (others=>'1'); --to_bcd(std_logic_vector(T1)); |
363 |
if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if; |
- |
|
364 |
if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if; |
- |
|
365 |
if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if; |
- |
|
366 |
CT0<=X"0000"; |
- |
|
367 |
O1<='0'; |
- |
|
368 |
O2<='0'; |
- |
|
369 |
CTburst<=X"0000"; |
- |
|
370 |
end if; |
- |
|
371 |
|
- |
|
372 |
if PB(0)='1' then |
- |
|
373 |
T1<=X"0000"; |
- |
|
374 |
T2<=X"0000"; |
- |
|
375 |
end if; |
- |
|
376 |
|
301 |
|
377 |
if DIPSW(0)='1' then |
- |
|
378 |
if CT0>X"F000" then |
- |
|
379 |
CT0<=X"0000"; |
- |
|
380 |
else |
- |
|
381 |
CT0<=CT0+1; |
- |
|
382 |
end if; |
- |
|
383 |
else |
- |
|
384 |
if CT0>X"0200" then |
- |
|
385 |
CT0<=X"0000"; |
- |
|
386 |
else |
- |
|
387 |
CT0<=CT0+1; |
- |
|
388 |
end if; |
- |
|
389 |
end if; |
- |
|
390 |
|
- |
|
391 |
if CTburst>2000 then |
- |
|
392 |
CTburst<=X"0000"; |
- |
|
393 |
end if; |
- |
|
394 |
|
- |
|
395 |
if (CTburst<1000) or (DIPSW(1)='0') then |
- |
|
396 |
if CT0=X"0000" then |
- |
|
397 |
O1<='1'; |
- |
|
398 |
end if; |
- |
|
399 |
|
- |
|
400 |
if CT0=T1+X"0000" then |
- |
|
401 |
O2<='1'; |
- |
|
402 |
end if; |
- |
|
403 |
end if; |
- |
|
404 |
|
- |
|
405 |
if CT0=T2+T1+X"0000" then |
- |
|
406 |
O1<='0'; |
- |
|
407 |
O2<='0'; |
- |
|
408 |
CTburst<=CTburst+1; |
- |
|
409 |
end if; |
- |
|
410 |
|
- |
|
411 |
end if; |
- |
|
412 |
|
- |
|
413 |
end process; |
- |
|
414 |
|
302 |
|
415 |
-- Display Result on LED |
- |
|
416 |
Number(3 downto 0) <= (others=>'0'); |
- |
|
417 |
Number(15 downto 4) <= to_bcd(std_logic_vector(T2)); |
- |
|
418 |
Number(19 downto 16) <= (others=>'0'); |
- |
|
419 |
Number(31 downto 20) <= to_bcd(std_logic_vector(T1)); |
- |
|
420 |
|
- |
|
421 |
|
- |
|
422 |
-- Test Diferencial In/Outs |
303 |
-- Diferencial In/Outs |
423 |
-- ======================== |
304 |
-- ======================== |
424 |
DIFbuffer1 : IBUFGDS |
305 |
DIFbuffer1 : IBUFGDS |
425 |
generic map ( |
306 |
generic map ( |
426 |
DIFF_TERM => TRUE, -- Differential Termination |
307 |
DIFF_TERM => TRUE, -- Differential Termination |
427 |
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
308 |
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
428 |
-- "0"-"16" |
309 |
-- "0"-"16" |
429 |
IOSTANDARD => "DEFAULT") |
310 |
IOSTANDARD => "DEFAULT") |
430 |
port map ( |
311 |
port map ( |
431 |
I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
312 |
I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
432 |
IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
313 |
IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
433 |
O => LO_CLOCK -- Buffer output |
314 |
O => LO_CLOCK -- Buffer output |
434 |
); |
315 |
); |
435 |
|
316 |
|
436 |
|
317 |
|
437 |
-- Output Signal on SATA Connector |
318 |
-- Output Signal on SATA Connector |
438 |
-- SD1AP <= Bar(0); |
319 |
-- SD1AP <= 'Z'; |
439 |
-- SD1AN <= Bar(1); |
320 |
-- SD1AN <= 'Z'; |
440 |
SD1BP <= 'Z'; |
321 |
SD1BP <= 'Z'; |
441 |
SD1BN <= 'Z'; |
322 |
SD1BN <= 'Z'; |
442 |
|
323 |
|
443 |
-- Input Here via SATA Cable |
324 |
-- Input Here via SATA Cable |
444 |
SD2AP <= 'Z'; |
325 |
SD2AP <= 'Z'; |
445 |
SD2AN <= 'Z'; |
326 |
SD2AN <= 'Z'; |
446 |
SD2BP <= 'Z'; |
327 |
SD2BP <= 'Z'; |
447 |
SD2BN <= 'Z'; |
328 |
SD2BN <= 'Z'; |
448 |
|
329 |
|
449 |
-- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them |
- |
|
450 |
-- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!! |
- |
|
451 |
DIF1P <= O1; |
- |
|
452 |
B(0) <= O1; |
- |
|
453 |
DIF1N <= not O1; |
- |
|
454 |
B(1) <= not O1; |
- |
|
455 |
DIF2P <= O2; |
- |
|
456 |
B(2) <= O2; |
- |
|
457 |
DIF2N <= not O2; |
- |
|
458 |
B(3) <= not O2; |
- |
|
459 |
|
- |
|
460 |
VGA_R(0) <= O1; |
- |
|
461 |
VGA_R(1) <= O2; |
- |
|
462 |
|
330 |
|
463 |
-- Unused Signals |
331 |
-- Unused Signals |
464 |
-- ============== |
332 |
-- ============== |
465 |
|
333 |
|
466 |
-- I2C Signals (on connector J30) |
334 |
-- I2C Signals (on connector J30) |
467 |
I2C_SCL <= 'Z'; |
335 |
I2C_SCL <= 'Z'; |
468 |
I2C_SDA <= 'Z'; |
336 |
I2C_SDA <= 'Z'; |
469 |
|
337 |
|
470 |
-- SPI Memory Interface |
338 |
-- SPI Memory Interface |
471 |
SPI_CS_n <= 'Z'; |
339 |
SPI_CS_n <= 'Z'; |
472 |
SPI_DO <= 'Z'; |
340 |
SPI_DO <= 'Z'; |
473 |
SPI_DI <= 'Z'; |
341 |
SPI_DI <= 'Z'; |
474 |
SPI_CLK <= 'Z'; |
342 |
SPI_CLK <= 'Z'; |
475 |
SPI_WP_n <= 'Z'; |
343 |
SPI_WP_n <= 'Z'; |
476 |
|
344 |
|
477 |
ANA_OUTD <= 'Z'; |
345 |
ANA_OUTD <= 'Z'; |
478 |
ANA_REFD <= 'Z'; |
346 |
ANA_REFD <= 'Z'; |
479 |
|
347 |
|
480 |
VGA_R <= "ZZ"; |
348 |
VGA_R <= "ZZ"; |
481 |
VGA_G <= "ZZ"; |
349 |
VGA_G <= "ZZ"; |
482 |
VGA_B <= "ZZ"; |
350 |
VGA_B <= "ZZ"; |
483 |
VGA_VS <= 'Z'; |
351 |
VGA_VS <= 'Z'; |
484 |
VGA_HS <= 'Z'; |
352 |
VGA_HS <= 'Z'; |
485 |
|
353 |
|
486 |
end architecture gtime_a; |
354 |
end architecture gtime_a; |