Rev 3173 Rev 3176
1 ---------------------------------------------------------------------------------- 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz 2 -- Company: www.mlab.cz
3 -- Based on code written by MIHO. 3 -- Based on code written by MIHO.
4 -- 4 --
5 -- HW Design Name: S3AN01A 5 -- HW Design Name: S3AN01A
6 -- Project Name: gtime 6 -- Project Name: gtime
7 -- Target Devices: XC3S50AN-4 7 -- Target Devices: XC3S50AN-4
8 -- Tool versions: ISE 13.3 8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A. 9 -- Description: Time and frequency synchronisation for RDMS01A.
10 -- 10 --
11 -- Dependencies: CLKGEN01B, GPS01A 11 -- Dependencies: CLKGEN01B, GPS01A
12 -- 12 --
13 -- Version: $Id: gtime.vhd 3173 2013-07-15 21:17:51Z kakl $ 13 -- Version: $Id: gtime.vhd 3176 2013-07-17 14:27:37Z kakl $
14 -- 14 --
15 ---------------------------------------------------------------------------------- 15 ----------------------------------------------------------------------------------
16   16  
17 library IEEE; 17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL; 18 use IEEE.STD_LOGIC_1164.ALL;
19 use IEEE.numeric_std.ALL; 19 use IEEE.numeric_std.ALL;
20   20  
21 library UNISIM; 21 library UNISIM;
22 use UNISIM.vcomponents.all; 22 use UNISIM.vcomponents.all;
23   23  
24 entity gtime is 24 entity gtime is
25 generic ( 25 generic (
26 -- Top Value for 100MHz Clock Counter 26 -- Top Value for 100MHz Clock Counter
27 --!!!KAKL MAXCOUNT: integer := 30_000_000; 27 --!!!KAKL MAXCOUNT: integer := 30_000_000;
28 MAXCOUNT: integer := 10_000; 28 MAXCOUNT: integer := 10_000;
29 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider 29 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
30 ); 30 );
31 port ( 31 port (
32 -- Main Clock 32 -- Main Clock
33 CLK100MHz: in std_logic; 33 CLK100MHz: in std_logic;
34   34  
35 -- Mode Signals (usualy not used) 35 -- Mode Signals (usualy not used)
36 M: in std_logic_vector(2 downto 0); 36 M: in std_logic_vector(2 downto 0);
37 VS: in std_logic_vector(2 downto 0); 37 VS: in std_logic_vector(2 downto 0);
38   38  
39 -- Dipswitch Inputs 39 -- Dipswitch Inputs
40 DIPSW: in std_logic_vector(7 downto 0); 40 DIPSW: in std_logic_vector(7 downto 0);
41   41  
42 -- Push Buttons 42 -- Push Buttons
43 PB: in std_logic_vector(3 downto 0); 43 PB: in std_logic_vector(3 downto 0);
44   44  
45 -- LED Bar Outputs 45 -- LED Bar Outputs
46 LED: out std_logic_vector(7 downto 0); 46 LED: out std_logic_vector(7 downto 0);
47   47  
48 -- LED Display (8 digit with 7 segments and ddecimal point) 48 -- LED Display (8 digit with 7 segments and ddecimal point)
49 LD_A_n: out std_logic; 49 LD_A_n: out std_logic;
50 LD_B_n: out std_logic; 50 LD_B_n: out std_logic;
51 LD_C_n: out std_logic; 51 LD_C_n: out std_logic;
52 LD_D_n: out std_logic; 52 LD_D_n: out std_logic;
53 LD_E_n: out std_logic; 53 LD_E_n: out std_logic;
54 LD_F_n: out std_logic; 54 LD_F_n: out std_logic;
55 LD_G_n: out std_logic; 55 LD_G_n: out std_logic;
56 LD_DP_n: out std_logic; 56 LD_DP_n: out std_logic;
57 LD_0_n: out std_logic; 57 LD_0_n: out std_logic;
58 LD_1_n: out std_logic; 58 LD_1_n: out std_logic;
59 LD_2_n: out std_logic; 59 LD_2_n: out std_logic;
60 LD_3_n: out std_logic; 60 LD_3_n: out std_logic;
61 LD_4_n: out std_logic; 61 LD_4_n: out std_logic;
62 LD_5_n: out std_logic; 62 LD_5_n: out std_logic;
63 LD_6_n: out std_logic; 63 LD_6_n: out std_logic;
64 LD_7_n: out std_logic; 64 LD_7_n: out std_logic;
65   65  
66 -- VGA Video Out Port 66 -- VGA Video Out Port
67 VGA_R: out std_logic_vector(1 downto 0); 67 VGA_R: out std_logic_vector(1 downto 0);
68 VGA_G: out std_logic_vector(1 downto 0); 68 VGA_G: out std_logic_vector(1 downto 0);
69 VGA_B: out std_logic_vector(1 downto 0); 69 VGA_B: out std_logic_vector(1 downto 0);
70 VGA_VS: out std_logic; 70 VGA_VS: out std_logic;
71 VGA_HS: out std_logic; 71 VGA_HS: out std_logic;
72   72  
73 -- Bank 1 Pins - Inputs for this Test 73 -- Bank 1 Pins - Inputs for this Test
74 B: inout std_logic_vector(24 downto 0); 74 B: inout std_logic_vector(24 downto 0);
75 75
76 -- PS/2 Bidirectional Port (open collector, J31 and J32) 76 -- PS/2 Bidirectional Port (open collector, J31 and J32)
77 -- PS2_CLK1: inout std_logic; 77 -- PS2_CLK1: inout std_logic;
78 -- PS2_DATA1: inout std_logic; 78 -- PS2_DATA1: inout std_logic;
79 PS2_CLK2: inout std_logic; 79 PS2_CLK2: inout std_logic;
80 PS2_DATA2: inout std_logic; 80 PS2_DATA2: inout std_logic;
81   81  
82 -- Diferencial Signals on 4 pin header (J7) 82 -- Diferencial Signals on 4 pin header (J7)
83 DIF1P: inout std_logic; 83 DIF1P: inout std_logic;
84 DIF1N: inout std_logic; 84 DIF1N: inout std_logic;
85 DIF2P: inout std_logic; 85 DIF2P: inout std_logic;
86 DIF2N: inout std_logic; 86 DIF2N: inout std_logic;
87 87
88   88  
89 -- I2C Signals (on connector J30) 89 -- I2C Signals (on connector J30)
90 I2C_SCL: inout std_logic; 90 I2C_SCL: inout std_logic;
91 I2C_SDA: inout std_logic; 91 I2C_SDA: inout std_logic;
92   92  
93 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) 93 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
94 SD1AP: inout std_logic; 94 SD1AP: inout std_logic;
95 SD1AN: inout std_logic; 95 SD1AN: inout std_logic;
96 SD1BP: inout std_logic; 96 SD1BP: inout std_logic;
97 SD1BN: inout std_logic; 97 SD1BN: inout std_logic;
98 SD2AP: inout std_logic; 98 SD2AP: inout std_logic;
99 SD2AN: inout std_logic; 99 SD2AN: inout std_logic;
100 SD2BP: inout std_logic; 100 SD2BP: inout std_logic;
101 SD2BN: inout std_logic; 101 SD2BN: inout std_logic;
102   102  
103 -- Analog In Out 103 -- Analog In Out
104 ANA_OUTD: out std_logic; 104 ANA_OUTD: out std_logic;
105 ANA_REFD: out std_logic; 105 ANA_REFD: out std_logic;
106 ANA_IND: in std_logic; 106 ANA_IND: in std_logic;
107   107  
108 -- SPI Memory Interface 108 -- SPI Memory Interface
109 SPI_CS_n: inout std_logic; 109 SPI_CS_n: inout std_logic;
110 SPI_DO: inout std_logic; 110 SPI_DO: inout std_logic;
111 SPI_DI: inout std_logic; 111 SPI_DI: inout std_logic;
112 SPI_CLK: inout std_logic; 112 SPI_CLK: inout std_logic;
113 SPI_WP_n: inout std_logic 113 SPI_WP_n: inout std_logic
114 ); 114 );
115 end entity gtime; 115 end entity gtime;
116   116  
117   117  
118 architecture gtime_a of gtime is 118 architecture gtime_a of gtime is
119   119  
120 function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is 120 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is
121 variable i : integer:=0; 121 variable i : integer:=0;
122 variable mybcd : std_logic_vector(11 downto 0) := (others => '0'); 122 variable mybcd : std_logic_vector(19 downto 0) := (others => '0');
123 variable bint : std_logic_vector(7 downto 0) := bin; 123 variable bint : std_logic_vector(15 downto 0) := bin;
124 begin 124 begin
125 for i in 0 to 7 loop -- repeating 8 times. 125 for i in 0 to 15 loop -- repeating 16 times.
126 mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits. 126 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits.
127 mybcd(0) := bint(7); 127 mybcd(0) := bint(15);
128 bint(7 downto 1) := bint(6 downto 0); 128 bint(15 downto 1) := bint(14 downto 0);
129 bint(0) :='0'; 129 bint(0) :='0';
130   130  
131   131  
132 if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. 132 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
133 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); 133 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
134 end if; 134 end if;
135   135  
136 if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. 136 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
137 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); 137 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
138 end if; 138 end if;
139   139  
140 if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. 140 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
141 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); 141 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
142 end if; 142 end if;
-   143  
-   144 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
-   145 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
-   146 end if;
-   147  
-   148 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
-   149 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
-   150 end if;
-   151  
143 end loop; 152 end loop;
144 153
145 return mybcd; 154 return mybcd;
146 end to_bcd; 155 end to_bcd;
147   156  
148   157  
149 -- LED Demo Signals 158 -- LED Demo Signals
150 -- ---------------- 159 -- ----------------
151   160  
152 signal Counter: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary) 161 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
153 signal CounterMaxcount: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary) 162 signal CounterMaxcount: unsigned(14 downto 0) := "000000000000000"; -- Main Counter 10 kHz, max. 327.67 MHz (binary)
154 signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) 163 signal Bar: unsigned(7 downto 0) := X"00"; -- Register for Bar output (binary)
155   164  
156 signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) -  
157   165  
158 -- LED Display 166 -- LED Display
159 -- ----------- 167 -- -----------
160   168  
161 signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input 169 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
-   170 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
-   171 signal HalfFreq: std_logic_vector(31 downto 0);
162 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider 172 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
163 signal Enable: std_logic; 173 signal Enable: std_logic;
164 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output 174 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
165 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output 175 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
166 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output 176 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
167   177  
168 178
169 signal LO_CLOCK: std_logic; 179 signal LO_CLOCK: std_logic;
170   180  
171 signal Decko: std_logic; 181 signal Decko: std_logic;
172 signal State: unsigned(2 downto 0) := (others => '0'); 182 signal State: unsigned(2 downto 0) := (others => '0');
173 183
174 begin 184 begin
175   185  
176 -- Basic LED Blinking Test -  
177 -- ======================= -  
178   -  
179 -- LED Bar Counter 186 -- Counter
180 process (LO_CLOCK) 187 process (LO_CLOCK)
181 begin 188 begin
182 189
183 if rising_edge(LO_CLOCK) then 190 if rising_edge(LO_CLOCK) then
184 191
185 if (State = 3) or (State = 0) then 192 if (State = 3) or (State = 0) then
186 if Counter < MAXCOUNT-1 then 193 if Counter < MAXCOUNT-1 then
187 Counter <= Counter + 1; 194 Counter <= Counter + 1;
188 else 195 else
189 Counter <= (others => '0'); 196 Counter <= (others => '0');
190 CounterMaxcount <= CounterMaxcount + 1; 197 CounterMaxcount <= CounterMaxcount + 1;
191 end if; 198 end if;
192 end if; 199 end if;
193 if (State = 1) then 200 if (State = 1) then
194 Number(15 downto 0) <= std_logic_vector(Counter(15 downto 0)); 201 Freq(15 downto 0) <= std_logic_vector("00"&Counter);
195 Number(31 downto 16) <= std_logic_vector(CounterMaxcount(15 downto 0)); 202 Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount);
196 end if; 203 end if;
197 if (State = 2) then 204 if (State = 2) then
198 CounterMaxcount <= (others => '0'); 205 CounterMaxcount <= (others => '0');
199 Counter <= (others => '0'); 206 Counter <= (others => '0');
200 end if; 207 end if;
201 end if; 208 end if;
202   209  
203 end process; 210 end process;
204   211  
205   212  
-   213 -- Sampling 1PPS signal
206 process (LO_CLOCK) 214 process (LO_CLOCK)
207 begin 215 begin
208 if rising_edge(LO_CLOCK) then 216 if rising_edge(LO_CLOCK) then
209 Decko <= DIPSW(0); 217 Decko <= B(22);
210 end if; 218 end if;
211 end process; 219 end process;
212   220  
-   221 -- Automata for controling the Counter
213 process (LO_CLOCK) 222 process (LO_CLOCK)
214 begin 223 begin
215 if rising_edge(LO_CLOCK) then 224 if rising_edge(LO_CLOCK) then
216 if (Decko = '1') then 225 if (Decko = '1') then
217 if (State < 3) then 226 if (State < 3) then
218 State <= State + 1; 227 State <= State + 1;
219 end if; 228 end if;
220 else 229 else
221 State <= (others => '0'); 230 State <= (others => '0');
222 end if; 231 end if;
223 end if; 232 end if;
224 end process; 233 end process;
225   234  
226 -  
227 -  
228 LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter 235 -- Coding to BCD for LED Display
229   236  
-   237 -- HalfFreq(14 downto 0) <= Freq(15 downto 1);
-   238 -- HalfFreq(15) <= '0';
-   239 -- HalfFreq(30 downto 16) <= Freq(31 downto 17);
-   240 -- HalfFreq(31) <= '0';
230 -- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity 241 -- Number(15 downto 0) <= to_bcd(HalfFreq(15 downto 0))(15 downto 0);
-   242 -- Number(35 downto 16) <= to_bcd(HalfFreq(31 downto 16))(19 downto 0);
-   243 Number(15 downto 0) <= Freq(15 downto 0);
-   244 Number(31 downto 16) <= Freq(31 downto 16);
-   245  
-   246 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
-   247 LED(6 downto 4) <= (others => '0');
-   248 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
231   249  
232 -- LED Display (multiplexed) 250 -- LED Display (multiplexed)
233 -- ========================= 251 -- =========================
234   252  
235 -- Connect LED Display Output Ports (negative outputs) 253 -- Connect LED Display Output Ports (negative outputs)
236 LD_A_n <= not (Segments(0) and Enable); 254 LD_A_n <= not (Segments(0) and Enable);
237 LD_B_n <= not (Segments(1) and Enable); 255 LD_B_n <= not (Segments(1) and Enable);
238 LD_C_n <= not (Segments(2) and Enable); 256 LD_C_n <= not (Segments(2) and Enable);
239 LD_D_n <= not (Segments(3) and Enable); 257 LD_D_n <= not (Segments(3) and Enable);
240 LD_E_n <= not (Segments(4) and Enable); 258 LD_E_n <= not (Segments(4) and Enable);
241 LD_F_n <= not (Segments(5) and Enable); 259 LD_F_n <= not (Segments(5) and Enable);
242 LD_G_n <= not (Segments(6) and Enable); 260 LD_G_n <= not (Segments(6) and Enable);
243 LD_DP_n <= not (Segments(7) and Enable); 261 LD_DP_n <= not (Segments(7) and Enable);
244   262  
245 LD_0_n <= not Digits(0); 263 LD_0_n <= not Digits(0);
246 LD_1_n <= not Digits(1); 264 LD_1_n <= not Digits(1);
247 LD_2_n <= not Digits(2); 265 LD_2_n <= not Digits(2);
248 LD_3_n <= not Digits(3); 266 LD_3_n <= not Digits(3);
249 LD_4_n <= not Digits(4); 267 LD_4_n <= not Digits(4);
250 LD_5_n <= not Digits(5); 268 LD_5_n <= not Digits(5);
251 LD_6_n <= not Digits(6); 269 LD_6_n <= not Digits(6);
252 LD_7_n <= not Digits(7); 270 LD_7_n <= not Digits(7);
253   271  
254 -- Time Multiplex 272 -- Time Multiplex
255 process (CLK100MHz) 273 process (CLK100MHz)
256 begin 274 begin
257 if rising_edge(CLK100MHz) then 275 if rising_edge(CLK100MHz) then
258 if MuxCounter < MUXCOUNT-1 then 276 if MuxCounter < MUXCOUNT-1 then
259 MuxCounter <= MuxCounter + 1; 277 MuxCounter <= MuxCounter + 1;
260 else 278 else
261 MuxCounter <= (others => '0'); 279 MuxCounter <= (others => '0');
262 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left 280 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
263 Enable <= '0'; 281 Enable <= '0';
264 end if; 282 end if;
265 if MuxCounter > (MUXCOUNT-4) then 283 if MuxCounter > (MUXCOUNT-4) then
266 Enable <= '1'; 284 Enable <= '1';
267 end if; 285 end if;
268 end if; 286 end if;
269 end process; 287 end process;
270   288  
271 -- HEX to 7 Segmet Decoder 289 -- HEX to 7 Segmet Decoder
272 -- -- A 290 -- -- A
273 -- | | F B 291 -- | | F B
274 -- -- G 292 -- -- G
275 -- | | E C 293 -- | | E C
276 -- -- D H 294 -- -- D H
277 -- ABCDEFGH 295 -- ABCDEFGH
278 Segments <= "11111100" when Code="0000" else -- Digit 0 296 Segments <= "11111100" when Code="0000" else -- Digit 0
279 "01100000" when Code="0001" else -- Digit 1 297 "01100000" when Code="0001" else -- Digit 1
280 "11011010" when Code="0010" else -- Digit 2 298 "11011010" when Code="0010" else -- Digit 2
281 "11110010" when Code="0011" else -- Digit 3 299 "11110010" when Code="0011" else -- Digit 3
282 "01100110" when Code="0100" else -- Digit 4 300 "01100110" when Code="0100" else -- Digit 4
283 "10110110" when Code="0101" else -- Digit 5 301 "10110110" when Code="0101" else -- Digit 5
284 "10111110" when Code="0110" else -- Digit 6 302 "10111110" when Code="0110" else -- Digit 6
285 "11100000" when Code="0111" else -- Digit 7 303 "11100000" when Code="0111" else -- Digit 7
286 "11111110" when Code="1000" else -- Digit 8 304 "11111110" when Code="1000" else -- Digit 8
287 "11110110" when Code="1001" else -- Digit 9 305 "11110110" when Code="1001" else -- Digit 9
288 "11101110" when Code="1010" else -- Digit A 306 "11101110" when Code="1010" else -- Digit A
289 "00111110" when Code="1011" else -- Digit b 307 "00111110" when Code="1011" else -- Digit b
290 "10011100" when Code="1100" else -- Digit C 308 "10011100" when Code="1100" else -- Digit C
291 "01111010" when Code="1101" else -- Digit d 309 "01111010" when Code="1101" else -- Digit d
292 "10011110" when Code="1110" else -- Digit E 310 "10011110" when Code="1110" else -- Digit E
293 "10001110" when Code="1111" else -- Digit F 311 "10001110" when Code="1111" else -- Digit F
294 "00000000"; 312 "00000000";
295   313  
296 Code <= Number( 3 downto 0) when Digits="00000001" else 314 Code <= Number( 3 downto 0) when Digits="00000001" else
297 Number( 7 downto 4) when Digits="00000010" else 315 Number( 7 downto 4) when Digits="00000010" else
298 Number(11 downto 8) when Digits="00000100" else 316 Number(11 downto 8) when Digits="00000100" else
299 Number(15 downto 12) when Digits="00001000" else 317 Number(15 downto 12) when Digits="00001000" else
300 Number(19 downto 16) when Digits="00010000" else 318 Number(19 downto 16) when Digits="00010000" else
301 Number(23 downto 20) when Digits="00100000" else 319 Number(23 downto 20) when Digits="00100000" else
302 Number(27 downto 24) when Digits="01000000" else 320 Number(27 downto 24) when Digits="01000000" else
303 Number(31 downto 28) when Digits="10000000" else 321 Number(31 downto 28) when Digits="10000000" else
304 "0000"; 322 "0000";
305   323  
306   324  
307 -- Display on 7seg. 325 -- Display on 7seg.
308 -- Number(3 downto 0) <= (others=>'0'); 326 -- Number(3 downto 0) <= (others=>'0');
309 -- Number(15 downto 4) <= (others=>'1'); --to_bcd(std_logic_vector(T2)); 327 -- Number(15 downto 4) <= (others=>'1'); --to_bcd(std_logic_vector(T2));
310 -- Number(19 downto 16) <= (others=>'0'); 328 -- Number(19 downto 16) <= (others=>'0');
311 -- Number(31 downto 20) <= (others=>'1'); --to_bcd(std_logic_vector(T1)); 329 -- Number(31 downto 20) <= (others=>'1'); --to_bcd(std_logic_vector(T1));
312 330
313   331  
314 -- Diferencial In/Outs 332 -- Diferencial In/Outs
315 -- ======================== 333 -- ========================
316 DIFbuffer1 : IBUFGDS 334 DIFbuffer1 : IBUFGDS
317 generic map ( 335 generic map (
318 DIFF_TERM => FALSE, -- Differential Termination 336 DIFF_TERM => FALSE, -- Differential Termination
319 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 337 IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer,
320 -- "0"-"16" 338 -- "0"-"16"
321 IOSTANDARD => "DEFAULT") 339 IOSTANDARD => "DEFAULT")
322 port map ( 340 port map (
323 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) 341 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
324 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) 342 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
325 O => LO_CLOCK -- Buffer output 343 O => LO_CLOCK -- Buffer output
326 ); 344 );
327   345  
-   346 OBUFDS_inst : OBUFDS
-   347 generic map (
-   348 IOSTANDARD => "DEFAULT")
-   349 port map (
-   350 O => SD2AP, -- Diff_p output (connect directly to top-level port)
-   351 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
-   352 I => LO_CLOCK -- Buffer input
-   353 );
328 354
329 -- Output Signal on SATA Connector 355 -- Output Signal on SATA Connector
330 -- SD1AP <= 'Z'; 356 -- SD1AP <= 'Z';
331 -- SD1AN <= 'Z'; 357 -- SD1AN <= 'Z';
332 SD1BP <= 'Z'; 358 SD1BP <= 'Z';
333 SD1BN <= 'Z'; 359 SD1BN <= 'Z';
334   360  
335 -- Input Here via SATA Cable 361 -- Input Here via SATA Cable
336 SD2AP <= 'Z'; 362 -- SD2AP <= 'Z';
337 SD2AN <= 'Z'; 363 -- SD2AN <= 'Z';
338 SD2BP <= 'Z'; 364 SD2BP <= 'Z';
339 SD2BN <= 'Z'; 365 SD2BN <= 'Z';
340   366  
341   367  
342 -- Unused Signals 368 -- Unused Signals
343 -- ============== 369 -- ==============
344   370  
345 -- I2C Signals (on connector J30) 371 -- I2C Signals (on connector J30)
346 I2C_SCL <= 'Z'; 372 I2C_SCL <= 'Z';
347 I2C_SDA <= 'Z'; 373 I2C_SDA <= 'Z';
348   374  
349 -- SPI Memory Interface 375 -- SPI Memory Interface
350 SPI_CS_n <= 'Z'; 376 SPI_CS_n <= 'Z';
351 SPI_DO <= 'Z'; 377 SPI_DO <= 'Z';
352 SPI_DI <= 'Z'; 378 SPI_DI <= 'Z';
353 SPI_CLK <= 'Z'; 379 SPI_CLK <= 'Z';
354 SPI_WP_n <= 'Z'; 380 SPI_WP_n <= 'Z';
355   381  
356 ANA_OUTD <= 'Z'; 382 ANA_OUTD <= 'Z';
357 ANA_REFD <= 'Z'; 383 ANA_REFD <= 'Z';
358   384  
359 VGA_R <= "ZZ"; 385 VGA_R <= "ZZ";
360 VGA_G <= "ZZ"; 386 VGA_G <= "ZZ";
361 VGA_B <= "ZZ"; 387 VGA_B <= "ZZ";
362 VGA_VS <= 'Z'; 388 VGA_VS <= 'Z';
363 VGA_HS <= 'Z'; 389 VGA_HS <= 'Z';
364   390  
365 end architecture gtime_a; 391 end architecture gtime_a;