Rev 3176 Rev 3177
1 ---------------------------------------------------------------------------------- 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz 2 -- Company: www.mlab.cz
3 -- Based on code written by MIHO. 3 -- Based on code written by MIHO.
4 -- 4 --
5 -- HW Design Name: S3AN01A 5 -- HW Design Name: S3AN01A
6 -- Project Name: gtime 6 -- Project Name: gtime
7 -- Target Devices: XC3S50AN-4 7 -- Target Devices: XC3S50AN-4
8 -- Tool versions: ISE 13.3 8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A. 9 -- Description: Time and frequency synchronisation for RDMS01A.
10 -- 10 --
11 -- Dependencies: CLKGEN01B, GPS01A 11 -- Dependencies: CLKGEN01B, GPS01A
12 -- 12 --
13 -- Version: $Id: gtime.vhd 3176 2013-07-17 14:27:37Z kakl $ 13 -- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $
14 -- 14 --
15 ---------------------------------------------------------------------------------- 15 ----------------------------------------------------------------------------------
16   16  
17 library IEEE; 17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL; 18 use IEEE.STD_LOGIC_1164.ALL;
19 use IEEE.numeric_std.ALL; 19 use IEEE.numeric_std.ALL;
20   20  
21 library UNISIM; 21 library UNISIM;
22 use UNISIM.vcomponents.all; 22 use UNISIM.vcomponents.all;
23   23  
24 entity gtime is 24 entity gtime is
25 generic ( 25 generic (
26 -- Top Value for 100MHz Clock Counter 26 -- Top Value for 100MHz Clock Counter
27 --!!!KAKL MAXCOUNT: integer := 30_000_000; 27 --!!!KAKL MAXCOUNT: integer := 30_000_000;
28 MAXCOUNT: integer := 10_000; 28 MAXCOUNT: integer := 10_000;
29 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider 29 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
30 ); 30 );
31 port ( 31 port (
32 -- Main Clock 32 -- Main Clock
33 CLK100MHz: in std_logic; 33 CLK100MHz: in std_logic;
34   34  
35 -- Mode Signals (usualy not used) 35 -- Mode Signals (usualy not used)
36 M: in std_logic_vector(2 downto 0); 36 M: in std_logic_vector(2 downto 0);
37 VS: in std_logic_vector(2 downto 0); 37 VS: in std_logic_vector(2 downto 0);
38   38  
39 -- Dipswitch Inputs 39 -- Dipswitch Inputs
40 DIPSW: in std_logic_vector(7 downto 0); 40 DIPSW: in std_logic_vector(7 downto 0);
41   41  
42 -- Push Buttons 42 -- Push Buttons
43 PB: in std_logic_vector(3 downto 0); 43 PB: in std_logic_vector(3 downto 0);
44   44  
45 -- LED Bar Outputs 45 -- LED Bar Outputs
46 LED: out std_logic_vector(7 downto 0); 46 LED: out std_logic_vector(7 downto 0);
47   47  
48 -- LED Display (8 digit with 7 segments and ddecimal point) 48 -- LED Display (8 digit with 7 segments and ddecimal point)
49 LD_A_n: out std_logic; 49 LD_A_n: out std_logic;
50 LD_B_n: out std_logic; 50 LD_B_n: out std_logic;
51 LD_C_n: out std_logic; 51 LD_C_n: out std_logic;
52 LD_D_n: out std_logic; 52 LD_D_n: out std_logic;
53 LD_E_n: out std_logic; 53 LD_E_n: out std_logic;
54 LD_F_n: out std_logic; 54 LD_F_n: out std_logic;
55 LD_G_n: out std_logic; 55 LD_G_n: out std_logic;
56 LD_DP_n: out std_logic; 56 LD_DP_n: out std_logic;
57 LD_0_n: out std_logic; 57 LD_0_n: out std_logic;
58 LD_1_n: out std_logic; 58 LD_1_n: out std_logic;
59 LD_2_n: out std_logic; 59 LD_2_n: out std_logic;
60 LD_3_n: out std_logic; 60 LD_3_n: out std_logic;
61 LD_4_n: out std_logic; 61 LD_4_n: out std_logic;
62 LD_5_n: out std_logic; 62 LD_5_n: out std_logic;
63 LD_6_n: out std_logic; 63 LD_6_n: out std_logic;
64 LD_7_n: out std_logic; 64 LD_7_n: out std_logic;
65   65  
66 -- VGA Video Out Port 66 -- VGA Video Out Port
67 VGA_R: out std_logic_vector(1 downto 0); 67 VGA_R: out std_logic_vector(1 downto 0);
68 VGA_G: out std_logic_vector(1 downto 0); 68 VGA_G: out std_logic_vector(1 downto 0);
69 VGA_B: out std_logic_vector(1 downto 0); 69 VGA_B: out std_logic_vector(1 downto 0);
70 VGA_VS: out std_logic; 70 VGA_VS: out std_logic;
71 VGA_HS: out std_logic; 71 VGA_HS: out std_logic;
72   72  
73 -- Bank 1 Pins - Inputs for this Test 73 -- Bank 1 Pins - Inputs for this Test
74 B: inout std_logic_vector(24 downto 0); 74 B: inout std_logic_vector(24 downto 0);
75 75
76 -- PS/2 Bidirectional Port (open collector, J31 and J32) 76 -- PS/2 Bidirectional Port (open collector, J31 and J32)
77 -- PS2_CLK1: inout std_logic; 77 -- PS2_CLK1: inout std_logic;
78 -- PS2_DATA1: inout std_logic; 78 -- PS2_DATA1: inout std_logic;
79 PS2_CLK2: inout std_logic; 79 PS2_CLK2: inout std_logic;
80 PS2_DATA2: inout std_logic; 80 PS2_DATA2: inout std_logic;
81   81  
82 -- Diferencial Signals on 4 pin header (J7) 82 -- Diferencial Signals on 4 pin header (J7)
83 DIF1P: inout std_logic; 83 DIF1P: inout std_logic;
84 DIF1N: inout std_logic; 84 DIF1N: inout std_logic;
85 DIF2P: inout std_logic; 85 DIF2P: inout std_logic;
86 DIF2N: inout std_logic; 86 DIF2N: inout std_logic;
87 87
88   88  
89 -- I2C Signals (on connector J30) 89 -- I2C Signals (on connector J30)
90 I2C_SCL: inout std_logic; 90 I2C_SCL: inout std_logic;
91 I2C_SDA: inout std_logic; 91 I2C_SDA: inout std_logic;
92   92  
93 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) 93 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
94 SD1AP: inout std_logic; 94 SD1AP: inout std_logic;
95 SD1AN: inout std_logic; 95 SD1AN: inout std_logic;
96 SD1BP: inout std_logic; 96 SD1BP: inout std_logic;
97 SD1BN: inout std_logic; 97 SD1BN: inout std_logic;
98 SD2AP: inout std_logic; 98 SD2AP: inout std_logic;
99 SD2AN: inout std_logic; 99 SD2AN: inout std_logic;
100 SD2BP: inout std_logic; 100 SD2BP: inout std_logic;
101 SD2BN: inout std_logic; 101 SD2BN: inout std_logic;
102   102  
103 -- Analog In Out 103 -- Analog In Out
104 ANA_OUTD: out std_logic; 104 ANA_OUTD: out std_logic;
105 ANA_REFD: out std_logic; 105 ANA_REFD: out std_logic;
106 ANA_IND: in std_logic; 106 ANA_IND: in std_logic;
107   107  
108 -- SPI Memory Interface 108 -- SPI Memory Interface
109 SPI_CS_n: inout std_logic; 109 SPI_CS_n: inout std_logic;
110 SPI_DO: inout std_logic; 110 SPI_DO: inout std_logic;
111 SPI_DI: inout std_logic; 111 SPI_DI: inout std_logic;
112 SPI_CLK: inout std_logic; 112 SPI_CLK: inout std_logic;
113 SPI_WP_n: inout std_logic 113 SPI_WP_n: inout std_logic
114 ); 114 );
115 end entity gtime; 115 end entity gtime;
116   116  
117   117  
118 architecture gtime_a of gtime is 118 architecture gtime_a of gtime is
119   119  
120 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is 120 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is
121 variable i : integer:=0; 121 variable i : integer:=0;
122 variable mybcd : std_logic_vector(19 downto 0) := (others => '0'); 122 variable mybcd : std_logic_vector(19 downto 0) := (others => '0');
123 variable bint : std_logic_vector(15 downto 0) := bin; 123 variable bint : std_logic_vector(15 downto 0) := bin;
124 begin 124 begin
125 for i in 0 to 15 loop -- repeating 16 times. 125 for i in 0 to 15 loop -- repeating 16 times.
126 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits. 126 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits.
127 mybcd(0) := bint(15); 127 mybcd(0) := bint(15);
128 bint(15 downto 1) := bint(14 downto 0); 128 bint(15 downto 1) := bint(14 downto 0);
129 bint(0) :='0'; 129 bint(0) :='0';
130   130  
131   131  
132 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. 132 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
133 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); 133 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
134 end if; 134 end if;
135   135  
136 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. 136 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
137 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); 137 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
138 end if; 138 end if;
139   139  
140 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. 140 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
141 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); 141 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
142 end if; 142 end if;
143   143  
144 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4. 144 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
145 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3); 145 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
146 end if; 146 end if;
147   147  
148 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4. 148 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
149 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3); 149 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
150 end if; 150 end if;
151   151  
152 end loop; 152 end loop;
153 153
154 return mybcd; 154 return mybcd;
155 end to_bcd; 155 end to_bcd;
156   156  
157   157  
158 -- LED Demo Signals 158 -- LED Demo Signals
159 -- ---------------- 159 -- ----------------
160   160  
161 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary) 161 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
162 signal CounterMaxcount: unsigned(14 downto 0) := "000000000000000"; -- Main Counter 10 kHz, max. 327.67 MHz (binary) 162 signal CounterMaxcount: unsigned(14 downto 0) := "000000000000000"; -- Main Counter 10 kHz, max. 327.67 MHz (binary)
163 signal Bar: unsigned(7 downto 0) := X"00"; -- Register for Bar output (binary) 163 signal Bar: unsigned(7 downto 0) := X"00"; -- Register for Bar output (binary)
164   164  
165   165  
166 -- LED Display 166 -- LED Display
167 -- ----------- 167 -- -----------
168   168  
-   169 signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
169 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input 170 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
170 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency 171 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
171 signal HalfFreq: std_logic_vector(31 downto 0); 172 signal HalfFreq: std_logic_vector(31 downto 0);
172 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider 173 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
173 signal Enable: std_logic; 174 signal Enable: std_logic;
174 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output 175 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
175 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output 176 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
176 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output 177 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
177   178  
178 179
179 signal LO_CLOCK: std_logic; 180 signal LO_CLOCK: std_logic;
-   181 signal EXT_CLOCK: std_logic;
180   182  
181 signal Decko: std_logic; 183 signal Decko: std_logic;
182 signal State: unsigned(2 downto 0) := (others => '0'); 184 signal State: unsigned(2 downto 0) := (others => '0');
183 185
184 begin 186 begin
185   187  
-   188 process (EXT_CLOCK)
-   189 begin
-   190
-   191 if rising_edge(EXT_CLOCK) then
-   192 LO_CLOCK <= not LO_CLOCK;
-   193 end if;
-   194 end process;
-   195  
-   196  
186 -- Counter 197 -- Counter
187 process (LO_CLOCK) 198 process (LO_CLOCK)
188 begin 199 begin
189 200
190 if rising_edge(LO_CLOCK) then 201 if rising_edge(LO_CLOCK) then
191 202
192 if (State = 3) or (State = 0) then 203 if (State = 3) or (State = 0) then
193 if Counter < MAXCOUNT-1 then 204 if Counter < MAXCOUNT-1 then
194 Counter <= Counter + 1; 205 Counter <= Counter + 1;
195 else 206 else
196 Counter <= (others => '0'); 207 Counter <= (others => '0');
197 CounterMaxcount <= CounterMaxcount + 1; 208 CounterMaxcount <= CounterMaxcount + 1;
198 end if; 209 end if;
199 end if; 210 end if;
200 if (State = 1) then 211 if (State = 1) then
201 Freq(15 downto 0) <= std_logic_vector("00"&Counter); 212 Freq(15 downto 0) <= std_logic_vector("00"&Counter);
202 Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount); 213 Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount);
203 end if; 214 end if;
204 if (State = 2) then 215 if (State = 2) then
205 CounterMaxcount <= (others => '0'); 216 CounterMaxcount <= (others => '0');
206 Counter <= (others => '0'); 217 Counter <= (others => '0');
207 end if; 218 end if;
208 end if; 219 end if;
209   220  
210 end process; 221 end process;
211   222  
212   223  
213 -- Sampling 1PPS signal 224 -- Sampling 1PPS signal
214 process (LO_CLOCK) 225 process (LO_CLOCK)
215 begin 226 begin
216 if rising_edge(LO_CLOCK) then 227 if rising_edge(LO_CLOCK) then
217 Decko <= B(22); 228 Decko <= B(22);
218 end if; 229 end if;
219 end process; 230 end process;
220   231  
221 -- Automata for controling the Counter 232 -- Automata for controling the Counter
222 process (LO_CLOCK) 233 process (LO_CLOCK)
223 begin 234 begin
224 if rising_edge(LO_CLOCK) then 235 if rising_edge(LO_CLOCK) then
225 if (Decko = '1') then 236 if (Decko = '1') then
226 if (State < 3) then 237 if (State < 3) then
227 State <= State + 1; 238 State <= State + 1;
228 end if; 239 end if;
229 else 240 else
230 State <= (others => '0'); 241 State <= (others => '0');
231 end if; 242 end if;
232 end if; 243 end if;
233 end process; 244 end process;
234   245  
235 -- Coding to BCD for LED Display 246 -- Coding to BCD for LED Display
236   247  
237 -- HalfFreq(14 downto 0) <= Freq(15 downto 1); -  
238 -- HalfFreq(15) <= '0'; 248 process (Decko)
239 -- HalfFreq(30 downto 16) <= Freq(31 downto 17); 249 begin
240 -- HalfFreq(31) <= '0'; 250 if falling_edge(Decko) then
241 -- Number(15 downto 0) <= to_bcd(HalfFreq(15 downto 0))(15 downto 0); 251 NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0);
242 -- Number(35 downto 16) <= to_bcd(HalfFreq(31 downto 16))(19 downto 0); 252 NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0);
243 Number(15 downto 0) <= Freq(15 downto 0); 253 end if;
244 Number(31 downto 16) <= Freq(31 downto 16); 254 end process;
245   255  
-   256 Number(35 downto 0) <= NumberPom(35 downto 0);
-   257
246 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar 258 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
247 LED(6 downto 4) <= (others => '0'); 259 LED(6 downto 4) <= (others => '0');
248 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar 260 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
249   261  
250 -- LED Display (multiplexed) 262 -- LED Display (multiplexed)
251 -- ========================= 263 -- =========================
252   264  
253 -- Connect LED Display Output Ports (negative outputs) 265 -- Connect LED Display Output Ports (negative outputs)
254 LD_A_n <= not (Segments(0) and Enable); 266 LD_A_n <= not (Segments(0) and Enable);
255 LD_B_n <= not (Segments(1) and Enable); 267 LD_B_n <= not (Segments(1) and Enable);
256 LD_C_n <= not (Segments(2) and Enable); 268 LD_C_n <= not (Segments(2) and Enable);
257 LD_D_n <= not (Segments(3) and Enable); 269 LD_D_n <= not (Segments(3) and Enable);
258 LD_E_n <= not (Segments(4) and Enable); 270 LD_E_n <= not (Segments(4) and Enable);
259 LD_F_n <= not (Segments(5) and Enable); 271 LD_F_n <= not (Segments(5) and Enable);
260 LD_G_n <= not (Segments(6) and Enable); 272 LD_G_n <= not (Segments(6) and Enable);
261 LD_DP_n <= not (Segments(7) and Enable); 273 LD_DP_n <= not (Segments(7) and Enable);
262   274  
263 LD_0_n <= not Digits(0); 275 LD_0_n <= not Digits(0);
264 LD_1_n <= not Digits(1); 276 LD_1_n <= not Digits(1);
265 LD_2_n <= not Digits(2); 277 LD_2_n <= not Digits(2);
266 LD_3_n <= not Digits(3); 278 LD_3_n <= not Digits(3);
267 LD_4_n <= not Digits(4); 279 LD_4_n <= not Digits(4);
268 LD_5_n <= not Digits(5); 280 LD_5_n <= not Digits(5);
269 LD_6_n <= not Digits(6); 281 LD_6_n <= not Digits(6);
270 LD_7_n <= not Digits(7); 282 LD_7_n <= not Digits(7);
271   283  
272 -- Time Multiplex 284 -- Time Multiplex
273 process (CLK100MHz) 285 process (CLK100MHz)
274 begin 286 begin
275 if rising_edge(CLK100MHz) then 287 if rising_edge(CLK100MHz) then
276 if MuxCounter < MUXCOUNT-1 then 288 if MuxCounter < MUXCOUNT-1 then
277 MuxCounter <= MuxCounter + 1; 289 MuxCounter <= MuxCounter + 1;
278 else 290 else
279 MuxCounter <= (others => '0'); 291 MuxCounter <= (others => '0');
280 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left 292 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
281 Enable <= '0'; 293 Enable <= '0';
282 end if; 294 end if;
283 if MuxCounter > (MUXCOUNT-4) then 295 if MuxCounter > (MUXCOUNT-4) then
284 Enable <= '1'; 296 Enable <= '1';
285 end if; 297 end if;
286 end if; 298 end if;
287 end process; 299 end process;
288   300  
289 -- HEX to 7 Segmet Decoder 301 -- HEX to 7 Segmet Decoder
290 -- -- A 302 -- -- A
291 -- | | F B 303 -- | | F B
292 -- -- G 304 -- -- G
293 -- | | E C 305 -- | | E C
294 -- -- D H 306 -- -- D H
295 -- ABCDEFGH 307 -- ABCDEFGH
296 Segments <= "11111100" when Code="0000" else -- Digit 0 308 Segments <= "11111100" when Code="0000" else -- Digit 0
297 "01100000" when Code="0001" else -- Digit 1 309 "01100000" when Code="0001" else -- Digit 1
298 "11011010" when Code="0010" else -- Digit 2 310 "11011010" when Code="0010" else -- Digit 2
299 "11110010" when Code="0011" else -- Digit 3 311 "11110010" when Code="0011" else -- Digit 3
300 "01100110" when Code="0100" else -- Digit 4 312 "01100110" when Code="0100" else -- Digit 4
301 "10110110" when Code="0101" else -- Digit 5 313 "10110110" when Code="0101" else -- Digit 5
302 "10111110" when Code="0110" else -- Digit 6 314 "10111110" when Code="0110" else -- Digit 6
303 "11100000" when Code="0111" else -- Digit 7 315 "11100000" when Code="0111" else -- Digit 7
304 "11111110" when Code="1000" else -- Digit 8 316 "11111110" when Code="1000" else -- Digit 8
305 "11110110" when Code="1001" else -- Digit 9 317 "11110110" when Code="1001" else -- Digit 9
306 "11101110" when Code="1010" else -- Digit A 318 "11101110" when Code="1010" else -- Digit A
307 "00111110" when Code="1011" else -- Digit b 319 "00111110" when Code="1011" else -- Digit b
308 "10011100" when Code="1100" else -- Digit C 320 "10011100" when Code="1100" else -- Digit C
309 "01111010" when Code="1101" else -- Digit d 321 "01111010" when Code="1101" else -- Digit d
310 "10011110" when Code="1110" else -- Digit E 322 "10011110" when Code="1110" else -- Digit E
311 "10001110" when Code="1111" else -- Digit F 323 "10001110" when Code="1111" else -- Digit F
312 "00000000"; 324 "00000000";
313   325  
314 Code <= Number( 3 downto 0) when Digits="00000001" else 326 Code <= Number( 3 downto 0) when Digits="00000001" else
315 Number( 7 downto 4) when Digits="00000010" else 327 Number( 7 downto 4) when Digits="00000010" else
316 Number(11 downto 8) when Digits="00000100" else 328 Number(11 downto 8) when Digits="00000100" else
317 Number(15 downto 12) when Digits="00001000" else 329 Number(15 downto 12) when Digits="00001000" else
318 Number(19 downto 16) when Digits="00010000" else 330 Number(19 downto 16) when Digits="00010000" else
319 Number(23 downto 20) when Digits="00100000" else 331 Number(23 downto 20) when Digits="00100000" else
320 Number(27 downto 24) when Digits="01000000" else 332 Number(27 downto 24) when Digits="01000000" else
321 Number(31 downto 28) when Digits="10000000" else 333 Number(31 downto 28) when Digits="10000000" else
322 "0000"; 334 "0000";
323   335  
324   336  
325 -- Display on 7seg. -  
326 -- Number(3 downto 0) <= (others=>'0'); -  
327 -- Number(15 downto 4) <= (others=>'1'); --to_bcd(std_logic_vector(T2)); -  
328 -- Number(19 downto 16) <= (others=>'0'); -  
329 -- Number(31 downto 20) <= (others=>'1'); --to_bcd(std_logic_vector(T1)); -  
330 -  
331   337  
332 -- Diferencial In/Outs 338 -- Diferencial In/Outs
333 -- ======================== 339 -- ========================
334 DIFbuffer1 : IBUFGDS 340 DIFbuffer1 : IBUFGDS
335 generic map ( 341 generic map (
336 DIFF_TERM => FALSE, -- Differential Termination 342 DIFF_TERM => FALSE, -- Differential Termination
337 IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer, 343 IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer,
338 -- "0"-"16" 344 -- "0"-"16"
339 IOSTANDARD => "DEFAULT") 345 IOSTANDARD => "DEFAULT")
340 port map ( 346 port map (
341 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) 347 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
342 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) 348 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
343 O => LO_CLOCK -- Buffer output 349 O => EXT_CLOCK -- Buffer output
344 ); 350 );
345   351  
346 OBUFDS_inst : OBUFDS 352 OBUFDS_inst : OBUFDS
347 generic map ( 353 generic map (
348 IOSTANDARD => "DEFAULT") 354 IOSTANDARD => "DEFAULT")
349 port map ( 355 port map (
350 O => SD2AP, -- Diff_p output (connect directly to top-level port) 356 O => SD2AP, -- Diff_p output (connect directly to top-level port)
351 OB => SD2AN, -- Diff_n output (connect directly to top-level port) 357 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
352 I => LO_CLOCK -- Buffer input 358 I => EXT_CLOCK -- Buffer input
353 ); 359 );
354 360
355 -- Output Signal on SATA Connector 361 -- Output Signal on SATA Connector
356 -- SD1AP <= 'Z'; 362 -- SD1AP <= 'Z';
357 -- SD1AN <= 'Z'; 363 -- SD1AN <= 'Z';
358 SD1BP <= 'Z'; 364 SD1BP <= 'Z';
359 SD1BN <= 'Z'; 365 SD1BN <= 'Z';
360   366  
361 -- Input Here via SATA Cable 367 -- Input Here via SATA Cable
362 -- SD2AP <= 'Z'; 368 -- SD2AP <= 'Z';
363 -- SD2AN <= 'Z'; 369 -- SD2AN <= 'Z';
364 SD2BP <= 'Z'; 370 SD2BP <= 'Z';
365 SD2BN <= 'Z'; 371 SD2BN <= 'Z';
366   372  
367   373  
368 -- Unused Signals 374 -- Unused Signals
369 -- ============== 375 -- ==============
370   376  
371 -- I2C Signals (on connector J30) 377 -- I2C Signals (on connector J30)
372 I2C_SCL <= 'Z'; 378 I2C_SCL <= 'Z';
373 I2C_SDA <= 'Z'; 379 I2C_SDA <= 'Z';
374   380  
375 -- SPI Memory Interface 381 -- SPI Memory Interface
376 SPI_CS_n <= 'Z'; 382 SPI_CS_n <= 'Z';
377 SPI_DO <= 'Z'; 383 SPI_DO <= 'Z';
378 SPI_DI <= 'Z'; 384 SPI_DI <= 'Z';
379 SPI_CLK <= 'Z'; 385 SPI_CLK <= 'Z';
380 SPI_WP_n <= 'Z'; 386 SPI_WP_n <= 'Z';
381   387  
382 ANA_OUTD <= 'Z'; 388 ANA_OUTD <= 'Z';
383 ANA_REFD <= 'Z'; 389 ANA_REFD <= 'Z';
384   390  
385 VGA_R <= "ZZ"; 391 VGA_R <= "ZZ";
386 VGA_G <= "ZZ"; 392 VGA_G <= "ZZ";
387 VGA_B <= "ZZ"; 393 VGA_B <= "ZZ";
388 VGA_VS <= 'Z'; 394 VGA_VS <= 'Z';
389 VGA_HS <= 'Z'; 395 VGA_HS <= 'Z';
390   396  
391 end architecture gtime_a; 397 end architecture gtime_a;