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-- Company: www.mlab.cz |
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-- Company: www.mlab.cz |
3 |
-- Based on code written by MIHO. |
3 |
-- Based on code written by MIHO. |
4 |
-- |
4 |
-- |
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-- HW Design Name: S3AN01A |
5 |
-- HW Design Name: S3AN01A |
6 |
-- Project Name: gtime |
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-- Project Name: gtime |
7 |
-- Target Devices: XC3S50AN-4 |
7 |
-- Target Devices: XC3S50AN-4 |
8 |
-- Tool versions: ISE 13.3 |
8 |
-- Tool versions: ISE 13.3 |
9 |
-- Description: Time and frequency synchronisation for RDMS01A. |
9 |
-- Description: Time and frequency synchronisation for RDMS01A. |
10 |
-- |
10 |
-- |
11 |
-- Dependencies: CLKGEN01B, GPS01A |
11 |
-- Dependencies: CLKGEN01B, GPS01A |
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-- |
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-- |
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-- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $ |
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-- Version: $Id: gtime.vhd 3219 2013-07-25 09:13:34Z kakl $ |
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-- |
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-- |
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---------------------------------------------------------------------------------- |
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---------------------------------------------------------------------------------- |
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|
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|
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library IEEE; |
17 |
library IEEE; |
18 |
use IEEE.STD_LOGIC_1164.ALL; |
18 |
use IEEE.STD_LOGIC_1164.ALL; |
19 |
use IEEE.numeric_std.ALL; |
19 |
use IEEE.numeric_std.ALL; |
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|
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|
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library UNISIM; |
21 |
library UNISIM; |
22 |
use UNISIM.vcomponents.all; |
22 |
use UNISIM.vcomponents.all; |
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|
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|
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entity gtime is |
24 |
entity gtime is |
25 |
generic ( |
25 |
generic ( |
26 |
-- Top Value for 100MHz Clock Counter |
26 |
-- Top Value for 100MHz Clock Counter |
27 |
--!!!KAKL MAXCOUNT: integer := 30_000_000; |
- |
|
28 |
MAXCOUNT: integer := 10_000; |
27 |
MAXCOUNT: integer := 10_000; -- Maximum for the first counter |
29 |
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
28 |
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
30 |
); |
29 |
); |
31 |
port ( |
30 |
port ( |
32 |
-- Main Clock |
31 |
-- Clock on PCB |
33 |
CLK100MHz: in std_logic; |
32 |
CLK100MHz: in std_logic; |
34 |
|
33 |
|
35 |
-- Mode Signals (usualy not used) |
34 |
-- Mode Signals (usualy not used) |
36 |
M: in std_logic_vector(2 downto 0); |
35 |
M: in std_logic_vector(2 downto 0); |
37 |
VS: in std_logic_vector(2 downto 0); |
36 |
VS: in std_logic_vector(2 downto 0); |
38 |
|
37 |
|
39 |
-- Dipswitch Inputs |
38 |
-- Dipswitch Inputs |
40 |
DIPSW: in std_logic_vector(7 downto 0); |
39 |
DIPSW: in std_logic_vector(7 downto 0); |
41 |
|
40 |
|
42 |
-- Push Buttons |
41 |
-- Push Buttons |
43 |
PB: in std_logic_vector(3 downto 0); |
42 |
PB: in std_logic_vector(3 downto 0); |
44 |
|
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|
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-- LED Bar Outputs |
44 |
-- LED Bar Outputs |
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LED: out std_logic_vector(7 downto 0); |
45 |
LED: out std_logic_vector(7 downto 0); |
47 |
|
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|
48 |
-- LED Display (8 digit with 7 segments and ddecimal point) |
47 |
-- LED Display (8 digit with 7 segments and ddecimal point) |
49 |
LD_A_n: out std_logic; |
48 |
LD_A_n: out std_logic; |
50 |
LD_B_n: out std_logic; |
49 |
LD_B_n: out std_logic; |
51 |
LD_C_n: out std_logic; |
50 |
LD_C_n: out std_logic; |
52 |
LD_D_n: out std_logic; |
51 |
LD_D_n: out std_logic; |
53 |
LD_E_n: out std_logic; |
52 |
LD_E_n: out std_logic; |
54 |
LD_F_n: out std_logic; |
53 |
LD_F_n: out std_logic; |
55 |
LD_G_n: out std_logic; |
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LD_G_n: out std_logic; |
56 |
LD_DP_n: out std_logic; |
55 |
LD_DP_n: out std_logic; |
57 |
LD_0_n: out std_logic; |
56 |
LD_0_n: out std_logic; |
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LD_1_n: out std_logic; |
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LD_1_n: out std_logic; |
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LD_2_n: out std_logic; |
58 |
LD_2_n: out std_logic; |
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LD_3_n: out std_logic; |
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LD_3_n: out std_logic; |
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LD_4_n: out std_logic; |
60 |
LD_4_n: out std_logic; |
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LD_5_n: out std_logic; |
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LD_5_n: out std_logic; |
63 |
LD_6_n: out std_logic; |
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LD_6_n: out std_logic; |
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LD_7_n: out std_logic; |
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LD_7_n: out std_logic; |
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|
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|
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-- VGA Video Out Port |
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-- VGA Video Out Port |
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VGA_R: out std_logic_vector(1 downto 0); |
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VGA_R: out std_logic_vector(1 downto 0); |
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VGA_G: out std_logic_vector(1 downto 0); |
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VGA_G: out std_logic_vector(1 downto 0); |
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VGA_B: out std_logic_vector(1 downto 0); |
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VGA_B: out std_logic_vector(1 downto 0); |
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VGA_VS: out std_logic; |
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VGA_VS: out std_logic; |
71 |
VGA_HS: out std_logic; |
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VGA_HS: out std_logic; |
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|
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|
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-- Bank 1 Pins - Inputs for this Test |
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-- Bank 1 Pins - Inputs for this Test |
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B: inout std_logic_vector(24 downto 0); |
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B: inout std_logic_vector(24 downto 0); |
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|
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|
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-- PS/2 Bidirectional Port (open collector, J31 and J32) |
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-- PS/2 Bidirectional Port (open collector, J31 and J32) |
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-- PS2_CLK1: inout std_logic; |
76 |
PS2_CLK1: inout std_logic; |
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-- PS2_DATA1: inout std_logic; |
77 |
PS2_DATA1: inout std_logic; |
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PS2_CLK2: inout std_logic; |
78 |
PS2_CLK2: inout std_logic; |
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PS2_DATA2: inout std_logic; |
79 |
PS2_DATA2: inout std_logic; |
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|
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|
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-- Diferencial Signals on 4 pin header (J7) |
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-- Diferencial Signals on 4 pin header (J7) |
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DIF1P: inout std_logic; |
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DIF1P: inout std_logic; |
84 |
DIF1N: inout std_logic; |
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DIF1N: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2N: inout std_logic; |
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DIF2N: inout std_logic; |
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|
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|
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|
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|
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-- I2C Signals (on connector J30) |
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-- I2C Signals (on connector J30) |
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I2C_SCL: inout std_logic; |
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I2C_SCL: inout std_logic; |
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I2C_SDA: inout std_logic; |
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I2C_SDA: inout std_logic; |
92 |
|
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|
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-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
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-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
94 |
SD1AP: inout std_logic; |
93 |
SD1AP: inout std_logic; |
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SD1AN: inout std_logic; |
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SD1AN: inout std_logic; |
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SD1BP: inout std_logic; |
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SD1BP: inout std_logic; |
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SD1BN: inout std_logic; |
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SD1BN: inout std_logic; |
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SD2AP: inout std_logic; |
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SD2AP: inout std_logic; |
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SD2AN: inout std_logic; |
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SD2AN: inout std_logic; |
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SD2BP: inout std_logic; |
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SD2BP: inout std_logic; |
101 |
SD2BN: inout std_logic; |
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SD2BN: inout std_logic; |
102 |
|
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|
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-- Analog In Out |
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-- Analog In Out |
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ANA_OUTD: out std_logic; |
103 |
ANA_OUTD: out std_logic; |
105 |
ANA_REFD: out std_logic; |
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ANA_REFD: out std_logic; |
106 |
ANA_IND: in std_logic; |
105 |
ANA_IND: in std_logic; |
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|
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|
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-- SPI Memory Interface |
107 |
-- SPI Memory Interface |
109 |
SPI_CS_n: inout std_logic; |
108 |
SPI_CS_n: inout std_logic; |
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SPI_DO: inout std_logic; |
109 |
SPI_DO: inout std_logic; |
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SPI_DI: inout std_logic; |
110 |
SPI_DI: inout std_logic; |
112 |
SPI_CLK: inout std_logic; |
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SPI_CLK: inout std_logic; |
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SPI_WP_n: inout std_logic |
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SPI_WP_n: inout std_logic |
114 |
); |
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); |
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end entity gtime; |
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end entity gtime; |
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|
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|
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|
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|
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architecture gtime_a of gtime is |
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architecture gtime_a of gtime is |
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|
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|
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function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is |
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|
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variable i : integer:=0; |
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|
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variable mybcd : std_logic_vector(19 downto 0) := (others => '0'); |
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|
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variable bint : std_logic_vector(15 downto 0) := bin; |
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|
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begin |
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|
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for i in 0 to 15 loop -- repeating 16 times. |
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|
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mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits. |
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|
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mybcd(0) := bint(15); |
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|
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bint(15 downto 1) := bint(14 downto 0); |
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|
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bint(0) :='0'; |
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|
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|
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|
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|
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|
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if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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|
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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|
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end if; |
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|
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|
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|
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if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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|
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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|
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end if; |
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|
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|
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|
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if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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|
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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|
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end if; |
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|
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|
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|
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if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4. |
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|
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mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3); |
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|
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end if; |
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|
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|
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|
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if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4. |
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|
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mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3); |
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|
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end if; |
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|
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|
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|
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end loop; |
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|
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|
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|
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return mybcd; |
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|
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end to_bcd; |
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|
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|
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|
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|
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|
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-- LED Demo Signals |
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-- Counter |
159 |
-- ---------------- |
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-- ---------------- |
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|
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|
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signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary) |
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signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 2 Hz (binary) |
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signal CounterMaxcount: unsigned(14 downto 0) := "000000000000000"; -- Main Counter 10 kHz, max. 327.67 MHz (binary) |
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|
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signal Bar: unsigned(7 downto 0) := X"00"; -- Register for Bar output (binary) |
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|
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|
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|
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|
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|
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-- LED Display |
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-- LED Display |
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-- ----------- |
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-- ----------- |
168 |
|
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|
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signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input |
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|
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signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input |
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signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input |
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signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency |
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signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency |
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signal HalfFreq: std_logic_vector(31 downto 0); |
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|
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal Enable: std_logic; |
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signal Enable: std_logic; |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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|
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|
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|
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|
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signal LO_CLOCK: std_logic; |
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-- signal LO_CLOCK: std_logic; -- Frequency divided by 2 |
181 |
signal EXT_CLOCK: std_logic; |
139 |
signal EXT_CLOCK: std_logic; -- Input Frequency |
182 |
|
140 |
|
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signal Decko: std_logic; |
141 |
signal Decko: std_logic; -- D flip-flop |
184 |
signal State: unsigned(2 downto 0) := (others => '0'); |
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signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata |
185 |
|
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|
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begin |
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signal SCLK: std_logic; |
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|
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signal SCLK2: std_logic; |
187 |
|
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|
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process (EXT_CLOCK) |
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|
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begin |
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|
190 |
|
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|
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if rising_edge(EXT_CLOCK) then |
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|
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LO_CLOCK <= not LO_CLOCK; |
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|
193 |
end if; |
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|
194 |
end process; |
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|
195 |
|
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|
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|
148 |
begin |
196 |
|
149 |
|
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-- Counter |
150 |
-- Counter |
198 |
process (LO_CLOCK) |
151 |
process (EXT_CLOCK) |
199 |
begin |
152 |
begin |
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|
153 |
|
201 |
if rising_edge(LO_CLOCK) then |
154 |
if rising_edge(EXT_CLOCK) then |
202 |
|
155 |
|
203 |
if (State = 3) or (State = 0) then |
156 |
if (State = 2) or (State = 0) then |
204 |
if Counter < MAXCOUNT-1 then |
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|
205 |
Counter <= Counter + 1; |
157 |
Counter <= Counter + 1; |
206 |
else |
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|
207 |
Counter <= (others => '0'); |
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|
208 |
CounterMaxcount <= CounterMaxcount + 1; |
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|
209 |
end if; |
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|
210 |
end if; |
158 |
end if; |
211 |
if (State = 1) then |
159 |
if (State = 1) then |
212 |
Freq(15 downto 0) <= std_logic_vector("00"&Counter); |
160 |
Freq(31 downto 0) <= std_logic_vector(Counter); |
213 |
Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount); |
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|
214 |
end if; |
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|
215 |
if (State = 2) then |
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|
216 |
CounterMaxcount <= (others => '0'); |
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|
217 |
Counter <= (others => '0'); |
161 |
Counter <= (others => '0'); |
218 |
end if; |
162 |
end if; |
219 |
end if; |
163 |
end if; |
220 |
|
164 |
|
221 |
end process; |
165 |
end process; |
222 |
|
166 |
|
223 |
|
167 |
|
224 |
-- Sampling 1PPS signal |
168 |
-- Sampling 1PPS signal |
225 |
process (LO_CLOCK) |
169 |
process (EXT_CLOCK) |
226 |
begin |
170 |
begin |
227 |
if rising_edge(LO_CLOCK) then |
171 |
if rising_edge(EXT_CLOCK) then |
228 |
Decko <= B(22); |
172 |
Decko <= B(22); |
229 |
end if; |
173 |
end if; |
230 |
end process; |
174 |
end process; |
231 |
|
175 |
|
232 |
-- Automata for controling the Counter |
176 |
-- Automata for controlling the Counter |
233 |
process (LO_CLOCK) |
177 |
process (EXT_CLOCK) |
234 |
begin |
178 |
begin |
235 |
if rising_edge(LO_CLOCK) then |
179 |
if rising_edge(EXT_CLOCK) then |
236 |
if (Decko = '1') then |
180 |
if (Decko = '1') then |
237 |
if (State < 3) then |
181 |
if (State < 2) then |
238 |
State <= State + 1; |
182 |
State <= State + 1; |
239 |
end if; |
183 |
end if; |
240 |
else |
184 |
else |
241 |
State <= (others => '0'); |
185 |
State <= (others => '0'); |
242 |
end if; |
186 |
end if; |
243 |
end if; |
187 |
end if; |
244 |
end process; |
188 |
end process; |
245 |
|
189 |
|
246 |
-- Coding to BCD for LED Display |
190 |
-- Coding to BCD for LED Display |
247 |
|
191 |
|
248 |
process (Decko) |
192 |
process (Decko) |
249 |
begin |
193 |
begin |
250 |
if falling_edge(Decko) then |
194 |
if Decko = '0' then |
251 |
NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0); |
195 |
LED(6) <= '1'; |
- |
|
196 |
else |
252 |
NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0); |
197 |
LED(6) <= '0'; |
253 |
end if; |
198 |
end if; |
254 |
end process; |
199 |
end process; |
255 |
|
- |
|
256 |
Number(35 downto 0) <= NumberPom(35 downto 0); |
- |
|
257 |
|
200 |
|
- |
|
201 |
SCLK <= B(0); |
- |
|
202 |
-- SCLK2 <= ((not Decko) OR SCLK); |
- |
|
203 |
|
- |
|
204 |
process (Decko,SCLK) |
- |
|
205 |
begin |
- |
|
206 |
if (Decko = '0') then |
- |
|
207 |
Number(31 downto 0) <= Freq(31 downto 0); |
- |
|
208 |
else |
- |
|
209 |
if rising_edge(SCLK) then |
- |
|
210 |
Number(30 downto 0) <= Number(31 downto 1); |
- |
|
211 |
end if; |
- |
|
212 |
end if; |
- |
|
213 |
end process; |
- |
|
214 |
|
- |
|
215 |
B(1) <= Number(0); |
- |
|
216 |
B(2) <= Decko; |
- |
|
217 |
|
258 |
LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar |
218 |
LED(7) <= Decko; -- Display 1PPS pulse on LEDbar |
259 |
LED(6 downto 4) <= (others => '0'); |
219 |
LED(5 downto 0) <= (others => '0'); |
260 |
LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar |
- |
|
261 |
|
220 |
|
262 |
-- LED Display (multiplexed) |
221 |
-- LED Display (multiplexed) |
263 |
-- ========================= |
222 |
-- ========================= |
264 |
|
223 |
|
265 |
-- Connect LED Display Output Ports (negative outputs) |
224 |
-- Connect LED Display Output Ports (negative outputs) |
266 |
LD_A_n <= not (Segments(0) and Enable); |
225 |
LD_A_n <= not (Segments(0) and Enable); |
267 |
LD_B_n <= not (Segments(1) and Enable); |
226 |
LD_B_n <= not (Segments(1) and Enable); |
268 |
LD_C_n <= not (Segments(2) and Enable); |
227 |
LD_C_n <= not (Segments(2) and Enable); |
269 |
LD_D_n <= not (Segments(3) and Enable); |
228 |
LD_D_n <= not (Segments(3) and Enable); |
270 |
LD_E_n <= not (Segments(4) and Enable); |
229 |
LD_E_n <= not (Segments(4) and Enable); |
271 |
LD_F_n <= not (Segments(5) and Enable); |
230 |
LD_F_n <= not (Segments(5) and Enable); |
272 |
LD_G_n <= not (Segments(6) and Enable); |
231 |
LD_G_n <= not (Segments(6) and Enable); |
273 |
LD_DP_n <= not (Segments(7) and Enable); |
232 |
LD_DP_n <= not (Segments(7) and Enable); |
274 |
|
233 |
|
275 |
LD_0_n <= not Digits(0); |
234 |
LD_0_n <= not Digits(0); |
276 |
LD_1_n <= not Digits(1); |
235 |
LD_1_n <= not Digits(1); |
277 |
LD_2_n <= not Digits(2); |
236 |
LD_2_n <= not Digits(2); |
278 |
LD_3_n <= not Digits(3); |
237 |
LD_3_n <= not Digits(3); |
279 |
LD_4_n <= not Digits(4); |
238 |
LD_4_n <= not Digits(4); |
280 |
LD_5_n <= not Digits(5); |
239 |
LD_5_n <= not Digits(5); |
281 |
LD_6_n <= not Digits(6); |
240 |
LD_6_n <= not Digits(6); |
282 |
LD_7_n <= not Digits(7); |
241 |
LD_7_n <= not Digits(7); |
283 |
|
242 |
|
284 |
-- Time Multiplex |
243 |
-- Time Multiplex |
285 |
process (CLK100MHz) |
244 |
process (CLK100MHz) |
286 |
begin |
245 |
begin |
287 |
if rising_edge(CLK100MHz) then |
246 |
if rising_edge(CLK100MHz) then |
288 |
if MuxCounter < MUXCOUNT-1 then |
247 |
if MuxCounter < MUXCOUNT-1 then |
289 |
MuxCounter <= MuxCounter + 1; |
248 |
MuxCounter <= MuxCounter + 1; |
290 |
else |
249 |
else |
291 |
MuxCounter <= (others => '0'); |
250 |
MuxCounter <= (others => '0'); |
292 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
251 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
293 |
Enable <= '0'; |
252 |
Enable <= '0'; |
294 |
end if; |
253 |
end if; |
295 |
if MuxCounter > (MUXCOUNT-4) then |
254 |
if MuxCounter > (MUXCOUNT-4) then |
296 |
Enable <= '1'; |
255 |
Enable <= '1'; |
297 |
end if; |
256 |
end if; |
298 |
end if; |
257 |
end if; |
299 |
end process; |
258 |
end process; |
300 |
|
259 |
|
301 |
-- HEX to 7 Segmet Decoder |
260 |
-- HEX to 7 Segmet Decoder |
302 |
-- -- A |
261 |
-- -- A |
303 |
-- | | F B |
262 |
-- | | F B |
304 |
-- -- G |
263 |
-- -- G |
305 |
-- | | E C |
264 |
-- | | E C |
306 |
-- -- D H |
265 |
-- -- D H |
307 |
-- ABCDEFGH |
266 |
-- ABCDEFGH |
308 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
267 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
309 |
"01100000" when Code="0001" else -- Digit 1 |
268 |
"01100000" when Code="0001" else -- Digit 1 |
310 |
"11011010" when Code="0010" else -- Digit 2 |
269 |
"11011010" when Code="0010" else -- Digit 2 |
311 |
"11110010" when Code="0011" else -- Digit 3 |
270 |
"11110010" when Code="0011" else -- Digit 3 |
312 |
"01100110" when Code="0100" else -- Digit 4 |
271 |
"01100110" when Code="0100" else -- Digit 4 |
313 |
"10110110" when Code="0101" else -- Digit 5 |
272 |
"10110110" when Code="0101" else -- Digit 5 |
314 |
"10111110" when Code="0110" else -- Digit 6 |
273 |
"10111110" when Code="0110" else -- Digit 6 |
315 |
"11100000" when Code="0111" else -- Digit 7 |
274 |
"11100000" when Code="0111" else -- Digit 7 |
316 |
"11111110" when Code="1000" else -- Digit 8 |
275 |
"11111110" when Code="1000" else -- Digit 8 |
317 |
"11110110" when Code="1001" else -- Digit 9 |
276 |
"11110110" when Code="1001" else -- Digit 9 |
318 |
"11101110" when Code="1010" else -- Digit A |
277 |
"11101110" when Code="1010" else -- Digit A |
319 |
"00111110" when Code="1011" else -- Digit b |
278 |
"00111110" when Code="1011" else -- Digit b |
320 |
"10011100" when Code="1100" else -- Digit C |
279 |
"10011100" when Code="1100" else -- Digit C |
321 |
"01111010" when Code="1101" else -- Digit d |
280 |
"01111010" when Code="1101" else -- Digit d |
322 |
"10011110" when Code="1110" else -- Digit E |
281 |
"10011110" when Code="1110" else -- Digit E |
323 |
"10001110" when Code="1111" else -- Digit F |
282 |
"10001110" when Code="1111" else -- Digit F |
324 |
"00000000"; |
283 |
"00000000"; |
325 |
|
284 |
|
326 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
285 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
327 |
Number( 7 downto 4) when Digits="00000010" else |
286 |
Number( 7 downto 4) when Digits="00000010" else |
328 |
Number(11 downto 8) when Digits="00000100" else |
287 |
Number(11 downto 8) when Digits="00000100" else |
329 |
Number(15 downto 12) when Digits="00001000" else |
288 |
Number(15 downto 12) when Digits="00001000" else |
330 |
Number(19 downto 16) when Digits="00010000" else |
289 |
Number(19 downto 16) when Digits="00010000" else |
331 |
Number(23 downto 20) when Digits="00100000" else |
290 |
Number(23 downto 20) when Digits="00100000" else |
332 |
Number(27 downto 24) when Digits="01000000" else |
291 |
Number(27 downto 24) when Digits="01000000" else |
333 |
Number(31 downto 28) when Digits="10000000" else |
292 |
Number(31 downto 28) when Digits="10000000" else |
334 |
"0000"; |
293 |
"0000"; |
335 |
|
294 |
|
336 |
|
295 |
|
337 |
|
- |
|
338 |
-- Diferencial In/Outs |
296 |
-- Diferencial In/Outs |
339 |
-- ======================== |
297 |
-- ======================== |
340 |
DIFbuffer1 : IBUFGDS |
298 |
DIFbuffer1 : IBUFGDS |
341 |
generic map ( |
299 |
generic map ( |
342 |
DIFF_TERM => FALSE, -- Differential Termination |
300 |
DIFF_TERM => FALSE, -- Differential Termination |
343 |
IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer, |
301 |
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
344 |
-- "0"-"16" |
302 |
-- "0"-"16" |
345 |
IOSTANDARD => "DEFAULT") |
303 |
IOSTANDARD => "LVPECL_33") |
346 |
port map ( |
304 |
port map ( |
347 |
I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
305 |
I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
348 |
IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
306 |
IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
349 |
O => EXT_CLOCK -- Buffer output |
307 |
O => EXT_CLOCK -- Buffer output - Counter INPUT |
350 |
); |
308 |
); |
351 |
|
309 |
|
352 |
OBUFDS_inst : OBUFDS |
310 |
OBUFDS_inst : OBUFDS |
353 |
generic map ( |
311 |
generic map ( |
354 |
IOSTANDARD => "DEFAULT") |
312 |
IOSTANDARD => "LVDS_33") |
355 |
port map ( |
313 |
port map ( |
356 |
O => SD2AP, -- Diff_p output (connect directly to top-level port) |
314 |
O => SD2AP, -- Diff_p output (connect directly to top-level port) |
357 |
OB => SD2AN, -- Diff_n output (connect directly to top-level port) |
315 |
OB => SD2AN, -- Diff_n output (connect directly to top-level port) |
358 |
I => EXT_CLOCK -- Buffer input |
316 |
I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS |
359 |
); |
317 |
); |
360 |
|
318 |
|
361 |
-- Output Signal on SATA Connector |
319 |
-- Output Signal on SATA Connector |
362 |
-- SD1AP <= 'Z'; |
320 |
-- SD1AP <= 'Z'; -- Counter INPUT |
363 |
-- SD1AN <= 'Z'; |
321 |
-- SD1AN <= 'Z'; |
364 |
SD1BP <= 'Z'; |
322 |
SD1BP <= 'Z'; |
365 |
SD1BN <= 'Z'; |
323 |
SD1BN <= 'Z'; |
366 |
|
324 |
|
367 |
-- Input Here via SATA Cable |
325 |
-- Input Here via SATA Cable |
368 |
-- SD2AP <= 'Z'; |
326 |
-- SD2AP <= 'Z'; -- Counter OUTPUT |
369 |
-- SD2AN <= 'Z'; |
327 |
-- SD2AN <= 'Z'; |
370 |
SD2BP <= 'Z'; |
328 |
SD2BP <= 'Z'; |
371 |
SD2BN <= 'Z'; |
329 |
SD2BN <= 'Z'; |
372 |
|
330 |
|
373 |
|
331 |
|
374 |
-- Unused Signals |
332 |
-- Unused Signals |
375 |
-- ============== |
333 |
-- ============== |
376 |
|
334 |
|
- |
|
335 |
-- Differential inputs onn header |
- |
|
336 |
DIF1N <= 'Z'; |
- |
|
337 |
DIF1P <= 'Z'; |
- |
|
338 |
DIF2N <= 'Z'; |
- |
|
339 |
DIF2P <= 'Z'; |
- |
|
340 |
|
377 |
-- I2C Signals (on connector J30) |
341 |
-- I2C Signals (on connector J30) |
378 |
I2C_SCL <= 'Z'; |
342 |
I2C_SCL <= 'Z'; |
379 |
I2C_SDA <= 'Z'; |
343 |
I2C_SDA <= 'Z'; |
380 |
|
344 |
|
381 |
-- SPI Memory Interface |
345 |
-- SPI Memory Interface |
382 |
SPI_CS_n <= 'Z'; |
346 |
SPI_CS_n <= 'Z'; |
383 |
SPI_DO <= 'Z'; |
347 |
SPI_DO <= 'Z'; |
384 |
SPI_DI <= 'Z'; |
348 |
SPI_DI <= 'Z'; |
385 |
SPI_CLK <= 'Z'; |
349 |
SPI_CLK <= 'Z'; |
386 |
SPI_WP_n <= 'Z'; |
350 |
SPI_WP_n <= 'Z'; |
387 |
|
351 |
|
- |
|
352 |
-- A/D |
388 |
ANA_OUTD <= 'Z'; |
353 |
ANA_OUTD <= 'Z'; |
389 |
ANA_REFD <= 'Z'; |
354 |
ANA_REFD <= 'Z'; |
390 |
|
355 |
|
- |
|
356 |
-- VGA |
391 |
VGA_R <= "ZZ"; |
357 |
VGA_R <= "ZZ"; |
392 |
VGA_G <= "ZZ"; |
358 |
VGA_G <= "ZZ"; |
393 |
VGA_B <= "ZZ"; |
359 |
VGA_B <= "ZZ"; |
394 |
VGA_VS <= 'Z'; |
360 |
VGA_VS <= 'Z'; |
395 |
VGA_HS <= 'Z'; |
361 |
VGA_HS <= 'Z'; |
396 |
|
362 |
|
- |
|
363 |
-- PS2 |
- |
|
364 |
PS2_DATA2 <= 'Z'; |
- |
|
365 |
PS2_CLK2 <='Z'; |
- |
|
366 |
|
397 |
end architecture gtime_a; |
367 |
end architecture gtime_a; |