| 1 |
#nolist |
1 |
#nolist |
| 2 |
// |
2 |
// |
| 3 |
// Komplete definition of all Special Feature Registers for CCS C compiler |
3 |
// Komplete definition of all Special Feature Registers for CCS C compiler |
| 4 |
// |
4 |
// |
| 5 |
// PIC16F87 |
5 |
// PIC16F87 |
| 6 |
// PIC16F88 |
6 |
// PIC16F88 |
| 7 |
// |
7 |
// |
| 8 |
// (c)miho 2005 |
8 |
// (c)miho 2005 |
| 9 |
// |
9 |
// |
| 10 |
// History: |
10 |
// History: |
| 11 |
// |
11 |
// |
| 12 |
// 1.00 First Version, not verified yet |
12 |
// 1.00 First Version, not verified yet |
| 13 |
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13 |
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| 14 |
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14 |
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| 15 |
// SFR Registers in Memory Bank 0 |
15 |
// SFR Registers in Memory Bank 0 |
| 16 |
// |
16 |
// |
| 17 |
#byte INDF = 0x00 |
17 |
#byte INDF = 0x00 |
| 18 |
#byte TMR0 = 0x01 |
18 |
#byte TMR0 = 0x01 |
| 19 |
#byte PCL = 0x02 |
19 |
#byte PCL = 0x02 |
| 20 |
#byte STATUS = 0x03 |
20 |
#byte STATUS = 0x03 |
| 21 |
#bit IRP = STATUS.7 |
21 |
#bit IRP = STATUS.7 |
| 22 |
#bit RP1 = STATUS.6 |
22 |
#bit RP1 = STATUS.6 |
| 23 |
#bit RP0 = STATUS.5 |
23 |
#bit RP0 = STATUS.5 |
| 24 |
#bit TO = STATUS.4 |
24 |
#bit TO = STATUS.4 |
| 25 |
#bit PD = STATUS.3 |
25 |
#bit PD = STATUS.3 |
| 26 |
#bit Z = STATUS.2 |
26 |
#bit Z = STATUS.2 |
| 27 |
#bit DC = STATUS.1 |
27 |
#bit DC = STATUS.1 |
| 28 |
#bit C = STATUS.0 |
28 |
#bit C = STATUS.0 |
| 29 |
#byte FSR = 0x04 |
29 |
#byte FSR = 0x04 |
| 30 |
#byte PORTA = 0x05 |
30 |
#byte PORTA = 0x05 |
| 31 |
#byte PORTB = 0x06 |
31 |
#byte PORTB = 0x06 |
| 32 |
#byte PCLATH = 0x0A |
32 |
#byte PCLATH = 0x0A |
| 33 |
#byte INTCON = 0x0B |
33 |
#byte INTCON = 0x0B |
| 34 |
#bit GIE = INTCON.7 |
34 |
#bit GIE = INTCON.7 |
| 35 |
#bit PEIE = INTCON.6 |
35 |
#bit PEIE = INTCON.6 |
| 36 |
#bit TMR0IE = INTCON.5 |
36 |
#bit TMR0IE = INTCON.5 |
| 37 |
#bit INT0IE = INTCON.4 |
37 |
#bit INT0IE = INTCON.4 |
| 38 |
#bit RBIE = INTCON.3 |
38 |
#bit RBIE = INTCON.3 |
| 39 |
#bit TMR0IF = INTCON.2 |
39 |
#bit TMR0IF = INTCON.2 |
| 40 |
#bit INT0IF = INTCON.1 |
40 |
#bit INT0IF = INTCON.1 |
| 41 |
#bit RBIF = INTCON.0 |
41 |
#bit RBIF = INTCON.0 |
| 42 |
#byte PIR1 = 0x0C |
42 |
#byte PIR1 = 0x0C |
| 43 |
#bit ADIF = PIR1.6 |
43 |
#bit ADIF = PIR1.6 |
| 44 |
#bit RCIF = PIR1.5 |
44 |
#bit RCIF = PIR1.5 |
| 45 |
#bit TXIF = PIR1.4 |
45 |
#bit TXIF = PIR1.4 |
| 46 |
#bit SSPIF = PIR1.3 |
46 |
#bit SSPIF = PIR1.3 |
| 47 |
#bit CCP1IF = PIR1.2 |
47 |
#bit CCP1IF = PIR1.2 |
| 48 |
#bit TMR2IF = PIR1.1 |
48 |
#bit TMR2IF = PIR1.1 |
| 49 |
#bit TMR1IF = PIR1.0 |
49 |
#bit TMR1IF = PIR1.0 |
| 50 |
#byte PIR2 = 0x0D |
50 |
#byte PIR2 = 0x0D |
| 51 |
#bit OSFIF = PIR2.7 |
51 |
#bit OSFIF = PIR2.7 |
| 52 |
#bit CMIF = PIR2.6 |
52 |
#bit CMIF = PIR2.6 |
| 53 |
#bit EEIF = PIR2.4 |
53 |
#bit EEIF = PIR2.4 |
| 54 |
#byte TMR1L = 0x0E |
54 |
#byte TMR1L = 0x0E |
| 55 |
#byte TMR1H = 0x0F |
55 |
#byte TMR1H = 0x0F |
| 56 |
#byte T1CON = 0x10 |
56 |
#byte T1CON = 0x10 |
| 57 |
#bit T1RUN = T1CON.6 |
57 |
#bit T1RUN = T1CON.6 |
| 58 |
#bit T1CKPS1 = T1CON.5 |
58 |
#bit T1CKPS1 = T1CON.5 |
| 59 |
#bit T1CKPS0 = T1CON.4 |
59 |
#bit T1CKPS0 = T1CON.4 |
| 60 |
#bit T1OSCEN = T1CON.3 |
60 |
#bit T1OSCEN = T1CON.3 |
| 61 |
#bit T1SYNC = T1CON.2 |
61 |
#bit T1SYNC = T1CON.2 |
| 62 |
#bit TMR1CS = T1CON.1 |
62 |
#bit TMR1CS = T1CON.1 |
| 63 |
#bit TMR1ON = T1CON.0 |
63 |
#bit TMR1ON = T1CON.0 |
| 64 |
#byte TMR2 = 0x11 |
64 |
#byte TMR2 = 0x11 |
| 65 |
#byte T2CON = 0x12 |
65 |
#byte T2CON = 0x12 |
| 66 |
#bit TOUTPS3 = T2CON.6 |
66 |
#bit TOUTPS3 = T2CON.6 |
| 67 |
#bit TOUTPS2 = T2CON.5 |
67 |
#bit TOUTPS2 = T2CON.5 |
| 68 |
#bit TOUTPS1 = T2CON.4 |
68 |
#bit TOUTPS1 = T2CON.4 |
| 69 |
#bit TOUTPS0 = T2CON.3 |
69 |
#bit TOUTPS0 = T2CON.3 |
| 70 |
#bit TMR2ON = T2CON.2 |
70 |
#bit TMR2ON = T2CON.2 |
| 71 |
#bit T2CKPS1 = T2CON.1 |
71 |
#bit T2CKPS1 = T2CON.1 |
| 72 |
#bit T2CKPS0 = T2CON.0 |
72 |
#bit T2CKPS0 = T2CON.0 |
| 73 |
#byte SSPBUF = 0x13 |
73 |
#byte SSPBUF = 0x13 |
| 74 |
#byte SSPCON1 = 0x14 |
74 |
#byte SSPCON1 = 0x14 |
| 75 |
#bit WCOL = SSPCON1.7 |
75 |
#bit WCOL = SSPCON1.7 |
| 76 |
#bit SSPOV = SSPCON1.6 |
76 |
#bit SSPOV = SSPCON1.6 |
| 77 |
#bit SSPEN = SSPCON1.5 |
77 |
#bit SSPEN = SSPCON1.5 |
| 78 |
#bit CKP = SSPCON1.4 |
78 |
#bit CKP = SSPCON1.4 |
| 79 |
#bit SSPM3 = SSPCON1.3 |
79 |
#bit SSPM3 = SSPCON1.3 |
| 80 |
#bit SSPM2 = SSPCON1.2 |
80 |
#bit SSPM2 = SSPCON1.2 |
| 81 |
#bit SSPM1 = SSPCON1.1 |
81 |
#bit SSPM1 = SSPCON1.1 |
| 82 |
#bit SSPM0 = SSPCON1.0 |
82 |
#bit SSPM0 = SSPCON1.0 |
| 83 |
#byte CCPR1L = 0x15 |
83 |
#byte CCPR1L = 0x15 |
| 84 |
#byte CCPR1H = 0x16 |
84 |
#byte CCPR1H = 0x16 |
| 85 |
#byte CCP1CON = 0x17 |
85 |
#byte CCP1CON = 0x17 |
| 86 |
#bit CCP1X = CCP1CON.5 |
86 |
#bit CCP1X = CCP1CON.5 |
| 87 |
#bit CCP1Y = CCP1CON.4 |
87 |
#bit CCP1Y = CCP1CON.4 |
| 88 |
#bit CCP1M3 = CCP1CON.3 |
88 |
#bit CCP1M3 = CCP1CON.3 |
| 89 |
#bit CCP1M2 = CCP1CON.2 |
89 |
#bit CCP1M2 = CCP1CON.2 |
| 90 |
#bit CCP1M1 = CCP1CON.1 |
90 |
#bit CCP1M1 = CCP1CON.1 |
| 91 |
#bit CCP1M0 = CCP1CON.0 |
91 |
#bit CCP1M0 = CCP1CON.0 |
| 92 |
#byte RCSTA = 0x18 |
92 |
#byte RCSTA = 0x18 |
| 93 |
#bit SPEN = RCSTA.7 |
93 |
#bit SPEN = RCSTA.7 |
| 94 |
#bit RX9 = RCSTA.6 |
94 |
#bit RX9 = RCSTA.6 |
| 95 |
#bit SREN = RCSTA.5 |
95 |
#bit SREN = RCSTA.5 |
| 96 |
#bit CREN = RCSTA.4 |
96 |
#bit CREN = RCSTA.4 |
| 97 |
#bit ADDEN = RCSTA.3 |
97 |
#bit ADDEN = RCSTA.3 |
| 98 |
#bit FERR = RCSTA.2 |
98 |
#bit FERR = RCSTA.2 |
| 99 |
#bit OERR = RCSTA.1 |
99 |
#bit OERR = RCSTA.1 |
| 100 |
#bit RX9D = RCSTA.0 |
100 |
#bit RX9D = RCSTA.0 |
| 101 |
#byte TXREG = 0x19 |
101 |
#byte TXREG = 0x19 |
| 102 |
#byte RCREG = 0x1A |
102 |
#byte RCREG = 0x1A |
| 103 |
#byte ADRESH = 0x1E // F88 only |
103 |
#byte ADRESH = 0x1E // F88 only |
| 104 |
#byte ADCON0 = 0x1F // F88 only |
104 |
#byte ADCON0 = 0x1F // F88 only |
| 105 |
#bit ADCS1 = ADCON0.7 |
105 |
#bit ADCS1 = ADCON0.7 |
| 106 |
#bit ADCS0 = ADCON0.6 |
106 |
#bit ADCS0 = ADCON0.6 |
| 107 |
#bit CHS2 = ADCON0.5 |
107 |
#bit CHS2 = ADCON0.5 |
| 108 |
#bit CHS1 = ADCON0.4 |
108 |
#bit CHS1 = ADCON0.4 |
| 109 |
#bit CHS0 = ADCON0.3 |
109 |
#bit CHS0 = ADCON0.3 |
| 110 |
#bit GO = ADCON0.2 |
110 |
#bit GO = ADCON0.2 |
| 111 |
#bit ADON = ADCON0.0 |
111 |
#bit ADON = ADCON0.0 |
| 112 |
|
112 |
|
| 113 |
|
113 |
|
| 114 |
// SFR Registers in Memory Bank 1 |
114 |
// SFR Registers in Memory Bank 1 |
| 115 |
// |
115 |
// |
| 116 |
#byte INDF_1 = 0x80 // miror |
116 |
#byte INDF_1 = 0x80 // miror |
| 117 |
#byte OPTION = 0x81 |
117 |
#byte OPTION = 0x81 |
| 118 |
#bit RBPU = OPTION.7 |
118 |
#bit RBPU = OPTION.7 |
| 119 |
#bit INTEDG = OPTION.6 |
119 |
#bit INTEDG = OPTION.6 |
| 120 |
#bit T0CS = OPTION.5 |
120 |
#bit T0CS = OPTION.5 |
| 121 |
#bit T0SE = OPTION.4 |
121 |
#bit T0SE = OPTION.4 |
| 122 |
#bit PSA = OPTION.3 |
122 |
#bit PSA = OPTION.3 |
| 123 |
#bit PS2 = OPTION.2 |
123 |
#bit PS2 = OPTION.2 |
| 124 |
#bit PS1 = OPTION.1 |
124 |
#bit PS1 = OPTION.1 |
| 125 |
#bit PS0 = OPTION.0 |
125 |
#bit PS0 = OPTION.0 |
| 126 |
#byte PCL = 0x82 |
126 |
#byte PCL = 0x82 |
| 127 |
#byte STATUS_1 = 0x83 // mirror |
127 |
#byte STATUS_1 = 0x83 // mirror |
| 128 |
#bit IRP_1 = STATUS_1.7 |
128 |
#bit IRP_1 = STATUS_1.7 |
| 129 |
#bit RP1_1 = STATUS_1.6 |
129 |
#bit RP1_1 = STATUS_1.6 |
| 130 |
#bit RP0_1 = STATUS_1.5 |
130 |
#bit RP0_1 = STATUS_1.5 |
| 131 |
#bit TO_1 = STATUS_1.4 |
131 |
#bit TO_1 = STATUS_1.4 |
| 132 |
#bit PD_1 = STATUS_1.3 |
132 |
#bit PD_1 = STATUS_1.3 |
| 133 |
#bit Z_1 = STATUS_1.2 |
133 |
#bit Z_1 = STATUS_1.2 |
| 134 |
#bit DC_1 = STATUS_1.1 |
134 |
#bit DC_1 = STATUS_1.1 |
| 135 |
#bit C_1 = STATUS_1.0 |
135 |
#bit C_1 = STATUS_1.0 |
| 136 |
#byte FSR = 0x84 |
136 |
#byte FSR = 0x84 |
| 137 |
#byte TRISA = 0x85 |
137 |
#byte TRISA = 0x85 |
| 138 |
#byte TRISB = 0x86 |
138 |
#byte TRISB = 0x86 |
| 139 |
#byte PCLATH_1 = 0x8A // mirror |
139 |
#byte PCLATH_1 = 0x8A // mirror |
| 140 |
#byte INTCON_1 = 0x8B // mirror |
140 |
#byte INTCON_1 = 0x8B // mirror |
| 141 |
#bit GIE_1 = INTCON_1.7 |
141 |
#bit GIE_1 = INTCON_1.7 |
| 142 |
#bit PEIE_1 = INTCON_1.6 |
142 |
#bit PEIE_1 = INTCON_1.6 |
| 143 |
#bit TMR0IE_1 = INTCON_1.5 |
143 |
#bit TMR0IE_1 = INTCON_1.5 |
| 144 |
#bit INT0IE_1 = INTCON_1.4 |
144 |
#bit INT0IE_1 = INTCON_1.4 |
| 145 |
#bit RBIE_1 = INTCON_1.3 |
145 |
#bit RBIE_1 = INTCON_1.3 |
| 146 |
#bit TMR0IF_1 = INTCON_1.2 |
146 |
#bit TMR0IF_1 = INTCON_1.2 |
| 147 |
#bit INT0IF_1 = INTCON_1.1 |
147 |
#bit INT0IF_1 = INTCON_1.1 |
| 148 |
#bit RBIF_1 = INTCON_1.0 |
148 |
#bit RBIF_1 = INTCON_1.0 |
| 149 |
#byte PIE1 = 0x8C |
149 |
#byte PIE1 = 0x8C |
| 150 |
#bit ADIE = PIE1.6 |
150 |
#bit ADIE = PIE1.6 |
| 151 |
#bit RCIE = PIE1.5 |
151 |
#bit RCIE = PIE1.5 |
| 152 |
#bit TXIE = PIE1.4 |
152 |
#bit TXIE = PIE1.4 |
| 153 |
#bit SSPIE = PIE1.3 |
153 |
#bit SSPIE = PIE1.3 |
| 154 |
#bit CCP1IE = PIE1.2 |
154 |
#bit CCP1IE = PIE1.2 |
| 155 |
#bit TMR2IE = PIE1.1 |
155 |
#bit TMR2IE = PIE1.1 |
| 156 |
#bit TMR1IE = PIE1.0 |
156 |
#bit TMR1IE = PIE1.0 |
| 157 |
#byte PIE2 = 0x8D |
157 |
#byte PIE2 = 0x8D |
| 158 |
#bit OSFIE = PIE2.7 |
158 |
#bit OSFIE = PIE2.7 |
| 159 |
#bit CMIE = PIE2.6 |
159 |
#bit CMIE = PIE2.6 |
| 160 |
#bit EEIE = PIE2.4 |
160 |
#bit EEIE = PIE2.4 |
| 161 |
#byte PCON = 0x8E |
161 |
#byte PCON = 0x8E |
| 162 |
#bit POR = PCON.1 |
162 |
#bit POR = PCON.1 |
| 163 |
#bit BOR = PCON.0 |
163 |
#bit BOR = PCON.0 |
| 164 |
#byte OSCCON = 0x8F |
164 |
#byte OSCCON = 0x8F |
| 165 |
#bit IRCF2 = OSCCON.6 |
165 |
#bit IRCF2 = OSCCON.6 |
| 166 |
#bit IRCF1 = OSCCON.5 |
166 |
#bit IRCF1 = OSCCON.5 |
| 167 |
#bit IRCF0 = OSCCON.4 |
167 |
#bit IRCF0 = OSCCON.4 |
| 168 |
#bit OSTS = OSCCON.3 |
168 |
#bit OSTS = OSCCON.3 |
| 169 |
#bit IOFS = OSCCON.2 |
169 |
#bit IOFS = OSCCON.2 |
| 170 |
#bit SCS1 = OSCCON.1 |
170 |
#bit SCS1 = OSCCON.1 |
| 171 |
#bit SCS0 = OSCCON.0 |
171 |
#bit SCS0 = OSCCON.0 |
| 172 |
#byte OSCTUNE = 0x90 |
172 |
#byte OSCTUNE = 0x90 |
| 173 |
#bit TUN5 = OSCTUNE.5 |
173 |
#bit TUN5 = OSCTUNE.5 |
| 174 |
#bit TUN4 = OSCTUNE.4 |
174 |
#bit TUN4 = OSCTUNE.4 |
| 175 |
#bit TUN3 = OSCTUNE.3 |
175 |
#bit TUN3 = OSCTUNE.3 |
| 176 |
#bit TUN2 = OSCTUNE.2 |
176 |
#bit TUN2 = OSCTUNE.2 |
| 177 |
#bit TUN1 = OSCTUNE.1 |
177 |
#bit TUN1 = OSCTUNE.1 |
| 178 |
#bit TUN0 = OSCTUNE.0 |
178 |
#bit TUN0 = OSCTUNE.0 |
| 179 |
#byte PR2 = 0x92 |
179 |
#byte PR2 = 0x92 |
| 180 |
#byte SSPADD = 0x93 |
180 |
#byte SSPADD = 0x93 |
| 181 |
#byte SSPSTAT = 0x94 |
181 |
#byte SSPSTAT = 0x94 |
| 182 |
#bit SMP = SSPSTAT.7 |
182 |
#bit SMP = SSPSTAT.7 |
| 183 |
#bit CKE = SSPSTAT.6 |
183 |
#bit CKE = SSPSTAT.6 |
| 184 |
#bit DA = SSPSTAT.5 |
184 |
#bit DA = SSPSTAT.5 |
| 185 |
#bit P = SSPSTAT.4 |
185 |
#bit P = SSPSTAT.4 |
| 186 |
#bit S = SSPSTAT.3 |
186 |
#bit S = SSPSTAT.3 |
| 187 |
#bit RW = SSPSTAT.2 |
187 |
#bit RW = SSPSTAT.2 |
| 188 |
#bit UA = SSPSTAT.1 |
188 |
#bit UA = SSPSTAT.1 |
| 189 |
#bit BF = SSPSTAT.0 |
189 |
#bit BF = SSPSTAT.0 |
| 190 |
#byte TXSTA = 0x98 |
190 |
#byte TXSTA = 0x98 |
| 191 |
#bit CSRC = TXSTA.7 |
191 |
#bit CSRC = TXSTA.7 |
| 192 |
#bit TX9 = TXSTA.6 |
192 |
#bit TX9 = TXSTA.6 |
| 193 |
#bit TXEN = TXSTA.5 |
193 |
#bit TXEN = TXSTA.5 |
| 194 |
#bit SYNC = TXSTA.4 |
194 |
#bit SYNC = TXSTA.4 |
| 195 |
#bit BRGH = TXSTA.2 |
195 |
#bit BRGH = TXSTA.2 |
| 196 |
#bit TRMT = TXSTA.1 |
196 |
#bit TRMT = TXSTA.1 |
| 197 |
#bit TX9D = TXSTA.0 |
197 |
#bit TX9D = TXSTA.0 |
| 198 |
#byte SPBRG = 0x99 |
198 |
#byte SPBRG = 0x99 |
| 199 |
#byte ANSEL = 0x9B // F88 only |
199 |
#byte ANSEL = 0x9B // F88 only |
| 200 |
#bit ANS6 = ANSEL.6 |
200 |
#bit ANS6 = ANSEL.6 |
| 201 |
#bit ANS5 = ANSEL.5 |
201 |
#bit ANS5 = ANSEL.5 |
| 202 |
#bit ANS4 = ANSEL.4 |
202 |
#bit ANS4 = ANSEL.4 |
| 203 |
#bit ANS3 = ANSEL.3 |
203 |
#bit ANS3 = ANSEL.3 |
| 204 |
#bit ANS2 = ANSEL.2 |
204 |
#bit ANS2 = ANSEL.2 |
| 205 |
#bit ANS1 = ANSEL.1 |
205 |
#bit ANS1 = ANSEL.1 |
| 206 |
#bit ANS0 = ANSEL.0 |
206 |
#bit ANS0 = ANSEL.0 |
| 207 |
#byte CMCON = 0x9C |
207 |
#byte CMCON = 0x9C |
| 208 |
#bit C2OUT = CMCON.7 |
208 |
#bit C2OUT = CMCON.7 |
| 209 |
#bit C1OUT = CMCON.6 |
209 |
#bit C1OUT = CMCON.6 |
| 210 |
#bit C2INV = CMCON.5 |
210 |
#bit C2INV = CMCON.5 |
| 211 |
#bit C1INV = CMCON.4 |
211 |
#bit C1INV = CMCON.4 |
| 212 |
#bit CIS = CMCON.3 |
212 |
#bit CIS = CMCON.3 |
| 213 |
#bit CM2 = CMCON.2 |
213 |
#bit CM2 = CMCON.2 |
| 214 |
#bit CM1 = CMCON.1 |
214 |
#bit CM1 = CMCON.1 |
| 215 |
#bit CM0 = CMCON.0 |
215 |
#bit CM0 = CMCON.0 |
| 216 |
#byte CVRCON = 0x9D |
216 |
#byte CVRCON = 0x9D |
| 217 |
#bit CVREN = CVRCON.7 |
217 |
#bit CVREN = CVRCON.7 |
| 218 |
#bit CVROE = CVRCON.6 |
218 |
#bit CVROE = CVRCON.6 |
| 219 |
#bit CVRR = CVRCON.5 |
219 |
#bit CVRR = CVRCON.5 |
| 220 |
#bit CVR3 = CVRCON.3 |
220 |
#bit CVR3 = CVRCON.3 |
| 221 |
#bit CVR2 = CVRCON.2 |
221 |
#bit CVR2 = CVRCON.2 |
| 222 |
#bit CVR1 = CVRCON.1 |
222 |
#bit CVR1 = CVRCON.1 |
| 223 |
#bit CVR0 = CVRCON.0 |
223 |
#bit CVR0 = CVRCON.0 |
| 224 |
#byte ADRESL = 0x9E // F88 only |
224 |
#byte ADRESL = 0x9E // F88 only |
| 225 |
#byte ADCON1 = 0x9F // F88 only |
225 |
#byte ADCON1 = 0x9F // F88 only |
| 226 |
#bit ADFM = ADCON1.7 |
226 |
#bit ADFM = ADCON1.7 |
| 227 |
#bit ADCS2 = ADCON1.6 |
227 |
#bit ADCS2 = ADCON1.6 |
| 228 |
#bit VCFG1 = ADCON1.5 |
228 |
#bit VCFG1 = ADCON1.5 |
| 229 |
#bit VCFG0 = ADCON1.4 |
229 |
#bit VCFG0 = ADCON1.4 |
| 230 |
|
230 |
|
| 231 |
|
231 |
|
| 232 |
// SFR Registers in Memory Bank 2 |
232 |
// SFR Registers in Memory Bank 2 |
| 233 |
// |
233 |
// |
| 234 |
#byte INDF_2 = 0x100 // mirror |
234 |
#byte INDF_2 = 0x100 // mirror |
| 235 |
#byte TMR0_2 = 0x101 // mirror |
235 |
#byte TMR0_2 = 0x101 // mirror |
| 236 |
#byte PCL_2 = 0x102 // mirror |
236 |
#byte PCL_2 = 0x102 // mirror |
| 237 |
#byte STATUS_2 = 0x103 // mirror |
237 |
#byte STATUS_2 = 0x103 // mirror |
| 238 |
#bit IRP_2 = STATUS_2.7 |
238 |
#bit IRP_2 = STATUS_2.7 |
| 239 |
#bit RP1_2 = STATUS_2.6 |
239 |
#bit RP1_2 = STATUS_2.6 |
| 240 |
#bit RP0_2 = STATUS_2.5 |
240 |
#bit RP0_2 = STATUS_2.5 |
| 241 |
#bit TO_2 = STATUS_2.4 |
241 |
#bit TO_2 = STATUS_2.4 |
| 242 |
#bit PD_2 = STATUS_2.3 |
242 |
#bit PD_2 = STATUS_2.3 |
| 243 |
#bit Z_2 = STATUS_2.2 |
243 |
#bit Z_2 = STATUS_2.2 |
| 244 |
#bit DC_2 = STATUS_2.1 |
244 |
#bit DC_2 = STATUS_2.1 |
| 245 |
#bit C_2 = STATUS_2.0 |
245 |
#bit C_2 = STATUS_2.0 |
| 246 |
#byte FSR_2 = 0x104 // mirror |
246 |
#byte FSR_2 = 0x104 // mirror |
| 247 |
#byte WDTCON = 0x105 |
247 |
#byte WDTCON = 0x105 |
| 248 |
#bit WDTPS3 = WDTCON.4 |
248 |
#bit WDTPS3 = WDTCON.4 |
| 249 |
#bit WDTPS2 = WDTCON.3 |
249 |
#bit WDTPS2 = WDTCON.3 |
| 250 |
#bit WDTPS1 = WDTCON.2 |
250 |
#bit WDTPS1 = WDTCON.2 |
| 251 |
#bit WDTPS0 = WDTCON.1 |
251 |
#bit WDTPS0 = WDTCON.1 |
| 252 |
#bit SWDTEN = WDTCON.0 |
252 |
#bit SWDTEN = WDTCON.0 |
| 253 |
#byte PORTB_2 = 0x106 // mirror |
253 |
#byte PORTB_2 = 0x106 // mirror |
| 254 |
#byte PCLATH_2 = 0x10A // mirror |
254 |
#byte PCLATH_2 = 0x10A // mirror |
| 255 |
#byte INTCON_2 = 0x10B // mirror |
255 |
#byte INTCON_2 = 0x10B // mirror |
| 256 |
#bit GIE_2 = INTCON_2.7 |
256 |
#bit GIE_2 = INTCON_2.7 |
| 257 |
#bit PEIE_2 = INTCON_2.6 |
257 |
#bit PEIE_2 = INTCON_2.6 |
| 258 |
#bit TMR0IE_2 = INTCON_2.5 |
258 |
#bit TMR0IE_2 = INTCON_2.5 |
| 259 |
#bit INT0IE_2 = INTCON_2.4 |
259 |
#bit INT0IE_2 = INTCON_2.4 |
| 260 |
#bit RBIE_2 = INTCON_2.3 |
260 |
#bit RBIE_2 = INTCON_2.3 |
| 261 |
#bit TMR0IF_2 = INTCON_2.2 |
261 |
#bit TMR0IF_2 = INTCON_2.2 |
| 262 |
#bit INT0IF_2 = INTCON_2.1 |
262 |
#bit INT0IF_2 = INTCON_2.1 |
| 263 |
#bit RBIF_2 = INTCON_2.0 |
263 |
#bit RBIF_2 = INTCON_2.0 |
| 264 |
#byte EEDATA = 0x10C |
264 |
#byte EEDATA = 0x10C |
| 265 |
#byte EEADR = 0x10D |
265 |
#byte EEADR = 0x10D |
| 266 |
#byte EEDATH = 0x10E |
266 |
#byte EEDATH = 0x10E |
| 267 |
#byte EEADRH = 0x10F |
267 |
#byte EEADRH = 0x10F |
| 268 |
|
268 |
|
| 269 |
|
269 |
|
| 270 |
// SFR Registers in Memory Bank 3 |
270 |
// SFR Registers in Memory Bank 3 |
| 271 |
// |
271 |
// |
| 272 |
#byte INDF_3 = 0x180 // mirror |
272 |
#byte INDF_3 = 0x180 // mirror |
| 273 |
#byte OPTION_3 = 0x181 // mirror |
273 |
#byte OPTION_3 = 0x181 // mirror |
| 274 |
#bit RBPU_3 = OPTION_3.7 |
274 |
#bit RBPU_3 = OPTION_3.7 |
| 275 |
#bit INTEDG_3 = OPTION_3.6 |
275 |
#bit INTEDG_3 = OPTION_3.6 |
| 276 |
#bit T0CS_3 = OPTION_3.5 |
276 |
#bit T0CS_3 = OPTION_3.5 |
| 277 |
#bit T0SE_3 = OPTION_3.4 |
277 |
#bit T0SE_3 = OPTION_3.4 |
| 278 |
#bit PSA_3 = OPTION_3.3 |
278 |
#bit PSA_3 = OPTION_3.3 |
| 279 |
#bit PS2_3 = OPTION_3.2 |
279 |
#bit PS2_3 = OPTION_3.2 |
| 280 |
#bit PS1_3 = OPTION_3.1 |
280 |
#bit PS1_3 = OPTION_3.1 |
| 281 |
#bit PS0_3 = OPTION_3.0 |
281 |
#bit PS0_3 = OPTION_3.0 |
| 282 |
#byte PCL_3 = 0x182 // mirror |
282 |
#byte PCL_3 = 0x182 // mirror |
| 283 |
#byte STATUS_3 = 0x183 // mirror |
283 |
#byte STATUS_3 = 0x183 // mirror |
| 284 |
#bit IRP_3 = STATUS_3.7 |
284 |
#bit IRP_3 = STATUS_3.7 |
| 285 |
#bit RP1_3 = STATUS_3.6 |
285 |
#bit RP1_3 = STATUS_3.6 |
| 286 |
#bit RP0_3 = STATUS_3.5 |
286 |
#bit RP0_3 = STATUS_3.5 |
| 287 |
#bit TO_3 = STATUS_3.4 |
287 |
#bit TO_3 = STATUS_3.4 |
| 288 |
#bit PD_3 = STATUS_3.3 |
288 |
#bit PD_3 = STATUS_3.3 |
| 289 |
#bit Z_3 = STATUS_3.2 |
289 |
#bit Z_3 = STATUS_3.2 |
| 290 |
#bit DC_3 = STATUS_3.1 |
290 |
#bit DC_3 = STATUS_3.1 |
| 291 |
#bit C_3 = STATUS_3.0 |
291 |
#bit C_3 = STATUS_3.0 |
| 292 |
#byte FSR_3 = 0x184 // mirror |
292 |
#byte FSR_3 = 0x184 // mirror |
| 293 |
#byte TRISB_3 = 0x186 // mirror |
293 |
#byte TRISB_3 = 0x186 // mirror |
| 294 |
#byte PLATH_3 = 0x18A // mirror |
294 |
#byte PLATH_3 = 0x18A // mirror |
| 295 |
#byte INTCON_3 = 0x18B // mirror |
295 |
#byte INTCON_3 = 0x18B // mirror |
| 296 |
#bit GIE_3 = INTCON_3.7 |
296 |
#bit GIE_3 = INTCON_3.7 |
| 297 |
#bit PEIE_3 = INTCON_3.6 |
297 |
#bit PEIE_3 = INTCON_3.6 |
| 298 |
#bit TMR0IE_3 = INTCON_3.5 |
298 |
#bit TMR0IE_3 = INTCON_3.5 |
| 299 |
#bit INT0IE_3 = INTCON_3.4 |
299 |
#bit INT0IE_3 = INTCON_3.4 |
| 300 |
#bit RBIE_3 = INTCON_3.3 |
300 |
#bit RBIE_3 = INTCON_3.3 |
| 301 |
#bit TMR0IF_3 = INTCON_3.2 |
301 |
#bit TMR0IF_3 = INTCON_3.2 |
| 302 |
#bit INT0IF_3 = INTCON_3.1 |
302 |
#bit INT0IF_3 = INTCON_3.1 |
| 303 |
#bit RBIF_3 = INTCON_3.0 |
303 |
#bit RBIF_3 = INTCON_3.0 |
| 304 |
#byte EECON1 = 0x18C |
304 |
#byte EECON1 = 0x18C |
| 305 |
#bit EEPGD = EECON1.7 |
305 |
#bit EEPGD = EECON1.7 |
| 306 |
#bit FREE = EECON1.4 |
306 |
#bit FREE = EECON1.4 |
| 307 |
#bit WRERR = EECON1.3 |
307 |
#bit WRERR = EECON1.3 |
| 308 |
#bit WREN = EECON1.2 |
308 |
#bit WREN = EECON1.2 |
| 309 |
#bit WR = EECON1.1 |
309 |
#bit WR = EECON1.1 |
| 310 |
#bit RD = EECON1.0 |
310 |
#bit RD = EECON1.0 |
| 311 |
#byte EECON2 = 0x18D |
311 |
#byte EECON2 = 0x18D |
| 312 |
|
312 |
|
| 313 |
|
313 |
|
| 314 |
#list |
314 |
#list |