Rev 2131 Rev 2139
1 /********************************************* 1 /*********************************************
2 * 2 *
3 * RFM01 simple library 3 * RFM01 simple library
4 * 4 *
5 * $HeadURL: svn://www.mlab.cz/home/MLAB/Designs/duckweed_collector/SW/library/RF02/RF02.cpp $ 5 * $HeadURL: svn://www.mlab.cz/home/MLAB/Designs/duckweed_collector/SW/library/RF02/RF02.cpp $
6 * $Id: RF02.cpp 2129 2011-08-18 18:40:43Z kakl $ 6 * $Id: RF02.cpp 2129 2011-08-18 18:40:43Z kakl $
7 * 7 *
8 * code based on the code of "benedikt k." and "contrechoc" 8 * code based on the code of "benedikt k." and "contrechoc"
9 * 9 *
10 * tested on arduino 22 10 * tested on arduino 22
11 * 11 *
12 *********************************************/ 12 *********************************************/
13   13  
14 #include <avr/io.h> 14 #include <avr/io.h>
15 #include <stdlib.h> 15 #include <stdlib.h>
16   16  
17 #include "rf01.h" 17 #include "rf01.h"
18   18  
19 #define F_CPU 16000000UL 19 #define F_CPU 16000000UL
20 #include <util/delay.h> 20 #include <util/delay.h>
21   21  
22 #define RF_PORT PORTB 22 #define RF_PORT PORTB
23 #define RF_DDR DDRB 23 #define RF_DDR DDRB
24 #define RF_PIN PINB 24 #define RF_PIN PINB
25   25  
26 #define SDI 5 // RF01 SDI, arduino 13 cannot be changed 26 #define SDI 5 // RF01 SDI, arduino 13 cannot be changed
27 #define SCK 4 // RF01 SCK, arduino 12 cannot be changed 27 #define SCK 4 // RF01 SCK, arduino 12 cannot be changed
28 #define CS 3 // RF01 nSEL, arduino 11 cannot be changed 28 #define CS 3 // RF01 nSEL, arduino 11 cannot be changed
29 #define SDO 2 // RF01 SDO, arduino 10 cannot be changed 29 #define SDO 2 // RF01 SDO, arduino 10 cannot be changed
30 //----------------- // RF01 niRQ, arduino 2 cannot be changed 30 //----------------- // RF01 niRQ, arduino 2 cannot be changed
31 //------------------// RF01 nFFS: 1-10k Pullup too Vcc 31 //------------------// RF01 nFFS: 1-10k Pullup too Vcc
32   32  
33   33  
34 #ifndef cbi 34 #ifndef cbi
35 #define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit)) 35 #define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
36 #endif 36 #endif
37 #ifndef sbi 37 #ifndef sbi
38 #define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit)) 38 #define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
39 #endif 39 #endif
40   40  
41 unsigned char _rx_buffer[32]; // recv buf 41 unsigned char _rx_buffer[32]; // recv buf
42   42  
43 #include <util/delay.h> 43 #include <util/delay.h>
44   44  
45 void rf01_prepAll() 45 void rf01_prepAll()
46 { 46 {
47 RF_PORT=(1<<CS); 47 RF_PORT=(1<<CS);
48 RF_DDR=(1<<SDI)|(1<<SCK)|(1<<CS); 48 RF_DDR=(1<<SDI)|(1<<SCK)|(1<<CS);
49   49  
50 for (unsigned char i=0; i<11; i++) _delay_ms(10); // wait until POR done 50 for (unsigned char i=0; i<11; i++) _delay_ms(10); // wait until POR done
51   51  
52 rf01_trans(0x0000); 52 rf01_trans(0x0000); // cargo cult settings
53 rf01_trans(0x8000|0x1000|0x70|0x02); //band 53 rf01_trans(0x8000|0x1000|0x70|0x02); //band
54 rf01_trans(0xA640); // freq 54 rf01_trans(0xA640); // freq
55 rf01_trans(0xC823); //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 9600 Bd 55 rf01_trans(0xC823); //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 9600 Bd
56 rf01_trans(0xC69B); 56 rf01_trans(0xC69B);
57 rf01_trans(0xC42A); 57 rf01_trans(0xC42A);
58 rf01_trans(0xC240); //* 58 rf01_trans(0xC240); //*
59 rf01_trans(0xC080); //* 59 rf01_trans(0xC080); //*
60 rf01_trans(0xCE88); // FIFO mode 60 rf01_trans(0xCE88); // FIFO mode
61 rf01_trans(0xCE8B); //* 61 rf01_trans(0xCE8B); //*
62 rf01_trans(0xC081); //* 62 rf01_trans(0xC081); //*
63 } 63 }
64   64  
65 void rf01_trans(unsigned short wert) 65 void rf01_trans(unsigned short wert)
66 { unsigned char i; 66 { unsigned char i;
67   67  
68 cbi(RF_PORT, CS); 68 cbi(RF_PORT, CS);
69 for (i=0; i<16; i++) 69 for (i=0; i<16; i++)
70 { if (wert&32768) 70 { if (wert&32768)
71 sbi(RF_PORT, SDI); 71 sbi(RF_PORT, SDI);
72 else 72 else
73 cbi(RF_PORT, SDI); 73 cbi(RF_PORT, SDI);
74 sbi(RF_PORT, SCK); 74 sbi(RF_PORT, SCK);
75 sbi(RF_PORT, SCK); 75 sbi(RF_PORT, SCK);
76 sbi(RF_PORT, SCK); 76 sbi(RF_PORT, SCK);
77 wert<<=1; 77 wert<<=1;
78 cbi(RF_PORT, SCK); 78 cbi(RF_PORT, SCK);
79 } 79 }
80 sbi(RF_PORT, CS); 80 sbi(RF_PORT, CS);
81 } 81 }
82   82  
83 void rf01_rxdata(unsigned char *data, unsigned char number) 83 void rf01_rxdata(unsigned char *data, unsigned char number)
84 { unsigned char i,j,c; 84 { unsigned char i,j,c;
85   85  
86 rf01_trans(0xCE89); // set FIFO mode 86 rf01_trans(0xCE89); // set FIFO mode
87 rf01_trans(0xCE8B); // enable FIFO 87 rf01_trans(0xCE8B); // enable FIFO
88 cbi(RF_PORT, SDI); 88 cbi(RF_PORT, SDI);
89 asm("nop"); 89 asm("nop");
90 asm("nop"); 90 asm("nop");
91 asm("nop"); 91 asm("nop");
92 for (i=0; i<number; i++) 92 for (i=0; i<number; i++)
93 { cbi(RF_PORT, CS); 93 { cbi(RF_PORT, CS);
94 asm("nop"); 94 asm("nop");
95 asm("nop"); 95 asm("nop");
96 asm("nop"); 96 asm("nop");
97 while (!(RF_PIN&(1<<SDO))); // wait until data in FIFO 97 while (!(RF_PIN&(1<<SDO))); // wait until data in FIFO
98 for (j=0; j<16; j++) // read and discard status register 98 for (j=0; j<16; j++) // read and discard status register
99 { 99 {
100 sbi(RF_PORT, SCK); 100 sbi(RF_PORT, SCK);
101 asm("nop"); 101 asm("nop");
102 asm("nop"); 102 asm("nop");
103 asm("nop"); 103 asm("nop");
104 cbi(RF_PORT, SCK); 104 cbi(RF_PORT, SCK);
105 asm("nop"); 105 asm("nop");
106 asm("nop"); 106 asm("nop");
107 asm("nop"); 107 asm("nop");
108 } 108 }
109 c=0; 109 c=0;
110 for (j=0; j<8; j++) 110 for (j=0; j<8; j++)
111 { c<<=1; 111 { c<<=1;
112 if (RF_PIN&(1<<SDO)) 112 if (RF_PIN&(1<<SDO))
113 c|=1; 113 c|=1;
114 sbi(RF_PORT, SCK); 114 sbi(RF_PORT, SCK);
115 asm("nop"); 115 asm("nop");
116 asm("nop"); 116 asm("nop");
117 asm("nop"); 117 asm("nop");
118 cbi(RF_PORT, SCK); 118 cbi(RF_PORT, SCK);
119 asm("nop"); 119 asm("nop");
120 asm("nop"); 120 asm("nop");
121 asm("nop"); 121 asm("nop");
122 } 122 }
123 *data++=c; 123 *data++=c;
124 sbi(RF_PORT, CS); 124 sbi(RF_PORT, CS);
125 asm("nop"); 125 asm("nop");
126 asm("nop"); 126 asm("nop");
127 asm("nop"); 127 asm("nop");
128 } 128 }
129 } 129 }