Rev 3557 Rev 3559
1 (kicad_pcb (version 3) (host pcbnew "(2014-03-14 BZR 4749)-product") 1 (kicad_pcb (version 3) (host pcbnew "(2014-03-14 BZR 4749)-product")
2   2  
3 (general 3 (general
4 (links 0) 4 (links 0)
5 (no_connects 0) 5 (no_connects 0)
6 (area 0 0 0 0) 6 (area 0 0 0 0)
7 (thickness 1.6) 7 (thickness 1.6)
8 (drawings 0) 8 (drawings 0)
9 (tracks 0) 9 (tracks 0)
10 (zones 0) 10 (zones 0)
11 (modules 0) 11 (modules 0)
12 (nets 1) 12 (nets 1)
13 ) 13 )
14   14  
15 (page A4) 15 (page A4)
16 (layers 16 (layers
17 (15 F.Cu signal) 17 (15 F.Cu signal)
18 (0 B.Cu signal) 18 (0 B.Cu signal)
19 (16 B.Adhes user) 19 (16 B.Adhes user)
20 (17 F.Adhes user) 20 (17 F.Adhes user)
21 (18 B.Paste user) 21 (18 B.Paste user)
22 (19 F.Paste user) 22 (19 F.Paste user)
23 (20 B.SilkS user) 23 (20 B.SilkS user)
24 (21 F.SilkS user) 24 (21 F.SilkS user)
25 (22 B.Mask user) 25 (22 B.Mask user)
26 (23 F.Mask user) 26 (23 F.Mask user)
27 (24 Dwgs.User user) 27 (24 Dwgs.User user)
28 (25 Cmts.User user) 28 (25 Cmts.User user)
29 (26 Eco1.User user) 29 (26 Eco1.User user)
30 (27 Eco2.User user) 30 (27 Eco2.User user)
31 (28 Edge.Cuts user) 31 (28 Edge.Cuts user)
32 ) 32 )
33   33  
34 (setup 34 (setup
35 (last_trace_width 0.254) 35 (last_trace_width 0.254)
36 (trace_clearance 0.254) 36 (trace_clearance 0.254)
37 (zone_clearance 0.508) 37 (zone_clearance 0.508)
38 (zone_45_only no) 38 (zone_45_only no)
39 (trace_min 0.254) 39 (trace_min 0.254)
40 (segment_width 0.2) 40 (segment_width 0.2)
41 (edge_width 0.15) 41 (edge_width 0.15)
42 (via_size 0.889) 42 (via_size 0.889)
43 (via_drill 0.635) 43 (via_drill 0.635)
44 (via_min_size 0.889) 44 (via_min_size 0.889)
45 (via_min_drill 0.508) 45 (via_min_drill 0.508)
46 (uvia_size 0.508) 46 (uvia_size 0.508)
47 (uvia_drill 0.127) 47 (uvia_drill 0.127)
48 (uvias_allowed no) 48 (uvias_allowed no)
49 (uvia_min_size 0.508) 49 (uvia_min_size 0.508)
50 (uvia_min_drill 0.127) 50 (uvia_min_drill 0.127)
51 (pcb_text_width 0.3) 51 (pcb_text_width 0.3)
52 (pcb_text_size 1 1) 52 (pcb_text_size 1 1)
53 (mod_edge_width 0.15) 53 (mod_edge_width 0.15)
54 (mod_text_size 1 1) 54 (mod_text_size 1 1)
55 (mod_text_width 0.15) 55 (mod_text_width 0.15)
56 (pad_size 1 1) 56 (pad_size 1 1)
57 (pad_drill 0.6) 57 (pad_drill 0.6)
58 (pad_to_mask_clearance 0) 58 (pad_to_mask_clearance 0)
59 (aux_axis_origin 0 0) 59 (aux_axis_origin 0 0)
60 (visible_elements FFFFFF7F) 60 (visible_elements FFFFFF7F)
61 (pcbplotparams 61 (pcbplotparams
62 (layerselection 3178497) 62 (layerselection 3178497)
63 (usegerberextensions true) 63 (usegerberextensions true)
64 (excludeedgelayer true) 64 (excludeedgelayer true)
65 (linewidth 0.150000) 65 (linewidth 0.150000)
66 (plotframeref false) 66 (plotframeref false)
67 (viasonmask false) 67 (viasonmask false)
68 (mode 1) 68 (mode 1)
69 (useauxorigin false) 69 (useauxorigin false)
70 (hpglpennumber 1) 70 (hpglpennumber 1)
71 (hpglpenspeed 20) 71 (hpglpenspeed 20)
72 (hpglpendiameter 15) 72 (hpglpendiameter 15)
73 (hpglpenoverlay 2) 73 (hpglpenoverlay 2)
74 (psnegative false) 74 (psnegative false)
75 (psa4output false) 75 (psa4output false)
76 (plotreference true) 76 (plotreference true)
77 (plotvalue true) 77 (plotvalue true)
78 (plotothertext true) 78 (plotothertext true)
79 (plotinvisibletext false) 79 (plotinvisibletext false)
80 (padsonsilk false) 80 (padsonsilk false)
81 (subtractmaskfromsilk false) 81 (subtractmaskfromsilk false)
82 (outputformat 1) 82 (outputformat 1)
83 (mirror false) 83 (mirror false)
84 (drillshape 1) 84 (drillshape 1)
85 (scaleselection 1) 85 (scaleselection 1)
86 (outputdirectory "")) 86 (outputdirectory ""))
87 ) 87 )
88   88  
89 (net 0 "") 89 (net 0 "")
90   90  
91 (net_class Default "This is the default net class." 91 (net_class Default "This is the default net class."
92 (clearance 0.254) 92 (clearance 0.254)
93 (trace_width 0.254) 93 (trace_width 0.254)
94 (via_dia 0.889) 94 (via_dia 0.889)
95 (via_drill 0.635) 95 (via_drill 0.635)
96 (uvia_dia 0.508) 96 (uvia_dia 0.508)
97 (uvia_drill 0.127) 97 (uvia_drill 0.127)
98 ) 98 )
99   99  
100 ) 100 )