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-- Company: www.mlab.cz |
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-- Company: www.mlab.cz |
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-- Based on code writen by MIHO. |
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-- Based on code written by MIHO. |
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-- |
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-- |
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-- Create Date: 29/08/2011 |
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|
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-- Design Name: S3AN01A Test Design |
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-- Design Name: S3AN01A |
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-- Project Name: PulseGen |
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-- Project Name: PulseGen |
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-- Target Devices: XC3S50AN-4 |
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-- Target Devices: XC3S50AN-4 |
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-- Tool versions: ISE 13.3 |
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-- Tool versions: ISE 13.3 |
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-- Description: Sample of Pulse Generator at S3AN01A MLAB board. |
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-- Description: Sample of Pulse Generator at S3AN01A MLAB board. |
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-- |
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-- |
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-- Dependencies: External PS/2 Keyboard has to be connected. |
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-- Dependencies: External PS/2 Keyboard has to be connected. |
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-- |
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-- |
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-- Version: $Id: PulseGen.vhd 2533 2012-09-02 13:36:25Z kakl $ |
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-- Version: $Id: PulseGen.vhd 2534 2012-09-02 13:40:37Z kakl $ |
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-- |
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-- |
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---------------------------------------------------------------------------------- |
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---------------------------------------------------------------------------------- |
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|
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|
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library IEEE; |
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library IEEE; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.numeric_std.ALL; |
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use IEEE.numeric_std.ALL; |
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use WORK.PS2_pkg.ALL; |
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use WORK.PS2_pkg.ALL; |
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|
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|
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library UNISIM; |
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library UNISIM; |
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use UNISIM.vcomponents.all; |
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use UNISIM.vcomponents.all; |
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|
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|
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entity PulseGen is |
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entity PulseGen is |
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generic ( |
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generic ( |
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-- Top Value for 100MHz Clock Counter |
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-- Top Value for 100MHz Clock Counter |
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MAXCOUNT: integer := 30_000_000; |
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MAXCOUNT: integer := 30_000_000; |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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); |
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); |
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port ( |
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port ( |
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-- Main Clock |
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-- Main Clock |
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CLK100MHz: in std_logic; |
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CLK100MHz: in std_logic; |
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|
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|
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-- Mode Signals (usualy not used) |
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-- Mode Signals (usualy not used) |
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M: in std_logic_vector(2 downto 0); |
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M: in std_logic_vector(2 downto 0); |
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VS: in std_logic_vector(2 downto 0); |
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VS: in std_logic_vector(2 downto 0); |
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|
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|
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-- Dipswitch Inputs |
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-- Dipswitch Inputs |
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DIPSW: in std_logic_vector(7 downto 0); |
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DIPSW: in std_logic_vector(7 downto 0); |
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|
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|
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-- Push Buttons |
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-- Push Buttons |
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PB: in std_logic_vector(3 downto 0); |
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PB: in std_logic_vector(3 downto 0); |
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|
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|
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-- LED Bar Outputs |
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-- LED Bar Outputs |
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LED: out std_logic_vector(7 downto 0); |
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LED: out std_logic_vector(7 downto 0); |
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|
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|
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-- LED Display (8 digit with 7 segments and ddecimal point) |
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-- LED Display (8 digit with 7 segments and ddecimal point) |
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LD_A_n: out std_logic; |
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LD_A_n: out std_logic; |
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LD_B_n: out std_logic; |
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LD_B_n: out std_logic; |
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LD_C_n: out std_logic; |
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LD_C_n: out std_logic; |
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LD_D_n: out std_logic; |
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LD_D_n: out std_logic; |
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LD_E_n: out std_logic; |
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LD_E_n: out std_logic; |
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LD_F_n: out std_logic; |
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LD_F_n: out std_logic; |
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LD_G_n: out std_logic; |
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LD_G_n: out std_logic; |
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LD_DP_n: out std_logic; |
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LD_DP_n: out std_logic; |
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LD_0_n: out std_logic; |
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LD_0_n: out std_logic; |
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LD_1_n: out std_logic; |
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LD_1_n: out std_logic; |
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LD_2_n: out std_logic; |
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LD_2_n: out std_logic; |
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LD_3_n: out std_logic; |
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LD_3_n: out std_logic; |
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LD_4_n: out std_logic; |
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LD_4_n: out std_logic; |
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LD_5_n: out std_logic; |
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LD_5_n: out std_logic; |
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LD_6_n: out std_logic; |
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LD_6_n: out std_logic; |
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LD_7_n: out std_logic; |
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LD_7_n: out std_logic; |
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|
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|
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-- VGA Video Out Port |
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-- VGA Video Out Port |
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VGA_R: out std_logic_vector(1 downto 0); |
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VGA_R: out std_logic_vector(1 downto 0); |
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VGA_G: out std_logic_vector(1 downto 0); |
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VGA_G: out std_logic_vector(1 downto 0); |
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VGA_B: out std_logic_vector(1 downto 0); |
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VGA_B: out std_logic_vector(1 downto 0); |
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VGA_VS: out std_logic; |
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VGA_VS: out std_logic; |
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VGA_HS: out std_logic; |
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VGA_HS: out std_logic; |
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|
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|
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-- Bank 1 Pins - Inputs for this Test |
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-- Bank 1 Pins - Inputs for this Test |
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B: inout std_logic_vector(24 downto 0); |
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B: inout std_logic_vector(24 downto 0); |
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|
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|
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-- PS/2 Bidirectional Port (open collector, J31 and J32) |
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-- PS/2 Bidirectional Port (open collector, J31 and J32) |
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-- PS2_CLK1: inout std_logic; |
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-- PS2_CLK1: inout std_logic; |
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-- PS2_DATA1: inout std_logic; |
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-- PS2_DATA1: inout std_logic; |
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PS2_CLK2: inout std_logic; |
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PS2_CLK2: inout std_logic; |
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PS2_DATA2: inout std_logic; |
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PS2_DATA2: inout std_logic; |
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|
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|
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-- Diferencial Signals on 4 pin header (J7) |
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-- Diferencial Signals on 4 pin header (J7) |
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DIF1P: inout std_logic; |
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DIF1P: inout std_logic; |
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DIF1N: inout std_logic; |
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DIF1N: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2N: inout std_logic; |
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DIF2N: inout std_logic; |
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|
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|
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|
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|
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-- I2C Signals (on connector J30) |
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-- I2C Signals (on connector J30) |
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I2C_SCL: inout std_logic; |
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I2C_SCL: inout std_logic; |
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I2C_SDA: inout std_logic; |
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I2C_SDA: inout std_logic; |
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|
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|
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-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
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-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
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SD1AP: inout std_logic; |
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SD1AP: inout std_logic; |
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SD1AN: inout std_logic; |
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SD1AN: inout std_logic; |
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SD1BP: inout std_logic; |
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SD1BP: inout std_logic; |
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SD1BN: inout std_logic; |
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SD1BN: inout std_logic; |
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SD2AP: inout std_logic; |
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SD2AP: inout std_logic; |
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SD2AN: inout std_logic; |
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SD2AN: inout std_logic; |
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SD2BP: inout std_logic; |
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SD2BP: inout std_logic; |
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SD2BN: inout std_logic; |
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SD2BN: inout std_logic; |
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|
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|
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-- Analog In Out |
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-- Analog In Out |
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ANA_OUTD: out std_logic; |
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ANA_OUTD: out std_logic; |
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ANA_REFD: out std_logic; |
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ANA_REFD: out std_logic; |
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ANA_IND: in std_logic; |
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ANA_IND: in std_logic; |
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|
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|
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-- SPI Memory Interface |
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-- SPI Memory Interface |
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SPI_CS_n: inout std_logic; |
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SPI_CS_n: inout std_logic; |
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SPI_DO: inout std_logic; |
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SPI_DO: inout std_logic; |
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SPI_DI: inout std_logic; |
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SPI_DI: inout std_logic; |
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SPI_CLK: inout std_logic; |
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SPI_CLK: inout std_logic; |
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SPI_WP_n: inout std_logic |
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SPI_WP_n: inout std_logic |
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); |
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); |
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end entity PulseGen; |
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end entity PulseGen; |
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|
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|
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|
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|
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architecture PulseGen_a of PulseGen is |
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architecture PulseGen_a of PulseGen is |
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|
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|
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function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is |
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function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is |
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variable i : integer:=0; |
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variable i : integer:=0; |
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variable mybcd : std_logic_vector(11 downto 0) := (others => '0'); |
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variable mybcd : std_logic_vector(11 downto 0) := (others => '0'); |
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variable bint : std_logic_vector(7 downto 0) := bin; |
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variable bint : std_logic_vector(7 downto 0) := bin; |
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begin |
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begin |
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for i in 0 to 7 loop -- repeating 8 times. |
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for i in 0 to 7 loop -- repeating 8 times. |
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mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits. |
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mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits. |
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mybcd(0) := bint(7); |
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mybcd(0) := bint(7); |
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bint(7 downto 1) := bint(6 downto 0); |
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bint(7 downto 1) := bint(6 downto 0); |
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bint(0) :='0'; |
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bint(0) :='0'; |
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|
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|
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|
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|
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if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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end if; |
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end if; |
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end loop; |
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end loop; |
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|
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|
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return mybcd; |
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return mybcd; |
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end to_bcd; |
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end to_bcd; |
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|
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|
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|
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|
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-- O1: ____|^^^^^^^|______ |
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-- O1: ____|^^^^^^^|______ |
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-- O2: _________|^^|______ |
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-- O2: _________|^^|______ |
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-- t1 t2 |
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-- t1 t2 |
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-- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz |
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-- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz |
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|
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|
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signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2 |
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signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2 |
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signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2 |
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signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2 |
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signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer |
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signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer |
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signal O1: std_logic := '0'; -- Output 1 |
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signal O1: std_logic := '0'; -- Output 1 |
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signal O2: std_logic := '0'; -- Output 2 |
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signal O2: std_logic := '0'; -- Output 2 |
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signal CTburst: unsigned(15 downto 0) := X"0000"; -- Pulse counter |
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signal CTburst: unsigned(15 downto 0) := X"0000"; -- Pulse counter |
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|
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|
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-- LED Demo Signals |
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-- LED Demo Signals |
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-- ---------------- |
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-- ---------------- |
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|
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|
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signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary) |
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signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary) |
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signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) |
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signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) |
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|
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|
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signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) |
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signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) |
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|
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|
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-- LED Display |
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-- LED Display |
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-- ----------- |
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-- ----------- |
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|
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|
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signal Number: std_logic_vector(32 downto 0); -- LED Display Input |
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signal Number: std_logic_vector(32 downto 0); -- LED Display Input |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal Enable: std_logic; |
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signal Enable: std_logic; |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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|
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|
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-- PS/2 Port |
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-- PS/2 Port |
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-- --------- |
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-- --------- |
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|
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|
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-- Interface Signals |
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-- Interface Signals |
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signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code |
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signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code |
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signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
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signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code |
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signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock) |
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signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock) |
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signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code |
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signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code |
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|
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|
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-- Result |
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-- Result |
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signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory) |
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signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory) |
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|
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|
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-- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese |
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-- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese |
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|
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|
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-- VGA Demo Signals |
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-- VGA Demo Signals |
195 |
-- ---------------- |
194 |
-- ---------------- |
196 |
|
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|
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signal CLK: std_logic; -- Main Clock - global distribution network |
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signal CLK: std_logic; -- Main Clock - global distribution network |
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signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG |
197 |
signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG |
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signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network |
198 |
signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network |
200 |
signal VGA_Blank: boolean; -- Blank |
199 |
signal VGA_Blank: boolean; -- Blank |
201 |
signal VGA_Hsync: boolean; -- Horisontal Synchronisation |
200 |
signal VGA_Hsync: boolean; -- Horisontal Synchronisation |
202 |
signal VGA_Vsync: boolean; -- Vertical Synchronisation |
201 |
signal VGA_Vsync: boolean; -- Vertical Synchronisation |
203 |
|
202 |
|
204 |
signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter |
203 |
signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter |
205 |
signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter |
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signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter |
206 |
|
205 |
|
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signal PinState: std_logic; -- For IB1 Port Test |
206 |
signal PinState: std_logic; -- For IB1 Port Test |
208 |
signal Red: std_logic_vector(1 downto 0); |
207 |
signal Red: std_logic_vector(1 downto 0); |
209 |
signal Green: std_logic_vector(1 downto 0); |
208 |
signal Green: std_logic_vector(1 downto 0); |
210 |
signal Blue: std_logic_vector(1 downto 0); |
209 |
signal Blue: std_logic_vector(1 downto 0); |
211 |
|
210 |
|
212 |
-- ADDA |
211 |
-- ADDA |
213 |
signal ADDA_DataIn: std_logic_vector(7 downto 0); |
212 |
signal ADDA_DataIn: std_logic_vector(7 downto 0); |
214 |
|
213 |
|
215 |
begin |
214 |
begin |
216 |
|
215 |
|
217 |
-- Basic LED Blinking Test |
216 |
-- Basic LED Blinking Test |
218 |
-- ======================= |
217 |
-- ======================= |
219 |
|
218 |
|
220 |
-- LED Bar Counter |
219 |
-- LED Bar Counter |
221 |
process (CLK100MHz) |
220 |
process (CLK100MHz) |
222 |
begin |
221 |
begin |
223 |
if rising_edge(CLK100MHz) then |
222 |
if rising_edge(CLK100MHz) then |
224 |
if Counter < MAXCOUNT-1 then |
223 |
if Counter < MAXCOUNT-1 then |
225 |
Counter <= Counter + 1; |
224 |
Counter <= Counter + 1; |
226 |
else |
225 |
else |
227 |
Counter <= (others => '0'); |
226 |
Counter <= (others => '0'); |
228 |
Bar <= Bar + 1; |
227 |
Bar <= Bar + 1; |
229 |
end if; |
228 |
end if; |
230 |
end if; |
229 |
end if; |
231 |
end process; |
230 |
end process; |
232 |
|
231 |
|
233 |
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter |
232 |
LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter |
234 |
|
233 |
|
235 |
FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity |
234 |
FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity |
236 |
|
235 |
|
237 |
-- LED Display (multiplexed) |
236 |
-- LED Display (multiplexed) |
238 |
-- ========================= |
237 |
-- ========================= |
239 |
|
238 |
|
240 |
-- Connect LED Display Output Ports (negative outputs) |
239 |
-- Connect LED Display Output Ports (negative outputs) |
241 |
LD_A_n <= not (Segments(0) and Enable); |
240 |
LD_A_n <= not (Segments(0) and Enable); |
242 |
LD_B_n <= not (Segments(1) and Enable); |
241 |
LD_B_n <= not (Segments(1) and Enable); |
243 |
LD_C_n <= not (Segments(2) and Enable); |
242 |
LD_C_n <= not (Segments(2) and Enable); |
244 |
LD_D_n <= not (Segments(3) and Enable); |
243 |
LD_D_n <= not (Segments(3) and Enable); |
245 |
LD_E_n <= not (Segments(4) and Enable); |
244 |
LD_E_n <= not (Segments(4) and Enable); |
246 |
LD_F_n <= not (Segments(5) and Enable); |
245 |
LD_F_n <= not (Segments(5) and Enable); |
247 |
LD_G_n <= not (Segments(6) and Enable); |
246 |
LD_G_n <= not (Segments(6) and Enable); |
248 |
LD_DP_n <= not (Segments(7) and Enable); |
247 |
LD_DP_n <= not (Segments(7) and Enable); |
249 |
|
248 |
|
250 |
LD_0_n <= not Digits(0); |
249 |
LD_0_n <= not Digits(0); |
251 |
LD_1_n <= not Digits(1); |
250 |
LD_1_n <= not Digits(1); |
252 |
LD_2_n <= not Digits(2); |
251 |
LD_2_n <= not Digits(2); |
253 |
LD_3_n <= not Digits(3); |
252 |
LD_3_n <= not Digits(3); |
254 |
LD_4_n <= not Digits(4); |
253 |
LD_4_n <= not Digits(4); |
255 |
LD_5_n <= not Digits(5); |
254 |
LD_5_n <= not Digits(5); |
256 |
LD_6_n <= not Digits(6); |
255 |
LD_6_n <= not Digits(6); |
257 |
LD_7_n <= not Digits(7); |
256 |
LD_7_n <= not Digits(7); |
258 |
|
257 |
|
259 |
-- Time Multiplex |
258 |
-- Time Multiplex |
260 |
process (CLK100MHz) |
259 |
process (CLK100MHz) |
261 |
begin |
260 |
begin |
262 |
if rising_edge(CLK100MHz) then |
261 |
if rising_edge(CLK100MHz) then |
263 |
if MuxCounter < MUXCOUNT-1 then |
262 |
if MuxCounter < MUXCOUNT-1 then |
264 |
MuxCounter <= MuxCounter + 1; |
263 |
MuxCounter <= MuxCounter + 1; |
265 |
else |
264 |
else |
266 |
MuxCounter <= (others => '0'); |
265 |
MuxCounter <= (others => '0'); |
267 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
266 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
268 |
Enable <= '0'; |
267 |
Enable <= '0'; |
269 |
end if; |
268 |
end if; |
270 |
if MuxCounter > (MUXCOUNT-4) then |
269 |
if MuxCounter > (MUXCOUNT-4) then |
271 |
Enable <= '1'; |
270 |
Enable <= '1'; |
272 |
end if; |
271 |
end if; |
273 |
end if; |
272 |
end if; |
274 |
end process; |
273 |
end process; |
275 |
|
274 |
|
276 |
-- BCD to 7 Segmet Decoder |
275 |
-- BCD to 7 Segmet Decoder |
277 |
-- -- A |
276 |
-- -- A |
278 |
-- | | F B |
277 |
-- | | F B |
279 |
-- -- G |
278 |
-- -- G |
280 |
-- | | E C |
279 |
-- | | E C |
281 |
-- -- D H |
280 |
-- -- D H |
282 |
-- ABCDEFGH |
281 |
-- ABCDEFGH |
283 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
282 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
284 |
"01100000" when Code="0001" else -- Digit 1 |
283 |
"01100000" when Code="0001" else -- Digit 1 |
285 |
"11011010" when Code="0010" else -- Digit 2 |
284 |
"11011010" when Code="0010" else -- Digit 2 |
286 |
"11110010" when Code="0011" else -- Digit 3 |
285 |
"11110010" when Code="0011" else -- Digit 3 |
287 |
"01100110" when Code="0100" else -- Digit 4 |
286 |
"01100110" when Code="0100" else -- Digit 4 |
288 |
"10110110" when Code="0101" else -- Digit 5 |
287 |
"10110110" when Code="0101" else -- Digit 5 |
289 |
"10111110" when Code="0110" else -- Digit 6 |
288 |
"10111110" when Code="0110" else -- Digit 6 |
290 |
"11100000" when Code="0111" else -- Digit 7 |
289 |
"11100000" when Code="0111" else -- Digit 7 |
291 |
"11111110" when Code="1000" else -- Digit 8 |
290 |
"11111110" when Code="1000" else -- Digit 8 |
292 |
"11110110" when Code="1001" else -- Digit 9 |
291 |
"11110110" when Code="1001" else -- Digit 9 |
293 |
"11101110" when Code="1010" else -- Digit A |
292 |
"11101110" when Code="1010" else -- Digit A |
294 |
"00111110" when Code="1011" else -- Digit b |
293 |
"00111110" when Code="1011" else -- Digit b |
295 |
"10011100" when Code="1100" else -- Digit C |
294 |
"10011100" when Code="1100" else -- Digit C |
296 |
"01111010" when Code="1101" else -- Digit d |
295 |
"01111010" when Code="1101" else -- Digit d |
297 |
"10011110" when Code="1110" else -- Digit E |
296 |
"10011110" when Code="1110" else -- Digit E |
298 |
"10001110" when Code="1111" else -- Digit F |
297 |
"10001110" when Code="1111" else -- Digit F |
299 |
"00000000"; |
298 |
"00000000"; |
300 |
|
299 |
|
301 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
300 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
302 |
Number( 7 downto 4) when Digits="00000010" else |
301 |
Number( 7 downto 4) when Digits="00000010" else |
303 |
Number(11 downto 8) when Digits="00000100" else |
302 |
Number(11 downto 8) when Digits="00000100" else |
304 |
Number(15 downto 12) when Digits="00001000" else |
303 |
Number(15 downto 12) when Digits="00001000" else |
305 |
Number(19 downto 16) when Digits="00010000" else |
304 |
Number(19 downto 16) when Digits="00010000" else |
306 |
Number(23 downto 20) when Digits="00100000" else |
305 |
Number(23 downto 20) when Digits="00100000" else |
307 |
Number(27 downto 24) when Digits="01000000" else |
306 |
Number(27 downto 24) when Digits="01000000" else |
308 |
Number(31 downto 28) when Digits="10000000" else |
307 |
Number(31 downto 28) when Digits="10000000" else |
309 |
"0000"; |
308 |
"0000"; |
310 |
|
309 |
|
311 |
-- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0 |
310 |
-- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0 |
312 |
-- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1 |
311 |
-- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1 |
313 |
-- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2 |
312 |
-- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2 |
314 |
-- "11111111"; |
313 |
-- "11111111"; |
315 |
|
314 |
|
316 |
-- Number(31 downto 28) <= Key(3 downto 0); |
315 |
-- Number(31 downto 28) <= Key(3 downto 0); |
317 |
|
316 |
|
318 |
-- Number( 7 downto 0) <= std_logic_vector(BAR); |
317 |
-- Number( 7 downto 0) <= std_logic_vector(BAR); |
319 |
-- Number(31 downto 24) <= DIPSW; |
318 |
-- Number(31 downto 24) <= DIPSW; |
320 |
|
319 |
|
321 |
-- PS/2 Port |
320 |
-- PS/2 Port |
322 |
-- ========= |
321 |
-- ========= |
323 |
|
322 |
|
324 |
-- Instantiate PS/2 Keyboard Interface Handler |
323 |
-- Instantiate PS/2 Keyboard Interface Handler |
325 |
PS2_Keyboard: PS2 generic map( |
324 |
PS2_Keyboard: PS2 generic map( |
326 |
CLKFREQ => 100_000_000 |
325 |
CLKFREQ => 100_000_000 |
327 |
) |
326 |
) |
328 |
port map( |
327 |
port map( |
329 |
-- Main Clock |
328 |
-- Main Clock |
330 |
Clk => CLK100MHz, |
329 |
Clk => CLK100MHz, |
331 |
|
330 |
|
332 |
-- PS/2 Port |
331 |
-- PS/2 Port |
333 |
PS2_Clk => PS2_CLK2, |
332 |
PS2_Clk => PS2_CLK2, |
334 |
PS2_Data => PS2_DATA2, |
333 |
PS2_Data => PS2_DATA2, |
335 |
|
334 |
|
336 |
-- Result - valid when PS2_Valid |
335 |
-- Result - valid when PS2_Valid |
337 |
PS2_Code => PS2_Code, |
336 |
PS2_Code => PS2_Code, |
338 |
PS2_Attribs => PS2_Attribs, |
337 |
PS2_Attribs => PS2_Attribs, |
339 |
PS2_Valid => PS2_Valid, |
338 |
PS2_Valid => PS2_Valid, |
340 |
|
339 |
|
341 |
-- Immediate State of Shifts |
340 |
-- Immediate State of Shifts |
342 |
PS2_Shifts => PS2_Shifts |
341 |
PS2_Shifts => PS2_Shifts |
343 |
); -- PS2 |
342 |
); -- PS2 |
344 |
|
343 |
|
345 |
process (CLK100MHz) |
344 |
process (CLK100MHz) |
346 |
begin |
345 |
begin |
347 |
if rising_edge(CLK100MHz) then |
346 |
if rising_edge(CLK100MHz) then |
348 |
if PS2_Valid and PS2_Attribs(7)='0' then |
347 |
if PS2_Valid and PS2_Attribs(7)='0' then |
349 |
-- Valid Scan Code with no Break Attribute |
348 |
-- Valid Scan Code with no Break Attribute |
350 |
PS2_Result( 7 downto 0) <= PS2_Code; |
349 |
PS2_Result( 7 downto 0) <= PS2_Code; |
351 |
PS2_Result(15 downto 8) <= PS2_Attribs; |
350 |
PS2_Result(15 downto 8) <= PS2_Attribs; |
352 |
end if; |
351 |
end if; |
353 |
|
352 |
|
354 |
if PS2_Valid and PS2_Attribs(7)='0' then |
353 |
if PS2_Valid and PS2_Attribs(7)='0' then |
355 |
if PS2_Code = X"74" and T1<2000 then T1<=T1+1; end if; |
354 |
if PS2_Code = X"74" and T1<2000 then T1<=T1+1; end if; |
356 |
if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if; |
355 |
if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if; |
357 |
if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if; |
356 |
if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if; |
358 |
if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if; |
357 |
if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if; |
359 |
CT0<=X"0000"; |
358 |
CT0<=X"0000"; |
360 |
O1<='0'; |
359 |
O1<='0'; |
361 |
O2<='0'; |
360 |
O2<='0'; |
362 |
CTburst<=X"0000"; |
361 |
CTburst<=X"0000"; |
363 |
end if; |
362 |
end if; |
364 |
|
363 |
|
365 |
if PB(0)='1' then |
364 |
if PB(0)='1' then |
366 |
T1<=X"0000"; |
365 |
T1<=X"0000"; |
367 |
T2<=X"0000"; |
366 |
T2<=X"0000"; |
368 |
end if; |
367 |
end if; |
369 |
|
368 |
|
370 |
if DIPSW(0)='1' then |
369 |
if DIPSW(0)='1' then |
371 |
if CT0>X"F000" then |
370 |
if CT0>X"F000" then |
372 |
CT0<=X"0000"; |
371 |
CT0<=X"0000"; |
373 |
else |
372 |
else |
374 |
CT0<=CT0+1; |
373 |
CT0<=CT0+1; |
375 |
end if; |
374 |
end if; |
376 |
else |
375 |
else |
377 |
if CT0>X"0200" then |
376 |
if CT0>X"0200" then |
378 |
CT0<=X"0000"; |
377 |
CT0<=X"0000"; |
379 |
else |
378 |
else |
380 |
CT0<=CT0+1; |
379 |
CT0<=CT0+1; |
381 |
end if; |
380 |
end if; |
382 |
end if; |
381 |
end if; |
383 |
|
382 |
|
384 |
if CTburst>2000 then |
383 |
if CTburst>2000 then |
385 |
CTburst<=X"0000"; |
384 |
CTburst<=X"0000"; |
386 |
end if; |
385 |
end if; |
387 |
|
386 |
|
388 |
if (CTburst<1000) or (DIPSW(1)='0') then |
387 |
if (CTburst<1000) or (DIPSW(1)='0') then |
389 |
if CT0=X"0000" then |
388 |
if CT0=X"0000" then |
390 |
O1<='1'; |
389 |
O1<='1'; |
391 |
end if; |
390 |
end if; |
392 |
|
391 |
|
393 |
if CT0=T1+X"0000" then |
392 |
if CT0=T1+X"0000" then |
394 |
O2<='1'; |
393 |
O2<='1'; |
395 |
end if; |
394 |
end if; |
396 |
end if; |
395 |
end if; |
397 |
|
396 |
|
398 |
if CT0=T2+T1+X"0000" then |
397 |
if CT0=T2+T1+X"0000" then |
399 |
O1<='0'; |
398 |
O1<='0'; |
400 |
O2<='0'; |
399 |
O2<='0'; |
401 |
CTburst<=CTburst+1; |
400 |
CTburst<=CTburst+1; |
402 |
end if; |
401 |
end if; |
403 |
|
402 |
|
404 |
end if; |
403 |
end if; |
405 |
|
404 |
|
406 |
end process; |
405 |
end process; |
407 |
|
406 |
|
408 |
-- Display Result on LED |
407 |
-- Display Result on LED |
409 |
Number(3 downto 0) <= (others=>'0'); |
408 |
Number(3 downto 0) <= (others=>'0'); |
410 |
Number(15 downto 4) <= to_bcd(std_logic_vector(T2)); |
409 |
Number(15 downto 4) <= to_bcd(std_logic_vector(T2)); |
411 |
Number(19 downto 16) <= (others=>'0'); |
410 |
Number(19 downto 16) <= (others=>'0'); |
412 |
Number(31 downto 20) <= to_bcd(std_logic_vector(T1)); |
411 |
Number(31 downto 20) <= to_bcd(std_logic_vector(T1)); |
413 |
|
412 |
|
414 |
|
413 |
|
415 |
-- Test Diferencial In/Outs |
414 |
-- Test Diferencial In/Outs |
416 |
-- ======================== |
415 |
-- ======================== |
417 |
|
416 |
|
418 |
-- Output Signal on SATA Connector |
417 |
-- Output Signal on SATA Connector |
419 |
SD1AP <= Bar(0); |
418 |
SD1AP <= Bar(0); |
420 |
SD1AN <= Bar(1); |
419 |
SD1AN <= Bar(1); |
421 |
SD1BP <= Bar(2); |
420 |
SD1BP <= Bar(2); |
422 |
SD1BN <= Bar(3); |
421 |
SD1BN <= Bar(3); |
423 |
|
422 |
|
424 |
-- Input Here via SATA Cable |
423 |
-- Input Here via SATA Cable |
425 |
SD2AP <= 'Z'; |
424 |
SD2AP <= 'Z'; |
426 |
SD2AN <= 'Z'; |
425 |
SD2AN <= 'Z'; |
427 |
SD2BP <= 'Z'; |
426 |
SD2BP <= 'Z'; |
428 |
SD2BN <= 'Z'; |
427 |
SD2BN <= 'Z'; |
429 |
|
428 |
|
430 |
-- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them |
429 |
-- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them |
431 |
-- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!! |
430 |
-- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!! |
432 |
DIF1P <= O1; |
431 |
DIF1P <= O1; |
433 |
B(0) <= O1; |
432 |
B(0) <= O1; |
434 |
DIF1N <= not O1; |
433 |
DIF1N <= not O1; |
435 |
B(1) <= not O1; |
434 |
B(1) <= not O1; |
436 |
DIF2P <= O2; |
435 |
DIF2P <= O2; |
437 |
B(2) <= O2; |
436 |
B(2) <= O2; |
438 |
DIF2N <= not O2; |
437 |
DIF2N <= not O2; |
439 |
B(3) <= not O2; |
438 |
B(3) <= not O2; |
440 |
|
439 |
|
441 |
VGA_R(0) <= O1; |
440 |
VGA_R(0) <= O1; |
442 |
VGA_R(1) <= O2; |
441 |
VGA_R(1) <= O2; |
443 |
|
442 |
|
444 |
-- Unused Signals |
443 |
-- Unused Signals |
445 |
-- ============== |
444 |
-- ============== |
446 |
|
445 |
|
447 |
-- I2C Signals (on connector J30) |
446 |
-- I2C Signals (on connector J30) |
448 |
I2C_SCL <= 'Z'; |
447 |
I2C_SCL <= 'Z'; |
449 |
I2C_SDA <= 'Z'; |
448 |
I2C_SDA <= 'Z'; |
450 |
|
449 |
|
451 |
-- SPI Memory Interface |
450 |
-- SPI Memory Interface |
452 |
SPI_CS_n <= 'Z'; |
451 |
SPI_CS_n <= 'Z'; |
453 |
SPI_DO <= 'Z'; |
452 |
SPI_DO <= 'Z'; |
454 |
SPI_DI <= 'Z'; |
453 |
SPI_DI <= 'Z'; |
455 |
SPI_CLK <= 'Z'; |
454 |
SPI_CLK <= 'Z'; |
456 |
SPI_WP_n <= 'Z'; |
455 |
SPI_WP_n <= 'Z'; |
457 |
|
456 |
|
458 |
ANA_OUTD <= 'Z'; |
457 |
ANA_OUTD <= 'Z'; |
459 |
ANA_REFD <= 'Z'; |
458 |
ANA_REFD <= 'Z'; |
460 |
|
459 |
|
461 |
VGA_R <= "ZZ"; |
460 |
VGA_R <= "ZZ"; |
462 |
VGA_G <= "ZZ"; |
461 |
VGA_G <= "ZZ"; |
463 |
VGA_B <= "ZZ"; |
462 |
VGA_B <= "ZZ"; |
464 |
VGA_VS <= 'Z'; |
463 |
VGA_VS <= 'Z'; |
465 |
VGA_HS <= 'Z'; |
464 |
VGA_HS <= 'Z'; |
466 |
|
465 |
|
467 |
end architecture PulseGen_a; |
466 |
end architecture PulseGen_a; |