Rev 3091 Rev 3243
1 -- ======================================================================== 1 -- ========================================================================
2 -- 2 --
3 -- S3AN01_ChipScope 3 -- S3AN01_ChipScope
4 -- 4 --
5 -- Logic Analyser based on Xilinx ChipScope IP Core for S3AN01 Board 5 -- Logic Analyser based on Xilinx ChipScope IP Core for S3AN01 Board
6 -- 6 --
7 -- (c) miho 2013 / http://www.mlab.cz/PermaLink/XILINX_ChipScope 7 -- (c) miho 2013 / http://www.mlab.cz/PermaLink/XILINX_ChipScope
8 -- 8 --
9 -- Demo application contains some Clock Logic (DCM block and 9 -- Demo application contains some Clock Logic (DCM block and
10 -- clock switch to be able to set different sample clocks). 10 -- clock switch to be able to set different sample clocks).
11 -- The main function is ChipScope Logic Analyser with 16 data inputs 11 -- The main function is ChipScope Logic Analyser with 16 data inputs
12 -- (with 24 bit trigger) and storage for 1024 Data Samples. 12 -- (with 24 bit trigger) and storage for 1024 Data Samples.
13 -- 13 --
14 -- Sampling clock is selectable to 170/100/50/20/10/5/2/1MHz 14 -- Sampling clock is selectable to 170/100/50/20/10/5/2/1MHz
15 -- 15 --
16 -- To implement the design the ChipScope license is required. 16 -- To implement the design the ChipScope license is required.
17 -- 17 --
18 -- To use (the logic analyser) no speceial license is needed, 18 -- To use (the logic analyser) no speceial license is needed,
19 -- WebPack ISE or Lab Tools is enough). Requires some compatible 19 -- WebPack ISE or Lab Tools is enough). Requires some compatible
20 -- JTAG cable. Compatible with MLAB Xilinx Virtual Cable as well 20 -- JTAG cable. Compatible with MLAB Xilinx Virtual Cable as well
21 -- http://www.mlab.cz/PermaLink/XILINX_XVC 21 -- http://www.mlab.cz/PermaLink/XILINX_XVC
22 -- 22 --
23 -- Device: Spartan3AN XC3S50AN-4TQG144C 23 -- Device: Spartan3AN XC3S50AN-4TQG144C
24 -- 24 --
25 -- Software: ISE WebPack 14.5 25 -- Software: ISE WebPack 14.5
26 -- 26 --
27 -- ======================================================================== 27 -- ========================================================================
28   28  
29   29  
30 -- Standard Library 30 -- Standard Library
31 library IEEE; 31 library IEEE;
32 use IEEE.STD_LOGIC_1164.ALL; 32 use IEEE.STD_LOGIC_1164.ALL;
33 use IEEE.numeric_std.ALL; 33 use IEEE.numeric_std.ALL;
34   34  
35   35  
36 -- Xilinx Library (necessary for DMC and other Xilinx blocks) 36 -- Xilinx Library (necessary for DMC and other Xilinx blocks)
37 library UNISIM; 37 library UNISIM;
38 use UNISIM.VComponents.all; 38 use UNISIM.VComponents.all;
39   39  
40   40  
41 -- Interface 41 -- Interface
42 entity S3AN01_ChipScope is 42 entity S3AN01_ChipScope is
43 generic( 43 generic(
44 ILA_WIDE: boolean := TRUE; -- TRUE/FALSE -> 18bit x 1024 / 9bit x 2048 logic analyser 44 ILA_WIDE: boolean := TRUE; -- TRUE/FALSE -> 18bit x 1024 / 9bit x 2048 logic analyser
45 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider 45 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
46 ); 46 );
47 port( 47 port(
48 -- Main Clock 48 -- Main Clock
49 CLK100MHz: in std_logic; -- 100MHz external xtal clock source 49 CLK100MHz: in std_logic; -- 100MHz external xtal clock source
50   50  
51 -- Mode Signals (usualy not used) 51 -- Mode Signals (usualy not used)
52 VS: out std_logic_vector(2 downto 0); -- SPI Flash Vendor Mode Select 52 VS: out std_logic_vector(2 downto 0); -- SPI Flash Vendor Mode Select
53   53  
54 -- Dipswitch Inputs 54 -- Dipswitch Inputs
55 DIPSW: in std_logic_vector(7 downto 0); 55 DIPSW: in std_logic_vector(7 downto 0);
56   56  
57 -- LED Bar Outputs 57 -- LED Bar Outputs
58 LED: out std_logic_vector(7 downto 0); 58 LED: out std_logic_vector(7 downto 0);
59   59  
60 -- LED Display (8 digits with 7 segments and decimal point) 60 -- LED Display (8 digits with 7 segments and decimal point)
61 LD_CA_n: out std_logic_vector(7 downto 0); 61 LD_CA_n: out std_logic_vector(7 downto 0);
62 LD_SEG_n: out std_logic_vector(7 downto 0); 62 LD_SEG_n: out std_logic_vector(7 downto 0);
63   63  
64 -- Bank 1 Pins Inputs 64 -- Bank 1 Pins Inputs
65 P: in std_logic_vector(24 downto 0); 65 P: in std_logic_vector(24 downto 0);
66   66  
67 -- Diferencial Signals on 4 pin header (J7) 67 -- Diferencial Signals on 4 pin header (J7)
68 DIF1P: inout std_logic; 68 DIF1P: inout std_logic;
69 DIF1N: inout std_logic; 69 DIF1N: inout std_logic;
70 DIF2P: inout std_logic; 70 DIF2P: inout std_logic;
71 DIF2N: inout std_logic 71 DIF2N: inout std_logic
72 ); 72 );
73 end S3AN01_ChipScope; 73 end S3AN01_ChipScope;
74   74  
75   75  
76 -- Implementation 76 -- Implementation
77 architecture S3AN01_ChipScope_a of S3AN01_ChipScope is 77 architecture S3AN01_ChipScope_a of S3AN01_ChipScope is
78   78  
79 -- Clock Signals 79 -- Clock Signals
80 -- ============= 80 -- =============
81   81  
82 -- DCM Signals 82 -- DCM Signals
83 signal DCM_CLK0: std_logic; -- DCM output for feedback 83 signal DCM_CLK0: std_logic; -- DCM output for feedback
84 signal DCM_CLKFX: std_logic; -- DCM output of the fastest clock 84 signal DCM_CLKFX: std_logic; -- DCM output of the fastest clock
85 signal CLK_FAST: std_logic; -- Main clock for ILA 85 signal CLK_FAST: std_logic; -- Main clock for ILA
86 signal CLK_FAST_Q: std_logic; -- Auxiliary signal (for CLK_FAST sent to pin) 86 signal CLK_FAST_Q: std_logic; -- Auxiliary signal (for CLK_FAST sent to pin)
87   87  
88 -- 100MHz Clock Switch 88 -- 100MHz Clock Switch
89 -- CLK100MHz Clock Domain 89 -- CLK100MHz Clock Domain
90 signal CLK100MHz_CE: std_logic; -- Gate Signal for slow dwn of the 100MHz clock 90 signal CLK100MHz_CE: std_logic; -- Gate Signal for slow dwn of the 100MHz clock
91 signal CLK100MHz_Gated: std_logic; -- Gated Clocks 91 signal CLK100MHz_Gated: std_logic; -- Gated Clocks
92 signal CLK100MHz_CE_Cnt: unsigned(6 downto 0) := (others => '0'); -- Gate Signal Counter (min frequency is 1/100 of CLK100MHz 92 signal CLK100MHz_CE_Cnt: unsigned(6 downto 0) := (others => '0'); -- Gate Signal Counter (min frequency is 1/100 of CLK100MHz
93   93  
94 -- 1 Hot Clock Select Signals 94 -- 1 Hot Clock Select Signals
95 -- CLK100MHz Clock Domain 95 -- CLK100MHz Clock Domain
96 signal SET_CLK_MAX: std_logic := '0'; -- Clock Select Signal - Maximim (150-170Mhz) 96 signal SET_CLK_MAX: std_logic := '0'; -- Clock Select Signal - Maximim (150-170Mhz)
97 signal SET_CLK_100MHz: std_logic := '1'; -- Clock Select Signal - 100MHz 97 signal SET_CLK_100MHz: std_logic := '1'; -- Clock Select Signal - 100MHz
98 signal SET_CLK_50MHz: std_logic := '0'; -- Clock Select Signal - 50MHz 98 signal SET_CLK_50MHz: std_logic := '0'; -- Clock Select Signal - 50MHz
99 signal SET_CLK_20Mhz: std_logic := '0'; -- Clock Select Signal - 20MHz 99 signal SET_CLK_20Mhz: std_logic := '0'; -- Clock Select Signal - 20MHz
100 signal SET_CLK_10Mhz: std_logic := '0'; -- Clock Select Signal - 10MHz 100 signal SET_CLK_10Mhz: std_logic := '0'; -- Clock Select Signal - 10MHz
101 signal SET_CLK_5Mhz: std_logic := '0'; -- Clock Select Signal - 5MHz 101 signal SET_CLK_5Mhz: std_logic := '0'; -- Clock Select Signal - 5MHz
102 signal SET_CLK_2Mhz: std_logic := '0'; -- Clock Select Signal - 2MHz 102 signal SET_CLK_2Mhz: std_logic := '0'; -- Clock Select Signal - 2MHz
103 signal SET_CLK_1Mhz: std_logic := '0'; -- Clock Select Signal - 1MHz 103 signal SET_CLK_1Mhz: std_logic := '0'; -- Clock Select Signal - 1MHz
104   104  
105 -- Signals from and to ChipScope Virtual IO (set and display frequency) 105 -- Signals from and to ChipScope Virtual IO (set and display frequency)
106 -- CLK_FAST and CLK100MHz time domain 106 -- CLK_FAST and CLK100MHz time domain
107 signal SYNC_IN: std_logic_vector(7 downto 0); -- Input to ChipScope VIO 107 signal SYNC_IN: std_logic_vector(7 downto 0); -- Input to ChipScope VIO
108 signal SYNC_OUT: std_logic_vector(7 downto 0); -- Output from ChipScope VIO 108 signal SYNC_OUT: std_logic_vector(7 downto 0); -- Output from ChipScope VIO
109 signal SW_SYNC: std_logic_vector(7 downto 0) := (others => '0'); -- Asyn inputs synced 109 signal SW_SYNC: std_logic_vector(7 downto 0) := (others => '0'); -- Asyn inputs synced
110   110  
111   111  
112 -- LED Ouput with time multiplex 112 -- LED Ouput with time multiplex
113 -- ============================= 113 -- =============================
114   114  
115 signal WideBCD: std_logic_vector(2*5-1 downto 0); -- Constant width of ILA in BCD (2 char wide) 115 signal WideBCD: std_logic_vector(2*5-1 downto 0); -- Constant width of ILA in BCD (2 char wide)
116 signal FrequencyBCD: std_logic_vector(3*5-1 downto 0); -- Selected frequency in BCD (3 char wide) 116 signal FrequencyBCD: std_logic_vector(3*5-1 downto 0); -- Selected frequency in BCD (3 char wide)
117 signal Code: std_logic_vector(4 downto 0); -- BCD to 7 Segment Decoder Output 117 signal Code: std_logic_vector(4 downto 0); -- BCD to 7 Segment Decoder Output
118 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output 118 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
119   119  
120 -- Time Multiplex 120 -- Time Multiplex
121 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider 121 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
122 signal LedEnable: std_logic; -- LED Display Brightness 122 signal LedEnable: std_logic; -- LED Display Brightness
123 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output 123 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
124   124  
125   125  
126 -- Test Generator signals 126 -- Test Generator signals
127 -- ====================== 127 -- ======================
128 128
129 signal Counter: std_logic_vector(7 downto 0); -- Counter 129 signal Counter: std_logic_vector(7 downto 0); -- Counter
130   130  
131   131  
132 -- ChipScope Signals 132 -- ChipScope Signals
133 -- ================= 133 -- =================
134   134  
135 -- Input data 135 -- Input data
136 -- CLK_FAST Clock Domain 136 -- CLK_FAST Clock Domain
137 signal DataReg: std_logic_vector(P'range); -- Data and Trigger input 137 signal DataReg: std_logic_vector(P'range); -- Data and Trigger input
138 138
139 -- Trigger Output 139 -- Trigger Output
140 signal TriggerOut: std_logic; -- Trigegr output from ChipScope ILA to pin 140 signal TriggerOut: std_logic; -- Trigegr output from ChipScope ILA to pin
141   141  
142 -- User Outputs from ChipScope Virtual IO 142 -- User Outputs from ChipScope Virtual IO
143 signal SYNC_OUT_USER: std_logic_vector(2 downto 0); -- Output from ChipScope VIO 143 signal SYNC_OUT_USER: std_logic_vector(2 downto 0); -- Output from ChipScope VIO
144   144  
145 -- ChipScope Control Signals 145 -- ChipScope Control Signals
146 signal Control0: std_logic_vector(35 downto 0); 146 signal Control0: std_logic_vector(35 downto 0);
147 signal Control1: std_logic_vector(35 downto 0); 147 signal Control1: std_logic_vector(35 downto 0);
148 signal Control2: std_logic_vector(35 downto 0); 148 signal Control2: std_logic_vector(35 downto 0);
149   149  
150 -- ChipScope Control Block 150 -- ChipScope Control Block
151 component ChipScope_ICON 151 component ChipScope_ICON
152 port ( 152 port (
153 CONTROL0: inout std_logic_vector(35 downto 0); 153 CONTROL0: inout std_logic_vector(35 downto 0);
154 CONTROL1: inout std_logic_vector(35 downto 0); 154 CONTROL1: inout std_logic_vector(35 downto 0);
155 CONTROL2: inout std_logic_vector(35 downto 0) 155 CONTROL2: inout std_logic_vector(35 downto 0)
156 ); 156 );
157 end component; 157 end component;
158   158  
159 -- ChipScope Virtual I/O Block 159 -- ChipScope Virtual I/O Block
160 component ChipScope_VIO_FreqSel 160 component ChipScope_VIO_FreqSel
161 port ( 161 port (
162 CONTROL: inout std_logic_vector(35 downto 0); 162 CONTROL: inout std_logic_vector(35 downto 0);
163 CLK: in std_logic; 163 CLK: in std_logic;
164 SYNC_IN: in std_logic_vector(7 downto 0); 164 SYNC_IN: in std_logic_vector(7 downto 0);
165 SYNC_OUT: out std_logic_vector(7 downto 0) 165 SYNC_OUT: out std_logic_vector(7 downto 0)
166 ); 166 );
167 end component; 167 end component;
168   168  
169 -- ChipScope Virtual I/O Block 169 -- ChipScope Virtual I/O Block
170 component ChipScope_VIO_UserOut 170 component ChipScope_VIO_UserOut
171 port ( 171 port (
172 CONTROL: inout std_logic_vector(35 downto 0); 172 CONTROL: inout std_logic_vector(35 downto 0);
173 CLK: in std_logic; 173 CLK: in std_logic;
174 SYNC_OUT: out std_logic_vector(2 downto 0) 174 SYNC_OUT: out std_logic_vector(2 downto 0)
175 ); 175 );
176 end component; 176 end component;
177   177  
178 -- ChipScope Integrated Logic Analyser 178 -- ChipScope Integrated Logic Analyser
179 component ChipScope_ILA_18_1024 179 component ChipScope_ILA_18_1024
180 port ( 180 port (
181 CONTROL: inout std_logic_vector(35 downto 0); 181 CONTROL: inout std_logic_vector(35 downto 0);
182 CLK: in std_logic; 182 CLK: in std_logic;
183 DATA: in std_logic_vector(17 downto 0); -- 18 bits wide data 183 DATA: in std_logic_vector(17 downto 0); -- 18 bits wide data
184 TRIG0: in std_logic_vector(23 downto 0); 184 TRIG0: in std_logic_vector(23 downto 0);
185 TRIG_OUT: out std_logic 185 TRIG_OUT: out std_logic
186 ); 186 );
187 end component; 187 end component;
188   188  
189 -- ChipScope Integrated Logic Analyser 189 -- ChipScope Integrated Logic Analyser
190 component ChipScope_ILA_9_2048 190 component ChipScope_ILA_9_2048
191 port ( 191 port (
192 CONTROL: inout std_logic_vector(35 downto 0); 192 CONTROL: inout std_logic_vector(35 downto 0);
193 CLK: in std_logic; 193 CLK: in std_logic;
194 DATA: in std_logic_vector(8 downto 0); -- 9 bits wide data 194 DATA: in std_logic_vector(8 downto 0); -- 9 bits wide data
195 TRIG0: in std_logic_vector(23 downto 0); 195 TRIG0: in std_logic_vector(23 downto 0);
196 TRIG_OUT: out std_logic 196 TRIG_OUT: out std_logic
197 ); 197 );
198 end component; 198 end component;
199   199  
200 begin 200 begin
201   201  
202   202  
203 -- =================================================== 203 -- ===================================================
204 -- Clock Network and Clock Switching 204 -- Clock Network and Clock Switching
205 -- =================================================== 205 -- ===================================================
206 -- 206 --
207 -- The fastest clock signal is generated from 100MHz by DCM. 207 -- The fastest clock signal is generated from 100MHz by DCM.
208 -- The design maximim is 170MHz for selected device. 208 -- The design maximim is 170MHz for selected device.
209 -- 209 --
210 -- For lower frequency the 100MHz clocks are gated in BUFGCE 210 -- For lower frequency the 100MHz clocks are gated in BUFGCE
211 -- acording to SET_CLK_xxx signals. 211 -- acording to SET_CLK_xxx signals.
212 -- 212 --
213 -- For Logic Analyser we use 170MHz from DCM or gated 100MHz 213 -- For Logic Analyser we use 170MHz from DCM or gated 100MHz
214 -- switchd by BUFGMUX block. 214 -- switchd by BUFGMUX block.
215 215
216   216  
217 -- DCM_SP: Digital Clock Manager Circuit 217 -- DCM_SP: Digital Clock Manager Circuit
218 -- Spartan-3A 218 -- Spartan-3A
219 -- Xilinx HDL Language Template, version 14.5 219 -- Xilinx HDL Language Template, version 14.5
220 -- 220 --
221 -- CLKFB without BUFG (we do not need phase relation to the original clock) 221 -- CLKFB without BUFG (we do not need phase relation to the original clock)
222 -- 222 --
223 -- Design Limits (XC3S50AN-4): 223 -- Design Limits (XC3S50AN-4):
224 -- 224 --
225 -- 5/3 -> 166MHz - o.k. (best 5.9ns - 169.5MHz) 225 -- 5/3 -> 166MHz - o.k. (best 5.9ns - 169.5MHz)
226 -- 17/10 -> 170MHz - o.k. (best 5.748ns - 174MHz) <------ Used Here 226 -- 17/10 -> 170MHz - o.k. (best 5.748ns - 174MHz) <------ Used Here
227 -- 12/7 -> 171MHz - Timing Error 227 -- 12/7 -> 171MHz - Timing Error
228 -- 7/4 -> 175MHz - Timing Error 228 -- 7/4 -> 175MHz - Timing Error
229 -- 18/10 -> 180MHz - Timing Error 229 -- 18/10 -> 180MHz - Timing Error
230 -- 230 --
231 DCM_SP_inst: DCM_SP 231 DCM_SP_inst: DCM_SP
232 generic map ( 232 generic map (
233 CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 233 CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
234 CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32 234 CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32
235 CLKFX_MULTIPLY => 17, -- Can be any integer from 2 to 32 235 CLKFX_MULTIPLY => 17, -- Can be any integer from 2 to 32
236 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature 236 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
237 CLKIN_PERIOD => 10.0, -- Specify period of input clock 237 CLKIN_PERIOD => 10.0, -- Specify period of input clock
238 CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" 238 CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
239 CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" 239 CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
240 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15 240 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15
241 DLL_FREQUENCY_MODE => "HIGH", -- "HIGH" or "LOW" frequency mode for DLL 241 DLL_FREQUENCY_MODE => "HIGH", -- "HIGH" or "LOW" frequency mode for DLL
242 DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE 242 DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
243 PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 243 PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
244 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE 244 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
245 ) 245 )
246 port map ( 246 port map (
247 CLK0 => DCM_CLK0, -- 0 degree DCM CLK ouptput 247 CLK0 => DCM_CLK0, -- 0 degree DCM CLK ouptput
248 -- CLK180 => CLK180, -- 180 degree DCM CLK output 248 -- CLK180 => CLK180, -- 180 degree DCM CLK output
249 -- CLK270 => CLK270, -- 270 degree DCM CLK output 249 -- CLK270 => CLK270, -- 270 degree DCM CLK output
250 -- CLK2X => CLK2X, -- 2X DCM CLK output 250 -- CLK2X => CLK2X, -- 2X DCM CLK output
251 -- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out 251 -- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
252 -- CLK90 => CLK90, -- 90 degree DCM CLK output 252 -- CLK90 => CLK90, -- 90 degree DCM CLK output
253 -- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE) 253 -- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
254 CLKFX => DCM_CLKFX, -- DCM CLK synthesis out (M/D) 254 CLKFX => DCM_CLKFX, -- DCM CLK synthesis out (M/D)
255 -- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out 255 -- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
256 -- LOCKED => LOCKED, -- DCM LOCK status output 256 -- LOCKED => LOCKED, -- DCM LOCK status output
257 -- PSDONE => PSDONE, -- Dynamic phase adjust done output 257 -- PSDONE => PSDONE, -- Dynamic phase adjust done output
258 -- STATUS => STATUS, -- 8-bit DCM status bits output 258 -- STATUS => STATUS, -- 8-bit DCM status bits output
259 CLKFB => DCM_CLK0, -- DCM clock feedback 259 CLKFB => DCM_CLK0, -- DCM clock feedback
260 CLKIN => CLK100MHz, -- Clock input (from IBUFG, BUFG or DCM) 260 CLKIN => CLK100MHz, -- Clock input (from IBUFG, BUFG or DCM)
261 -- PSCLK => PSCLK, -- Dynamic phase adjust clock input 261 -- PSCLK => PSCLK, -- Dynamic phase adjust clock input
262 -- PSEN => PSEN, -- Dynamic phase adjust enable input 262 -- PSEN => PSEN, -- Dynamic phase adjust enable input
263 -- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement 263 -- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
264 RST => '0' -- DCM asynchronous reset input 264 RST => '0' -- DCM asynchronous reset input
265 ); 265 );
266   266  
267   267  
268 -- Generate Clock Gate signal for 100MHz Clock 268 -- Generate Clock Gate signal for 100MHz Clock
269 process (CLK100MHz) 269 process (CLK100MHz)
270 begin 270 begin
271 if rising_edge(CLK100MHz) then 271 if rising_edge(CLK100MHz) then
272 if CLK100MHz_CE_Cnt=0 then 272 if CLK100MHz_CE_Cnt=0 then
273 CLK100MHz_CE <= '1'; 273 CLK100MHz_CE <= '1';
274 if SET_CLK_100MHz='1' then 274 if SET_CLK_100MHz='1' then
275 CLK100MHz_CE_Cnt <= to_unsigned(1-1, CLK100MHz_CE_Cnt'length); 275 CLK100MHz_CE_Cnt <= to_unsigned(1-1, CLK100MHz_CE_Cnt'length);
276 elsif SET_CLK_50MHz='1' then 276 elsif SET_CLK_50MHz='1' then
277 CLK100MHz_CE_Cnt <= to_unsigned(2-1, CLK100MHz_CE_Cnt'length); 277 CLK100MHz_CE_Cnt <= to_unsigned(2-1, CLK100MHz_CE_Cnt'length);
278 elsif SET_CLK_20MHz='1' then 278 elsif SET_CLK_20MHz='1' then
279 CLK100MHz_CE_Cnt <= to_unsigned(5-1, CLK100MHz_CE_Cnt'length); 279 CLK100MHz_CE_Cnt <= to_unsigned(5-1, CLK100MHz_CE_Cnt'length);
280 elsif SET_CLK_10MHz='1' then 280 elsif SET_CLK_10MHz='1' then
281 CLK100MHz_CE_Cnt <= to_unsigned(10-1, CLK100MHz_CE_Cnt'length); 281 CLK100MHz_CE_Cnt <= to_unsigned(10-1, CLK100MHz_CE_Cnt'length);
282 elsif SET_CLK_5MHz='1' then 282 elsif SET_CLK_5MHz='1' then
283 CLK100MHz_CE_Cnt <= to_unsigned(20-1, CLK100MHz_CE_Cnt'length); 283 CLK100MHz_CE_Cnt <= to_unsigned(20-1, CLK100MHz_CE_Cnt'length);
284 elsif SET_CLK_2MHz='1' then 284 elsif SET_CLK_2MHz='1' then
285 CLK100MHz_CE_Cnt <= to_unsigned(50-1, CLK100MHz_CE_Cnt'length); 285 CLK100MHz_CE_Cnt <= to_unsigned(50-1, CLK100MHz_CE_Cnt'length);
286 elsif SET_CLK_1MHz='1' then 286 elsif SET_CLK_1MHz='1' then
287 CLK100MHz_CE_Cnt <= to_unsigned(100-1, CLK100MHz_CE_Cnt'length); 287 CLK100MHz_CE_Cnt <= to_unsigned(100-1, CLK100MHz_CE_Cnt'length);
288 end if; 288 end if;
289 else 289 else
290 CLK100MHz_CE <= '0'; 290 CLK100MHz_CE <= '0';
291 CLK100MHz_CE_Cnt <= CLK100MHz_CE_Cnt-1; 291 CLK100MHz_CE_Cnt <= CLK100MHz_CE_Cnt-1;
292 end if; 292 end if;
293 end if; 293 end if;
294 end process; 294 end process;
295   295  
296   296  
297 -- Gate 100MHz Clocks (to produce 100/50/20/10/5/2/1 MHz) 297 -- Gate 100MHz Clocks (to produce 100/50/20/10/5/2/1 MHz)
298 -- Generates 5ns pulses with 10/20/50/100/200/500/1000ns period 298 -- Generates 5ns pulses with 10/20/50/100/200/500/1000ns period
299 BUFGCE_CLK100MHz: BUFGCE 299 BUFGCE_CLK100MHz: BUFGCE
300 port map ( 300 port map (
301 I => CLK100MHz, -- Clock buffer input 301 I => CLK100MHz, -- Clock buffer input
302 CE => CLK100MHz_CE, -- Clock enable input 302 CE => CLK100MHz_CE, -- Clock enable input
303 O => CLK100MHz_Gated -- Clock buffer ouptput 303 O => CLK100MHz_Gated -- Clock buffer ouptput
304 ); 304 );
305   305  
306   306  
307 -- Switch (gated) 100MHz and the fastest Clock signal from DCM 307 -- Switch (gated) 100MHz and the fastest Clock signal from DCM
308 BUFGMUX_CLK_FAST: BUFGMUX 308 BUFGMUX_CLK_FAST: BUFGMUX
309 port map ( 309 port map (
310 I0 => CLK100MHz_Gated, -- Clock0 input -- 100/50/20/10/50/20/1MHz 310 I0 => CLK100MHz_Gated, -- Clock0 input -- 100/50/20/10/50/20/1MHz
311 I1 => DCM_CLKFX, -- Clock1 input -- 170MHz 311 I1 => DCM_CLKFX, -- Clock1 input -- 170MHz
312 S => SET_CLK_MAX, -- Clock select input 312 S => SET_CLK_MAX, -- Clock select input
313 O => CLK_FAST -- Clock MUX output 313 O => CLK_FAST -- Clock MUX output
314 ); 314 );
315   315  
316   316  
317 -- Assynchrnous inputs and inputs from CLK_FAST clock domain must be synchronised 317 -- Assynchrnous inputs and inputs from CLK_FAST clock domain must be synchronised
318 -- SYNC_OUT - CLK_FAST clock domain 318 -- SYNC_OUT - CLK_FAST clock domain
319 -- DIPSW - External (off-chip) async inputs 319 -- DIPSW - External (off-chip) async inputs
320 process (CLK100MHz) 320 process (CLK100MHz)
321 begin 321 begin
322 if rising_edge(CLK100MHz) then 322 if rising_edge(CLK100MHz) then
323 SW_SYNC <= SYNC_OUT or DIPSW; 323 SW_SYNC <= SYNC_OUT or DIPSW;
324 end if; 324 end if;
325 end process; 325 end process;
326   326  
327   327  
328 -- Ferquency Selector 328 -- Ferquency Selector
329 -- FSM - 1 hot 329 -- FSM - 1 hot
330 process (CLK100MHz) 330 process (CLK100MHz)
331 variable TMP: std_logic_vector(SYNC_OUT'range); 331 variable TMP: std_logic_vector(SYNC_OUT'range);
332 variable NEW_DATA: std_logic; 332 variable NEW_DATA: std_logic;
333 begin 333 begin
334 if rising_edge(CLK100MHz) then 334 if rising_edge(CLK100MHz) then
335 TMP := (others => '0'); 335 TMP := (others => '0');
336 NEW_DATA := '1'; 336 NEW_DATA := '1';
337 if SW_SYNC(7)='1' then 337 if SW_SYNC(7)='1' then
338 TMP(7) := '1'; 338 TMP(7) := '1';
339 elsif SW_SYNC(6)='1' then 339 elsif SW_SYNC(6)='1' then
340 TMP(6) := '1'; 340 TMP(6) := '1';
341 elsif SW_SYNC(5)='1' then 341 elsif SW_SYNC(5)='1' then
342 TMP(5) := '1'; 342 TMP(5) := '1';
343 elsif SW_SYNC(4)='1' then 343 elsif SW_SYNC(4)='1' then
344 TMP(4) := '1'; 344 TMP(4) := '1';
345 elsif SW_SYNC(3)='1' then 345 elsif SW_SYNC(3)='1' then
346 TMP(3) := '1'; 346 TMP(3) := '1';
347 elsif SW_SYNC(2)='1' then 347 elsif SW_SYNC(2)='1' then
348 TMP(2) := '1'; 348 TMP(2) := '1';
349 elsif SW_SYNC(1)='1' then 349 elsif SW_SYNC(1)='1' then
350 TMP(1) := '1'; 350 TMP(1) := '1';
351 elsif SW_SYNC(0)='1' then 351 elsif SW_SYNC(0)='1' then
352 TMP(0) := '1'; 352 TMP(0) := '1';
353 else 353 else
354 NEW_DATA := '0'; 354 NEW_DATA := '0';
355 end if; 355 end if;
356 if NEW_DATA='1' then 356 if NEW_DATA='1' then
357 SET_CLK_MAX <= TMP(7); 357 SET_CLK_MAX <= TMP(7);
358 SET_CLK_100MHz <= TMP(6); 358 SET_CLK_100MHz <= TMP(6);
359 SET_CLK_50MHz <= TMP(5); 359 SET_CLK_50MHz <= TMP(5);
360 SET_CLK_20MHz <= TMP(4); 360 SET_CLK_20MHz <= TMP(4);
361 SET_CLK_10MHz <= TMP(3); 361 SET_CLK_10MHz <= TMP(3);
362 SET_CLK_5MHz <= TMP(2); 362 SET_CLK_5MHz <= TMP(2);
363 SET_CLK_2MHz <= TMP(1); 363 SET_CLK_2MHz <= TMP(1);
364 SET_CLK_1MHz <= TMP(0); 364 SET_CLK_1MHz <= TMP(0);
365 end if; 365 end if;
366 end if; 366 end if;
367 end process; 367 end process;
368   368  
369   369  
370 -- Send selected frequency to ChipScope Virtual IO 370 -- Send selected frequency to ChipScope Virtual IO
371 -- Sync it to the CLK_FAST timing domain 371 -- Sync it to the CLK_FAST timing domain
372 SET_CLK_proc: process (CLK_FAST) 372 SET_CLK_proc: process (CLK_FAST)
373 begin 373 begin
374 if rising_edge(CLK_FAST) then 374 if rising_edge(CLK_FAST) then
375 SYNC_IN(7) <= SET_CLK_MAX; 375 SYNC_IN(7) <= SET_CLK_MAX;
376 SYNC_IN(6) <= SET_CLK_100MHz; 376 SYNC_IN(6) <= SET_CLK_100MHz;
377 SYNC_IN(5) <= SET_CLK_50MHz; 377 SYNC_IN(5) <= SET_CLK_50MHz;
378 SYNC_IN(4) <= SET_CLK_20Mhz; 378 SYNC_IN(4) <= SET_CLK_20Mhz;
379 SYNC_IN(3) <= SET_CLK_10Mhz; 379 SYNC_IN(3) <= SET_CLK_10Mhz;
380 SYNC_IN(2) <= SET_CLK_5Mhz; 380 SYNC_IN(2) <= SET_CLK_5Mhz;
381 SYNC_IN(1) <= SET_CLK_2Mhz; 381 SYNC_IN(1) <= SET_CLK_2Mhz;
382 SYNC_IN(0) <= SET_CLK_1Mhz; 382 SYNC_IN(0) <= SET_CLK_1Mhz;
383 end if; 383 end if;
384 end process; 384 end process;
385   385  
386   386  
387 -- =================================================== 387 -- ===================================================
388 -- ChipScope Instance - Control / Virtual IO / ILA 388 -- ChipScope Instance - Control / Virtual IO / ILA
389 -- =================================================== 389 -- ===================================================
390   390  
391   391  
392 -- ChipScope Instance - Control Block 392 -- ChipScope Instance - Control Block
393 MyChipScopeICON: ChipScope_ICON 393 MyChipScopeICON: ChipScope_ICON
394 port map ( 394 port map (
395 CONTROL0 => Control0, 395 CONTROL0 => Control0,
396 CONTROL1 => Control1, 396 CONTROL1 => Control1,
397 CONTROL2 => Control2 397 CONTROL2 => Control2
398 ); 398 );
399   399  
400   400  
401 -- ChipScope Instance - Virtual I/O Block 401 -- ChipScope Instance - Virtual I/O Block
402 MyChipScopeVIO_FreqSel: ChipScope_VIO_FreqSel 402 MyChipScopeVIO_FreqSel: ChipScope_VIO_FreqSel
403 port map ( 403 port map (
404 CONTROL => Control0, 404 CONTROL => Control0,
405 CLK => CLK_FAST, 405 CLK => CLK_FAST,
406 SYNC_IN => SYNC_IN, 406 SYNC_IN => SYNC_IN,
407 SYNC_OUT => SYNC_OUT 407 SYNC_OUT => SYNC_OUT
408 ); 408 );
409   409  
410   410  
411 -- ChipScope Instance - Virtual I/O Block 411 -- ChipScope Instance - Virtual I/O Block
412 MyChipScopeVIO_UserOut: ChipScope_VIO_UserOut 412 MyChipScopeVIO_UserOut: ChipScope_VIO_UserOut
413 port map ( 413 port map (
414 CONTROL => Control1, 414 CONTROL => Control1,
415 CLK => CLK_FAST, 415 CLK => CLK_FAST,
416 SYNC_OUT => SYNC_OUT_USER 416 SYNC_OUT => SYNC_OUT_USER
417 ); 417 );
418   418  
419   419  
420 -- ChipScope Instance - Integrated Logic Analyser 420 -- ChipScope Instance - Integrated Logic Analyser
421 ILA_18_1024: if ILA_WIDE generate 421 ILA_18_1024: if ILA_WIDE generate
422 begin 422 begin
423 MyChipScopeILA: ChipScope_ILA_18_1024 423 MyChipScopeILA: ChipScope_ILA_18_1024
424 port map ( 424 port map (
425 CONTROL => Control2, 425 CONTROL => Control2,
426 CLK => CLK_FAST, 426 CLK => CLK_FAST,
427 DATA => DataReg(17 downto 0), 427 DATA => DataReg(17 downto 0),
428 TRIG0 => DataReg(23 downto 0), 428 TRIG0 => DataReg(23 downto 0),
429 TRIG_OUT => TriggerOut 429 TRIG_OUT => TriggerOut
430 ); 430 );
431 end generate; 431 end generate;
432 ILA_9_2048: if not ILA_WIDE generate 432 ILA_9_2048: if not ILA_WIDE generate
433 begin 433 begin
434 MyChipScopeILA: ChipScope_ILA_9_2048 434 MyChipScopeILA: ChipScope_ILA_9_2048
435 port map ( 435 port map (
436 CONTROL => Control2, 436 CONTROL => Control2,
437 CLK => CLK_FAST, 437 CLK => CLK_FAST,
438 DATA => DataReg(8 downto 0), 438 DATA => DataReg(8 downto 0),
439 TRIG0 => DataReg(23 downto 0), 439 TRIG0 => DataReg(23 downto 0),
440 TRIG_OUT => TriggerOut 440 TRIG_OUT => TriggerOut
441 ); 441 );
442 end generate; 442 end generate;
443   443  
444   444  
445 -- Data inputs (ILA does not like to have data inputs connected to io pins) 445 -- Data inputs (ILA does not like to have data inputs connected to io pins)
446 process(CLK_FAST) 446 process(CLK_FAST)
447 begin 447 begin
448 if rising_edge(CLK_FAST) then 448 if rising_edge(CLK_FAST) then
449 DataReg <= P(DataReg'range); 449 DataReg <= P(DataReg'range);
450 end if; 450 end if;
451 end process; 451 end process;
452   452  
453   453  
454 -- VIO User Outputs 454 -- VIO User Outputs
455 VS <= SYNC_OUT_USER; 455 VS <= SYNC_OUT_USER;
456   456  
457   457  
458 -- Trigger Output (Diferencial signal) 458 -- Trigger Output (Diferencial signal)
459 OBUFDS_TriggerOut: OBUFDS 459 OBUFDS_TriggerOut: OBUFDS
460 generic map ( 460 generic map (
461 IOSTANDARD => "DEFAULT" 461 IOSTANDARD => "DEFAULT"
462 ) 462 )
463 port map ( 463 port map (
464 I => TriggerOut, -- Buffer input 464 I => TriggerOut, -- Buffer input
465 O => DIF1P, -- Diff_p output (connect directly to top-level port) 465 O => DIF1P, -- Diff_p output (connect directly to top-level port)
466 OB => DIF1N -- Diff_n output (connect directly to top-level port) 466 OB => DIF1N -- Diff_n output (connect directly to top-level port)
467 ); 467 );
468   468  
469   469  
470 -- =================================================== 470 -- ===================================================
471 -- LED Display (multiplexed) 471 -- LED Display (multiplexed)
472 -- =================================================== 472 -- ===================================================
473   473  
474   474  
475 -- Frequency in BCD 475 -- Frequency in BCD
476 FrequencyBCD <= "00001"&"00111"&"00000" when SET_CLK_MAX='1' else -- 170 MHz 476 FrequencyBCD <= "00001"&"00111"&"00000" when SET_CLK_MAX='1' else -- 170 MHz
477 "00001"&"00000"&"00000" when SET_CLK_100MHz='1' else -- 100 MHz 477 "00001"&"00000"&"00000" when SET_CLK_100MHz='1' else -- 100 MHz
478 "11111"&"00101"&"00000" when SET_CLK_50MHz='1' else -- 50 MHz 478 "11111"&"00101"&"00000" when SET_CLK_50MHz='1' else -- 50 MHz
479 "11111"&"00010"&"00000" when SET_CLK_20MHz='1' else -- 20 MHz 479 "11111"&"00010"&"00000" when SET_CLK_20MHz='1' else -- 20 MHz
480 "11111"&"00001"&"00000" when SET_CLK_10MHz='1' else -- 10 MHz 480 "11111"&"00001"&"00000" when SET_CLK_10MHz='1' else -- 10 MHz
481 "11111"&"11111"&"00101" when SET_CLK_5MHz='1' else -- 5 MHz 481 "11111"&"11111"&"00101" when SET_CLK_5MHz='1' else -- 5 MHz
482 "11111"&"11111"&"00010" when SET_CLK_2MHz='1' else -- 2 MHz 482 "11111"&"11111"&"00010" when SET_CLK_2MHz='1' else -- 2 MHz
483 "11111"&"11111"&"00001" when SET_CLK_1MHz='1' else -- 1 MHz 483 "11111"&"11111"&"00001" when SET_CLK_1MHz='1' else -- 1 MHz
484 "11111"&"11111"&"11111"; 484 "11111"&"11111"&"11111";
485   485  
486   486  
487 -- ILA width in BCD 487 -- ILA width in BCD
488 ILA_DCD_18_1024: if ILA_WIDE generate 488 ILA_DCD_18_1024: if ILA_WIDE generate
489 begin 489 begin
490 WideBCD <= "00001"&"01000"; 490 WideBCD <= "00001"&"01000";
491 end generate; 491 end generate;
492 ILA_DCD_9_2048: if not ILA_WIDE generate 492 ILA_DCD_9_2048: if not ILA_WIDE generate
493 begin 493 begin
494 WideBCD <= "11111"&"01001"; 494 WideBCD <= "11111"&"01001";
495 end generate; 495 end generate;
496   496  
497   497  
498 -- Input data selector ( WIDE / ILA / FREQ ) 498 -- Input data selector ( WIDE / ILA / FREQ )
499 Code <= FrequencyBCD( 4 downto 0) when Digits="00000001" else 499 Code <= FrequencyBCD( 4 downto 0) when Digits="00000001" else
500 FrequencyBCD( 9 downto 5) when Digits="00000010" else 500 FrequencyBCD( 9 downto 5) when Digits="00000010" else
501 FrequencyBCD(14 downto 10) when Digits="00000100" else 501 FrequencyBCD(14 downto 10) when Digits="00000100" else
502 "10010" when Digits="00001000" else -- A 502 "10010" when Digits="00001000" else -- A
503 "10001" when Digits="00010000" else -- L 503 "10001" when Digits="00010000" else -- L
504 "10000" when Digits="00100000" else -- I 504 "10000" when Digits="00100000" else -- I
505 WideBCD( 4 downto 0) when Digits="01000000" else 505 WideBCD( 4 downto 0) when Digits="01000000" else
506 WideBCD( 9 downto 5) when Digits="10000000" else 506 WideBCD( 9 downto 5) when Digits="10000000" else
507 "11111"; 507 "11111";
508   508  
509   509  
510 -- Time Multiplex 510 -- Time Multiplex
511 process (CLK100MHz) 511 process (CLK100MHz)
512 begin 512 begin
513 if rising_edge(CLK100MHz) then 513 if rising_edge(CLK100MHz) then
514 if MuxCounter < MUXCOUNT-1 then 514 if MuxCounter < MUXCOUNT-1 then
515 MuxCounter <= MuxCounter + 1; 515 MuxCounter <= MuxCounter + 1;
516 else 516 else
517 MuxCounter <= (others => '0'); 517 MuxCounter <= (others => '0');
518 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left (1 hot encoded) 518 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left (1 hot encoded)
519 end if; 519 end if;
520 -- Display brightness (1/2) 520 -- Display brightness (1/2)
521 if MuxCounter > (MUXCOUNT-MUXCOUNT/2) then 521 if MuxCounter > (MUXCOUNT-MUXCOUNT/2) then
522 LedEnable <= '1'; 522 LedEnable <= '1';
523 else 523 else
524 LedEnable <= '0'; 524 LedEnable <= '0';
525 end if; 525 end if;
526 end if; 526 end if;
527 end process; 527 end process;
528   528  
529   529  
530 -- BCD to 7 Segmet Decoder 530 -- BCD to 7 Segmet Decoder
531 -- -- A 531 -- -- A
532 -- | | F B 532 -- | | F B
533 -- -- G 533 -- -- G
534 -- | | E C 534 -- | | E C
535 -- -- D H 535 -- -- D H
536 -- HGFEDCBA 536 -- HGFEDCBA
537 Segments <= "00111111" when Code="00000" else -- Digit 0 -- Hex Didits 537 Segments <= "00111111" when Code="00000" else -- Digit 0 -- Hex Didits
538 "00000110" when Code="00001" else -- Digit 1 538 "00000110" when Code="00001" else -- Digit 1
539 "01011011" when Code="00010" else -- Digit 2 539 "01011011" when Code="00010" else -- Digit 2
540 "01001111" when Code="00011" else -- Digit 3 540 "01001111" when Code="00011" else -- Digit 3
541 "01100110" when Code="00100" else -- Digit 4 541 "01100110" when Code="00100" else -- Digit 4
542 "01101101" when Code="00101" else -- Digit 5 542 "01101101" when Code="00101" else -- Digit 5
543 "01111101" when Code="00110" else -- Digit 6 543 "01111101" when Code="00110" else -- Digit 6
544 "00000111" when Code="00111" else -- Digit 7 544 "00000111" when Code="00111" else -- Digit 7
545 "01111111" when Code="01000" else -- Digit 8 545 "01111111" when Code="01000" else -- Digit 8
546 "01101111" when Code="01001" else -- Digit 9 546 "01101111" when Code="01001" else -- Digit 9
547 "01110111" when Code="01010" else -- Digit A 547 "01110111" when Code="01010" else -- Digit A
548 "01111100" when Code="01011" else -- Digit b 548 "01111100" when Code="01011" else -- Digit b
549 "00111001" when Code="01100" else -- Digit C 549 "00111001" when Code="01100" else -- Digit C
550 "01011110" when Code="01101" else -- Digit d 550 "01011110" when Code="01101" else -- Digit d
551 "01111001" when Code="01110" else -- Digit E 551 "01111001" when Code="01110" else -- Digit E
552 "00110001" when Code="01111" else -- Digit F 552 "00110001" when Code="01111" else -- Digit F
553 "00000110" when Code="10000" else -- Digit I -- User Digits 553 "00000110" when Code="10000" else -- Digit I -- User Digits
554 "00111000" when Code="10001" else -- Digit L 554 "00111000" when Code="10001" else -- Digit L
555 "01110111" when Code="10010" else -- Digit A 555 "01110111" when Code="10010" else -- Digit A
556 "00000000"; -- none 556 "00000000"; -- none
557   557  
558   558  
559 -- Connect LED Display Output Ports (negative outputs) 559 -- Connect LED Display Output Ports (negative outputs)
560 LD_CA_n <= not Digits; 560 LD_CA_n <= not Digits;
561 LD_SEG_n <= not Segments when LedEnable='1' else "11111111"; 561 LD_SEG_n <= not Segments when LedEnable='1' else "11111111";
562   562  
563   563  
564 -- =================================================== 564 -- ===================================================
565 -- Test generator (counter) 565 -- Test generator (counter)
566 -- =================================================== 566 -- ===================================================
567   567  
568 -- Test counter 568 -- Test counter
569 process(CLK100MHz) 569 process(CLK100MHz)
570 begin 570 begin
571 if rising_edge(CLK100MHz) then 571 if rising_edge(CLK100MHz) then
572 Counter <= std_logic_vector(unsigned(Counter) + 1); 572 Counter <= std_logic_vector(unsigned(Counter) + 1);
573 end if; 573 end if;
574 end process; 574 end process;
575   575  
576   576  
577 -- Test outputs 577 -- Test outputs
578 LED <= Counter; 578 LED <= Counter;
579   579  
580   580  
581 -- CLK_FAST Output - DDR register 581 -- CLK_FAST Output - DDR register
582 ODDR2_FastClk: ODDR2 582 ODDR2_FastClk: ODDR2
583 generic map( 583 generic map(
584 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 584 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
585 INIT => '0', -- Sets initial state of the Q output to '0' or '1' 585 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
586 SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset 586 SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset
587 ) 587 )
588 port map ( 588 port map (
589 C0 => CLK_FAST, -- 1-bit clock input 589 C0 => CLK_FAST, -- 1-bit clock input
590 C1 => not CLK_FAST, -- 1-bit clock input 590 C1 => not CLK_FAST, -- 1-bit clock input
591 CE => '1', -- 1-bit clock enable input 591 CE => '1', -- 1-bit clock enable input
592 D0 => '0', -- 1-bit data input (associated with C0) 592 D0 => '0', -- 1-bit data input (associated with C0)
593 D1 => '1', -- 1-bit data input (associated with C1) 593 D1 => '1', -- 1-bit data input (associated with C1)
594 R => '0', -- 1-bit reset input 594 R => '0', -- 1-bit reset input
595 S => '0', -- 1-bit set input 595 S => '0', -- 1-bit set input
596 Q => CLK_FAST_Q -- 1-bit output data 596 Q => CLK_FAST_Q -- 1-bit output data
597 ); 597 );
598   598  
599   599  
600 -- CLK_FAST Output - differncial pin buffer 600 -- CLK_FAST Output - differncial pin buffer
601 OBUFDS_FastClkOut: OBUFDS 601 OBUFDS_FastClkOut: OBUFDS
602 generic map ( 602 generic map (
603 IOSTANDARD => "DEFAULT" 603 IOSTANDARD => "DEFAULT"
604 ) 604 )
605 port map ( 605 port map (
606 I => CLK_FAST_Q, -- Buffer input 606 I => CLK_FAST_Q, -- Buffer input
607 O => DIF2P, -- Diff_p output (connect directly to top-level port) 607 O => DIF2P, -- Diff_p output (connect directly to top-level port)
608 OB => DIF2N -- Diff_n output (connect directly to top-level port) 608 OB => DIF2N -- Diff_n output (connect directly to top-level port)
609 ); 609 );
610   610  
611   611  
612 end S3AN01_ChipScope_a; 612 end S3AN01_ChipScope_a;