| 1 |
(kicad_pcb (version 4) (host pcbnew "(2015-04-05 BZR 5577)-product") |
1 |
(kicad_pcb (version 20160815) (host pcbnew "(2016-09-17 revision 679eef1)-makepkg") |
| 2 |
|
2 |
|
| 3 |
(general |
3 |
(general |
| 4 |
(links 0) |
4 |
(links 59) |
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| 11 |
(modules 0) |
11 |
(modules 35) |
| 12 |
(nets 1) |
12 |
(nets 14) |
| 13 |
) |
13 |
) |
| 14 |
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| 15 |
(page A4) |
15 |
(page A4) |
| 16 |
(title_block |
16 |
(title_block |
| 17 |
(title NAME) |
17 |
(title NAME) |
| 18 |
(date "%d. %m. %Y") |
18 |
(date "%d. %m. %Y") |
| 19 |
(rev REV) |
19 |
(rev REV) |
| 20 |
(company "Mlab www.mlab.cz") |
20 |
(company "Mlab www.mlab.cz") |
| 21 |
(comment 1 VERSION) |
21 |
(comment 1 VERSION) |
| 22 |
(comment 2 "Short description\\nTwo lines are maximum") |
22 |
(comment 2 "Short description\\nTwo lines are maximum") |
| 23 |
(comment 3 "nickname <email@example.com>") |
23 |
(comment 3 "nickname <email@example.com>") |
| 24 |
) |
24 |
) |
| 25 |
|
25 |
|
| 26 |
(layers |
26 |
(layers |
| 27 |
(0 F.Cu signal) |
27 |
(0 F.Cu signal) |
| 28 |
(31 B.Cu signal) |
28 |
(31 B.Cu signal) |
| 29 |
(32 B.Adhes user) |
29 |
(32 B.Adhes user) |
| 30 |
(33 F.Adhes user) |
30 |
(33 F.Adhes user) |
| 31 |
(34 B.Paste user) |
31 |
(34 B.Paste user) |
| 32 |
(35 F.Paste user) |
32 |
(35 F.Paste user) |
| 33 |
(36 B.SilkS user) |
33 |
(36 B.SilkS user) |
| 34 |
(37 F.SilkS user) |
34 |
(37 F.SilkS user) |
| 35 |
(38 B.Mask user) |
35 |
(38 B.Mask user) |
| 36 |
(39 F.Mask user) |
36 |
(39 F.Mask user) |
| 37 |
(40 Dwgs.User user) |
37 |
(40 Dwgs.User user) |
| 38 |
(41 Cmts.User user) |
38 |
(41 Cmts.User user) |
| 39 |
(42 Eco1.User user) |
39 |
(42 Eco1.User user) |
| 40 |
(43 Eco2.User user) |
40 |
(43 Eco2.User user) |
| 41 |
(44 Edge.Cuts user) |
41 |
(44 Edge.Cuts user) |
| 42 |
(45 Margin user) |
42 |
(45 Margin user) |
| 43 |
(46 B.CrtYd user) |
43 |
(46 B.CrtYd user) |
| 44 |
(47 F.CrtYd user) |
44 |
(47 F.CrtYd user) |
| 45 |
(48 B.Fab user) |
45 |
(48 B.Fab user) |
| 46 |
(49 F.Fab user) |
46 |
(49 F.Fab user) |
| 47 |
) |
47 |
) |
| 48 |
|
48 |
|
| 49 |
(setup |
49 |
(setup |
| 50 |
(last_trace_width 0.25) |
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(zone_clearance 0.508) |
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| 53 |
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| 54 |
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(trace_min 0.2) |
| 55 |
(segment_width 0.2) |
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(segment_width 0.2) |
| 56 |
(edge_width 0.15) |
56 |
(edge_width 0.15) |
| 57 |
(via_size 0.6) |
57 |
(via_size 0.6) |
| 58 |
(via_drill 0.4) |
58 |
(via_drill 0.4) |
| 59 |
(via_min_size 0.4) |
59 |
(via_min_size 0.4) |
| 60 |
(via_min_drill 0.3) |
60 |
(via_min_drill 0.3) |
| 61 |
(uvia_size 0.3) |
61 |
(uvia_size 0.3) |
| 62 |
(uvia_drill 0.1) |
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(uvia_drill 0.1) |
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(uvias_allowed no) |
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(uvias_allowed no) |
| 64 |
(uvia_min_size 0.2) |
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(pcb_text_width 0.3) |
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(pcb_text_width 0.3) |
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(pcb_text_size 1.5 1.5) |
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(mod_text_size 1 1) |
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(pad_size 1.524 1.524) |
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(pad_size 1.524 1.524) |
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(pad_drill 0.762) |
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(layerselection 0x00030_80000001) |
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(usegerberextensions false) |
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(excludeedgelayer true) |
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(plotframeref false) |
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| 82 |
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(viasonmask false) |
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(mode 1) |
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(mode 1) |
| 84 |
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(hpglpennumber 1) |
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(hpglpennumber 1) |
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(hpglpenspeed 20) |
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(psnegative false) |
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(plotvalue true) |
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(padsonsilk false) |
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(padsonsilk false) |
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(subtractmaskfromsilk false) |
| 95 |
(subtractmaskfromsilk false) |
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(outputformat 1) |
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(outputformat 1) |
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(mirror false) |
| 97 |
(mirror false) |
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(drillshape 1) |
| 98 |
(drillshape 1) |
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(scaleselection 1) |
| 99 |
(scaleselection 1) |
99 |
(outputdirectory "")) |
| 100 |
(outputdirectory "")) |
100 |
) |
| 101 |
) |
101 |
|
| 102 |
|
102 |
(net 0 "") |
| 103 |
(net 0 "") |
103 |
(net 1 "Net-(C1-Pad2)") |
| 104 |
|
104 |
(net 2 "Net-(C1-Pad1)") |
| 105 |
(net_class Default "This is the default net class." |
105 |
(net 3 "Net-(C10-Pad1)") |
| 106 |
(clearance 0.2) |
106 |
(net 4 GND) |
| 107 |
(trace_width 0.25) |
107 |
(net 5 "Net-(C3-Pad1)") |
| 108 |
(via_dia 0.6) |
108 |
(net 6 "Net-(C3-Pad2)") |
| 109 |
(via_drill 0.4) |
109 |
(net 7 "Net-(C6-Pad1)") |
| 110 |
(uvia_dia 0.3) |
110 |
(net 8 "Net-(C7-Pad1)") |
| 111 |
(uvia_drill 0.1) |
111 |
(net 9 "Net-(C11-Pad2)") |
| 112 |
) |
112 |
(net 10 "Net-(C11-Pad1)") |
| 113 |
|
113 |
(net 11 "Net-(C13-Pad1)") |
| 114 |
) |
114 |
(net 12 "Net-(C17-Pad1)") |
| - |
|
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(net 13 "Net-(C17-Pad2)") |
| - |
|
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|
| - |
|
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(net_class Default "This is the default net class." |
| - |
|
118 |
(clearance 0.2) |
| - |
|
119 |
(trace_width 0.25) |
| - |
|
120 |
(via_dia 0.6) |
| - |
|
121 |
(via_drill 0.4) |
| - |
|
122 |
(uvia_dia 0.3) |
| - |
|
123 |
(uvia_drill 0.1) |
| - |
|
124 |
(diff_pair_gap 0.25) |
| - |
|
125 |
(diff_pair_width 0.2) |
| - |
|
126 |
(add_net GND) |
| - |
|
127 |
(add_net "Net-(C1-Pad1)") |
| - |
|
128 |
(add_net "Net-(C1-Pad2)") |
| - |
|
129 |
(add_net "Net-(C10-Pad1)") |
| - |
|
130 |
(add_net "Net-(C11-Pad1)") |
| - |
|
131 |
(add_net "Net-(C11-Pad2)") |
| - |
|
132 |
(add_net "Net-(C13-Pad1)") |
| - |
|
133 |
(add_net "Net-(C17-Pad1)") |
| - |
|
134 |
(add_net "Net-(C17-Pad2)") |
| - |
|
135 |
(add_net "Net-(C3-Pad1)") |
| - |
|
136 |
(add_net "Net-(C3-Pad2)") |
| - |
|
137 |
(add_net "Net-(C6-Pad1)") |
| - |
|
138 |
(add_net "Net-(C7-Pad1)") |
| - |
|
139 |
) |
| - |
|
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|
| - |
|
141 |
(module Mlab_R:SMD-0805 (layer B.Cu) (tedit 584E60E0) (tstamp 584E5CBA) |
| - |
|
142 |
(at 16.256 -20.32) |
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(net 1 "Net-(C1-Pad2)")) |
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(pad 1 smd rect (at -0.9525 0) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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161 |
(net 2 "Net-(C1-Pad1)")) |
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162 |
(model MLAB_3D/Resistors/chip_cms.wrl |
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(scale (xyz 0.1 0.1 0.1)) |
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) |
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) |
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(module Mlab_R:SMD-0805 (layer B.Cu) (tedit 584E60E0) (tstamp 584E5CC0) |
| - |
|
170 |
(at 21.59 -28.956 90) |
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(path /584A9E07) |
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(attr smd) |
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(fp_circle (center -1.651 -0.762) (end -1.651 -0.635) (layer B.SilkS) (width 0.15)) |
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(pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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(net 3 "Net-(C10-Pad1)")) |
| - |
|
188 |
(pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
| - |
|
189 |
(net 4 GND)) |
| - |
|
190 |
(model MLAB_3D/Resistors/chip_cms.wrl |
| - |
|
191 |
(at (xyz 0 0 0)) |
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|
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(scale (xyz 0.1 0.1 0.1)) |
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(rotate (xyz 0 0 0)) |
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) |
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) |
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|
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|
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(module Mlab_R:SMD-0805 (layer B.Cu) (tedit 584E60E0) (tstamp 584E5CC6) |
| - |
|
198 |
(at 23.622 -17.018 90) |
| - |
|
199 |
(path /584A88A6) |
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200 |
(attr smd) |
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(fp_text reference C3 (at 0 0.3175 90) (layer B.SilkS) |
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(effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror)) |
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) |
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(fp_text value 33pF (at 0.127 -0.381 90) (layer B.SilkS) |
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(effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror)) |
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) |
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(pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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(net 5 "Net-(C3-Pad1)")) |
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(pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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217 |
(net 6 "Net-(C3-Pad2)")) |
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|
218 |
(model MLAB_3D/Resistors/chip_cms.wrl |
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(at (xyz 0 0 0)) |
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(scale (xyz 0.1 0.1 0.1)) |
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(rotate (xyz 0 0 0)) |
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) |
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) |
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|
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|
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(module Mlab_R:SMD-0805 (layer B.Cu) (tedit 584E60E0) (tstamp 584E5CCC) |
| - |
|
226 |
(at 23.622 -13.208 90) |
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|
227 |
(path /584E93D8) |
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|
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(attr smd) |
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(fp_text reference C4 (at 0 0.3175 90) (layer B.SilkS) |
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) |
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(pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
| - |
|
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(net 4 GND)) |
| - |
|
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(pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
| - |
|
245 |
(net 5 "Net-(C3-Pad1)")) |
| - |
|
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(model MLAB_3D/Resistors/chip_cms.wrl |
| - |
|
247 |
(at (xyz 0 0 0)) |
| - |
|
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(scale (xyz 0.1 0.1 0.1)) |
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|
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(rotate (xyz 0 0 0)) |
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) |
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) |
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|
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|
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(module Mlab_R:SMD-0805 (layer B.Cu) (tedit 584E60E0) (tstamp 584E5CD2) |
| - |
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