Rev 204 Rev 830
1 EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) 1 EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)
2 Copyright (R) National Semiconductor Corporation 1990,1991 2 Copyright (R) National Semiconductor Corporation 1990,1991
3   3  
4 Document file for GAL4.EQN 4 Document file for GAL4.EQN
5 Device: 16V8 5 Device: 16V8
6   6  
7 $LABELS 20 nc D7 D6 D5 D4 D3 D2 D1 D0 GND nc CLOCK DATA RES nc nc VCCON VPPON 7 $LABELS 20 nc D7 D6 D5 D4 D3 D2 D1 D0 GND nc CLOCK DATA RES nc nc VCCON VPPON
8 DQ VCC 8 DQ VCC
9   9  
10   10  
11 Pin Label Type 11 Pin Label Type
12 --- ----- ---- 12 --- ----- ----
13 2 D7 com input 13 2 D7 com input
14 3 D6 com input 14 3 D6 com input
15 4 D5 com input 15 4 D5 com input
16 5 D4 com input 16 5 D4 com input
17 6 D3 com input 17 6 D3 com input
18 7 D2 com input 18 7 D2 com input
19 8 D1 com input 19 8 D1 com input
20 9 D0 com input 20 9 D0 com input
21 10 GND ground pin 21 10 GND ground pin
22 12 CLOCK pos,trst,com output 22 12 CLOCK pos,trst,com output
23 13 DATA pos,trst,com feedback 23 13 DATA pos,trst,com feedback
24 14 RES pos,trst,com output 24 14 RES pos,trst,com output
25 17 VCCON pos,trst,com output 25 17 VCCON pos,trst,com output
26 18 VPPON pos,trst,com output 26 18 VPPON pos,trst,com output
27 19 DQ pos,trst,com output 27 19 DQ pos,trst,com output
28 20 VCC power pin 28 20 VCC power pin
29   29  
30 EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) 30 EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)
31 Copyright (R) National Semiconductor Corporation 1990,1991 31 Copyright (R) National Semiconductor Corporation 1990,1991
32   32  
33 Device Utilization: 33 Device Utilization:
34   34  
35 No of dedicated inputs used : 8/10 (80.0%) 35 No of dedicated inputs used : 8/10 (80.0%)
36 No of dedicated outputs used : 2/2 (100.0%) 36 No of dedicated outputs used : 2/2 (100.0%)
37 No of feedbacks used as dedicated outputs : 3/6 (50.0%) 37 No of feedbacks used as dedicated outputs : 3/6 (50.0%)
38 No of feedbacks used : 1/6 (16.7%) 38 No of feedbacks used : 1/6 (16.7%)
39   39  
40 ------------------------------------------ 40 ------------------------------------------
41 Pin Label Terms Usage 41 Pin Label Terms Usage
42 ------------------------------------------ 42 ------------------------------------------
43 19 DQ 2/8 (25.0%) 43 19 DQ 2/8 (25.0%)
44 18 VPPON 2/8 (25.0%) 44 18 VPPON 2/8 (25.0%)
45 17 VCCON 2/8 (25.0%) 45 17 VCCON 2/8 (25.0%)
46 14 RES 2/8 (25.0%) 46 14 RES 2/8 (25.0%)
47 13 DATA 3/8 (37.5%) 47 13 DATA 3/8 (37.5%)
48 12 CLOCK 3/8 (37.5%) 48 12 CLOCK 3/8 (37.5%)
49 ------------------------------------------ 49 ------------------------------------------
50 Total 12/64 (18.8%) 50 Total 12/64 (18.8%)
51 ------------------------------------------ 51 ------------------------------------------
52   52  
53 EQN2JED - Boolean Equations to JEDEC file assembler (Version V003) 53 EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)
54 Copyright (R) National Semiconductor Corporation 1990,1991 54 Copyright (R) National Semiconductor Corporation 1990,1991
55   55  
56 Chip diagram (DIP) 56 Chip diagram (DIP)
57   57  
58 ._____ _____. 58 ._____ _____.
59 | \__/ | 59 | \__/ |
60 | 1 20 | VCC 60 | 1 20 | VCC
61 D7 | 2 19 | DQ 61 D7 | 2 19 | DQ
62 D6 | 3 18 | VPPON 62 D6 | 3 18 | VPPON
63 D5 | 4 17 | VCCON 63 D5 | 4 17 | VCCON
64 D4 | 5 16 | 64 D4 | 5 16 |
65 D3 | 6 15 | 65 D3 | 6 15 |
66 D2 | 7 14 | RES 66 D2 | 7 14 | RES
67 D1 | 8 13 | DATA 67 D1 | 8 13 | DATA
68 D0 | 9 12 | CLOCK 68 D0 | 9 12 | CLOCK
69 GND | 10 11 | 69 GND | 10 11 |
70 |______________| 70 |______________|