Rev 204 Rev 830
1 {$A+,B-,D+,E+,F-,G-,I+,L+,N-,O-,R-,S+,V+,X-} 1 {$A+,B-,D+,E+,F-,G-,I+,L+,N-,O-,R-,S+,V+,X-}
2 {$M 16384,0,655360} 2 {$M 16384,0,655360}
3   3  
4 program TSTPGR(Input,Output); 4 program TSTPGR(Input,Output);
5   5  
6 {=============================================================} 6 {=============================================================}
7 {== Program pro testovani a ozivovani programatoru PICPGR ==} 7 {== Program pro testovani a ozivovani programatoru PICPGR ==}
8 {=============================================================} 8 {=============================================================}
9   9  
10 { (c)miho 2004 } 10 { (c)miho 2004 }
11   11  
12 {=============================================================} 12 {=============================================================}
13 { Historie: } 13 { Historie: }
14 { 1.00 Novy program } 14 { 1.00 Novy program }
15 {=============================================================} 15 {=============================================================}
16   16  
17   17  
18 uses CRT; 18 uses CRT;
19   19  
20 var PortAdr:word absolute 0:$408; 20 var PortAdr:word absolute 0:$408;
21   21  
22 procedure key; 22 procedure key;
23 begin readln; 23 begin readln;
24 end; 24 end;
25   25  
26 begin {== Uvodni tisk ==} 26 begin {== Uvodni tisk ==}
27   27  
28 writeln; 28 writeln;
29 writeln('Test Utility for PICPGR'); 29 writeln('Test Utility for PICPGR');
30 writeln('======================='); 30 writeln('=======================');
31 writeln('(c) miho 2004 v.1.00'); 31 writeln('(c) miho 2004 v.1.00');
32 writeln; 32 writeln;
33   33  
34 {== Overeni dostupnosti portu LTP1 ==} 34 {== Overeni dostupnosti portu LTP1 ==}
35   35  
36 if PortAdr=0 then begin writeln('No LPT port available!'); 36 if PortAdr=0 then begin writeln('No LPT port available!');
37 halt(1); 37 halt(1);
38 end; 38 end;
39   39  
40 {== Testovaci posloupnost ==} 40 {== Testovaci posloupnost ==}
41 writeln('Action PGC PGD VDD ... GND VPP Comment'); 41 writeln('Action PGC PGD VDD ... GND VPP Comment');
42 writeln('-------------------------------------------------------------------------------'); 42 writeln('-------------------------------------------------------------------------------');
43 port[PortAdr]:=0; 43 port[PortAdr]:=0;
44 writeln('OFF X X 0V . 0V 0V Standard state OFF'); 44 writeln('OFF X X 0V . 0V 0V Standard state OFF');
45 key; 45 key;
46   46  
47 port[PortAdr]:=$10; 47 port[PortAdr]:=$10;
48 writeln('Vdd ON X X +5V . 0V +5V'); 48 writeln('Vdd ON X X +5V . 0V +5V');
49 key; 49 key;
50   50  
51 port[PortAdr]:=$50; 51 port[PortAdr]:=$50;
52 writeln('Vdd ON and RESET X X +5V . 0V 0V'); 52 writeln('Vdd ON and RESET X X +5V . 0V 0V');
53 key; 53 key;
54   54  
55 port[PortAdr]:=$20; 55 port[PortAdr]:=$20;
56 writeln('Vpp ON X X 0V . 0V 0V Invalid state (missing Vdd)'); 56 writeln('Vpp ON X X 0V . 0V 0V Invalid state (missing Vdd)');
57 key; 57 key;
58   58  
59 port[PortAdr]:=$30; 59 port[PortAdr]:=$30;
60 writeln('Vpp and Vdd ON X X +5V . 0V +12V'); 60 writeln('Vpp and Vdd ON X X +5V . 0V +12V');
61 key; 61 key;
62   62  
63 port[PortAdr]:=$02; 63 port[PortAdr]:=$02;
64 writeln('Data 0 X L 0V . 0V 0V'); 64 writeln('Data 0 X L 0V . 0V 0V');
65 key; 65 key;
66   66  
67 port[PortAdr]:=$03; 67 port[PortAdr]:=$03;
68 writeln('Data 1 X H 0V . 0V 0V'); 68 writeln('Data 1 X H 0V . 0V 0V');
69 key; 69 key;
70   70  
71 port[PortAdr]:=$08; 71 port[PortAdr]:=$08;
72 writeln('Clock 0 L X 0V . 0V 0V'); 72 writeln('Clock 0 L X 0V . 0V 0V');
73 key; 73 key;
74   74  
75 port[PortAdr]:=$0C; 75 port[PortAdr]:=$0C;
76 writeln('Clock 1 H X 0V . 0V 0V'); 76 writeln('Clock 1 H X 0V . 0V 0V');
77 key; 77 key;
78   78  
79 writeln; 79 writeln;
80 writeln('Test PGD input, use 10k resistor to connect PDG to GND and VDD'); 80 writeln('Test PGD input, use 10k resistor to connect PDG to GND and VDD');
81 writeln; 81 writeln;
82 port[PortAdr]:=$10; 82 port[PortAdr]:=$10;
83   83  
84 repeat 84 repeat
85 if (port[PortAdr+1] and $40)<>0 then write('PGD State: H') 85 if (port[PortAdr+1] and $40)<>0 then write('PGD State: H')
86 else write('PGD State: L'); 86 else write('PGD State: L');
87 write(#$0D); 87 write(#$0D);
88 until keypressed and (readkey=#$0D); 88 until keypressed and (readkey=#$0D);
89   89  
90 writeln; 90 writeln;
91 writeln; 91 writeln;
92 writeln('Action PGC PGD VDD ... GND VPP Comment'); 92 writeln('Action PGC PGD VDD ... GND VPP Comment');
93 writeln('-------------------------------------------------------------------------------'); 93 writeln('-------------------------------------------------------------------------------');
94 port[PortAdr]:=$80+$3F; 94 port[PortAdr]:=$80+$3F;
95 writeln('OFF X X 0V . 0V 0V Alternative state OFF'); 95 writeln('OFF X X 0V . 0V 0V Alternative state OFF');
96 end. 96 end.