Rev 1759 Rev 1775
1   1  
2 //struct { 2 //struct {
3 unsigned int8 firenum=TDC_FIRENUM_0; 3 unsigned int8 firenum=TDC_FIRENUM_0;
4 unsigned int8 div_fire=TDC_DIV_FIRE_2; 4 unsigned int8 div_fire=TDC_DIV_FIRE_2;
5 unsigned int8 calresnum=TDC_CALPERIODS_2; 5 unsigned int8 calresnum=TDC_CALPERIODS_2;
6 unsigned int8 clkhsdiv=TDC_CLKHSDIV_1; 6 unsigned int8 clkhsdiv=TDC_CLKHSDIV_1;
7 unsigned int8 start_clkhs=TDC_CLKHS_ON; 7 unsigned int8 start_clkhs=TDC_CLKHS_ON;
8 unsigned int1 portnum=TDC_TPORTNUM_4; 8 unsigned int1 portnum=TDC_TPORTNUM_4;
9 unsigned int1 Tcycle=TDC_TCYCLE_SHORT; 9 unsigned int1 Tcycle=TDC_TCYCLE_SHORT;
10 unsigned int1 fakenum=TDC_TFAKENUM_2; 10 unsigned int1 fakenum=TDC_TFAKENUM_2;
11 unsigned int1 selclkT=TDC_TSELCLK_128HS; 11 unsigned int1 selclkT=TDC_TSELCLK_128HS;
12 unsigned int1 calibrate=TDC_CALIBRATE_EN; 12 unsigned int1 calibrate=TDC_CALIBRATE_EN;
13 unsigned int1 disautocal=TDC_AUTOCAL_EN; 13 unsigned int1 disautocal=TDC_AUTOCAL_EN;
14 unsigned int1 MRange=TDC_MRANGE2; 14 unsigned int1 MRange=TDC_MRANGE2;
15 unsigned int1 neg_stop2=TDC_NEG_STOP2; 15 unsigned int1 neg_stop2=TDC_NEG_STOP2;
16 unsigned int1 neg_stop1=TDC_NEG_STOP1; 16 unsigned int1 neg_stop1=TDC_NEG_STOP1;
17 unsigned int1 neg_start=TDC_NEG_START; 17 unsigned int1 neg_start=TDC_NEG_START;
18 //}reg0; 18 //}reg0;
19   19  
20 //struct { 20 //struct {
21 unsigned int hit2=TDC_MRANGE1_HIT2_NOAC; 21 unsigned int hit2=TDC_MRANGE1_HIT2_NOAC;
22 unsigned int hit1=TDC_MRANGE1_HIT1_NOAC; 22 unsigned int hit1=TDC_MRANGE1_HIT1_NOAC;
23 unsigned int1 fast_init=TDC_FAST_INIT_DIS; 23 unsigned int1 fast_init=TDC_FAST_INIT_DIS;
24 unsigned int hitin2=TDC_HITIN2_0; 24 unsigned int hitin2=TDC_HITIN2_0;
25 unsigned int hitin1=TDC_HITIN1_0; 25 unsigned int hitin1=TDC_HITIN1_0;
26 //}reg1; 26 //}reg1;
27   27  
28 //struct { 28 //struct {
29 unsigned int en_int=TDC_INT_ALU; 29 unsigned int en_int=TDC_INT_ALU;
30 unsigned int1 rfedge2=TDC_CH2EDGE_RIS; 30 unsigned int1 rfedge2=TDC_CH2EDGE_RIS;
31 unsigned int1 rfedge1=TDC_CH1EDGE_RIS; 31 unsigned int1 rfedge1=TDC_CH1EDGE_RIS;
32 unsigned int32 delval1=0; 32 unsigned int32 delval1=0;
33 //}reg2; 33 //}reg2;
34   34  
35 //struct { 35 //struct {
36 unsigned int1 en_err_val=TDC_ERRVAL_DIS; 36 unsigned int1 en_err_val=TDC_ERRVAL_DIS;
37 unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS; 37 unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS;
38 unsigned int32 delval2=0; 38 unsigned int32 delval2=0;
39 //}reg3; 39 //}reg3;
40   40  
41 //reg4 41 //reg4
42 unsigned int32 delval3=0; 42 unsigned int32 delval3=0;
43   43  
44 //reg5 44 //reg5
45 unsigned int conf_fire=0; 45 unsigned int conf_fire=0;
46 unsigned int1 en_startnoise=TDC_STARTNOISE_DIS; 46 unsigned int1 en_startnoise=TDC_STARTNOISE_DIS;
47 unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS; 47 unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS;
48 unsigned int repeat_fire=TDC_REPEAT_FIRE_0; 48 unsigned int repeat_fire=TDC_REPEAT_FIRE_0;
49 unsigned int16 phase_fire; 49 unsigned int16 phase_fire=0;
50   50  
51 //}TDC_registers; 51 //}TDC_registers;
52   52  
53   53  
54 void TDC_init() 54 void TDC_init()
55 { 55 {
56 output_low(TDC_ENABLE); 56 output_low(TDC_ENABLE);
57 spi_xfer(TDC_stream,0x70,8); 57 spi_xfer(TDC_stream,0x70,8);
58 output_high(TDC_ENABLE); 58 output_high(TDC_ENABLE);
59 } 59 }
60   60  
61 void TDC_reset() 61 void TDC_reset()
62 { 62 {
63 output_low(TDC_ENABLE); 63 output_low(TDC_ENABLE);
64 spi_xfer(TDC_stream,0x50,8); 64 spi_xfer(TDC_stream,0x50,8);
65 output_high(TDC_ENABLE); 65 output_high(TDC_ENABLE);
66 } 66 }
67   67  
68 void TDC_start_cycle() 68 void TDC_start_cycle()
69 { 69 {
70 output_low(TDC_ENABLE); 70 output_low(TDC_ENABLE);
71 spi_xfer(TDC_stream,0x01,8); 71 spi_xfer(TDC_stream,0x01,8);
72 output_high(TDC_ENABLE); 72 output_high(TDC_ENABLE);
73 } 73 }
74   74  
75 void TDC_start_temp() 75 void TDC_start_temp()
76 { 76 {
77 output_low(TDC_ENABLE); 77 output_low(TDC_ENABLE);
78 spi_xfer(TDC_stream,0x02,8); 78 spi_xfer(TDC_stream,0x02,8);
79 output_high(TDC_ENABLE); 79 output_high(TDC_ENABLE);
80 } 80 }
81   81  
82 void TDC_start_cal_resonator() 82 void TDC_start_cal_resonator()
83 { 83 {
84 output_low(TDC_ENABLE); 84 output_low(TDC_ENABLE);
85 spi_xfer(TDC_stream,0x03,8); 85 spi_xfer(TDC_stream,0x03,8);
86 output_high(TDC_ENABLE); 86 output_high(TDC_ENABLE);
87 } 87 }
88   88  
89 void TDC_start_cal() 89 void TDC_start_cal()
90 { 90 {
91 output_low(TDC_ENABLE); 91 output_low(TDC_ENABLE);
92 spi_xfer(TDC_stream,0x04,8); 92 spi_xfer(TDC_stream,0x04,8);
93 output_high(TDC_ENABLE); 93 output_high(TDC_ENABLE);
94 } 94 }
95   95  
96 unsigned int32 TDC_get_measurement(int num) 96 unsigned int32 TDC_get_measurement(int num)
97 { 97 {
98 unsigned int32 ret; 98 unsigned int32 ret;
99   99  
100 output_low(TDC_ENABLE); 100 output_low(TDC_ENABLE);
101 spi_xfer(TDC_stream,0xB0 + num - 1); 101 spi_xfer(TDC_stream,0xB0 + num - 1);
102 ret=spi_xfer(TDC_stream,0,32); 102 ret=spi_xfer(TDC_stream,0,32);
103 output_high(TDC_ENABLE); 103 output_high(TDC_ENABLE);
104 return ret; 104 return ret;
105 } 105 }
106   106  
107 unsigned int16 TDC_get_status() 107 unsigned int16 TDC_get_status()
108 { 108 {
109 unsigned int16 ret; 109 unsigned int16 ret;
110   110  
111 output_low(TDC_ENABLE); 111 output_low(TDC_ENABLE);
112 spi_xfer(TDC_stream,0xB4,8); 112 spi_xfer(TDC_stream,0xB4,8);
113 ret=spi_xfer(TDC_stream,0,16); 113 ret=spi_xfer(TDC_stream,0,16);
114 output_high(TDC_ENABLE); 114 output_high(TDC_ENABLE);
115 return ret; 115 return ret;
116 } 116 }
117   117  
118 unsigned int8 TDC_get_reg1() 118 unsigned int8 TDC_get_reg1()
119 { 119 {
120 unsigned int8 ret; 120 unsigned int8 ret;
121   121  
122 output_low(TDC_ENABLE); 122 output_low(TDC_ENABLE);
123 spi_xfer(TDC_stream,0xB5,8); 123 spi_xfer(TDC_stream,0xB5,8);
124 ret=spi_xfer(TDC_stream,0,8); 124 ret=spi_xfer(TDC_stream,0,8);
125 output_high(TDC_ENABLE); 125 output_high(TDC_ENABLE);
126 return ret; 126 return ret;
127 } 127 }
128   128  
129 void TDC_update_registers() 129 void TDC_update_registers()
130 { 130 {
131 //update reg0 131 //update reg0
132 output_low(TDC_ENABLE); 132 output_low(TDC_ENABLE);
133 spi_xfer(TDC_stream,0x80,8); 133 spi_xfer(TDC_stream,0x80,8);
134 spi_xfer(TDC_stream,firenum,4); 134 spi_xfer(TDC_stream,firenum,4);
135 spi_xfer(TDC_stream,div_fire,4); 135 spi_xfer(TDC_stream,div_fire,4);
136 spi_xfer(TDC_stream,calresnum,2); 136 spi_xfer(TDC_stream,calresnum,2);
137 spi_xfer(TDC_stream,clkhsdiv,2); 137 spi_xfer(TDC_stream,clkhsdiv,2);
138 spi_xfer(TDC_stream,start_clkhs,2); 138 spi_xfer(TDC_stream,start_clkhs,2);
139 spi_xfer(TDC_stream,portnum,1); 139 spi_xfer(TDC_stream,portnum,1);
140 spi_xfer(TDC_stream,Tcycle,1); 140 spi_xfer(TDC_stream,Tcycle,1);
141 spi_xfer(TDC_stream,fakenum,1); 141 spi_xfer(TDC_stream,fakenum,1);
142 spi_xfer(TDC_stream,selclkT,1); 142 spi_xfer(TDC_stream,selclkT,1);
143 spi_xfer(TDC_stream,calibrate,1); 143 spi_xfer(TDC_stream,calibrate,1);
144 spi_xfer(TDC_stream,disautocal,1); 144 spi_xfer(TDC_stream,disautocal,1);
145 spi_xfer(TDC_stream,MRange,1); 145 spi_xfer(TDC_stream,MRange,1);
146 spi_xfer(TDC_stream,neg_stop2,1); 146 spi_xfer(TDC_stream,neg_stop2,1);
147 spi_xfer(TDC_stream,neg_stop1,1); 147 spi_xfer(TDC_stream,neg_stop1,1);
148 spi_xfer(TDC_stream,neg_start,1); 148 spi_xfer(TDC_stream,neg_start,1);
149 output_high(TDC_ENABLE); 149 output_high(TDC_ENABLE);
150   150  
151 // update reg1 151 // update reg1
152 output_low(TDC_ENABLE); 152 output_low(TDC_ENABLE);
153 spi_xfer(TDC_stream,0x81,8); 153 spi_xfer(TDC_stream,0x81,8);
154 spi_xfer(TDC_stream,hit2,4); 154 spi_xfer(TDC_stream,hit2,4);
155 spi_xfer(TDC_stream,hit1,4); 155 spi_xfer(TDC_stream,hit1,4);
156 spi_xfer(TDC_stream,fast_init,1); 156 spi_xfer(TDC_stream,fast_init,1);
157 spi_xfer(TDC_stream,1,1); 157 spi_xfer(TDC_stream,1,1);
158 spi_xfer(TDC_stream,hitin2,3); 158 spi_xfer(TDC_stream,hitin2,3);
159 spi_xfer(TDC_stream,hitin1,3); 159 spi_xfer(TDC_stream,hitin1,3);
160 spi_xfer(TDC_stream,0,8); 160 spi_xfer(TDC_stream,0,8);
161 output_high(TDC_ENABLE); 161 output_high(TDC_ENABLE);
162   162  
163 // update reg2 163 // update reg2
164 output_low(TDC_ENABLE); 164 output_low(TDC_ENABLE);
165 spi_xfer(TDC_stream,0x82); 165 spi_xfer(TDC_stream,0x82);
166 spi_xfer(TDC_stream,en_int,3); 166 spi_xfer(TDC_stream,en_int,3);
167 spi_xfer(TDC_stream,rfedge2,1); 167 spi_xfer(TDC_stream,rfedge2,1);
168 spi_xfer(TDC_stream,rfedge1,1); 168 spi_xfer(TDC_stream,rfedge1,1);
169 spi_xfer(TDC_stream,delval1,19); 169 spi_xfer(TDC_stream,delval1,19);
170 output_high(TDC_ENABLE); 170 output_high(TDC_ENABLE);
171   171  
172 // update reg3 172 // update reg3
173 output_low(TDC_ENABLE); 173 output_low(TDC_ENABLE);
174 spi_xfer(TDC_stream,0x83); 174 spi_xfer(TDC_stream,0x83);
175 spi_xfer(TDC_stream,0,2); 175 spi_xfer(TDC_stream,0,2);
176 spi_xfer(TDC_stream,en_err_val,1); 176 spi_xfer(TDC_stream,en_err_val,1);
177 spi_xfer(TDC_stream,tim0_mr2,2); 177 spi_xfer(TDC_stream,tim0_mr2,2);
178 spi_xfer(TDC_stream,delval2,19); 178 spi_xfer(TDC_stream,delval2,19);
179 output_high(TDC_ENABLE); 179 output_high(TDC_ENABLE);
180   180  
181 // update reg4 181 // update reg4
182 output_low(TDC_ENABLE); 182 output_low(TDC_ENABLE);
183 spi_xfer(TDC_stream,0x84); 183 spi_xfer(TDC_stream,0x84);
184 spi_xfer(TDC_stream,0b00100,5); 184 spi_xfer(TDC_stream,0b00100,5);
185 spi_xfer(TDC_stream,delval3,19); 185 spi_xfer(TDC_stream,delval3,19);
186 output_high(TDC_ENABLE); 186 output_high(TDC_ENABLE);
187   187  
188 // update reg5 188 // update reg5
189 output_low(TDC_ENABLE); 189 output_low(TDC_ENABLE);
190 spi_xfer(TDC_stream,0x85); 190 spi_xfer(TDC_stream,0x85);
191 spi_xfer(TDC_stream,conf_fire,3); 191 spi_xfer(TDC_stream,conf_fire,3);
192 spi_xfer(TDC_stream,en_startnoise,1); 192 spi_xfer(TDC_stream,en_startnoise,1);
193 spi_xfer(TDC_stream,dis_phasenoise,1); 193 spi_xfer(TDC_stream,dis_phasenoise,1);
194 spi_xfer(TDC_stream,repeat_fire,3); 194 spi_xfer(TDC_stream,repeat_fire,3);
195 spi_xfer(TDC_stream,phase_fire,16); 195 spi_xfer(TDC_stream,phase_fire,16);
196 output_high(TDC_ENABLE); 196 output_high(TDC_ENABLE);
197 } 197 }
198   198