Rev 1980 Rev 2163
1   1  
2 //struct { 2 //struct {
3 unsigned int8 firenum=TDC_FIRENUM_0; 3 unsigned int8 firenum=TDC_FIRENUM_0;
4 unsigned int8 div_fire=TDC_DIV_FIRE_2; 4 unsigned int8 div_fire=TDC_DIV_FIRE_2;
5 unsigned int8 calresnum=TDC_CALPERIODS_2; 5 unsigned int8 calresnum=TDC_CALPERIODS_2;
6 unsigned int8 clkhsdiv=TDC_CLKHSDIV_1; 6 unsigned int8 clkhsdiv=TDC_CLKHSDIV_1;
7 unsigned int8 start_clkhs=TDC_CLKHS_ON; 7 unsigned int8 start_clkhs=TDC_CLKHS_ON;
8 unsigned int1 portnum=TDC_TPORTNUM_4; 8 unsigned int1 portnum=TDC_TPORTNUM_4;
9 unsigned int1 Tcycle=TDC_TCYCLE_SHORT; 9 unsigned int1 Tcycle=TDC_TCYCLE_SHORT;
10 unsigned int1 fakenum=TDC_TFAKENUM_2; 10 unsigned int1 fakenum=TDC_TFAKENUM_2;
11 unsigned int1 selclkT=TDC_TSELCLK_128HS; 11 unsigned int1 selclkT=TDC_TSELCLK_128HS;
12 unsigned int1 calibrate=TDC_CALIBRATE_EN; 12 unsigned int1 calibrate=TDC_CALIBRATE_EN;
13 unsigned int1 disautocal=TDC_AUTOCAL_EN; 13 unsigned int1 disautocal=TDC_AUTOCAL_EN;
14 unsigned int1 MRange=TDC_MRANGE2; 14 unsigned int1 MRange=TDC_MRANGE2;
15 unsigned int1 neg_stop2=TDC_NEG_STOP2; 15 unsigned int1 neg_stop2=TDC_NEG_STOP2;
16 unsigned int1 neg_stop1=TDC_NEG_STOP1; 16 unsigned int1 neg_stop1=TDC_NEG_STOP1;
17 unsigned int1 neg_start=TDC_NEG_START; 17 unsigned int1 neg_start=TDC_NEG_START;
18 //}reg0; 18 //}reg0;
19   19  
20 //struct { 20 //struct {
21 unsigned int hit2=TDC_MRANGE1_HIT2_NOAC; 21 unsigned int hit2=TDC_MRANGE1_HIT2_NOAC;
22 unsigned int hit1=TDC_MRANGE1_HIT1_NOAC; 22 unsigned int hit1=TDC_MRANGE1_HIT1_NOAC;
23 unsigned int1 fast_init=TDC_FAST_INIT_DIS; 23 unsigned int1 fast_init=TDC_FAST_INIT_DIS;
24 unsigned int hitin2=TDC_HITIN2_0; 24 unsigned int hitin2=TDC_HITIN2_0;
25 unsigned int hitin1=TDC_HITIN1_0; 25 unsigned int hitin1=TDC_HITIN1_0;
26 //}reg1; 26 //}reg1;
27   27  
28 //struct { 28 //struct {
29 unsigned int en_int=TDC_INT_ALU; 29 unsigned int en_int=TDC_INT_ALU;
30 unsigned int1 rfedge2=TDC_CH2EDGE_RIS; 30 unsigned int1 rfedge2=TDC_CH2EDGE_RIS;
31 unsigned int1 rfedge1=TDC_CH1EDGE_RIS; 31 unsigned int1 rfedge1=TDC_CH1EDGE_RIS;
32 unsigned int32 delval1=0; 32 unsigned int32 delval1=0;
33 //}reg2; 33 //}reg2;
34   34  
35 //struct { 35 //struct {
36 unsigned int1 en_err_val=TDC_ERRVAL_DIS; 36 unsigned int1 en_err_val=TDC_ERRVAL_DIS;
37 unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS; 37 unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS;
38 unsigned int32 delval2=0; 38 unsigned int32 delval2=0;
39 //}reg3; 39 //}reg3;
40   40  
41 //reg4 41 //reg4
42 unsigned int32 delval3=0; 42 unsigned int32 delval3=0;
43   43  
44 //reg5 44 //reg5
45 unsigned int conf_fire=0; 45 unsigned int conf_fire=0;
46 unsigned int1 en_startnoise=TDC_STARTNOISE_DIS; 46 unsigned int1 en_startnoise=TDC_STARTNOISE_DIS;
47 unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS; 47 unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS;
48 unsigned int repeat_fire=TDC_REPEAT_FIRE_0; 48 unsigned int repeat_fire=TDC_REPEAT_FIRE_0;
49 unsigned int16 phase_fire=0; 49 unsigned int16 phase_fire=0;
50   50  
51 //}TDC_registers; 51 //}TDC_registers;
52   52  
53   53  
54 /* 54 /*
55 1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR 55 1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR
56 1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR 56 1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR
57 0 1 1 1 0 0 0 0 Init 57 0 1 1 1 0 0 0 0 Init
58 0 1 0 1 0 0 0 0 Power On Reset 58 0 1 0 1 0 0 0 0 Power On Reset
59 0 0 0 0 0 0 0 1 Start_Cycle 59 0 0 0 0 0 0 0 1 Start_Cycle
60 0 0 0 0 0 0 1 0 Start_Temp 60 0 0 0 0 0 0 1 0 Start_Temp
61 0 0 0 0 0 0 1 1 Start_Cal_Resonator 61 0 0 0 0 0 0 1 1 Start_Cal_Resonator
62 0 0 0 0 0 1 0 0 Start_Cal_TDC 62 0 0 0 0 0 1 0 0 Start_Cal_TDC
63 */ 63 */
64   64  
65 void TDC_init() 65 void TDC_init()
66 { 66 {
67 output_low(TDC_ENABLE); 67 output_low(TDC_ENABLE);
68 spi_xfer(TDC_stream,0x70,8); 68 spi_xfer(TDC_stream,0x70,8);
69 output_high(TDC_ENABLE); 69 output_high(TDC_ENABLE);
70 } 70 }
71   71  
72 void TDC_reset() 72 void TDC_reset()
73 { 73 {
74 output_low(TDC_ENABLE); 74 output_low(TDC_ENABLE);
75 spi_xfer(TDC_stream,0x50,8); 75 spi_xfer(TDC_stream,0x50,8);
76 output_high(TDC_ENABLE); 76 output_high(TDC_ENABLE);
-   77  
-   78 //reset registers settings to default
-   79  
-   80 firenum=TDC_FIRENUM_0;
-   81 div_fire=TDC_DIV_FIRE_2;
-   82 calresnum=TDC_CALPERIODS_2;
-   83 clkhsdiv=TDC_CLKHSDIV_1;
-   84 start_clkhs=TDC_CLKHS_ON;
-   85 portnum=TDC_TPORTNUM_4;
-   86 Tcycle=TDC_TCYCLE_SHORT;
-   87 fakenum=TDC_TFAKENUM_2;
-   88 selclkT=TDC_TSELCLK_128HS;
-   89 calibrate=TDC_CALIBRATE_EN;
-   90 disautocal=TDC_AUTOCAL_EN;
-   91 MRange=TDC_MRANGE2;
-   92 neg_stop2=TDC_NEG_STOP2;
-   93 neg_stop1=TDC_NEG_STOP1;
-   94 neg_start=TDC_NEG_START;
-   95 hit2=TDC_MRANGE1_HIT2_NOAC;
-   96 hit1=TDC_MRANGE1_HIT1_NOAC;
-   97 fast_init=TDC_FAST_INIT_DIS;
-   98 hitin2=TDC_HITIN2_0;
-   99 hitin1=TDC_HITIN1_0;
-   100 en_int=TDC_INT_ALU;
-   101 rfedge2=TDC_CH2EDGE_RIS;
-   102 rfedge1=TDC_CH1EDGE_RIS;
-   103 en_err_val=TDC_ERRVAL_DIS;
-   104 tim0_mr2=TDC_TIM0MR2_16384CLKHS;
-   105 delval1=0;
-   106 delval2=0;
-   107 delval3=0;
-   108 conf_fire=0;
-   109 en_startnoise=TDC_STARTNOISE_DIS;
-   110 dis_phasenoise=TDC_PHASENOISE_DIS;
-   111 repeat_fire=TDC_REPEAT_FIRE_0;
-   112 phase_fire=0;
77 } 113 }
78   114  
79 void TDC_start_cycle() 115 void TDC_start_cycle()
80 { 116 {
81 output_low(TDC_ENABLE); 117 output_low(TDC_ENABLE);
82 spi_xfer(TDC_stream,0x01,8); 118 spi_xfer(TDC_stream,0x01,8);
83 output_high(TDC_ENABLE); 119 output_high(TDC_ENABLE);
84 } 120 }
85   121  
86 void TDC_start_temp() 122 void TDC_start_temp()
87 { 123 {
88 output_low(TDC_ENABLE); 124 output_low(TDC_ENABLE);
89 spi_xfer(TDC_stream,0x02,8); 125 spi_xfer(TDC_stream,0x02,8);
90 output_high(TDC_ENABLE); 126 output_high(TDC_ENABLE);
91 } 127 }
92   128  
93 void TDC_start_cal_resonator() 129 void TDC_start_cal_resonator()
94 { 130 {
95 output_low(TDC_ENABLE); 131 output_low(TDC_ENABLE);
96 spi_xfer(TDC_stream,0x03,8); 132 spi_xfer(TDC_stream,0x03,8);
97 output_high(TDC_ENABLE); 133 output_high(TDC_ENABLE);
98 } 134 }
99   135  
100 void TDC_start_cal() 136 void TDC_start_cal()
101 { 137 {
102 output_low(TDC_ENABLE); 138 output_low(TDC_ENABLE);
103 spi_xfer(TDC_stream,0x04,8); 139 spi_xfer(TDC_stream,0x04,8);
104 output_high(TDC_ENABLE); 140 output_high(TDC_ENABLE);
105 } 141 }
106   142  
107 unsigned int32 TDC_get_measurement(int num) 143 unsigned int32 TDC_get_measurement(int num)
108 { 144 {
109 unsigned int32 ret; 145 unsigned int32 ret=0;
110   146  
111 output_low(TDC_ENABLE); 147 output_low(TDC_ENABLE);
112 spi_xfer(TDC_stream,0xB0 + num - 1, 8); 148 spi_xfer(TDC_stream,0xB0 + num - 1, 8);
113 ret=spi_xfer(TDC_stream,0,32); 149 ret=spi_xfer(TDC_stream,0,32);
114 output_high(TDC_ENABLE); 150 output_high(TDC_ENABLE);
115 return ret; 151 return ret;
116 } 152 }
117   153  
118 unsigned int16 TDC_get_status() 154 unsigned int16 TDC_get_status()
119 { 155 {
120 unsigned int16 ret; 156 unsigned int16 ret;
121   157  
122 output_low(TDC_ENABLE); 158 output_low(TDC_ENABLE);
123 spi_xfer(TDC_stream,0xB4,8); 159 spi_xfer(TDC_stream,0xB4,8);
124 ret=spi_xfer(TDC_stream,0,16); 160 ret=spi_xfer(TDC_stream,0,16);
125 output_high(TDC_ENABLE); 161 output_high(TDC_ENABLE);
126 return ret; 162 return ret;
127 } 163 }
128   164  
129 unsigned int8 TDC_get_reg1() 165 unsigned int8 TDC_get_reg1()
130 { 166 {
131 unsigned int8 ret; 167 unsigned int8 ret;
132   168  
133 output_low(TDC_ENABLE); 169 output_low(TDC_ENABLE);
134 spi_xfer(TDC_stream,0xB5,8); 170 spi_xfer(TDC_stream,0xB5,8);
135 ret=spi_xfer(TDC_stream,0,8); 171 ret=spi_xfer(TDC_stream,0,8);
136 output_high(TDC_ENABLE); 172 output_high(TDC_ENABLE);
137 return ret; 173 return ret;
138 } 174 }
139   175  
140 void TDC_update_reg1() // updates reg1 only 176 void TDC_update_reg1() // updates reg1 only
141 { 177 {
142 output_low(TDC_ENABLE); 178 output_low(TDC_ENABLE);
143 spi_xfer(TDC_stream,0x81,8); 179 spi_xfer(TDC_stream,0x81,8);
144 spi_xfer(TDC_stream,hit2,4); 180 spi_xfer(TDC_stream,hit2,4);
145 spi_xfer(TDC_stream,hit1,4); 181 spi_xfer(TDC_stream,hit1,4);
146 spi_xfer(TDC_stream,fast_init,1); 182 spi_xfer(TDC_stream,fast_init,1);
147 spi_xfer(TDC_stream,1,1); 183 spi_xfer(TDC_stream,1,1);
148 spi_xfer(TDC_stream,hitin2,3); 184 spi_xfer(TDC_stream,hitin2,3);
149 spi_xfer(TDC_stream,hitin1,3); 185 spi_xfer(TDC_stream,hitin1,3);
150 spi_xfer(TDC_stream,0,8); 186 spi_xfer(TDC_stream,0,8);
151 output_high(TDC_ENABLE); 187 output_high(TDC_ENABLE);
152 } 188 }
153   189  
154 void TDC_update_registers() 190 void TDC_update_registers()
155 { 191 {
156 //update reg0 192 //update reg0
157 output_low(TDC_ENABLE); 193 output_low(TDC_ENABLE);
158 spi_xfer(TDC_stream,0x80,8); 194 spi_xfer(TDC_stream,0x80,8);
159 spi_xfer(TDC_stream,firenum,4); 195 spi_xfer(TDC_stream,firenum,4);
160 spi_xfer(TDC_stream,div_fire,4); 196 spi_xfer(TDC_stream,div_fire,4);
161 spi_xfer(TDC_stream,calresnum,2); 197 spi_xfer(TDC_stream,calresnum,2);
162 spi_xfer(TDC_stream,clkhsdiv,2); 198 spi_xfer(TDC_stream,clkhsdiv,2);
163 spi_xfer(TDC_stream,start_clkhs,2); 199 spi_xfer(TDC_stream,start_clkhs,2);
164 spi_xfer(TDC_stream,portnum,1); 200 spi_xfer(TDC_stream,portnum,1);
165 spi_xfer(TDC_stream,Tcycle,1); 201 spi_xfer(TDC_stream,Tcycle,1);
166 spi_xfer(TDC_stream,fakenum,1); 202 spi_xfer(TDC_stream,fakenum,1);
167 spi_xfer(TDC_stream,selclkT,1); 203 spi_xfer(TDC_stream,selclkT,1);
168 spi_xfer(TDC_stream,calibrate,1); 204 spi_xfer(TDC_stream,calibrate,1);
169 spi_xfer(TDC_stream,disautocal,1); 205 spi_xfer(TDC_stream,disautocal,1);
170 spi_xfer(TDC_stream,MRange,1); 206 spi_xfer(TDC_stream,MRange,1);
171 spi_xfer(TDC_stream,neg_stop2,1); 207 spi_xfer(TDC_stream,neg_stop2,1);
172 spi_xfer(TDC_stream,neg_stop1,1); 208 spi_xfer(TDC_stream,neg_stop1,1);
173 spi_xfer(TDC_stream,neg_start,1); 209 spi_xfer(TDC_stream,neg_start,1);
174 output_high(TDC_ENABLE); 210 output_high(TDC_ENABLE);
175   211  
176 TDC_update_reg1(); // update reg1 212 TDC_update_reg1(); // update reg1
177   213  
178 // update reg2 214 // update reg2
179 output_low(TDC_ENABLE); 215 output_low(TDC_ENABLE);
180 spi_xfer(TDC_stream,0x82); 216 spi_xfer(TDC_stream,0x82);
181 spi_xfer(TDC_stream,en_int,3); 217 spi_xfer(TDC_stream,en_int,3);
182 spi_xfer(TDC_stream,rfedge2,1); 218 spi_xfer(TDC_stream,rfedge2,1);
183 spi_xfer(TDC_stream,rfedge1,1); 219 spi_xfer(TDC_stream,rfedge1,1);
184 spi_xfer(TDC_stream,delval1,19); 220 spi_xfer(TDC_stream,delval1,19);
185 output_high(TDC_ENABLE); 221 output_high(TDC_ENABLE);
186   222  
187 // update reg3 223 // update reg3
188 output_low(TDC_ENABLE); 224 output_low(TDC_ENABLE);
189 spi_xfer(TDC_stream,0x83); 225 spi_xfer(TDC_stream,0x83);
190 spi_xfer(TDC_stream,0,2); 226 spi_xfer(TDC_stream,0,2);
191 spi_xfer(TDC_stream,en_err_val,1); 227 spi_xfer(TDC_stream,en_err_val,1);
192 spi_xfer(TDC_stream,tim0_mr2,2); 228 spi_xfer(TDC_stream,tim0_mr2,2);
193 spi_xfer(TDC_stream,delval2,19); 229 spi_xfer(TDC_stream,delval2,19);
194 output_high(TDC_ENABLE); 230 output_high(TDC_ENABLE);
195   231  
196 // update reg4 232 // update reg4
197 output_low(TDC_ENABLE); 233 output_low(TDC_ENABLE);
198 spi_xfer(TDC_stream,0x84); 234 spi_xfer(TDC_stream,0x84);
199 spi_xfer(TDC_stream,0b00100,5); 235 spi_xfer(TDC_stream,0b00100,5);
200 spi_xfer(TDC_stream,delval3,19); 236 spi_xfer(TDC_stream,delval3,19);
201 output_high(TDC_ENABLE); 237 output_high(TDC_ENABLE);
202   238  
203 // update reg5 239 // update reg5
204 output_low(TDC_ENABLE); 240 output_low(TDC_ENABLE);
205 spi_xfer(TDC_stream,0x85); 241 spi_xfer(TDC_stream,0x85);
206 spi_xfer(TDC_stream,conf_fire,3); 242 spi_xfer(TDC_stream,conf_fire,3);
207 spi_xfer(TDC_stream,en_startnoise,1); 243 spi_xfer(TDC_stream,en_startnoise,1);
208 spi_xfer(TDC_stream,dis_phasenoise,1); 244 spi_xfer(TDC_stream,dis_phasenoise,1);
209 spi_xfer(TDC_stream,repeat_fire,3); 245 spi_xfer(TDC_stream,repeat_fire,3);
210 spi_xfer(TDC_stream,phase_fire,16); 246 spi_xfer(TDC_stream,phase_fire,16);
211 output_high(TDC_ENABLE); 247 output_high(TDC_ENABLE);
212 } 248 }
213   249  
214 float TDC_mrange2_get_time(unsigned int shot) 250 float TDC_mrange2_get_time(unsigned int shot) // read start to stop time distance of desired shot
215 { 251 {
216 unsigned int32 measurement; 252 unsigned int32 measurement;
217 float time; 253 float time;
218   254  
219 switch (shot) 255 switch (shot) // determine which shot is desired to compute
220 { 256 {
221 case 1: 257 case 1:
222 hit2=TDC_MRANGE2_HIT2_1CH1; 258 hit2=TDC_MRANGE2_HIT2_1CH1;
223 break; 259 break;
224   260  
225 case 2: 261 case 2:
226 hit2=TDC_MRANGE2_HIT2_2CH1; 262 hit2=TDC_MRANGE2_HIT2_2CH1;
227 break; 263 break;
228   264  
229 case 3: 265 case 3:
230 hit2=TDC_MRANGE2_HIT2_3CH1; 266 hit2=TDC_MRANGE2_HIT2_3CH1;
231 break; 267 break;
232 } 268 }
233 TDC_update_reg1(); // tell to ALU which shot period must be computed 269 TDC_update_reg1(); // tell ALU which shot period must be computed
234 270
235 Delay_ms(50); // wait to computing of result 271 Delay_ms(50); // wait to computing of result
236 272
237 measurement=TDC_get_measurement(7&TDC_get_status()); // read computed value on pointer result register address 273 measurement=TDC_get_measurement(7&TDC_get_status()); // read computed value on pointer result register address
238 274
239   275  
240 switch (clkhsdiv) 276 switch (clkhsdiv) // calibrate measurement data to microseconds from known register setting
241 { 277 {
242 case TDC_CLKHSDIV_1: 278 case TDC_CLKHSDIV_1:
243 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS; 279 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS;
244 break; 280 break;
245   281  
246 case TDC_CLKHSDIV_2: 282 case TDC_CLKHSDIV_2:
247 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 2.0; 283 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 2.0;
248 break; 284 break;
249   285  
250 case TDC_CLKHSDIV_4: 286 case TDC_CLKHSDIV_4:
251 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 4.0; 287 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 4.0;
252 break; 288 break;
253 case TDC_CLKHSDIV_8: 289 case TDC_CLKHSDIV_8:
254 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 8.0; 290 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 8.0;
255 break; 291 break;
256 } 292 }
257 return time; 293 return time;
258 } 294 }
259   295  
260 float TDC_mrange1_get_time(unsigned int channel1, unsigned int shot1, unsigned int channel2, unsigned int shot2) 296 float TDC_mrange1_get_time(unsigned int channel1, unsigned int shot1, unsigned int channel2, unsigned int shot2)
261 { 297 {
262 unsigned int32 measurement; 298 unsigned int32 measurement;
263 float time; 299 float time;
264   300  
265 switch (shot1) 301 switch (shot1)
266 { 302 {
267 case 0: 303 case 0:
268 hit1=TDC_MRANGE1_HIT1_START; 304 hit1=TDC_MRANGE1_HIT1_START;
269 break; 305 break;
270 case 1: 306 case 1:
271 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_1CH1; else hit1=TDC_MRANGE1_HIT1_1CH2; 307 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_1CH1; else hit1=TDC_MRANGE1_HIT1_1CH2;
272 break; 308 break;
273   309  
274 case 2: 310 case 2:
275 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_2CH1; else hit1=TDC_MRANGE1_HIT1_2CH2; 311 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_2CH1; else hit1=TDC_MRANGE1_HIT1_2CH2;
276 break; 312 break;
277   313  
278 case 3: 314 case 3:
279 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_3CH1; else hit1=TDC_MRANGE1_HIT1_3CH2; 315 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_3CH1; else hit1=TDC_MRANGE1_HIT1_3CH2;
280 break; 316 break;
281   317  
282 case 4: 318 case 4:
283 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_4CH1; else hit1=TDC_MRANGE1_HIT1_4CH2; 319 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_4CH1; else hit1=TDC_MRANGE1_HIT1_4CH2;
284 break; 320 break;
285 } 321 }
286   322  
287 switch (shot2) 323 switch (shot2)
288 { 324 {
289 case 0: 325 case 0:
290 hit2=TDC_MRANGE1_HIT2_START; 326 hit2=TDC_MRANGE1_HIT2_START;
291 break; 327 break;
292   328  
293 case 1: 329 case 1:
294 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_1CH1; else hit2=TDC_MRANGE1_HIT2_1CH2; 330 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_1CH1; else hit2=TDC_MRANGE1_HIT2_1CH2;
295 break; 331 break;
296   332  
297 case 2: 333 case 2:
298 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_2CH1; else hit2=TDC_MRANGE1_HIT2_2CH2; 334 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_2CH1; else hit2=TDC_MRANGE1_HIT2_2CH2;
299 break; 335 break;
300   336  
301 case 3: 337 case 3:
302 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_3CH1; else hit2=TDC_MRANGE1_HIT2_3CH2; 338 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_3CH1; else hit2=TDC_MRANGE1_HIT2_3CH2;
303 break; 339 break;
304   340  
305 case 4: 341 case 4:
306 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_4CH1; else hit2=TDC_MRANGE1_HIT2_4CH2; 342 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_4CH1; else hit2=TDC_MRANGE1_HIT2_4CH2;
307 break; 343 break;
308 } 344 }
309   345  
310 TDC_update_reg1(); // tell to ALU which shot period must be computed 346 TDC_update_reg1(); // tell to ALU which shot period must be computed
311 347
312 Delay_ms(50); // wait to computing of result 348 Delay_ms(50); // wait to computing of result
313 349
314 measurement=TDC_get_measurement(7&TDC_get_status()); // read computed value on pointer result register address 350 measurement=TDC_get_measurement(7&TDC_get_status()); // read computed value on pointer result register address
315 351
316   352  
317 switch (clkhsdiv) 353 switch (clkhsdiv)
318 { 354 {
319 case TDC_CLKHSDIV_1: 355 case TDC_CLKHSDIV_1:
320 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS; 356 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS;
321 break; 357 break;
322   358  
323 case TDC_CLKHSDIV_2: 359 case TDC_CLKHSDIV_2:
324 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 2.0; 360 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 2.0;
325 break; 361 break;
326   362  
327 case TDC_CLKHSDIV_4: 363 case TDC_CLKHSDIV_4:
328 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 4.0; 364 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 4.0;
329 break; 365 break;
330 case TDC_CLKHSDIV_8: 366 case TDC_CLKHSDIV_8:
331 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 8.0; 367 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 8.0;
332 break; 368 break;
333 } 369 }
334 return time; 370 return time;
335 } 371 }