Rev 2184 Rev 2185
1   1  
2 //struct { 2 //struct {
3 unsigned int8 firenum=TDC_FIRENUM_0; 3 unsigned int8 firenum=TDC_FIRENUM_0;
4 unsigned int8 div_fire=TDC_DIV_FIRE_2; 4 unsigned int8 div_fire=TDC_DIV_FIRE_2;
5 unsigned int8 calresnum=TDC_CALPERIODS_2; 5 unsigned int8 calresnum=TDC_CALPERIODS_2;
6 unsigned int8 clkhsdiv=TDC_CLKHSDIV_1; 6 unsigned int8 clkhsdiv=TDC_CLKHSDIV_1;
7 unsigned int8 start_clkhs=TDC_CLKHS_ON; 7 unsigned int8 start_clkhs=TDC_CLKHS_ON;
8 unsigned int1 portnum=TDC_TPORTNUM_4; 8 unsigned int1 portnum=TDC_TPORTNUM_4;
9 unsigned int1 Tcycle=TDC_TCYCLE_SHORT; 9 unsigned int1 Tcycle=TDC_TCYCLE_SHORT;
10 unsigned int1 fakenum=TDC_TFAKENUM_2; 10 unsigned int1 fakenum=TDC_TFAKENUM_2;
11 unsigned int1 selclkT=TDC_TSELCLK_128HS; 11 unsigned int1 selclkT=TDC_TSELCLK_128HS;
12 unsigned int1 calibrate=TDC_CALIBRATE_EN; 12 unsigned int1 calibrate=TDC_CALIBRATE_EN;
13 unsigned int1 disautocal=TDC_AUTOCAL_EN; 13 unsigned int1 disautocal=TDC_AUTOCAL_EN;
14 unsigned int1 MRange=TDC_MRANGE2; 14 unsigned int1 MRange=TDC_MRANGE2;
15 unsigned int1 neg_stop2=TDC_NEG_STOP2; 15 unsigned int1 neg_stop2=TDC_NEG_STOP2;
16 unsigned int1 neg_stop1=TDC_NEG_STOP1; 16 unsigned int1 neg_stop1=TDC_NEG_STOP1;
17 unsigned int1 neg_start=TDC_NEG_START; 17 unsigned int1 neg_start=TDC_NEG_START;
18 //}reg0; 18 //}reg0;
19   19  
20 //struct { 20 //struct {
21 unsigned int hit2=TDC_MRANGE1_HIT2_NOAC; 21 unsigned int hit2=TDC_MRANGE1_HIT2_NOAC;
22 unsigned int hit1=TDC_MRANGE1_HIT1_NOAC; 22 unsigned int hit1=TDC_MRANGE1_HIT1_NOAC;
23 unsigned int1 fast_init=TDC_FAST_INIT_DIS; 23 unsigned int1 fast_init=TDC_FAST_INIT_DIS;
24 unsigned int hitin2=TDC_HITIN2_0; 24 unsigned int hitin2=TDC_HITIN2_0;
25 unsigned int hitin1=TDC_HITIN1_0; 25 unsigned int hitin1=TDC_HITIN1_0;
26 //}reg1; 26 //}reg1;
27   27  
28 //struct { 28 //struct {
29 unsigned int en_int=TDC_INT_ALU; 29 unsigned int en_int=TDC_INT_ALU;
30 unsigned int1 rfedge2=TDC_CH2EDGE_RIS; 30 unsigned int1 rfedge2=TDC_CH2EDGE_RIS;
31 unsigned int1 rfedge1=TDC_CH1EDGE_RIS; 31 unsigned int1 rfedge1=TDC_CH1EDGE_RIS;
32 unsigned int32 delval1=0; 32 unsigned int32 delval1=0;
33 //}reg2; 33 //}reg2;
34   34  
35 //struct { 35 //struct {
36 unsigned int1 en_err_val=TDC_ERRVAL_DIS; 36 unsigned int1 en_err_val=TDC_ERRVAL_DIS;
37 unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS; 37 unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS;
38 unsigned int32 delval2=0; 38 unsigned int32 delval2=0;
39 //}reg3; 39 //}reg3;
40   40  
41 //reg4 41 //reg4
42 unsigned int32 delval3=0; 42 unsigned int32 delval3=0;
43   43  
44 //reg5 44 //reg5
45 unsigned int conf_fire=0; 45 unsigned int conf_fire=0;
46 unsigned int1 en_startnoise=TDC_STARTNOISE_DIS; 46 unsigned int1 en_startnoise=TDC_STARTNOISE_DIS;
47 unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS; 47 unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS;
48 unsigned int repeat_fire=TDC_REPEAT_FIRE_0; 48 unsigned int repeat_fire=TDC_REPEAT_FIRE_0;
49 unsigned int16 phase_fire=0; 49 unsigned int16 phase_fire=0;
50   50  
51 //}TDC_registers; 51 //}TDC_registers;
52   52  
53   53  
54 /* 54 /*
55 1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR 55 1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR
56 1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR 56 1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR
57 0 1 1 1 0 0 0 0 Init 57 0 1 1 1 0 0 0 0 Init
58 0 1 0 1 0 0 0 0 Power On Reset 58 0 1 0 1 0 0 0 0 Power On Reset
59 0 0 0 0 0 0 0 1 Start_Cycle 59 0 0 0 0 0 0 0 1 Start_Cycle
60 0 0 0 0 0 0 1 0 Start_Temp 60 0 0 0 0 0 0 1 0 Start_Temp
61 0 0 0 0 0 0 1 1 Start_Cal_Resonator 61 0 0 0 0 0 0 1 1 Start_Cal_Resonator
62 0 0 0 0 0 1 0 0 Start_Cal_TDC 62 0 0 0 0 0 1 0 0 Start_Cal_TDC
63 */ 63 */
64   64  
65 void TDC_init() 65 void TDC_init()
66 { 66 {
67 output_low(TDC_ENABLE); 67 output_low(TDC_ENABLE);
68 spi_xfer(TDC_stream,0x70,8); 68 spi_xfer(TDC_stream,0x70,8);
69 output_high(TDC_ENABLE); 69 output_high(TDC_ENABLE);
70 } 70 }
71   71  
72 void TDC_reset() 72 void TDC_reset()
73 { 73 {
74 output_low(TDC_ENABLE); 74 output_low(TDC_ENABLE);
75 spi_xfer(TDC_stream,0x50,8); 75 spi_xfer(TDC_stream,0x50,8);
76 output_high(TDC_ENABLE); 76 output_high(TDC_ENABLE);
77   77  
78 //reset registers settings to default 78 //reset registers settings to default
79   79  
80 firenum=TDC_FIRENUM_0; 80 firenum=TDC_FIRENUM_0;
81 div_fire=TDC_DIV_FIRE_2; 81 div_fire=TDC_DIV_FIRE_2;
82 calresnum=TDC_CALPERIODS_2; 82 calresnum=TDC_CALPERIODS_2;
83 clkhsdiv=TDC_CLKHSDIV_1; 83 clkhsdiv=TDC_CLKHSDIV_1;
84 start_clkhs=TDC_CLKHS_ON; 84 start_clkhs=TDC_CLKHS_ON;
85 portnum=TDC_TPORTNUM_4; 85 portnum=TDC_TPORTNUM_4;
86 Tcycle=TDC_TCYCLE_SHORT; 86 Tcycle=TDC_TCYCLE_SHORT;
87 fakenum=TDC_TFAKENUM_2; 87 fakenum=TDC_TFAKENUM_2;
88 selclkT=TDC_TSELCLK_128HS; 88 selclkT=TDC_TSELCLK_128HS;
89 calibrate=TDC_CALIBRATE_EN; 89 calibrate=TDC_CALIBRATE_EN;
90 disautocal=TDC_AUTOCAL_EN; 90 disautocal=TDC_AUTOCAL_EN;
91 MRange=TDC_MRANGE2; 91 MRange=TDC_MRANGE2;
92 neg_stop2=TDC_NEG_STOP2; 92 neg_stop2=TDC_NEG_STOP2;
93 neg_stop1=TDC_NEG_STOP1; 93 neg_stop1=TDC_NEG_STOP1;
94 neg_start=TDC_NEG_START; 94 neg_start=TDC_NEG_START;
95 hit2=TDC_MRANGE1_HIT2_NOAC; 95 hit2=TDC_MRANGE1_HIT2_NOAC;
96 hit1=TDC_MRANGE1_HIT1_NOAC; 96 hit1=TDC_MRANGE1_HIT1_NOAC;
97 fast_init=TDC_FAST_INIT_DIS; 97 fast_init=TDC_FAST_INIT_DIS;
98 hitin2=TDC_HITIN2_0; 98 hitin2=TDC_HITIN2_0;
99 hitin1=TDC_HITIN1_0; 99 hitin1=TDC_HITIN1_0;
100 en_int=TDC_INT_ALU; 100 en_int=TDC_INT_ALU;
101 rfedge2=TDC_CH2EDGE_RIS; 101 rfedge2=TDC_CH2EDGE_RIS;
102 rfedge1=TDC_CH1EDGE_RIS; 102 rfedge1=TDC_CH1EDGE_RIS;
103 en_err_val=TDC_ERRVAL_DIS; 103 en_err_val=TDC_ERRVAL_DIS;
104 tim0_mr2=TDC_TIM0MR2_16384CLKHS; 104 tim0_mr2=TDC_TIM0MR2_16384CLKHS;
105 delval1=0; 105 delval1=0;
106 delval2=0; 106 delval2=0;
107 delval3=0; 107 delval3=0;
108 conf_fire=0; 108 conf_fire=0;
109 en_startnoise=TDC_STARTNOISE_DIS; 109 en_startnoise=TDC_STARTNOISE_DIS;
110 dis_phasenoise=TDC_PHASENOISE_DIS; 110 dis_phasenoise=TDC_PHASENOISE_DIS;
111 repeat_fire=TDC_REPEAT_FIRE_0; 111 repeat_fire=TDC_REPEAT_FIRE_0;
112 phase_fire=0; 112 phase_fire=0;
113 } 113 }
114   114  
115 void TDC_start_cycle() 115 void TDC_start_cycle()
116 { 116 {
117 output_low(TDC_ENABLE); 117 output_low(TDC_ENABLE);
118 spi_xfer(TDC_stream,0x01,8); 118 spi_xfer(TDC_stream,0x01,8);
119 output_high(TDC_ENABLE); 119 output_high(TDC_ENABLE);
120 } 120 }
121   121  
122 void TDC_start_temp() 122 void TDC_start_temp()
123 { 123 {
124 output_low(TDC_ENABLE); 124 output_low(TDC_ENABLE);
125 spi_xfer(TDC_stream,0x02,8); 125 spi_xfer(TDC_stream,0x02,8);
126 output_high(TDC_ENABLE); 126 output_high(TDC_ENABLE);
127 } 127 }
128   128  
129 void TDC_start_cal_resonator() 129 void TDC_start_cal_resonator()
130 { 130 {
131 output_low(TDC_ENABLE); 131 output_low(TDC_ENABLE);
132 spi_xfer(TDC_stream,0x03,8); 132 spi_xfer(TDC_stream,0x03,8);
133 output_high(TDC_ENABLE); 133 output_high(TDC_ENABLE);
134 } 134 }
135   135  
136 void TDC_start_cal() 136 void TDC_start_cal()
137 { 137 {
138 output_low(TDC_ENABLE); 138 output_low(TDC_ENABLE);
139 spi_xfer(TDC_stream,0x04,8); 139 spi_xfer(TDC_stream,0x04,8);
140 output_high(TDC_ENABLE); 140 output_high(TDC_ENABLE);
141 } 141 }
142   142  
143 unsigned int32 TDC_get_measurement(int num) 143 unsigned int32 TDC_get_measurement(int num)
144 { 144 {
145 unsigned int32 ret=0; 145 unsigned int32 ret=0;
146   146  
147 output_low(TDC_ENABLE); 147 output_low(TDC_ENABLE);
148 spi_xfer(TDC_stream,0xB0 + num - 1, 8); 148 spi_xfer(TDC_stream,0xB0 + num - 1, 8);
149 ret=spi_xfer(TDC_stream,0,32); 149 ret=spi_xfer(TDC_stream,0,32);
150 output_high(TDC_ENABLE); 150 output_high(TDC_ENABLE);
151 return ret; 151 return ret;
152 } 152 }
153   153  
154 unsigned int16 TDC_get_status() // reads status register 154 unsigned int16 TDC_get_status() // reads status register
155 { 155 {
156 unsigned int16 ret; 156 unsigned int16 ret;
157   157  
158 output_low(TDC_ENABLE); 158 output_low(TDC_ENABLE);
159 spi_xfer(TDC_stream,0xB4,8); 159 spi_xfer(TDC_stream,0xB4,8);
160 ret=spi_xfer(TDC_stream,0,16); 160 ret=spi_xfer(TDC_stream,0,16);
161 output_high(TDC_ENABLE); 161 output_high(TDC_ENABLE);
162 return ret; 162 return ret;
163 } 163 }
164   164  
165 unsigned int8 TDC_get_reg1() 165 unsigned int8 TDC_get_reg1()
166 { 166 {
167 unsigned int8 ret; 167 unsigned int8 ret;
168   168  
169 output_low(TDC_ENABLE); 169 output_low(TDC_ENABLE);
170 spi_xfer(TDC_stream,0xB5,8); 170 spi_xfer(TDC_stream,0xB5,8);
171 ret=spi_xfer(TDC_stream,0,8); 171 ret=spi_xfer(TDC_stream,0,8);
172 output_high(TDC_ENABLE); 172 output_high(TDC_ENABLE);
173 return ret; 173 return ret;
174 } 174 }
175   175  
176 void TDC_update_reg1() // updates reg1 only 176 void TDC_update_reg1() // updates reg1 only
177 { 177 {
178 output_low(TDC_ENABLE); 178 output_low(TDC_ENABLE);
179 spi_xfer(TDC_stream,0x81,8); 179 spi_xfer(TDC_stream,0x81,8);
180 spi_xfer(TDC_stream,hit2,4); 180 spi_xfer(TDC_stream,hit2,4);
181 spi_xfer(TDC_stream,hit1,4); 181 spi_xfer(TDC_stream,hit1,4);
182 spi_xfer(TDC_stream,fast_init,1); 182 spi_xfer(TDC_stream,fast_init,1);
183 spi_xfer(TDC_stream,1,1); 183 spi_xfer(TDC_stream,1,1);
184 spi_xfer(TDC_stream,hitin2,3); 184 spi_xfer(TDC_stream,hitin2,3);
185 spi_xfer(TDC_stream,hitin1,3); 185 spi_xfer(TDC_stream,hitin1,3);
186 spi_xfer(TDC_stream,0,8); 186 spi_xfer(TDC_stream,0,8);
187 output_high(TDC_ENABLE); 187 output_high(TDC_ENABLE);
188 } 188 }
189   189  
190 void TDC_update_registers() 190 void TDC_update_registers()
191 { 191 {
192 //update reg0 192 //update reg0
193 output_low(TDC_ENABLE); 193 output_low(TDC_ENABLE);
194 spi_xfer(TDC_stream,0x80,8); 194 spi_xfer(TDC_stream,0x80,8);
195 spi_xfer(TDC_stream,firenum,4); 195 spi_xfer(TDC_stream,firenum,4);
196 spi_xfer(TDC_stream,div_fire,4); 196 spi_xfer(TDC_stream,div_fire,4);
197 spi_xfer(TDC_stream,calresnum,2); 197 spi_xfer(TDC_stream,calresnum,2);
198 spi_xfer(TDC_stream,clkhsdiv,2); 198 spi_xfer(TDC_stream,clkhsdiv,2);
199 spi_xfer(TDC_stream,start_clkhs,2); 199 spi_xfer(TDC_stream,start_clkhs,2);
200 spi_xfer(TDC_stream,portnum,1); 200 spi_xfer(TDC_stream,portnum,1);
201 spi_xfer(TDC_stream,Tcycle,1); 201 spi_xfer(TDC_stream,Tcycle,1);
202 spi_xfer(TDC_stream,fakenum,1); 202 spi_xfer(TDC_stream,fakenum,1);
203 spi_xfer(TDC_stream,selclkT,1); 203 spi_xfer(TDC_stream,selclkT,1);
204 spi_xfer(TDC_stream,calibrate,1); 204 spi_xfer(TDC_stream,calibrate,1);
205 spi_xfer(TDC_stream,disautocal,1); 205 spi_xfer(TDC_stream,disautocal,1);
206 spi_xfer(TDC_stream,MRange,1); 206 spi_xfer(TDC_stream,MRange,1);
207 spi_xfer(TDC_stream,neg_stop2,1); 207 spi_xfer(TDC_stream,neg_stop2,1);
208 spi_xfer(TDC_stream,neg_stop1,1); 208 spi_xfer(TDC_stream,neg_stop1,1);
209 spi_xfer(TDC_stream,neg_start,1); 209 spi_xfer(TDC_stream,neg_start,1);
210 output_high(TDC_ENABLE); 210 output_high(TDC_ENABLE);
211   211  
212 TDC_update_reg1(); // update reg1 212 TDC_update_reg1(); // update reg1
213   213  
214 // update reg2 214 // update reg2
215 output_low(TDC_ENABLE); 215 output_low(TDC_ENABLE);
216 spi_xfer(TDC_stream,0x82); 216 spi_xfer(TDC_stream,0x82);
217 spi_xfer(TDC_stream,en_int,3); 217 spi_xfer(TDC_stream,en_int,3);
218 spi_xfer(TDC_stream,rfedge2,1); 218 spi_xfer(TDC_stream,rfedge2,1);
219 spi_xfer(TDC_stream,rfedge1,1); 219 spi_xfer(TDC_stream,rfedge1,1);
220 spi_xfer(TDC_stream,delval1,19); 220 spi_xfer(TDC_stream,delval1,19);
221 output_high(TDC_ENABLE); 221 output_high(TDC_ENABLE);
222   222  
223 // update reg3 223 // update reg3
224 output_low(TDC_ENABLE); 224 output_low(TDC_ENABLE);
225 spi_xfer(TDC_stream,0x83); 225 spi_xfer(TDC_stream,0x83);
226 spi_xfer(TDC_stream,0,2); 226 spi_xfer(TDC_stream,0,2);
227 spi_xfer(TDC_stream,en_err_val,1); 227 spi_xfer(TDC_stream,en_err_val,1);
228 spi_xfer(TDC_stream,tim0_mr2,2); 228 spi_xfer(TDC_stream,tim0_mr2,2);
229 spi_xfer(TDC_stream,delval2,19); 229 spi_xfer(TDC_stream,delval2,19);
230 output_high(TDC_ENABLE); 230 output_high(TDC_ENABLE);
231   231  
232 // update reg4 232 // update reg4
233 output_low(TDC_ENABLE); 233 output_low(TDC_ENABLE);
234 spi_xfer(TDC_stream,0x84); 234 spi_xfer(TDC_stream,0x84);
235 spi_xfer(TDC_stream,0b00100,5); 235 spi_xfer(TDC_stream,0b00100,5);
236 spi_xfer(TDC_stream,delval3,19); 236 spi_xfer(TDC_stream,delval3,19);
237 output_high(TDC_ENABLE); 237 output_high(TDC_ENABLE);
238   238  
239 // update reg5 239 // update reg5
240 output_low(TDC_ENABLE); 240 output_low(TDC_ENABLE);
241 spi_xfer(TDC_stream,0x85); 241 spi_xfer(TDC_stream,0x85);
242 spi_xfer(TDC_stream,conf_fire,3); 242 spi_xfer(TDC_stream,conf_fire,3);
243 spi_xfer(TDC_stream,en_startnoise,1); 243 spi_xfer(TDC_stream,en_startnoise,1);
244 spi_xfer(TDC_stream,dis_phasenoise,1); 244 spi_xfer(TDC_stream,dis_phasenoise,1);
245 spi_xfer(TDC_stream,repeat_fire,3); 245 spi_xfer(TDC_stream,repeat_fire,3);
246 spi_xfer(TDC_stream,phase_fire,16); 246 spi_xfer(TDC_stream,phase_fire,16);
247 output_high(TDC_ENABLE); 247 output_high(TDC_ENABLE);
248 } 248 }
249   249  
250 float TDC_mrange2_get_time(unsigned int shot) // read start to stop time distance of desired shot 250 float TDC_mrange2_get_time(unsigned int shot) // read start to stop time distance of desired shot
251 { 251 {
252 unsigned int32 measurement; 252 unsigned int32 measurement;
253 float time; 253 float time;
254   254  
255 switch (shot) // determine which shot is desired to compute 255 switch (shot) // determine which shot is desired to compute
256 { 256 {
257 case 1: 257 case 1:
258 hit2=TDC_MRANGE2_HIT2_1CH1; 258 hit2=TDC_MRANGE2_HIT2_1CH1;
259 break; 259 break;
260   260  
261 case 2: 261 case 2:
262 hit2=TDC_MRANGE2_HIT2_2CH1; 262 hit2=TDC_MRANGE2_HIT2_2CH1;
263 break; 263 break;
264   264  
265 case 3: 265 case 3:
266 hit2=TDC_MRANGE2_HIT2_3CH1; 266 hit2=TDC_MRANGE2_HIT2_3CH1;
267 break; 267 break;
268 } 268 }
269 TDC_update_reg1(); // tell ALU which shot period must be computed 269 TDC_update_reg1(); // tell ALU which shot period must be computed
270 270
271 Delay_ms(50); // wait to computing of result 271 Delay_ms(50); // wait to computing of result
272 272
273 measurement=TDC_get_measurement(7&TDC_get_status()); // read computed value on pointer result register address 273 measurement=TDC_get_measurement(7&TDC_get_status()); // read computed value on pointer result register address
274 274
275   275  
276 switch (clkhsdiv) // calibrate measurement data to microseconds from known register setting 276 switch (clkhsdiv) // calibrate measurement data to microseconds from known register setting
277 { 277 {
278 case TDC_CLKHSDIV_1: 278 case TDC_CLKHSDIV_1:
279 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS; 279 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS;
280 break; 280 break;
281   281  
282 case TDC_CLKHSDIV_2: 282 case TDC_CLKHSDIV_2:
283 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 2.0; 283 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 2.0;
284 break; 284 break;
285   285  
286 case TDC_CLKHSDIV_4: 286 case TDC_CLKHSDIV_4:
287 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 4.0; 287 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 4.0;
288 break; 288 break;
289 case TDC_CLKHSDIV_8: 289 case TDC_CLKHSDIV_8:
290 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 8.0; 290 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 8.0;
291 break; 291 break;
292 } 292 }
293 return time; 293 return time;
294 } 294 }
295   295  
296 float TDC_mrange1_get_time(unsigned int channel1, unsigned int shot1, unsigned int channel2, unsigned int shot2) 296 float TDC_mrange1_get_time(unsigned int channel1, unsigned int shot1, unsigned int channel2, unsigned int shot2)
297 { 297 {
298 unsigned int32 measurement; 298 unsigned int32 measurement;
299 float time; 299 float time;
300   300  
301 Delay_ms(10); // wait to computing of result 301 Delay_ms(10); // wait to computing of result
302   302  
303 switch (shot1) 303 switch (shot1)
304 { 304 {
305 case 0: 305 case 0:
306 hit1=TDC_MRANGE1_HIT1_START; 306 hit1=TDC_MRANGE1_HIT1_START;
307 break; 307 break;
308 case 1: 308 case 1:
309 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_1CH1; else hit1=TDC_MRANGE1_HIT1_1CH2; 309 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_1CH1; else hit1=TDC_MRANGE1_HIT1_1CH2;
310 break; 310 break;
311   311  
312 case 2: 312 case 2:
313 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_2CH1; else hit1=TDC_MRANGE1_HIT1_2CH2; 313 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_2CH1; else hit1=TDC_MRANGE1_HIT1_2CH2;
314 break; 314 break;
315   315  
316 case 3: 316 case 3:
317 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_3CH1; else hit1=TDC_MRANGE1_HIT1_3CH2; 317 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_3CH1; else hit1=TDC_MRANGE1_HIT1_3CH2;
318 break; 318 break;
319   319  
320 case 4: 320 case 4:
321 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_4CH1; else hit1=TDC_MRANGE1_HIT1_4CH2; 321 if (channel1 == 1) hit1=TDC_MRANGE1_HIT1_4CH1; else hit1=TDC_MRANGE1_HIT1_4CH2;
322 break; 322 break;
323 } 323 }
324   324  
325 switch (shot2) 325 switch (shot2)
326 { 326 {
327 case 0: 327 case 0:
328 hit2=TDC_MRANGE1_HIT2_START; 328 hit2=TDC_MRANGE1_HIT2_START;
329 break; 329 break;
330   330  
331 case 1: 331 case 1:
332 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_1CH1; else hit2=TDC_MRANGE1_HIT2_1CH2; 332 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_1CH1; else hit2=TDC_MRANGE1_HIT2_1CH2;
333 break; 333 break;
334   334  
335 case 2: 335 case 2:
336 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_2CH1; else hit2=TDC_MRANGE1_HIT2_2CH2; 336 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_2CH1; else hit2=TDC_MRANGE1_HIT2_2CH2;
337 break; 337 break;
338   338  
339 case 3: 339 case 3:
340 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_3CH1; else hit2=TDC_MRANGE1_HIT2_3CH2; 340 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_3CH1; else hit2=TDC_MRANGE1_HIT2_3CH2;
341 break; 341 break;
342   342  
343 case 4: 343 case 4:
344 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_4CH1; else hit2=TDC_MRANGE1_HIT2_4CH2; 344 if (channel2 == 1) hit2=TDC_MRANGE1_HIT2_4CH1; else hit2=TDC_MRANGE1_HIT2_4CH2;
345 break; 345 break;
346 } 346 }
347 347
348 // hit2=TDC_MRANGE1_HIT2_START; -  
349 // hit1=TDC_MRANGE1_HIT1_1CH1; -  
350   -  
351 TDC_update_reg1(); // tell to ALU which shot period must be computed 348 TDC_update_reg1(); // tell to ALU which shot period must be computed
352 349
353 Delay_ms(50); // wait to computing of result 350 Delay_ms(50); // wait to computing of result
354 351
355 measurement=TDC_get_measurement(7&TDC_get_status()); // read computed value on pointer result register address 352 measurement=TDC_get_measurement(7&TDC_get_status()); // read computed value on pointer result register address
356 353
357 printf("%Lu\r\n", (7&TDC_get_status())); 354 // printf("%Lu\r\n", (7&TDC_get_status()));
358 printf("%Lu\r\n", measurement); 355 // printf("%Lu\r\n", measurement);
359   356  
360 switch (clkhsdiv) 357 switch (clkhsdiv)
361 { 358 {
362 case TDC_CLKHSDIV_1: 359 case TDC_CLKHSDIV_1:
363 time=(measurement/65536.0)* 1.0e6/TDC_CLKHS; 360 time=(measurement/65536.0)* 1.0e6/TDC_CLKHS;
364 break; 361 break;
365   362  
366 case TDC_CLKHSDIV_2: 363 case TDC_CLKHSDIV_2:
367 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 2.0; 364 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 2.0;
368 break; 365 break;
369   366  
370 case TDC_CLKHSDIV_4: 367 case TDC_CLKHSDIV_4:
371 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 4.0; 368 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 4.0;
372 break; 369 break;
373 case TDC_CLKHSDIV_8: 370 case TDC_CLKHSDIV_8:
374 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 8.0; 371 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 8.0;
375 break; 372 break;
376 } 373 }
377 return time; 374 return time;
378 } 375 }