| 1 |
|
1 |
|
| 2 |
|
2 |
|
| 3 |
//register 0 |
3 |
//register 0 |
| 4 |
#define TDC_NEG_START_INV 1 |
4 |
#define TDC_NEG_START_INV 1 |
| 5 |
#define TDC_NEG_START 0 |
5 |
#define TDC_NEG_START 0 |
| 6 |
#define TDC_NEG_STOP1_INV 1 |
6 |
#define TDC_NEG_STOP1_INV 1 |
| 7 |
#define TDC_NEG_STOP1 0 |
7 |
#define TDC_NEG_STOP1 0 |
| 8 |
#define TDC_NEG_STOP2_INV 1 |
8 |
#define TDC_NEG_STOP2_INV 1 |
| 9 |
#define TDC_NEG_STOP2 0 |
9 |
#define TDC_NEG_STOP2 0 |
| 10 |
#define TDC_MRANGE1 0 |
10 |
#define TDC_MRANGE1 0 |
| 11 |
#define TDC_MRANGE2 1 |
11 |
#define TDC_MRANGE2 1 |
| 12 |
#define TDC_AUTOCAL_EN 0 |
12 |
#define TDC_AUTOCAL_EN 0 |
| 13 |
#define TDC_AUTOCAL_DIS 1 |
13 |
#define TDC_AUTOCAL_DIS 1 |
| 14 |
#define TDC_CALIBRATE_EN 1 |
14 |
#define TDC_CALIBRATE_EN 1 |
| 15 |
#define TDC_CALIBRATE_DIS 0 |
15 |
#define TDC_CALIBRATE_DIS 0 |
| 16 |
#define TDC_TSELCLK_32KHZ 0 |
16 |
#define TDC_TSELCLK_32KHZ 0 |
| 17 |
#define TDC_TSELCLK_128HS 1 |
17 |
#define TDC_TSELCLK_128HS 1 |
| 18 |
#define TDC_TFAKENUM_2 0 |
18 |
#define TDC_TFAKENUM_2 0 |
| 19 |
#define TDC_TFAKENUM_7 1 |
19 |
#define TDC_TFAKENUM_8 1 |
| 20 |
#define TDC_TCYCLE_SHORT 0 |
20 |
#define TDC_TCYCLE_SHORT 0 |
| 21 |
#define TDC_TCYSLE_LONG 1 |
21 |
#define TDC_TCYSLE_LONG 1 |
| 22 |
#define TDC_TPORTNUM_2 0 |
22 |
#define TDC_TPORTNUM_2 0 |
| 23 |
#define TDC_TPORTNUM_4 1 |
23 |
#define TDC_TPORTNUM_4 1 |
| 24 |
#define TDC_CLKHS_OFF 0 |
24 |
#define TDC_CLKHS_OFF 0 |
| 25 |
#define TDC_CLKHS_ON 1 |
25 |
#define TDC_CLKHS_ON 1 |
| 26 |
#define TDC_CLKHS_640US 2 |
26 |
#define TDC_CLKHS_640US 2 |
| 27 |
#define TDC_CLKHS_1280US 4 |
27 |
#define TDC_CLKHS_1280US 4 |
| 28 |
#define TDC_CLKHSDIV_1 0 |
28 |
#define TDC_CLKHSDIV_1 0 |
| 29 |
#define TDC_CLKHSDIV_2 1 |
29 |
#define TDC_CLKHSDIV_2 1 |
| 30 |
#define TDC_CLKHSDIV_4 2 |
30 |
#define TDC_CLKHSDIV_4 2 |
| 31 |
#define TDC_CLKHSDIV_8 3 |
31 |
#define TDC_CLKHSDIV_8 3 |
| 32 |
#define TDC_CALPERIODS_2 0 |
32 |
#define TDC_CALPERIODS_2 0 |
| 33 |
#define TDC_CALPERIODS_4 1 |
33 |
#define TDC_CALPERIODS_4 1 |
| 34 |
#define TDC_CALPERIODS_8 2 |
34 |
#define TDC_CALPERIODS_8 2 |
| 35 |
#define TDC_CALPERIODS_16 3 |
35 |
#define TDC_CALPERIODS_16 3 |
| 36 |
|
36 |
|
| 37 |
#define TDC_DIV_FIRE_2 1 |
37 |
#define TDC_DIV_FIRE_2 1 |
| 38 |
#define TDC_DIV_FIRE_3 2 |
38 |
#define TDC_DIV_FIRE_3 2 |
| 39 |
#define TDC_DIV_FIRE_4 3 |
39 |
#define TDC_DIV_FIRE_4 3 |
| 40 |
#define TDC_DIV_FIRE_5 4 |
40 |
#define TDC_DIV_FIRE_5 4 |
| 41 |
#define TDC_DIV_FIRE_6 5 |
41 |
#define TDC_DIV_FIRE_6 5 |
| 42 |
#define TDC_DIV_FIRE_7 6 |
42 |
#define TDC_DIV_FIRE_7 6 |
| 43 |
#define TDC_DIV_FIRE_8 7 |
43 |
#define TDC_DIV_FIRE_8 7 |
| 44 |
#define TDC_DIV_FIRE_9 8 |
44 |
#define TDC_DIV_FIRE_9 8 |
| 45 |
#define TDC_DIV_FIRE_10 9 |
45 |
#define TDC_DIV_FIRE_10 9 |
| 46 |
#define TDC_DIV_FIRE_11 10 |
46 |
#define TDC_DIV_FIRE_11 10 |
| 47 |
#define TDC_DIV_FIRE_12 11 |
47 |
#define TDC_DIV_FIRE_12 11 |
| 48 |
#define TDC_DIV_FIRE_13 12 |
48 |
#define TDC_DIV_FIRE_13 12 |
| 49 |
#define TDC_DIV_FIRE_14 13 |
49 |
#define TDC_DIV_FIRE_14 13 |
| 50 |
#define TDC_DIV_FIRE_15 14 |
50 |
#define TDC_DIV_FIRE_15 14 |
| 51 |
#define TDC_DIV_FIRE_16 15 |
51 |
#define TDC_DIV_FIRE_16 15 |
| 52 |
|
52 |
|
| 53 |
#define TDC_FIRENUM_0 0 |
53 |
#define TDC_FIRENUM_0 0 |
| 54 |
#define TDC_FIRENUM_1 1 |
54 |
#define TDC_FIRENUM_1 1 |
| 55 |
#define TDC_FIRENUM_2 2 |
55 |
#define TDC_FIRENUM_2 2 |
| 56 |
#define TDC_FIRENUM_3 3 |
56 |
#define TDC_FIRENUM_3 3 |
| 57 |
#define TDC_FIRENUM_4 4 |
57 |
#define TDC_FIRENUM_4 4 |
| 58 |
#define TDC_FIRENUM_5 5 |
58 |
#define TDC_FIRENUM_5 5 |
| 59 |
#define TDC_FIRENUM_6 6 |
59 |
#define TDC_FIRENUM_6 6 |
| 60 |
#define TDC_FIRENUM_7 7 |
60 |
#define TDC_FIRENUM_7 7 |
| 61 |
#define TDC_FIRENUM_8 8 |
61 |
#define TDC_FIRENUM_8 8 |
| 62 |
#define TDC_FIRENUM_9 9 |
62 |
#define TDC_FIRENUM_9 9 |
| 63 |
#define TDC_FIRENUM_10 10 |
63 |
#define TDC_FIRENUM_10 10 |
| 64 |
#define TDC_FIRENUM_11 11 |
64 |
#define TDC_FIRENUM_11 11 |
| 65 |
#define TDC_FIRENUM_12 12 |
65 |
#define TDC_FIRENUM_12 12 |
| 66 |
#define TDC_FIRENUM_13 13 |
66 |
#define TDC_FIRENUM_13 13 |
| 67 |
#define TDC_FIRENUM_14 14 |
67 |
#define TDC_FIRENUM_14 14 |
| 68 |
#define TDC_FIRENUM_15 15 |
68 |
#define TDC_FIRENUM_15 15 |
| 69 |
|
69 |
|
| 70 |
//register 1 |
70 |
//register 1 |
| 71 |
#define TDC_HITIN1_0 0 |
71 |
#define TDC_HITIN1_0 0 |
| 72 |
#define TDC_HITIN1_1 1 |
72 |
#define TDC_HITIN1_1 1 |
| 73 |
#define TDC_HITIN1_2 2 |
73 |
#define TDC_HITIN1_2 2 |
| 74 |
#define TDC_HITIN1_3 3 |
74 |
#define TDC_HITIN1_3 3 |
| 75 |
#define TDC_HITIN1_4 4 |
75 |
#define TDC_HITIN1_4 4 |
| 76 |
|
76 |
|
| 77 |
#define TDC_HITIN2_0 0 |
77 |
#define TDC_HITIN2_0 0 |
| 78 |
#define TDC_HITIN2_1 1 |
78 |
#define TDC_HITIN2_1 1 |
| 79 |
#define TDC_HITIN2_2 2 |
79 |
#define TDC_HITIN2_2 2 |
| 80 |
#define TDC_HITIN2_3 3 |
80 |
#define TDC_HITIN2_3 3 |
| 81 |
#define TDC_HITIN2_4 4 |
81 |
#define TDC_HITIN2_4 4 |
| 82 |
|
82 |
|
| 83 |
#define TDC_FAST_INIT_EN 1 |
83 |
#define TDC_FAST_INIT_EN 1 |
| 84 |
#define TDC_FAST_INIT_DIS 0 |
84 |
#define TDC_FAST_INIT_DIS 0 |
| 85 |
|
85 |
|
| 86 |
#define TDC_MRANGE1_HIT1_START 0 |
86 |
#define TDC_MRANGE1_HIT1_START 0 |
| 87 |
#define TDC_MRANGE1_HIT1_1CH1 1 |
87 |
#define TDC_MRANGE1_HIT1_1CH1 1 |
| 88 |
#define TDC_MRANGE1_HIT1_2CH1 2 |
88 |
#define TDC_MRANGE1_HIT1_2CH1 2 |
| 89 |
#define TDC_MRANGE1_HIT1_3CH1 3 |
89 |
#define TDC_MRANGE1_HIT1_3CH1 3 |
| 90 |
#define TDC_MRANGE1_HIT1_4CH1 4 |
90 |
#define TDC_MRANGE1_HIT1_4CH1 4 |
| 91 |
#define TDC_MRANGE1_HIT1_NOAC 5 |
91 |
#define TDC_MRANGE1_HIT1_NOAC 5 |
| 92 |
#define TDC_MRANGE1_HIT1_CAL1CH1 6 |
92 |
#define TDC_MRANGE1_HIT1_CAL1CH1 6 |
| 93 |
#define TDC_MRANGE1_HIT1_CAL2CH1 7 |
93 |
#define TDC_MRANGE1_HIT1_CAL2CH1 7 |
| 94 |
#define TDC_MRANGE1_HIT1_1CH2 9 |
94 |
#define TDC_MRANGE1_HIT1_1CH2 9 |
| 95 |
#define TDC_MRANGE1_HIT1_2CH2 0xA |
95 |
#define TDC_MRANGE1_HIT1_2CH2 0xA |
| 96 |
#define TDC_MRANGE1_HIT1_3CH2 0xB |
96 |
#define TDC_MRANGE1_HIT1_3CH2 0xB |
| 97 |
#define TDC_MRANGE1_HIT1_4CH2 0xC |
97 |
#define TDC_MRANGE1_HIT1_4CH2 0xC |
| 98 |
|
98 |
|
| 99 |
#define TDC_MRANGE2_HIT1_START 1 |
99 |
#define TDC_MRANGE2_HIT1_START 1 |
| 100 |
|
100 |
|
| 101 |
#define TDC_MRANGE1_HIT2_START 0 |
101 |
#define TDC_MRANGE1_HIT2_START 0 |
| 102 |
#define TDC_MRANGE1_HIT2_1CH1 1 |
102 |
#define TDC_MRANGE1_HIT2_1CH1 1 |
| 103 |
#define TDC_MRANGE1_HIT2_2CH1 2 |
103 |
#define TDC_MRANGE1_HIT2_2CH1 2 |
| 104 |
#define TDC_MRANGE1_HIT2_3CH1 3 |
104 |
#define TDC_MRANGE1_HIT2_3CH1 3 |
| 105 |
#define TDC_MRANGE1_HIT2_4CH1 4 |
105 |
#define TDC_MRANGE1_HIT2_4CH1 4 |
| 106 |
#define TDC_MRANGE1_HIT2_NOAC 5 |
106 |
#define TDC_MRANGE1_HIT2_NOAC 5 |
| 107 |
#define TDC_MRANGE1_HIT2_CAL1CH1 6 |
107 |
#define TDC_MRANGE1_HIT2_CAL1CH1 6 |
| 108 |
#define TDC_MRANGE1_HIT2_CAL2CH1 7 |
108 |
#define TDC_MRANGE1_HIT2_CAL2CH1 7 |
| 109 |
#define TDC_MRANGE1_HIT2_1CH2 9 |
109 |
#define TDC_MRANGE1_HIT2_1CH2 9 |
| 110 |
#define TDC_MRANGE1_HIT2_2CH2 0xA |
110 |
#define TDC_MRANGE1_HIT2_2CH2 0xA |
| 111 |
#define TDC_MRANGE1_HIT2_3CH2 0xB |
111 |
#define TDC_MRANGE1_HIT2_3CH2 0xB |
| 112 |
#define TDC_MRANGE1_HIT2_4CH2 0xC |
112 |
#define TDC_MRANGE1_HIT2_4CH2 0xC |
| 113 |
|
113 |
|
| 114 |
#define TDC_MRANGE2_HIT2_1CH1 2 |
114 |
#define TDC_MRANGE2_HIT2_1CH1 2 |
| 115 |
#define TDC_MRANGE2_HIT2_2CH1 3 |
115 |
#define TDC_MRANGE2_HIT2_2CH1 3 |
| 116 |
#define TDC_MRANGE2_HIT2_3CH1 4 |
116 |
#define TDC_MRANGE2_HIT2_3CH1 4 |
| 117 |
|
117 |
|
| 118 |
//register 2 |
118 |
//register 2 |
| 119 |
#define TDC_INT_TIMEOUT 4 |
119 |
#define TDC_INT_TIMEOUT 4 |
| 120 |
#define TDC_INT_ENDHIT 2 |
120 |
#define TDC_INT_ENDHIT 2 |
| 121 |
#define TDC_INT_ALU 1 |
121 |
#define TDC_INT_ALU 1 |
| 122 |
#define TDC_CH1EDGE_RIS 0 |
122 |
#define TDC_CH1EDGE_RIS 0 |
| 123 |
#define TDC_CH1EDGE_FAL 1 |
123 |
#define TDC_CH1EDGE_FAL 1 |
| 124 |
#define TDC_CH2EDGE_RIS 0 |
124 |
#define TDC_CH2EDGE_RIS 0 |
| 125 |
#define TDC_CH2EDGE_FAL 1 |
125 |
#define TDC_CH2EDGE_FAL 1 |
| 126 |
|
126 |
|
| 127 |
//register 3 |
127 |
//register 3 |
| 128 |
#define TDC_TIM0MR2_256CLKHS 0 |
128 |
#define TDC_TIM0MR2_256CLKHS 0 |
| 129 |
#define TDC_TIM0MR2_1024CLKHS 1 |
129 |
#define TDC_TIM0MR2_1024CLKHS 1 |
| 130 |
#define TDC_TIM0MR2_4096CLKHS 2 |
130 |
#define TDC_TIM0MR2_4096CLKHS 2 |
| 131 |
#define TDC_TIM0MR2_16384CLKHS 3 |
131 |
#define TDC_TIM0MR2_16384CLKHS 3 |
| 132 |
|
132 |
|
| 133 |
#define TDC_ERRVAL_EN 1 |
133 |
#define TDC_ERRVAL_EN 1 |
| 134 |
#define TDC_ERRVAL_DIS 0 |
134 |
#define TDC_ERRVAL_DIS 0 |
| 135 |
|
135 |
|
| 136 |
//register 5 |
136 |
//register 5 |
| 137 |
#define TDC_REPEAT_FIRE_0 0 |
137 |
#define TDC_REPEAT_FIRE_0 0 |
| 138 |
#define TDC_REPEAT_FIRE_1 1 |
138 |
#define TDC_REPEAT_FIRE_1 1 |
| 139 |
#define TDC_REPEAT_FIRE_2 2 |
139 |
#define TDC_REPEAT_FIRE_2 2 |
| 140 |
#define TDC_REPEAT_FIRE_3 3 |
140 |
#define TDC_REPEAT_FIRE_3 3 |
| 141 |
#define TDC_REPEAT_FIRE_4 4 |
141 |
#define TDC_REPEAT_FIRE_4 4 |
| 142 |
#define TDC_REPEAT_FIRE_5 5 |
142 |
#define TDC_REPEAT_FIRE_5 5 |
| 143 |
#define TDC_REPEAT_FIRE_6 6 |
143 |
#define TDC_REPEAT_FIRE_6 6 |
| 144 |
#define TDC_REPEAT_FIRE_7 7 |
144 |
#define TDC_REPEAT_FIRE_7 7 |
| 145 |
|
145 |
|
| 146 |
#define TDC_PHASENOISE_EN 0 |
146 |
#define TDC_PHASENOISE_EN 0 |
| 147 |
#define TDC_PHASENOISE_DIS 1 |
147 |
#define TDC_PHASENOISE_DIS 1 |
| 148 |
|
148 |
|
| 149 |
#define TDC_STARTNOISE_EN 1 |
149 |
#define TDC_STARTNOISE_EN 1 |
| 150 |
#define TDC_STARTNOISE_DIS 0 |
150 |
#define TDC_STARTNOISE_DIS 0 |
| 151 |
|
151 |
|
| 152 |
#include "GP2.c" |
152 |
#include "GP2.c" |