Rev 1965 Rev 1966
1 #include "main.h" 1 #include "main.h"
2   2  
3 #define VERSION 0.2 3 #define VERSION 0.2
4   4  
5 #define START PIN_D4 5 #define START PIN_D4
6 #define STOP1 PIN_D5 6 #define STOP1 PIN_D5
7 #define STOP2 PIN_D6 7 #define STOP2 PIN_D6
8   8  
9 #include "GP2.h" 9 #include "GP2.h"
10   10  
11 #define ONE_WIRE_PIN PIN_E2 11 #define ONE_WIRE_PIN PIN_E2
12 #include "ds1820.c" 12 #include "ds1820.c"
13   13  
14 void main() 14 void main()
15 { 15 {
16 setup_adc_ports(NO_ANALOGS|VSS_VDD); 16 setup_adc_ports(NO_ANALOGS|VSS_VDD);
17 setup_adc(ADC_CLOCK_DIV_2); 17 setup_adc(ADC_CLOCK_DIV_2);
18 setup_psp(PSP_DISABLED); 18 setup_psp(PSP_DISABLED);
19 setup_spi(SPI_SS_DISABLED); 19 setup_spi(SPI_SS_DISABLED);
20 setup_wdt(WDT_OFF); 20 setup_wdt(WDT_OFF);
21 setup_timer_0(RTCC_INTERNAL); 21 setup_timer_0(RTCC_INTERNAL);
22 setup_timer_1(T1_DISABLED); 22 setup_timer_1(T1_DISABLED);
23 setup_timer_2(T2_DISABLED,0,1); 23 setup_timer_2(T2_DISABLED,0,1);
24 setup_ccp1(CCP_OFF); 24 setup_ccp1(CCP_OFF);
25 setup_comparator(NC_NC_NC_NC); 25 setup_comparator(NC_NC_NC_NC);
26 setup_vref(FALSE); 26 setup_vref(FALSE);
27   27  
28 TDC_reset(); 28 TDC_reset();
29   29  
30 output_low(START); 30 output_low(START);
31 output_low(STOP1); 31 output_low(STOP1);
32 output_low(STOP2); 32 output_low(STOP2);
33   33  
34 delay_ms(50); 34 delay_ms(50);
35   35  
36 /* 36 /*
37 1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR 37 1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR
38 1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR 38 1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR
39 0 1 1 1 0 0 0 0 Init 39 0 1 1 1 0 0 0 0 Init
40 0 1 0 1 0 0 0 0 Power On Reset 40 0 1 0 1 0 0 0 0 Power On Reset
41 0 0 0 0 0 0 0 1 Start_Cycle 41 0 0 0 0 0 0 0 1 Start_Cycle
42 0 0 0 0 0 0 1 0 Start_Temp 42 0 0 0 0 0 0 1 0 Start_Temp
43 0 0 0 0 0 0 1 1 Start_Cal_Resonator 43 0 0 0 0 0 0 1 1 Start_Cal_Resonator
44 0 0 0 0 0 1 0 0 Start_Cal_TDC 44 0 0 0 0 0 1 0 0 Start_Cal_TDC
45 */ 45 */
46   46  
47 int32 ble; -  
48 int16 ret16; 47 int16 ret16;
49 int8 ret8; 48 int8 ret8;
50   49  
51   50  
52 while(TRUE) 51 while(TRUE)
53 { 52 {
54 delay_ms(100); 53 delay_ms(100);
55   -  
56   -  
57 TDC_reset(); 54 TDC_reset();
58 delay_ms(100); 55 delay_ms(100);
59 56
60 //----------------------------------------------- Nastaveni registru 57 //----------------------------------------------- Nastaveni registru
61 /* output_low(TDC_ENABLE); -  
62 ble=0; -  
63 ble=(8<<28)|(0<<24); // write addres -  
64 ble|=(0<<20)|(0<<16)|(0<<14)|(3<<12)|(1<<10)|(0<<9)|(0<<8)|(0<<7)|(1<<6)|(1<<5)|(0<<4)|(1<<3)|(0<<2)|(0<<1)|0; -  
65 spi_xfer(TDC_stream,ble,32); -  
66 output_high(TDC_ENABLE); -  
67 -  
68 output_low(TDC_ENABLE); -  
69 ble=0; -  
70 ble=(8<<28)|(1<<24); -  
71 ble|=(2<<20)|(1<<16)|(0<<15)|(1<<14)|(0<<11)|(4<<8)|0; -  
72 spi_xfer(TDC_stream,ble,32); -  
73 output_high(TDC_ENABLE); -  
74 -  
75 output_low(TDC_ENABLE); -  
76 ble=0; -  
77 ble=(8<<28)|(2<<24); -  
78 ble|=(1<<21)|(1<<20)|(1<<19)|0; -  
79 spi_xfer(TDC_stream,ble,32); -  
80 output_high(TDC_ENABLE); -  
81 -  
82 output_low(TDC_ENABLE); -  
83 ble=0; -  
84 ble=(8<<28)|(3<<24); -  
85 ble|=(0<<22)|(1<<21)|(1<<20)|(1<<19)|0; -  
86 spi_xfer(TDC_stream,ble,32); -  
87 output_high(TDC_ENABLE); -  
88 -  
89 output_low(TDC_ENABLE); -  
90 ble=0; -  
91 ble=(8<<28)|(4<<24); -  
92 ble|=(4<<19)|0; -  
93 spi_xfer(TDC_stream,ble,32); -  
94 output_high(TDC_ENABLE); -  
95 -  
96 output_low(TDC_ENABLE); -  
97 ble=0; -  
98 ble=(8<<28)|(5<<24); -  
99 ble|=(0<<21)|(0<<20)|(0<<19)|(0<<16)|0; -  
100 spi_xfer(TDC_stream,ble,32); -  
101 output_high(TDC_ENABLE); -  
102 */ -  
103   -  
104 hit1=TDC_MRANGE2_HIT1_START; 58 hit1=TDC_MRANGE2_HIT1_START;
105 // hit2=TDC_MRANGE2_HIT2_2CH1; -  
106 hitin1=TDC_HITIN1_4; 59 hitin1=TDC_HITIN1_4;
107 hitin2=TDC_HITIN2_0; 60 hitin2=TDC_HITIN2_0;
108 en_int= TDC_INT_ALU | TDC_INT_ENDHIT | TDC_INT_TIMEOUT; 61 en_int= TDC_INT_ALU | TDC_INT_ENDHIT | TDC_INT_TIMEOUT;
109 en_err_val=TDC_ERRVAL_EN; 62 en_err_val=TDC_ERRVAL_EN;
110 delval1=0x0; 63 delval1=0x0;
111 delval2=0x0; 64 delval2=0x0;
112 delval3=0x0; 65 delval3=0x0;
113 66
114 TDC_update_registers(); 67 TDC_update_registers();
115   68  
116 //----------------------------------------------- Vypis registru 69 //----------------------------------------------- Vypis registru
117 70
118 printf("- %LX %LX %LX %LX ", TDC_get_measurement(1), TDC_get_measurement(2), TDC_get_measurement(3), TDC_get_measurement(4)); 71 printf("- %LX %LX %LX %LX ", TDC_get_measurement(0), TDC_get_measurement(1), TDC_get_measurement(2), TDC_get_measurement(3));
119 72
120 output_low(TDC_ENABLE); 73 output_low(TDC_ENABLE);
121 ret8=0; 74 ret8=0;
122 ret8=(0b1011<<4)|4; 75 ret8=(0b1011<<4)|4;
123 spi_xfer(TDC_stream,ret8,8); 76 spi_xfer(TDC_stream,ret8,8);
124 ret16=spi_xfer(TDC_stream,0,16); 77 ret16=spi_xfer(TDC_stream,0,16);
125 output_high(TDC_ENABLE); 78 output_high(TDC_ENABLE);
126 printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&ret16); 79 printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&ret16);
127 80
128 printf("%X\r\n",TDC_get_reg1()); 81 printf("%X\r\n",TDC_get_reg1());
129 82
130 //----------------------------------------------- Mereni 83 //----------------------------------------------- Mereni
131 84
132 TDC_init(); 85 TDC_init();
133 86
134 delay_ms(50); 87 delay_ms(50);
135 88
136 TDC_start_cycle(); 89 TDC_start_cycle();
137 90
138 delay_ms(200); 91 delay_ms(200);
139 92
140 output_high(STOP2); // Merime jenom jednim kanalem (druhy zrejme musi byt v H) 93 output_high(STOP2); // Merime jenom jednim kanalem (druhy zrejme musi byt v H)
141 94
142 output_high(START); 95 output_high(START);
143 output_low(START); 96 output_low(START);
144 delay_us(1); 97 delay_us(15);
145 98
146 output_high(STOP1); 99 output_high(STOP1);
147 output_low(STOP1); 100 output_low(STOP1);
148 delay_us(1); 101 delay_us(1);
149 102
150 103
151 output_high(STOP1); 104 output_high(STOP1);
152 output_low(STOP1); 105 output_low(STOP1);
153 delay_us(1); 106 delay_us(10);
154 107
155 output_high(STOP1); 108 output_high(STOP1);
156 output_low(STOP1); 109 output_low(STOP1);
157 delay_us(1); 110 delay_us(1);
158 111
159 112
160 113
161 //----------------------------------------------- Pocitani 114 //----------------------------------------------- Pocitani
162 int32 nn; -  
163 for(nn=1;nn<=3;nn++) -  
164 { -  
165 delay_ms(500); -  
166   115  
167 printf("* %LX %LX %LX %LX ", TDC_get_measurement(1), TDC_get_measurement(2), TDC_get_measurement(3), TDC_get_measurement(4)); 116 printf(" %3.7f %3.7f %3.7f ", TDC_mrange2_get_time(1), TDC_mrange2_get_time(2), TDC_mrange2_get_time(3));
168 117
169 output_low(TDC_ENABLE); //status register 118 output_low(TDC_ENABLE); //status register
170 ret8=0; 119 ret8=0;
171 ret8=(0b1011<<4)|4; 120 ret8=(0b1011<<4)|4;
172 spi_xfer(TDC_stream,ret8,8); 121 spi_xfer(TDC_stream,ret8,8);
173 ret16=spi_xfer(TDC_stream,0,16); 122 ret16=spi_xfer(TDC_stream,0,16);
174 output_high(TDC_ENABLE); 123 output_high(TDC_ENABLE);
175 printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&ret16); 124 printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&TDC_get_status());
176 125
177 printf("%X\r\n",TDC_get_reg1()); 126 printf("%X\r\n",TDC_get_reg1());
178 127
179 switch (nn) -  
180 { -  
181 case 1: -  
182 hit2=TDC_MRANGE2_HIT2_1CH1; -  
183 break; -  
184   -  
185 case 2: -  
186 hit2=TDC_MRANGE2_HIT2_2CH1; -  
187 break; -  
188   -  
189 case 3: -  
190 hit2=TDC_MRANGE2_HIT2_3CH1; -  
191 break; -  
192 } -  
193 TDC_update_reg1(); -  
194 } -  
195 } 128 }
196 } 129 }