Rev 1966 Rev 1967
1 #include "main.h" 1 #include "main.h"
2   2  
3 #define VERSION 0.2 3 #define VERSION 0.2
4   4  
5 #define START PIN_D4 5 #define START PIN_D4
6 #define STOP1 PIN_D5 6 #define STOP1 PIN_D5
7 #define STOP2 PIN_D6 7 #define STOP2 PIN_D6
8   8  
9 #include "GP2.h" 9 #include "GP2.h"
10   10  
11 #define ONE_WIRE_PIN PIN_E2 11 #define ONE_WIRE_PIN PIN_E2
12 #include "ds1820.c" 12 #include "ds1820.c"
13   13  
14 void main() 14 void main()
15 { 15 {
16 setup_adc_ports(NO_ANALOGS|VSS_VDD); 16 setup_adc_ports(NO_ANALOGS|VSS_VDD);
17 setup_adc(ADC_CLOCK_DIV_2); 17 setup_adc(ADC_CLOCK_DIV_2);
18 setup_psp(PSP_DISABLED); 18 setup_psp(PSP_DISABLED);
19 setup_spi(SPI_SS_DISABLED); 19 setup_spi(SPI_SS_DISABLED);
20 setup_wdt(WDT_OFF); 20 setup_wdt(WDT_OFF);
21 setup_timer_0(RTCC_INTERNAL); 21 setup_timer_0(RTCC_INTERNAL);
22 setup_timer_1(T1_DISABLED); 22 setup_timer_1(T1_DISABLED);
23 setup_timer_2(T2_DISABLED,0,1); 23 setup_timer_2(T2_DISABLED,0,1);
24 setup_ccp1(CCP_OFF); 24 setup_ccp1(CCP_OFF);
25 setup_comparator(NC_NC_NC_NC); 25 setup_comparator(NC_NC_NC_NC);
26 setup_vref(FALSE); 26 setup_vref(FALSE);
27   27  
28 TDC_reset(); 28 TDC_reset();
29   29  
30 output_low(START); 30 output_low(START);
31 output_low(STOP1); 31 output_low(STOP1);
32 output_low(STOP2); 32 output_low(STOP2);
33   33  
34 delay_ms(50); 34 delay_ms(50);
35   35  
36 /* 36 /*
37 1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR 37 1 0 0 0 0 ADR2 ADR1 ADR0 Write into address ADR
38 1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR 38 1 0 1 1 0 ADR2 ADR1 ADR0 Read from address ADR
39 0 1 1 1 0 0 0 0 Init 39 0 1 1 1 0 0 0 0 Init
40 0 1 0 1 0 0 0 0 Power On Reset 40 0 1 0 1 0 0 0 0 Power On Reset
41 0 0 0 0 0 0 0 1 Start_Cycle 41 0 0 0 0 0 0 0 1 Start_Cycle
42 0 0 0 0 0 0 1 0 Start_Temp 42 0 0 0 0 0 0 1 0 Start_Temp
43 0 0 0 0 0 0 1 1 Start_Cal_Resonator 43 0 0 0 0 0 0 1 1 Start_Cal_Resonator
44 0 0 0 0 0 1 0 0 Start_Cal_TDC 44 0 0 0 0 0 1 0 0 Start_Cal_TDC
45 */ 45 */
46   46  
47 int16 ret16; 47 int16 ret16;
48 int8 ret8; 48 int8 ret8;
49   49  
50   -  
51 while(TRUE) -  
52 { -  
53 delay_ms(100); -  
54 TDC_reset(); 50 TDC_reset();
55 delay_ms(100); 51 delay_ms(100);
56 52
57 //----------------------------------------------- Nastaveni registru 53 //----------------------------------------------- Nastaveni registru
58 hit1=TDC_MRANGE2_HIT1_START; 54 hit1=TDC_MRANGE2_HIT1_START;
59 hitin1=TDC_HITIN1_4; 55 hitin1=TDC_HITIN1_4;
60 hitin2=TDC_HITIN2_0; 56 hitin2=TDC_HITIN2_0;
61 en_int= TDC_INT_ALU | TDC_INT_ENDHIT | TDC_INT_TIMEOUT; 57 en_int= TDC_INT_ALU | TDC_INT_ENDHIT | TDC_INT_TIMEOUT;
62 en_err_val=TDC_ERRVAL_EN; 58 en_err_val=TDC_ERRVAL_EN;
-   59 clkhsdiv=TDC_CLKHSDIV_4;
63 delval1=0x0; 60 delval1=0x0;
64 delval2=0x0; 61 delval2=0x0;
65 delval3=0x0; 62 delval3=0x0;
66 63
67 TDC_update_registers(); 64 TDC_update_registers();
68   65  
69 //----------------------------------------------- Vypis registru -  
70 66 while(TRUE)
71 printf("- %LX %LX %LX %LX ", TDC_get_measurement(0), TDC_get_measurement(1), TDC_get_measurement(2), TDC_get_measurement(3)); -  
72 67 {
73 output_low(TDC_ENABLE); -  
74 ret8=0; 68 delay_ms(100);
75 ret8=(0b1011<<4)|4; -  
76 spi_xfer(TDC_stream,ret8,8); -  
77 ret16=spi_xfer(TDC_stream,0,16); -  
78 output_high(TDC_ENABLE); -  
79 printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&ret16); -  
80 -  
81 printf("%X\r\n",TDC_get_reg1()); -  
82 69
83 //----------------------------------------------- Mereni 70 //----------------------------------------------- Mereni
84 71
85 TDC_init(); 72 TDC_init();
86 73
87 delay_ms(50); 74 delay_ms(50);
88 75
89 TDC_start_cycle(); 76 TDC_start_cycle();
90 77
91 delay_ms(200); 78 delay_ms(200);
92 79
93 output_high(STOP2); // Merime jenom jednim kanalem (druhy zrejme musi byt v H) 80 output_high(STOP2); // Merime jenom jednim kanalem (druhy zrejme musi byt v H)
94 81
95 output_high(START); 82 output_high(START);
96 output_low(START); 83 output_low(START);
97 delay_us(15); 84 delay_us(150);
98 85
99 output_high(STOP1); 86 output_high(STOP1);
100 output_low(STOP1); 87 output_low(STOP1);
101 delay_us(1); 88 delay_us(1);
102 89
103 -  
104 output_high(STOP1); 90 output_high(STOP1);
105 output_low(STOP1); 91 output_low(STOP1);
106 delay_us(10); 92 delay_us(10);
107 93
108 output_high(STOP1); 94 output_high(STOP1);
109 output_low(STOP1); 95 output_low(STOP1);
110 delay_us(1); 96 delay_us(1);
111 -  
112 -  
113 97
114 //----------------------------------------------- Pocitani 98 //----------------------------------------------- Pocitani
115   99  
116 printf(" %3.7f %3.7f %3.7f ", TDC_mrange2_get_time(1), TDC_mrange2_get_time(2), TDC_mrange2_get_time(3)); 100 printf("Time: %3.7f %3.7f %3.7f ", TDC_mrange2_get_time(1), TDC_mrange2_get_time(2), TDC_mrange2_get_time(3));
117 101
118 output_low(TDC_ENABLE); //status register 102 output_low(TDC_ENABLE); //status register
119 ret8=0; 103 ret8=0;
120 ret8=(0b1011<<4)|4; 104 ret8=(0b1011<<4)|4;
121 spi_xfer(TDC_stream,ret8,8); 105 spi_xfer(TDC_stream,ret8,8);
122 ret16=spi_xfer(TDC_stream,0,16); 106 ret16=spi_xfer(TDC_stream,0,16);
123 output_high(TDC_ENABLE); 107 output_high(TDC_ENABLE);
124 printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&TDC_get_status()); 108 printf("[%Lu %Lu %Lu %Lu %Lu %Lu %Lu]\r\n", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&TDC_get_status());
-   109  
-   110 TDC_start_temp();
-   111 output_low(TDC_ENABLE); //status register
125 112 ret8=0;
-   113 ret8=(0b1011<<4)|4;
126 printf("%X\r\n",TDC_get_reg1()); 114 spi_xfer(TDC_stream,ret8,8);
-   115 ret16=spi_xfer(TDC_stream,0,16);
-   116 output_high(TDC_ENABLE);
-   117 printf("Temp: [%Lu %Lu %Lu %Lu %Lu %Lu %Lu] ", (1&(ret16)>>12), (1&(ret16)>>11), (1&(ret16)>>10), 1&(ret16)>>9, 7&(ret16)>>6, 7&(ret16)>>3, 7&TDC_get_status());
-   118 printf(" %LX %LX %LX %LX \r\n", TDC_get_measurement(1), TDC_get_measurement(2), TDC_get_measurement(3), TDC_get_measurement(4));
127 119
128 } 120 }
129 } 121 }