Rev 3176 Rev 3177
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8 -- Tool versions: ISE 13.3 8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A. 9 -- Description: Time and frequency synchronisation for RDMS01A.
10 -- 10 --
11 -- Dependencies: CLKGEN01B, GPS01A 11 -- Dependencies: CLKGEN01B, GPS01A
12 -- 12 --
13 -- Version: $Id: gtime.vhd 3176 2013-07-17 14:27:37Z kakl $ 13 -- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $
14 -- 14 --
15 ---------------------------------------------------------------------------------- 15 ----------------------------------------------------------------------------------
16   16  
17 library IEEE; 17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL; 18 use IEEE.STD_LOGIC_1164.ALL;
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164   164  
165   165  
166 -- LED Display 166 -- LED Display
167 -- ----------- 167 -- -----------
168   168  
-   169 signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
169 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input 170 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
170 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency 171 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
171 signal HalfFreq: std_logic_vector(31 downto 0); 172 signal HalfFreq: std_logic_vector(31 downto 0);
172 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider 173 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
173 signal Enable: std_logic; 174 signal Enable: std_logic;
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175 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output 176 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
176 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output 177 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
177   178  
178 179
179 signal LO_CLOCK: std_logic; 180 signal LO_CLOCK: std_logic;
-   181 signal EXT_CLOCK: std_logic;
180   182  
181 signal Decko: std_logic; 183 signal Decko: std_logic;
182 signal State: unsigned(2 downto 0) := (others => '0'); 184 signal State: unsigned(2 downto 0) := (others => '0');
183 185
184 begin 186 begin
185   187  
-   188 process (EXT_CLOCK)
-   189 begin
-   190
-   191 if rising_edge(EXT_CLOCK) then
-   192 LO_CLOCK <= not LO_CLOCK;
-   193 end if;
-   194 end process;
-   195  
-   196  
186 -- Counter 197 -- Counter
187 process (LO_CLOCK) 198 process (LO_CLOCK)
188 begin 199 begin
189 200
190 if rising_edge(LO_CLOCK) then 201 if rising_edge(LO_CLOCK) then
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232 end if; 243 end if;
233 end process; 244 end process;
234   245  
235 -- Coding to BCD for LED Display 246 -- Coding to BCD for LED Display
236   247  
237 -- HalfFreq(14 downto 0) <= Freq(15 downto 1); -  
238 -- HalfFreq(15) <= '0'; 248 process (Decko)
239 -- HalfFreq(30 downto 16) <= Freq(31 downto 17); 249 begin
240 -- HalfFreq(31) <= '0'; 250 if falling_edge(Decko) then
241 -- Number(15 downto 0) <= to_bcd(HalfFreq(15 downto 0))(15 downto 0); 251 NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0);
242 -- Number(35 downto 16) <= to_bcd(HalfFreq(31 downto 16))(19 downto 0); 252 NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0);
-   253 end if;
243 Number(15 downto 0) <= Freq(15 downto 0); 254 end process;
-   255  
244 Number(31 downto 16) <= Freq(31 downto 16); 256 Number(35 downto 0) <= NumberPom(35 downto 0);
245   257
246 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar 258 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
247 LED(6 downto 4) <= (others => '0'); 259 LED(6 downto 4) <= (others => '0');
248 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar 260 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
249   261  
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320 Number(27 downto 24) when Digits="01000000" else 332 Number(27 downto 24) when Digits="01000000" else
321 Number(31 downto 28) when Digits="10000000" else 333 Number(31 downto 28) when Digits="10000000" else
322 "0000"; 334 "0000";
323   335  
324   336  
325 -- Display on 7seg. -  
326 -- Number(3 downto 0) <= (others=>'0'); -  
327 -- Number(15 downto 4) <= (others=>'1'); --to_bcd(std_logic_vector(T2)); -  
328 -- Number(19 downto 16) <= (others=>'0'); -  
329 -- Number(31 downto 20) <= (others=>'1'); --to_bcd(std_logic_vector(T1)); -  
330 -  
331   337  
332 -- Diferencial In/Outs 338 -- Diferencial In/Outs
333 -- ======================== 339 -- ========================
334 DIFbuffer1 : IBUFGDS 340 DIFbuffer1 : IBUFGDS
335 generic map ( 341 generic map (
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338 -- "0"-"16" 344 -- "0"-"16"
339 IOSTANDARD => "DEFAULT") 345 IOSTANDARD => "DEFAULT")
340 port map ( 346 port map (
341 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) 347 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
342 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) 348 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
343 O => LO_CLOCK -- Buffer output 349 O => EXT_CLOCK -- Buffer output
344 ); 350 );
345   351  
346 OBUFDS_inst : OBUFDS 352 OBUFDS_inst : OBUFDS
347 generic map ( 353 generic map (
348 IOSTANDARD => "DEFAULT") 354 IOSTANDARD => "DEFAULT")
349 port map ( 355 port map (
350 O => SD2AP, -- Diff_p output (connect directly to top-level port) 356 O => SD2AP, -- Diff_p output (connect directly to top-level port)
351 OB => SD2AN, -- Diff_n output (connect directly to top-level port) 357 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
352 I => LO_CLOCK -- Buffer input 358 I => EXT_CLOCK -- Buffer input
353 ); 359 );
354 360
355 -- Output Signal on SATA Connector 361 -- Output Signal on SATA Connector
356 -- SD1AP <= 'Z'; 362 -- SD1AP <= 'Z';
357 -- SD1AN <= 'Z'; 363 -- SD1AN <= 'Z';