| Line 14... |
Line 14... |
| 14 |
#FUSES NOLVP //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O |
14 |
#FUSES NOLVP //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O |
| 15 |
#FUSES NOWRT //Program memory not write protected |
15 |
#FUSES NOWRT //Program memory not write protected |
| 16 |
#FUSES NOWRTD //Data EEPROM not write protected |
16 |
#FUSES NOWRTD //Data EEPROM not write protected |
| 17 |
#FUSES IESO //Internal External Switch Over mode enabled |
17 |
#FUSES IESO //Internal External Switch Over mode enabled |
| 18 |
#FUSES FCMEN //Fail-safe clock monitor enabled |
18 |
#FUSES FCMEN //Fail-safe clock monitor enabled |
| 19 |
#FUSES PBADEN //PORTB pins are configured as analog input channels on RESET |
19 |
#FUSES NOPBADEN //PORTB pins are configured as analog input channels on RESET |
| 20 |
#FUSES NOWRTC //configuration not registers write protected |
20 |
#FUSES NOWRTC //configuration not registers write protected |
| 21 |
#FUSES NOWRTB //Boot block not write protected |
21 |
#FUSES NOWRTB //Boot block not write protected |
| 22 |
#FUSES NOEBTR //Memory not protected from table reads |
22 |
#FUSES NOEBTR //Memory not protected from table reads |
| 23 |
#FUSES NOEBTRB //Boot block not protected from table reads |
23 |
#FUSES NOEBTRB //Boot block not protected from table reads |
| 24 |
#FUSES NOCPB //No Boot Block code protection |
24 |
#FUSES NOCPB //No Boot Block code protection |
| 25 |
#FUSES MCLR //Master Clear pin enabled |
25 |
#FUSES NOMCLR //Master Clear pin disabled |
| 26 |
#FUSES LPT1OSC //Timer1 configured for low-power operation |
26 |
#FUSES LPT1OSC //Timer1 configured for low-power operation |
| 27 |
#FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode) |
27 |
#FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode) |
| 28 |
#FUSES PLL5 //Divide By 5(48MHz oscillator input) |
28 |
#FUSES PLL5 //Divide By 5(48MHz oscillator input) |
| 29 |
#FUSES CPUDIV1 //System Clock by 4 |
29 |
#FUSES CPUDIV1 //System Clock by 4 |
| 30 |
#FUSES USBDIV //USB clock source comes from PLL divide by 2 |
30 |
#FUSES USBDIV //USB clock source comes from PLL divide by 2 |
| 31 |
#FUSES VREGEN //USB voltage regulator enabled |
31 |
#FUSES VREGEN //USB voltage regulator enabled |
| 32 |
#FUSES ICPRT //ICPRT enabled |
32 |
#FUSES ICPRT //ICPRT enabled |
| 33 |
|
33 |
|
| 34 |
#use delay(clock=48000000) |
34 |
#use delay(clock=48000000) |
| 35 |
#use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8) |
35 |
#use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8) |
| 36 |
#use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8) |
- |
|
| 37 |
|
36 |
|