Rev 1757 Rev 1758
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1   1  
2 //struct { 2 //struct {
3 unsigned int8 firenum; 3 unsigned int8 firenum=TDC_FIRENUM_0;
4 unsigned int8 div_fire; 4 unsigned int8 div_fire=TDC_DIV_FIRE_2;
5 unsigned int8 calresnum :2; 5 unsigned int8 calresnum=TDC_CALPERIODS_2;
6 unsigned int8 clkhsdiv ; 6 unsigned int8 clkhsdiv=TDC_CLKHSDIV_1;
7 unsigned int8 start_clkhs:1; 7 unsigned int8 start_clkhs=TDC_CLKHS_ON;
8 unsigned int8 portnum :1; 8 unsigned int1 portnum=TDC_TPORTNUM_4;
9 unsigned int8 Tcycle :1; 9 unsigned int1 Tcycle=TDC_TCYCLE_SHORT;
10 unsigned int8 fakenum :1; 10 unsigned int1 fakenum=TDC_TFAKENUM_2;
11 unsigned int8 selclkT :1; 11 unsigned int1 selclkT=TDC_TSELCLK_128HS;
12 unsigned int8 calibrate :1; 12 unsigned int1 calibrate=TDC_CALIBRATE_EN;
13 unsigned int8 disautocal :1; 13 unsigned int1 disautocal=TDC_AUTOCAL_EN;
14 unsigned int8 MRange :1; 14 unsigned int1 MRange=TDC_MRANGE2;
15 unsigned int8 neg_stop2 :1; 15 unsigned int1 neg_stop2=TDC_NEG_STOP2;
16 unsigned int8 neg_stop1 :1; 16 unsigned int1 neg_stop1=TDC_NEG_STOP1;
17 unsigned int8 neg_start :1; 17 unsigned int1 neg_start=TDC_NEG_START;
18 //}reg0; 18 //}reg0;
19   19  
20 //struct { 20 //struct {
21 unsigned int hit2 :4; 21 unsigned int hit2=TDC_MRANGE1_HIT2_NOAC;
22 unsigned int hit1 :4; 22 unsigned int hit1=TDC_MRANGE1_HIT1_NOAC;
23 unsigned int fast_init :1; 23 unsigned int1 fast_init=TDC_FAST_INIT_DIS;
24 unsigned int sc :1; -  
25 unsigned int hitin2 :3; 24 unsigned int hitin2=TDC_HITIN2_0;
26 unsigned int hitin1 :3; 25 unsigned int hitin1=TDC_HITIN1_0;
27 //}reg1; 26 //}reg1;
28   27  
29 //struct { 28 //struct {
30 unsigned int en_int :3; 29 unsigned int en_int=TDC_INT_ALU;
31 unsigned int rfedge2 :1; 30 unsigned int1 rfedge2=TDC_CH2EDGE_RIS;
32 unsigned int rfedge1 :1; 31 unsigned int1 rfedge1=TDC_CH1EDGE_RIS;
33 unsigned int delval1 :3; 32 unsigned int32 delval1=0;
34 //}reg2; 33 //}reg2;
35   34  
36 //struct { 35 //struct {
37 unsigned int en_err_val :1; 36 unsigned int1 en_err_val=TDC_ERRVAL_DIS;
38 unsigned int tim0_mr2 :2; 37 unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS;
39 unsigned int32 delval :7; 38 unsigned int32 delval2=0;
40 //}reg3; 39 //}reg3;
41   40  
-   41 //reg4
-   42 unsigned int32 delval3=0;
-   43  
-   44 //reg5
-   45 unsigned int conf_fire=0;
-   46 unsigned int1 en_startnoise=TDC_STARTNOISE_DIS;
-   47 unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS;
-   48 unsigned int repeat_fire=TDC_REPEAT_FIRE_0;
-   49 unsigned int16 phase_fire;
-   50  
42 //}TDC_registers; 51 //}TDC_registers;
43   52  
44   53  
45 void TDC_init() 54 void TDC_init()
46 { 55 {
Line 117... Line 126...
117 return ret; 126 return ret;
118 } 127 }
119   128  
120 void TDC_update_registers() 129 void TDC_update_registers()
121 { 130 {
-   131 //update reg0
-   132 output_low(TDC_ENABLE);
-   133 spi_xfer(TDC_stream,0x80,8);
-   134 spi_xfer(TDC_stream,firenum,4);
-   135 spi_xfer(TDC_stream,div_fire,4);
-   136 spi_xfer(TDC_stream,calresnum,2);
-   137 spi_xfer(TDC_stream,clkhsdiv,2);
-   138 spi_xfer(TDC_stream,start_clkhs,2);
-   139 spi_xfer(TDC_stream,portnum,1);
-   140 spi_xfer(TDC_stream,Tcycle,1);
-   141 spi_xfer(TDC_stream,fakenum,1);
-   142 spi_xfer(TDC_stream,selclkT,1);
-   143 spi_xfer(TDC_stream,calibrate,1);
-   144 spi_xfer(TDC_stream,disautocal,1);
-   145 spi_xfer(TDC_stream,MRange,1);
-   146 spi_xfer(TDC_stream,neg_stop2,1);
-   147 spi_xfer(TDC_stream,neg_stop1,1);
-   148 spi_xfer(TDC_stream,neg_start,1);
-   149 output_high(TDC_ENABLE);
-   150  
-   151 // update reg1
122 output_low(TDC_ENABLE); 152 output_low(TDC_ENABLE);
123 spi_xfer(TDC_stream,0x81,8); 153 spi_xfer(TDC_stream,0x81,8);
-   154 spi_xfer(TDC_stream,hit2,4);
124 spi_xfer(TDC_stream,reg1.*,24); 155 spi_xfer(TDC_stream,hit1,4);
-   156 spi_xfer(TDC_stream,fast_init,1);
-   157 spi_xfer(TDC_stream,1,1);
-   158 spi_xfer(TDC_stream,hitin2,3);
-   159 spi_xfer(TDC_stream,hitin1,3);
-   160 spi_xfer(TDC_stream,0,8);
125 output_high(TDC_ENABLE); 161 output_high(TDC_ENABLE);
126   162  
-   163 // update reg2
127 /* output_low(TDC_ENABLE); 164 output_low(TDC_ENABLE);
128 spi_xfer(TDC_stream,0xB1); 165 spi_xfer(TDC_stream,0x82);
-   166 spi_xfer(TDC_stream,en_int,3);
-   167 spi_xfer(TDC_stream,rfedge2,1);
-   168 spi_xfer(TDC_stream,rfedge1,1);
-   169 spi_xfer(TDC_stream,delval1,19);
129 output_high(TDC_ENABLE); 170 output_high(TDC_ENABLE);
130   171  
-   172 // update reg3
131 output_low(TDC_ENABLE); 173 output_low(TDC_ENABLE);
132 spi_xfer(TDC_stream,0xB2); 174 spi_xfer(TDC_stream,0x83);
-   175 spi_xfer(TDC_stream,0,2);
-   176 spi_xfer(TDC_stream,en_err_val,1);
-   177 spi_xfer(TDC_stream,tim0_mr2,2);
-   178 spi_xfer(TDC_stream,delval2,19);
133 output_high(TDC_ENABLE); 179 output_high(TDC_ENABLE);
134   180  
-   181 // update reg4
135 output_low(TDC_ENABLE); 182 output_low(TDC_ENABLE);
136 spi_xfer(TDC_stream,0xB3); 183 spi_xfer(TDC_stream,0x84);
-   184 spi_xfer(TDC_stream,0b00100,5);
-   185 spi_xfer(TDC_stream,delval3,19);
137 output_high(TDC_ENABLE); 186 output_high(TDC_ENABLE);
138   187  
-   188 // update reg5
139 output_low(TDC_ENABLE); 189 output_low(TDC_ENABLE);
140 spi_xfer(TDC_stream,0xB4); 190 spi_xfer(TDC_stream,0x85);
-   191 spi_xfer(TDC_stream,conf_fire,3);
-   192 spi_xfer(TDC_stream,en_startnoise,1);
-   193 spi_xfer(TDC_stream,dis_phasenoise,1);
-   194 spi_xfer(TDC_stream,repeat_fire,3);
-   195 spi_xfer(TDC_stream,phase_fire,16);
141 output_high(TDC_ENABLE); */ 196 output_high(TDC_ENABLE);
142 } 197 }
143   198  
144 void TDC_set_firenum() -  
145 { -  
146 reg0.Tcycle=TDC_TCYCLE_SHORT; -  
147 } -