Rev 3690 Rev 4608
Line 7... Line 7...
7 <!-- This file contains project source information including a list of --> 7 <!-- This file contains project source information including a list of -->
8 <!-- project source files, project and process properties. This file, --> 8 <!-- project source files, project and process properties. This file, -->
9 <!-- along with the project source files, is sufficient to open and --> 9 <!-- along with the project source files, is sufficient to open and -->
10 <!-- implement in ISE Project Navigator. --> 10 <!-- implement in ISE Project Navigator. -->
11 <!-- --> 11 <!-- -->
12 <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> 12 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
13 </header> 13 </header>
14   14  
15 <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/> 15 <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
16   16  
17 <files> 17 <files>
18 <file xil_pn:name="src/PulseGen.vhd" xil_pn:type="FILE_VHDL"> 18 <file xil_pn:name="src/PulseGen.vhd" xil_pn:type="FILE_VHDL">
19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> 19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
20 <association xil_pn:name="Implementation" xil_pn:seqID="2"/> 20 <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
21 </file> 21 </file>
22 <file xil_pn:name="src/S3AN01B.ucf" xil_pn:type="FILE_UCF"> -  
23 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> -  
24 </file> -  
25 <file xil_pn:name="src/LIB/PS2.vhd" xil_pn:type="FILE_VHDL"> 22 <file xil_pn:name="src/LIB/PS2.vhd" xil_pn:type="FILE_VHDL">
26 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> 23 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
27 <association xil_pn:name="Implementation" xil_pn:seqID="1"/> 24 <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
28 </file> 25 </file>
-   26 <file xil_pn:name="src/S3AN01B.ucf" xil_pn:type="FILE_UCF">
-   27 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-   28 </file>
29 </files> 29 </files>
30   30  
31 <properties> 31 <properties>
32 <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> 32 <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
33 <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> 33 <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
Line 213... Line 213...
213 <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> 213 <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
214 <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> 214 <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
215 <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> 215 <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
216 <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> 216 <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
217 <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> 217 <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
218 <property xil_pn:name="Project Description" xil_pn:value="Pulse Generator from 10ns to 2us." xil_pn:valueState="non-default"/> 218 <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
219 <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/> 219 <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
220 <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> 220 <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
221 <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> 221 <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
222 <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> 222 <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
223 <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> 223 <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>