Rev 3165 Rev 3166
Line 15... Line 15...
15 <version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/> 15 <version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
16   16  
17 <files> 17 <files>
18 <file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL"> 18 <file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL">
19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> 19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
20 <association xil_pn:name="Implementation" xil_pn:seqID="2"/> -  
21 </file> -  
22 <file xil_pn:name="src/LIB/PS2.vhd" xil_pn:type="FILE_VHDL"> -  
23 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> -  
24 <association xil_pn:name="Implementation" xil_pn:seqID="1"/> 20 <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
25 </file> 21 </file>
26 <file xil_pn:name="src/S3AN01B.ucf" xil_pn:type="FILE_UCF"> 22 <file xil_pn:name="src/S3AN01B.ucf" xil_pn:type="FILE_UCF">
27 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> 23 <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
28 </file> 24 </file>
29 <file xil_pn:name="ILA.cdc" xil_pn:type="FILE_CDC"> -  
30 <association xil_pn:name="Implementation" xil_pn:seqID="0"/> -  
31 </file> -  
32 </files> 25 </files>
33   26  
34 <properties> 27 <properties>
35 <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> 28 <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
36 <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> 29 <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>