Rev 3176 Rev 3177
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7 <!-- This file contains project source information including a list of --> 7 <!-- This file contains project source information including a list of -->
8 <!-- project source files, project and process properties. This file, --> 8 <!-- project source files, project and process properties. This file, -->
9 <!-- along with the project source files, is sufficient to open and --> 9 <!-- along with the project source files, is sufficient to open and -->
10 <!-- implement in ISE Project Navigator. --> 10 <!-- implement in ISE Project Navigator. -->
11 <!-- --> 11 <!-- -->
12 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> 12 <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
13 </header> 13 </header>
14   14  
15 <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/> 15 <version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
16   16  
17 <files> 17 <files>
18 <file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL"> 18 <file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL">
19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> 19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
20 <association xil_pn:name="Implementation" xil_pn:seqID="1"/> 20 <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
Line 45... Line 45...
45 <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> 45 <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
46 <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> 46 <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
47 <property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/> 47 <property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
48 <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/> 48 <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
49 <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> 49 <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
50 <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> 50 <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
51 <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> 51 <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
52 <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> 52 <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
53 <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> 53 <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
54 <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> 54 <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
55 <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> 55 <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>