Rev 3165 Rev 3166
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15 ---------------------------------------------------------------------------------- 15 ----------------------------------------------------------------------------------
16   16  
17 library IEEE; 17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL; 18 use IEEE.STD_LOGIC_1164.ALL;
19 use IEEE.numeric_std.ALL; 19 use IEEE.numeric_std.ALL;
20 use WORK.PS2_pkg.ALL; -  
21   20  
22 library UNISIM; 21 library UNISIM;
23 use UNISIM.vcomponents.all; 22 use UNISIM.vcomponents.all;
24   23  
25 entity gtime is 24 entity gtime is
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145 144
146 return mybcd; 145 return mybcd;
147 end to_bcd; 146 end to_bcd;
148   147  
149   148  
150 -- O1: ____|^^^^^^^|______ -  
151 -- O2: _________|^^|______ -  
152 -- t1 t2 -  
153 -- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz -  
154   -  
155 signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2 -  
156 signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2 -  
157 signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer -  
158 signal O1: std_logic := '0'; -- Output 1 -  
159 signal O2: std_logic := '0'; -- Output 2 -  
160 signal CTburst: unsigned(15 downto 0) := X"0000"; -- Pulse counter -  
161 -  
162 -- LED Demo Signals 149 -- LED Demo Signals
163 -- ---------------- 150 -- ----------------
164   151  
165 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary) 152 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary)
166 signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) 153 signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary)
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175 signal Enable: std_logic; 162 signal Enable: std_logic;
176 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output 163 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
177 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output 164 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
178 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output 165 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
179   166  
180 -- PS/2 Port -  
181 -- --------- -  
182   -  
183 -- Interface Signals -  
184 signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code -  
185 signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code -  
186 signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock) -  
187 signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code -  
188   -  
189 -- Result -  
190 signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory) -  
191   -  
192 -- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese -  
193 -  
194 -- VGA Demo Signals -  
195 -- ---------------- -  
196   -  
197 signal CLK: std_logic; -- Main Clock - global distribution network -  
198 signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG -  
199 signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network -  
200 signal VGA_Blank: boolean; -- Blank -  
201 signal VGA_Hsync: boolean; -- Horisontal Synchronisation -  
202 signal VGA_Vsync: boolean; -- Vertical Synchronisation -  
203   -  
204 signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter -  
205 signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter -  
206   -  
207 signal PinState: std_logic; -- For IB1 Port Test -  
208 signal Red: std_logic_vector(1 downto 0); -  
209 signal Green: std_logic_vector(1 downto 0); -  
210 signal Blue: std_logic_vector(1 downto 0); -  
211   -  
212 -- ADDA -  
213 signal ADDA_DataIn: std_logic_vector(7 downto 0); -  
214 -  
215 167
216 signal LO_CLOCK: std_logic; 168 signal LO_CLOCK: std_logic;
217   169  
-   170 signal Decko: std_logic;
-   171 signal Disp: std_logic := '0';
-   172
218 begin 173 begin
219   174  
220 -- Basic LED Blinking Test 175 -- Basic LED Blinking Test
221 -- ======================= 176 -- =======================
222   177  
223 -- LED Bar Counter 178 -- LED Bar Counter
224 --!!!KAKL process (CLK100MHz) -  
225 process (LO_CLOCK) 179 process (LO_CLOCK)
226 begin 180 begin
227 -- if rising_edge(CLK100MHz) then -  
228 if DIPSW(0)='1' then -  
229 if rising_edge(LO_CLOCK) then 181 if rising_edge(LO_CLOCK) then
230 if Counter < MAXCOUNT-1 then 182 if Counter < MAXCOUNT-1 then
231 Counter <= Counter + 1; 183 Counter <= Counter + 1;
232 else 184 else
233 Counter <= (others => '0'); 185 Counter <= (others => '0');
234 Bar <= Bar + 1; 186 Bar <= Bar + 1;
235 end if; 187 end if;
236 end if; 188 end if;
237 end if; -  
238 end process; 189 end process;
239   190  
-   191 process (LO_CLOCK)
-   192 begin
-   193 if rising_edge(LO_CLOCK) then
-   194 Decko <= DIPSW(0);
-   195 end if;
-   196 end process;
-   197
-   198  
-   199 process (LO_CLOCK)
-   200 begin
-   201 if rising_edge(LO_CLOCK) then
-   202 if Decko = '1' then
-   203 if Disp = '0' then
-   204 Number(3 downto 0) <= std_logic_vector(Bar(3 downto 0));
-   205 Number(7 downto 4) <= std_logic_vector(Bar(7 downto 4));
-   206 Number(15 downto 8) <= (others=>'0');
-   207 Number(19 downto 16) <= (others=>'0');
-   208 Number(31 downto 20) <= (others=>'0'); --to_bcd(std_logic_vector(T1));
-   209 Disp <= '1';
-   210 end if;
-   211 else
-   212 Disp <= '0';
-   213 end if;
-   214 end if;
-   215 end process;
-   216
240 LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter 217 LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
241   218  
242 FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity 219 -- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
243   220  
244 -- LED Display (multiplexed) 221 -- LED Display (multiplexed)
245 -- ========================= 222 -- =========================
246   223  
247 -- Connect LED Display Output Ports (negative outputs) 224 -- Connect LED Display Output Ports (negative outputs)
Line 278... Line 255...
278 Enable <= '1'; 255 Enable <= '1';
279 end if; 256 end if;
280 end if; 257 end if;
281 end process; 258 end process;
282   259  
283 -- BCD to 7 Segmet Decoder 260 -- HEX to 7 Segmet Decoder
284 -- -- A 261 -- -- A
285 -- | | F B 262 -- | | F B
286 -- -- G 263 -- -- G
287 -- | | E C 264 -- | | E C
288 -- -- D H 265 -- -- D H
Line 313... Line 290...
313 Number(23 downto 20) when Digits="00100000" else 290 Number(23 downto 20) when Digits="00100000" else
314 Number(27 downto 24) when Digits="01000000" else 291 Number(27 downto 24) when Digits="01000000" else
315 Number(31 downto 28) when Digits="10000000" else 292 Number(31 downto 28) when Digits="10000000" else
316 "0000"; 293 "0000";
317   294  
318 -- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0 -  
319 -- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1 -  
320 -- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2 -  
321 -- "11111111"; -  
322 -  
323 -- Number(31 downto 28) <= Key(3 downto 0); -  
324   -  
325 -- Number( 7 downto 0) <= std_logic_vector(BAR); -  
326 -- Number(31 downto 24) <= DIPSW; -  
327   -  
328 -- PS/2 Port -  
329 -- ========= -  
330   -  
331 -- Instantiate PS/2 Keyboard Interface Handler -  
332 PS2_Keyboard: PS2 generic map( -  
333 CLKFREQ => 100_000_000 -  
334 ) -  
335 port map( -  
336 -- Main Clock -  
337 Clk => CLK100MHz, -  
338   -  
339 -- PS/2 Port -  
340 PS2_Clk => PS2_CLK2, -  
341 PS2_Data => PS2_DATA2, -  
342   -  
343 -- Result - valid when PS2_Valid -  
344 PS2_Code => PS2_Code, -  
345 PS2_Attribs => PS2_Attribs, -  
346 PS2_Valid => PS2_Valid, -  
347   -  
348 -- Immediate State of Shifts -  
349 PS2_Shifts => PS2_Shifts -  
350 ); -- PS2 -  
351   295  
352 process (CLK100MHz) 296 -- Display on 7seg.
353 begin -  
354 if rising_edge(CLK100MHz) then -  
355 if PS2_Valid and PS2_Attribs(7)='0' then 297 -- Number(3 downto 0) <= (others=>'0');
356 -- Valid Scan Code with no Break Attribute 298 -- Number(15 downto 4) <= (others=>'1'); --to_bcd(std_logic_vector(T2));
357 PS2_Result( 7 downto 0) <= PS2_Code; -  
358 PS2_Result(15 downto 8) <= PS2_Attribs; 299 -- Number(19 downto 16) <= (others=>'0');
359 end if; -  
360 -  
361 if PS2_Valid and PS2_Attribs(7)='0' then -  
362 if PS2_Code = X"74" and T1<2000 then T1<=T1+1; end if; 300 -- Number(31 downto 20) <= (others=>'1'); --to_bcd(std_logic_vector(T1));
363 if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if; -  
364 if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if; -  
365 if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if; -  
366 CT0<=X"0000"; -  
367 O1<='0'; -  
368 O2<='0'; -  
369 CTburst<=X"0000"; -  
370 end if; -  
371   -  
372 if PB(0)='1' then -  
373 T1<=X"0000"; -  
374 T2<=X"0000"; -  
375 end if; -  
376 301
377 if DIPSW(0)='1' then -  
378 if CT0>X"F000" then -  
379 CT0<=X"0000"; -  
380 else -  
381 CT0<=CT0+1; -  
382 end if; -  
383 else -  
384 if CT0>X"0200" then -  
385 CT0<=X"0000"; -  
386 else -  
387 CT0<=CT0+1; -  
388 end if; -  
389 end if; -  
390 -  
391 if CTburst>2000 then -  
392 CTburst<=X"0000"; -  
393 end if; -  
394   -  
395 if (CTburst<1000) or (DIPSW(1)='0') then -  
396 if CT0=X"0000" then -  
397 O1<='1'; -  
398 end if; -  
399 -  
400 if CT0=T1+X"0000" then -  
401 O2<='1'; -  
402 end if; -  
403 end if; -  
404 -  
405 if CT0=T2+T1+X"0000" then -  
406 O1<='0'; -  
407 O2<='0'; -  
408 CTburst<=CTburst+1; -  
409 end if; -  
410 -  
411 end if; -  
412 -  
413 end process; -  
414   302  
415 -- Display Result on LED -  
416 Number(3 downto 0) <= (others=>'0'); -  
417 Number(15 downto 4) <= to_bcd(std_logic_vector(T2)); -  
418 Number(19 downto 16) <= (others=>'0'); -  
419 Number(31 downto 20) <= to_bcd(std_logic_vector(T1)); -  
420 -  
421   -  
422 -- Test Diferencial In/Outs 303 -- Diferencial In/Outs
423 -- ======================== 304 -- ========================
424 DIFbuffer1 : IBUFGDS 305 DIFbuffer1 : IBUFGDS
425 generic map ( 306 generic map (
426 DIFF_TERM => TRUE, -- Differential Termination 307 DIFF_TERM => TRUE, -- Differential Termination
427 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 308 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
Line 433... Line 314...
433 O => LO_CLOCK -- Buffer output 314 O => LO_CLOCK -- Buffer output
434 ); 315 );
435   316  
436 317
437 -- Output Signal on SATA Connector 318 -- Output Signal on SATA Connector
438 -- SD1AP <= Bar(0); 319 -- SD1AP <= 'Z';
439 -- SD1AN <= Bar(1); 320 -- SD1AN <= 'Z';
440 SD1BP <= 'Z'; 321 SD1BP <= 'Z';
441 SD1BN <= 'Z'; 322 SD1BN <= 'Z';
442   323  
443 -- Input Here via SATA Cable 324 -- Input Here via SATA Cable
444 SD2AP <= 'Z'; 325 SD2AP <= 'Z';
445 SD2AN <= 'Z'; 326 SD2AN <= 'Z';
446 SD2BP <= 'Z'; 327 SD2BP <= 'Z';
447 SD2BN <= 'Z'; 328 SD2BN <= 'Z';
448   329  
449 -- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them -  
450 -- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!! -  
451 DIF1P <= O1; -  
452 B(0) <= O1; -  
453 DIF1N <= not O1; -  
454 B(1) <= not O1; -  
455 DIF2P <= O2; -  
456 B(2) <= O2; -  
457 DIF2N <= not O2; -  
458 B(3) <= not O2; -  
459 -  
460 VGA_R(0) <= O1; -  
461 VGA_R(1) <= O2; -  
462   330  
463 -- Unused Signals 331 -- Unused Signals
464 -- ============== 332 -- ==============
465   333  
466 -- I2C Signals (on connector J30) 334 -- I2C Signals (on connector J30)