Rev 3173 Rev 3176
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8 -- Tool versions: ISE 13.3 8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A. 9 -- Description: Time and frequency synchronisation for RDMS01A.
10 -- 10 --
11 -- Dependencies: CLKGEN01B, GPS01A 11 -- Dependencies: CLKGEN01B, GPS01A
12 -- 12 --
13 -- Version: $Id: gtime.vhd 3173 2013-07-15 21:17:51Z kakl $ 13 -- Version: $Id: gtime.vhd 3176 2013-07-17 14:27:37Z kakl $
14 -- 14 --
15 ---------------------------------------------------------------------------------- 15 ----------------------------------------------------------------------------------
16   16  
17 library IEEE; 17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL; 18 use IEEE.STD_LOGIC_1164.ALL;
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115 end entity gtime; 115 end entity gtime;
116   116  
117   117  
118 architecture gtime_a of gtime is 118 architecture gtime_a of gtime is
119   119  
120 function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is 120 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is
121 variable i : integer:=0; 121 variable i : integer:=0;
122 variable mybcd : std_logic_vector(11 downto 0) := (others => '0'); 122 variable mybcd : std_logic_vector(19 downto 0) := (others => '0');
123 variable bint : std_logic_vector(7 downto 0) := bin; 123 variable bint : std_logic_vector(15 downto 0) := bin;
124 begin 124 begin
125 for i in 0 to 7 loop -- repeating 8 times. 125 for i in 0 to 15 loop -- repeating 16 times.
126 mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits. 126 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits.
127 mybcd(0) := bint(7); 127 mybcd(0) := bint(15);
128 bint(7 downto 1) := bint(6 downto 0); 128 bint(15 downto 1) := bint(14 downto 0);
129 bint(0) :='0'; 129 bint(0) :='0';
130   130  
131   131  
132 if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. 132 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
133 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); 133 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
134 end if; 134 end if;
135   135  
136 if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. 136 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
137 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); 137 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
138 end if; 138 end if;
139   139  
140 if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. 140 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
141 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); 141 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
142 end if; 142 end if;
-   143  
-   144 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
-   145 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
-   146 end if;
-   147  
-   148 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
-   149 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
-   150 end if;
-   151  
143 end loop; 152 end loop;
144 153
145 return mybcd; 154 return mybcd;
146 end to_bcd; 155 end to_bcd;
147   156  
148   157  
149 -- LED Demo Signals 158 -- LED Demo Signals
150 -- ---------------- 159 -- ----------------
151   160  
152 signal Counter: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary) 161 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
153 signal CounterMaxcount: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary) 162 signal CounterMaxcount: unsigned(14 downto 0) := "000000000000000"; -- Main Counter 10 kHz, max. 327.67 MHz (binary)
154 signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) 163 signal Bar: unsigned(7 downto 0) := X"00"; -- Register for Bar output (binary)
155   164  
156 signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) -  
157   165  
158 -- LED Display 166 -- LED Display
159 -- ----------- 167 -- -----------
160   168  
161 signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input 169 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
-   170 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
-   171 signal HalfFreq: std_logic_vector(31 downto 0);
162 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider 172 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
163 signal Enable: std_logic; 173 signal Enable: std_logic;
164 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output 174 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
165 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output 175 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
166 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output 176 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
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171 signal Decko: std_logic; 181 signal Decko: std_logic;
172 signal State: unsigned(2 downto 0) := (others => '0'); 182 signal State: unsigned(2 downto 0) := (others => '0');
173 183
174 begin 184 begin
175   185  
176 -- Basic LED Blinking Test -  
177 -- ======================= -  
178   -  
179 -- LED Bar Counter 186 -- Counter
180 process (LO_CLOCK) 187 process (LO_CLOCK)
181 begin 188 begin
182 189
183 if rising_edge(LO_CLOCK) then 190 if rising_edge(LO_CLOCK) then
184 191
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189 Counter <= (others => '0'); 196 Counter <= (others => '0');
190 CounterMaxcount <= CounterMaxcount + 1; 197 CounterMaxcount <= CounterMaxcount + 1;
191 end if; 198 end if;
192 end if; 199 end if;
193 if (State = 1) then 200 if (State = 1) then
194 Number(15 downto 0) <= std_logic_vector(Counter(15 downto 0)); 201 Freq(15 downto 0) <= std_logic_vector("00"&Counter);
195 Number(31 downto 16) <= std_logic_vector(CounterMaxcount(15 downto 0)); 202 Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount);
196 end if; 203 end if;
197 if (State = 2) then 204 if (State = 2) then
198 CounterMaxcount <= (others => '0'); 205 CounterMaxcount <= (others => '0');
199 Counter <= (others => '0'); 206 Counter <= (others => '0');
200 end if; 207 end if;
201 end if; 208 end if;
202   209  
203 end process; 210 end process;
204   211  
205   212  
-   213 -- Sampling 1PPS signal
206 process (LO_CLOCK) 214 process (LO_CLOCK)
207 begin 215 begin
208 if rising_edge(LO_CLOCK) then 216 if rising_edge(LO_CLOCK) then
209 Decko <= DIPSW(0); 217 Decko <= B(22);
210 end if; 218 end if;
211 end process; 219 end process;
212   220  
-   221 -- Automata for controling the Counter
213 process (LO_CLOCK) 222 process (LO_CLOCK)
214 begin 223 begin
215 if rising_edge(LO_CLOCK) then 224 if rising_edge(LO_CLOCK) then
216 if (Decko = '1') then 225 if (Decko = '1') then
217 if (State < 3) then 226 if (State < 3) then
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221 State <= (others => '0'); 230 State <= (others => '0');
222 end if; 231 end if;
223 end if; 232 end if;
224 end process; 233 end process;
225   234  
226 -  
227 -  
228 LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter 235 -- Coding to BCD for LED Display
229   236  
-   237 -- HalfFreq(14 downto 0) <= Freq(15 downto 1);
-   238 -- HalfFreq(15) <= '0';
-   239 -- HalfFreq(30 downto 16) <= Freq(31 downto 17);
-   240 -- HalfFreq(31) <= '0';
230 -- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity 241 -- Number(15 downto 0) <= to_bcd(HalfFreq(15 downto 0))(15 downto 0);
-   242 -- Number(35 downto 16) <= to_bcd(HalfFreq(31 downto 16))(19 downto 0);
-   243 Number(15 downto 0) <= Freq(15 downto 0);
-   244 Number(31 downto 16) <= Freq(31 downto 16);
-   245  
-   246 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
-   247 LED(6 downto 4) <= (others => '0');
-   248 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
231   249  
232 -- LED Display (multiplexed) 250 -- LED Display (multiplexed)
233 -- ========================= 251 -- =========================
234   252  
235 -- Connect LED Display Output Ports (negative outputs) 253 -- Connect LED Display Output Ports (negative outputs)
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314 -- Diferencial In/Outs 332 -- Diferencial In/Outs
315 -- ======================== 333 -- ========================
316 DIFbuffer1 : IBUFGDS 334 DIFbuffer1 : IBUFGDS
317 generic map ( 335 generic map (
318 DIFF_TERM => FALSE, -- Differential Termination 336 DIFF_TERM => FALSE, -- Differential Termination
319 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 337 IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer,
320 -- "0"-"16" 338 -- "0"-"16"
321 IOSTANDARD => "DEFAULT") 339 IOSTANDARD => "DEFAULT")
322 port map ( 340 port map (
323 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) 341 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
324 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) 342 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
325 O => LO_CLOCK -- Buffer output 343 O => LO_CLOCK -- Buffer output
326 ); 344 );
327   345  
-   346 OBUFDS_inst : OBUFDS
-   347 generic map (
-   348 IOSTANDARD => "DEFAULT")
-   349 port map (
-   350 O => SD2AP, -- Diff_p output (connect directly to top-level port)
-   351 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
-   352 I => LO_CLOCK -- Buffer input
-   353 );
328 354
329 -- Output Signal on SATA Connector 355 -- Output Signal on SATA Connector
330 -- SD1AP <= 'Z'; 356 -- SD1AP <= 'Z';
331 -- SD1AN <= 'Z'; 357 -- SD1AN <= 'Z';
332 SD1BP <= 'Z'; 358 SD1BP <= 'Z';
333 SD1BN <= 'Z'; 359 SD1BN <= 'Z';
334   360  
335 -- Input Here via SATA Cable 361 -- Input Here via SATA Cable
336 SD2AP <= 'Z'; 362 -- SD2AP <= 'Z';
337 SD2AN <= 'Z'; 363 -- SD2AN <= 'Z';
338 SD2BP <= 'Z'; 364 SD2BP <= 'Z';
339 SD2BN <= 'Z'; 365 SD2BN <= 'Z';
340   366  
341   367  
342 -- Unused Signals 368 -- Unused Signals