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-- Tool versions: ISE 13.3 |
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-- Tool versions: ISE 13.3 |
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-- Description: Time and frequency synchronisation for RDMS01A. |
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-- Description: Time and frequency synchronisation for RDMS01A. |
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-- |
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-- |
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-- Dependencies: CLKGEN01B, GPS01A |
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-- Dependencies: CLKGEN01B, GPS01A |
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-- |
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-- |
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-- Version: $Id: gtime.vhd 3173 2013-07-15 21:17:51Z kakl $ |
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-- Version: $Id: gtime.vhd 3176 2013-07-17 14:27:37Z kakl $ |
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-- |
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-- |
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---------------------------------------------------------------------------------- |
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---------------------------------------------------------------------------------- |
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|
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|
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library IEEE; |
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library IEEE; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.STD_LOGIC_1164.ALL; |
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end entity gtime; |
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end entity gtime; |
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|
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|
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|
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|
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architecture gtime_a of gtime is |
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architecture gtime_a of gtime is |
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|
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|
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function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is |
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function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is |
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variable i : integer:=0; |
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variable i : integer:=0; |
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variable mybcd : std_logic_vector(11 downto 0) := (others => '0'); |
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variable mybcd : std_logic_vector(19 downto 0) := (others => '0'); |
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variable bint : std_logic_vector(7 downto 0) := bin; |
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variable bint : std_logic_vector(15 downto 0) := bin; |
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begin |
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begin |
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for i in 0 to 7 loop -- repeating 8 times. |
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for i in 0 to 15 loop -- repeating 16 times. |
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mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits. |
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mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits. |
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mybcd(0) := bint(7); |
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mybcd(0) := bint(15); |
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bint(7 downto 1) := bint(6 downto 0); |
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bint(15 downto 1) := bint(14 downto 0); |
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bint(0) :='0'; |
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bint(0) :='0'; |
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|
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|
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|
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|
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if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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end if; |
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end if; |
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|
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|
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if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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end if; |
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end if; |
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|
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|
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|
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if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4. |
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|
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mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3); |
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|
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end if; |
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|
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|
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|
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if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4. |
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|
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mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3); |
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|
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end if; |
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|
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end loop; |
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end loop; |
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|
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|
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return mybcd; |
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return mybcd; |
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end to_bcd; |
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end to_bcd; |
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|
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-- LED Demo Signals |
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-- LED Demo Signals |
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-- ---------------- |
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-- ---------------- |
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|
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|
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signal Counter: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary) |
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signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary) |
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signal CounterMaxcount: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary) |
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signal CounterMaxcount: unsigned(14 downto 0) := "000000000000000"; -- Main Counter 10 kHz, max. 327.67 MHz (binary) |
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signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) |
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signal Bar: unsigned(7 downto 0) := X"00"; -- Register for Bar output (binary) |
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|
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|
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signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) |
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|
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|
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|
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-- LED Display |
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-- LED Display |
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-- ----------- |
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-- ----------- |
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|
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|
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signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input |
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signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input |
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|
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signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency |
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|
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signal HalfFreq: std_logic_vector(31 downto 0); |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal Enable: std_logic; |
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signal Enable: std_logic; |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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Line 181... |
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signal Decko: std_logic; |
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signal Decko: std_logic; |
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signal State: unsigned(2 downto 0) := (others => '0'); |
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signal State: unsigned(2 downto 0) := (others => '0'); |
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|
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|
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begin |
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begin |
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|
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|
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-- Basic LED Blinking Test |
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|
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-- ======================= |
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|
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|
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|
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-- LED Bar Counter |
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-- Counter |
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process (LO_CLOCK) |
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process (LO_CLOCK) |
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begin |
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begin |
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|
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|
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if rising_edge(LO_CLOCK) then |
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if rising_edge(LO_CLOCK) then |
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|
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|
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Counter <= (others => '0'); |
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Counter <= (others => '0'); |
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CounterMaxcount <= CounterMaxcount + 1; |
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CounterMaxcount <= CounterMaxcount + 1; |
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end if; |
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end if; |
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end if; |
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end if; |
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if (State = 1) then |
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if (State = 1) then |
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Number(15 downto 0) <= std_logic_vector(Counter(15 downto 0)); |
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Freq(15 downto 0) <= std_logic_vector("00"&Counter); |
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Number(31 downto 16) <= std_logic_vector(CounterMaxcount(15 downto 0)); |
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Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount); |
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end if; |
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end if; |
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if (State = 2) then |
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if (State = 2) then |
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CounterMaxcount <= (others => '0'); |
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CounterMaxcount <= (others => '0'); |
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Counter <= (others => '0'); |
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Counter <= (others => '0'); |
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end if; |
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end if; |
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end if; |
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end if; |
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|
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end process; |
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end process; |
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|
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|
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|
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-- Sampling 1PPS signal |
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process (LO_CLOCK) |
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process (LO_CLOCK) |
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begin |
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begin |
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if rising_edge(LO_CLOCK) then |
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if rising_edge(LO_CLOCK) then |
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Decko <= DIPSW(0); |
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Decko <= B(22); |
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end if; |
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end if; |
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end process; |
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end process; |
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|
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|
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|
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-- Automata for controling the Counter |
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process (LO_CLOCK) |
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process (LO_CLOCK) |
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begin |
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begin |
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if rising_edge(LO_CLOCK) then |
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if rising_edge(LO_CLOCK) then |
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if (Decko = '1') then |
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if (Decko = '1') then |
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if (State < 3) then |
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if (State < 3) then |
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State <= (others => '0'); |
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State <= (others => '0'); |
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end if; |
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end if; |
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end if; |
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end if; |
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end process; |
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end process; |
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|
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|
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|
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|
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|
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|
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LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter |
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-- Coding to BCD for LED Display |
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|
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|
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|
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-- HalfFreq(14 downto 0) <= Freq(15 downto 1); |
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|
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-- HalfFreq(15) <= '0'; |
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|
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-- HalfFreq(30 downto 16) <= Freq(31 downto 17); |
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|
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-- HalfFreq(31) <= '0'; |
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-- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity |
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-- Number(15 downto 0) <= to_bcd(HalfFreq(15 downto 0))(15 downto 0); |
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|
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-- Number(35 downto 16) <= to_bcd(HalfFreq(31 downto 16))(19 downto 0); |
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|
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Number(15 downto 0) <= Freq(15 downto 0); |
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Number(31 downto 16) <= Freq(31 downto 16); |
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|
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|
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|
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LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar |
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|
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LED(6 downto 4) <= (others => '0'); |
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|
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LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar |
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|
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|
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-- LED Display (multiplexed) |
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-- LED Display (multiplexed) |
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-- ========================= |
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-- ========================= |
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|
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|
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-- Connect LED Display Output Ports (negative outputs) |
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-- Connect LED Display Output Ports (negative outputs) |
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-- Diferencial In/Outs |
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-- Diferencial In/Outs |
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-- ======================== |
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-- ======================== |
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DIFbuffer1 : IBUFGDS |
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DIFbuffer1 : IBUFGDS |
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generic map ( |
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generic map ( |
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DIFF_TERM => FALSE, -- Differential Termination |
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DIFF_TERM => FALSE, -- Differential Termination |
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IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
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IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer, |
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-- "0"-"16" |
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-- "0"-"16" |
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IOSTANDARD => "DEFAULT") |
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IOSTANDARD => "DEFAULT") |
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port map ( |
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port map ( |
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I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
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I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
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IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
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IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
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O => LO_CLOCK -- Buffer output |
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O => LO_CLOCK -- Buffer output |
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); |
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); |
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|
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|
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|
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OBUFDS_inst : OBUFDS |
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|
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generic map ( |
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|
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IOSTANDARD => "DEFAULT") |
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|
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port map ( |
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|
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O => SD2AP, -- Diff_p output (connect directly to top-level port) |
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|
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OB => SD2AN, -- Diff_n output (connect directly to top-level port) |
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|
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I => LO_CLOCK -- Buffer input |
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|
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); |
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|
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|
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-- Output Signal on SATA Connector |
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-- Output Signal on SATA Connector |
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-- SD1AP <= 'Z'; |
356 |
-- SD1AP <= 'Z'; |
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-- SD1AN <= 'Z'; |
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-- SD1AN <= 'Z'; |
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SD1BP <= 'Z'; |
358 |
SD1BP <= 'Z'; |
333 |
SD1BN <= 'Z'; |
359 |
SD1BN <= 'Z'; |
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|
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|
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-- Input Here via SATA Cable |
361 |
-- Input Here via SATA Cable |
336 |
SD2AP <= 'Z'; |
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-- SD2AP <= 'Z'; |
337 |
SD2AN <= 'Z'; |
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-- SD2AN <= 'Z'; |
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SD2BP <= 'Z'; |
364 |
SD2BP <= 'Z'; |
339 |
SD2BN <= 'Z'; |
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SD2BN <= 'Z'; |
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|
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|
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|
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|
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-- Unused Signals |
368 |
-- Unused Signals |