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-- Tool versions: ISE 13.3 |
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-- Tool versions: ISE 13.3 |
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-- Description: Time and frequency synchronisation for RDMS01A. |
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-- Description: Time and frequency synchronisation for RDMS01A. |
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-- |
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-- |
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-- Dependencies: CLKGEN01B, GPS01A |
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-- Dependencies: CLKGEN01B, GPS01A |
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-- |
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-- |
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-- Version: $Id: gtime.vhd 3172 2013-07-15 19:19:25Z kakl $ |
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-- Version: $Id: gtime.vhd 3173 2013-07-15 21:17:51Z kakl $ |
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-- |
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-- |
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---------------------------------------------------------------------------------- |
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---------------------------------------------------------------------------------- |
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|
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library IEEE; |
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library IEEE; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.STD_LOGIC_1164.ALL; |
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|
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entity gtime is |
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entity gtime is |
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generic ( |
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generic ( |
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-- Top Value for 100MHz Clock Counter |
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-- Top Value for 100MHz Clock Counter |
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--!!!KAKL MAXCOUNT: integer := 30_000_000; |
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--!!!KAKL MAXCOUNT: integer := 30_000_000; |
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MAXCOUNT: integer := 3_000_000; |
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MAXCOUNT: integer := 10_000; |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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); |
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); |
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port ( |
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port ( |
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-- Main Clock |
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-- Main Clock |
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CLK100MHz: in std_logic; |
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CLK100MHz: in std_logic; |
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|
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-- LED Demo Signals |
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-- LED Demo Signals |
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-- ---------------- |
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-- ---------------- |
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|
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|
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signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary) |
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signal Counter: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary) |
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|
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signal CounterMaxcount: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary) |
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signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) |
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signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) |
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|
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signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) |
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signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) |
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|
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|
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-- LED Display |
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-- LED Display |
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-- ----------- |
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-- ----------- |
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|
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signal Number: std_logic_vector(32 downto 0); -- LED Display Input |
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signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal Enable: std_logic; |
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signal Enable: std_logic; |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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|
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signal LO_CLOCK: std_logic; |
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signal LO_CLOCK: std_logic; |
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|
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signal Decko: std_logic; |
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signal Decko: std_logic; |
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signal Disp: std_logic := '0'; |
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|
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signal Reset: std_logic := '0'; |
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signal State: unsigned(2 downto 0) := (others => '0'); |
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|
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|
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begin |
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begin |
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|
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-- Basic LED Blinking Test |
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-- Basic LED Blinking Test |
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-- ======================= |
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-- ======================= |
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|
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-- LED Bar Counter |
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-- LED Bar Counter |
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process (LO_CLOCK) |
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process (LO_CLOCK) |
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begin |
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begin |
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if Reset = '0' then |
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|
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if rising_edge(LO_CLOCK) then |
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if rising_edge(LO_CLOCK) then |
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|
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if Disp = '1' then |
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if (State = 3) or (State = 0) then |
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Reset <= '1'; |
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|
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end if; |
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|
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Decko <= DIPSW(0); |
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|
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if Counter < MAXCOUNT-1 then |
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if Counter < MAXCOUNT-1 then |
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Counter <= Counter + 1; |
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Counter <= Counter + 1; |
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else |
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else |
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Counter <= (others => '0'); |
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Counter <= (others => '0'); |
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Bar <= Bar + 1; |
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CounterMaxcount <= CounterMaxcount + 1; |
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end if; |
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end if; |
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end if; |
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end if; |
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|
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|
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|
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if (State = 1) then |
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Number(15 downto 0) <= std_logic_vector(Counter(15 downto 0)); |
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Number(31 downto 16) <= std_logic_vector(CounterMaxcount(15 downto 0)); |
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else |
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end if; |
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|
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if (State = 2) then |
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|
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CounterMaxcount <= (others => '0'); |
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Bar <= (others => '0'); |
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Counter <= (others => '0'); |
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Reset <= '0'; |
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end if; |
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end if; |
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end if; |
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|
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end process; |
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end process; |
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|
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|
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process (LO_CLOCK) |
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process (LO_CLOCK) |
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begin |
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begin |
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if rising_edge(LO_CLOCK) then |
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if rising_edge(LO_CLOCK) then |
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if Decko = '1' then |
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Decko <= DIPSW(0); |
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if Disp = '0' then |
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end if; |
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Number(3 downto 0) <= std_logic_vector(Bar(3 downto 0)); |
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end process; |
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|
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|
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Number(7 downto 4) <= std_logic_vector(Bar(7 downto 4)); |
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process (LO_CLOCK) |
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|
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begin |
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Number(15 downto 8) <= (others=>'0'); |
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if rising_edge(LO_CLOCK) then |
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Number(19 downto 16) <= (others=>'0'); |
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if (Decko = '1') then |
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Number(31 downto 20) <= (others=>'0'); --to_bcd(std_logic_vector(T1)); |
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if (State < 3) then |
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Disp <= '1'; |
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State <= State + 1; |
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end if; |
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end if; |
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else |
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else |
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Disp <= '0'; |
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State <= (others => '0'); |
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end if; |
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end if; |
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end if; |
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end if; |
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end process; |
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end process; |
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|
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LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter |
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LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter |
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|
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|
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-- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity |
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-- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity |
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|
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|
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-- Diferencial In/Outs |
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-- Diferencial In/Outs |
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-- ======================== |
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-- ======================== |
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DIFbuffer1 : IBUFGDS |
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DIFbuffer1 : IBUFGDS |
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generic map ( |
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generic map ( |
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DIFF_TERM => TRUE, -- Differential Termination |
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DIFF_TERM => FALSE, -- Differential Termination |
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IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
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IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
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-- "0"-"16" |
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-- "0"-"16" |
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IOSTANDARD => "DEFAULT") |
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IOSTANDARD => "DEFAULT") |
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port map ( |
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port map ( |
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I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
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I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |