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36 |
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.c.s: |
37 |
.c.s: |
| 38 |
$(COMPILE) -S $< -o $@ |
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$(COMPILE) -S $< -o $@ |
| 39 |
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39 |
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| 40 |
# Fuse high byte: |
40 |
# Fuse high byte: |
| - |
|
41 |
# 0xD9 = 1 1 0 1 1 0 0 1 = Factory Default Value |
| 41 |
# 0xc9 = 1 1 0 0 1 0 0 1 <-- BOOTRST (boot reset vector at 0x0000) |
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# 0xC9 = 1 1 0 0 1 0 0 1 <-- BOOTRST (boot reset vector at 0x0000) |
| 42 |
# ^ ^ ^ ^ ^ ^ ^------ BOOTSZ0 |
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# ^ ^ ^ ^ ^ ^ ^------ BOOTSZ0 |
| 43 |
# | | | | | +-------- BOOTSZ1 |
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# | | | | | +-------- BOOTSZ1 |
| 44 |
# | | | | + --------- EESAVE (don't preserve EEPROM over chip erase) |
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# | | | | + --------- EESAVE (don't preserve EEPROM over chip erase) |
| 45 |
# | | | +-------------- CKOPT (full output swing) |
46 |
# | | | +-------------- CKOPT (full output swing) |
| 46 |
# | | +---------------- SPIEN (allow serial programming) |
47 |
# | | +---------------- SPIEN (allow serial programming) |
| 47 |
# | +------------------ WDTON (WDT not always on) |
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# | +------------------ WDTON (WDT not always on) |
| 48 |
# +-------------------- RSTDISBL (reset pin is enabled) |
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# +-------------------- RSTDISBL (reset pin is enabled) |
| 49 |
# Fuse low byte: |
50 |
# Fuse low byte: |
| - |
|
51 |
# 0xE1 = 1 1 1 0 0 0 0 1 = Factory Default Value |
| 50 |
# 0x9f = 1 0 0 1 1 1 1 1 |
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# 0x9F = 1 0 0 1 1 1 1 1 |
| 51 |
# ^ ^ \ / \--+--/ |
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# ^ ^ \ / \--+--/ |
| 52 |
# | | | +------- CKSEL 3..0 (external >8M crystal) |
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# | | | +------- CKSEL 3..0 (external >8M crystal) |
| 53 |
# | | +--------------- SUT 1..0 (crystal osc, BOD enabled) |
55 |
# | | +--------------- SUT 1..0 (crystal osc, BOD enabled) |
| 54 |
# | +------------------ BODEN (BrownOut Detector enabled) |
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# | +------------------ BODEN (BrownOut Detector enabled) |
| 55 |
# +-------------------- BODLEVEL (2.7V) |
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# +-------------------- BODLEVEL (2.7V) |