| Line 1... |
Line 1... |
| 1 |
(kicad_pcb (version 4) (host pcbnew 4.0.1-stable) |
1 |
(kicad_pcb (version 4) (host pcbnew 4.0.1-stable) |
| 2 |
|
2 |
|
| 3 |
(general |
3 |
(general |
| 4 |
(links 60) |
4 |
(links 60) |
| 5 |
(no_connects 0) |
5 |
(no_connects 0) |
| 6 |
(area 0.178999 -40.461001 40.461001 -0.178999) |
6 |
(area -3.556 -42.672 43.180001 2.540001) |
| 7 |
(thickness 1.6) |
7 |
(thickness 1.6) |
| 8 |
(drawings 12) |
8 |
(drawings 12) |
| 9 |
(tracks 168) |
9 |
(tracks 168) |
| 10 |
(zones 0) |
10 |
(zones 0) |
| 11 |
(modules 34) |
11 |
(modules 34) |
| Line 35... |
Line 35... |
| 35 |
(48 B.Fab user) |
35 |
(48 B.Fab user) |
| 36 |
(49 F.Fab user) |
36 |
(49 F.Fab user) |
| 37 |
) |
37 |
) |
| 38 |
|
38 |
|
| 39 |
(setup |
39 |
(setup |
| 40 |
(last_trace_width 1.2) |
40 |
(last_trace_width 0.25) |
| 41 |
(user_trace_width 0.8) |
41 |
(user_trace_width 0.8) |
| 42 |
(user_trace_width 0.9) |
42 |
(user_trace_width 0.9) |
| 43 |
(user_trace_width 1) |
43 |
(user_trace_width 1) |
| 44 |
(user_trace_width 1.2) |
44 |
(user_trace_width 1.2) |
| 45 |
(trace_clearance 0.2) |
45 |
(trace_clearance 0.2) |
| Line 48... |
Line 48... |
| 48 |
(trace_min 0.2) |
48 |
(trace_min 0.2) |
| 49 |
(segment_width 0.2) |
49 |
(segment_width 0.2) |
| 50 |
(edge_width 0.15) |
50 |
(edge_width 0.15) |
| 51 |
(via_size 0.8) |
51 |
(via_size 0.8) |
| 52 |
(via_drill 0.4) |
52 |
(via_drill 0.4) |
| 53 |
(via_min_size 0.4) |
53 |
(via_min_size 0.7) |
| 54 |
(via_min_drill 0.3) |
54 |
(via_min_drill 0.3) |
| 55 |
(uvia_size 0.3) |
55 |
(uvia_size 0.3) |
| 56 |
(uvia_drill 0.1) |
56 |
(uvia_drill 0.1) |
| 57 |
(uvias_allowed no) |
57 |
(uvias_allowed no) |
| 58 |
(uvia_min_size 0.2) |
58 |
(uvia_min_size 0.3) |
| 59 |
(uvia_min_drill 0.1) |
59 |
(uvia_min_drill 0.1) |
| 60 |
(pcb_text_width 0.3) |
60 |
(pcb_text_width 0.3) |
| 61 |
(pcb_text_size 1.5 1.5) |
61 |
(pcb_text_size 1.5 1.5) |
| 62 |
(mod_edge_width 0.15) |
62 |
(mod_edge_width 0.15) |
| 63 |
(mod_text_size 1 1) |
63 |
(mod_text_size 1 1) |
| Line 67... |
Line 67... |
| 67 |
(pad_to_mask_clearance 0.2) |
67 |
(pad_to_mask_clearance 0.2) |
| 68 |
(solder_mask_min_width 0.2) |
68 |
(solder_mask_min_width 0.2) |
| 69 |
(aux_axis_origin 0 0) |
69 |
(aux_axis_origin 0 0) |
| 70 |
(visible_elements 7FFFFF7F) |
70 |
(visible_elements 7FFFFF7F) |
| 71 |
(pcbplotparams |
71 |
(pcbplotparams |
| 72 |
(layerselection 0x00030_80000001) |
72 |
(layerselection 0x010f0_80000001) |
| 73 |
(usegerberextensions false) |
73 |
(usegerberextensions false) |
| 74 |
(excludeedgelayer true) |
74 |
(excludeedgelayer true) |
| 75 |
(linewidth 0.500000) |
75 |
(linewidth 0.500000) |
| 76 |
(plotframeref false) |
76 |
(plotframeref false) |
| 77 |
(viasonmask false) |
77 |
(viasonmask false) |
| Line 88... |
Line 88... |
| 88 |
(plotinvisibletext false) |
88 |
(plotinvisibletext false) |
| 89 |
(padsonsilk false) |
89 |
(padsonsilk false) |
| 90 |
(subtractmaskfromsilk false) |
90 |
(subtractmaskfromsilk false) |
| 91 |
(outputformat 1) |
91 |
(outputformat 1) |
| 92 |
(mirror false) |
92 |
(mirror false) |
| 93 |
(drillshape 1) |
93 |
(drillshape 0) |
| 94 |
(scaleselection 1) |
94 |
(scaleselection 1) |
| 95 |
(outputdirectory "")) |
95 |
(outputdirectory "")) |
| 96 |
) |
96 |
) |
| 97 |
|
97 |
|
| 98 |
(net 0 "") |
98 |
(net 0 "") |