Line 124... |
Line 124... |
124 |
ret=spi_xfer(TDC_stream,0,8); |
124 |
ret=spi_xfer(TDC_stream,0,8); |
125 |
output_high(TDC_ENABLE); |
125 |
output_high(TDC_ENABLE); |
126 |
return ret; |
126 |
return ret; |
127 |
} |
127 |
} |
128 |
|
128 |
|
- |
|
129 |
void TDC_update_reg1() // updates reg1 only |
- |
|
130 |
{ |
- |
|
131 |
output_low(TDC_ENABLE); |
- |
|
132 |
spi_xfer(TDC_stream,0x81,8); |
- |
|
133 |
spi_xfer(TDC_stream,hit2,4); |
- |
|
134 |
spi_xfer(TDC_stream,hit1,4); |
- |
|
135 |
spi_xfer(TDC_stream,fast_init,1); |
- |
|
136 |
spi_xfer(TDC_stream,1,1); |
- |
|
137 |
spi_xfer(TDC_stream,hitin2,3); |
- |
|
138 |
spi_xfer(TDC_stream,hitin1,3); |
- |
|
139 |
spi_xfer(TDC_stream,0,8); |
- |
|
140 |
output_high(TDC_ENABLE); |
- |
|
141 |
} |
- |
|
142 |
|
129 |
void TDC_update_registers() |
143 |
void TDC_update_registers() |
130 |
{ |
144 |
{ |
131 |
//update reg0 |
145 |
//update reg0 |
132 |
output_low(TDC_ENABLE); |
146 |
output_low(TDC_ENABLE); |
133 |
spi_xfer(TDC_stream,0x80,8); |
147 |
spi_xfer(TDC_stream,0x80,8); |
Line 146... |
Line 160... |
146 |
spi_xfer(TDC_stream,neg_stop2,1); |
160 |
spi_xfer(TDC_stream,neg_stop2,1); |
147 |
spi_xfer(TDC_stream,neg_stop1,1); |
161 |
spi_xfer(TDC_stream,neg_stop1,1); |
148 |
spi_xfer(TDC_stream,neg_start,1); |
162 |
spi_xfer(TDC_stream,neg_start,1); |
149 |
output_high(TDC_ENABLE); |
163 |
output_high(TDC_ENABLE); |
150 |
|
164 |
|
151 |
// update reg1 |
- |
|
152 |
output_low(TDC_ENABLE); |
- |
|
153 |
spi_xfer(TDC_stream,0x81,8); |
- |
|
154 |
spi_xfer(TDC_stream,hit2,4); |
- |
|
155 |
spi_xfer(TDC_stream,hit1,4); |
- |
|
156 |
spi_xfer(TDC_stream,fast_init,1); |
165 |
TDC_update_reg1(); // update reg1 |
157 |
spi_xfer(TDC_stream,1,1); |
- |
|
158 |
spi_xfer(TDC_stream,hitin2,3); |
- |
|
159 |
spi_xfer(TDC_stream,hitin1,3); |
- |
|
160 |
spi_xfer(TDC_stream,0,8); |
- |
|
161 |
output_high(TDC_ENABLE); |
- |
|
162 |
|
166 |
|
163 |
// update reg2 |
167 |
// update reg2 |
164 |
output_low(TDC_ENABLE); |
168 |
output_low(TDC_ENABLE); |
165 |
spi_xfer(TDC_stream,0x82); |
169 |
spi_xfer(TDC_stream,0x82); |
166 |
spi_xfer(TDC_stream,en_int,3); |
170 |
spi_xfer(TDC_stream,en_int,3); |
Line 194... |
Line 198... |
194 |
spi_xfer(TDC_stream,repeat_fire,3); |
198 |
spi_xfer(TDC_stream,repeat_fire,3); |
195 |
spi_xfer(TDC_stream,phase_fire,16); |
199 |
spi_xfer(TDC_stream,phase_fire,16); |
196 |
output_high(TDC_ENABLE); |
200 |
output_high(TDC_ENABLE); |
197 |
} |
201 |
} |
198 |
|
202 |
|
- |
|
203 |
float TDC_mrange2_get_time(unsigned int shot) |
- |
|
204 |
{ |
- |
|
205 |
switch (shot) |
- |
|
206 |
{ |
- |
|
207 |
case 1: |
- |
|
208 |
hit2=TDC_MRANGE2_HIT2_1CH1; |
- |
|
209 |
break; |
- |
|
210 |
|
- |
|
211 |
case 2: |
- |
|
212 |
hit2=TDC_MRANGE2_HIT2_2CH1; |
- |
|
213 |
break; |
- |
|
214 |
|
- |
|
215 |
case 3: |
- |
|
216 |
hit2=TDC_MRANGE2_HIT2_3CH1; |
- |
|
217 |
break; |
- |
|
218 |
} |
- |
|
219 |
TDC_update_reg1(); |
- |
|
220 |
} |