| Line 114... |
Line 114... |
| 114 |
#define TDC_MRANGE2_HIT2_1CH1 2 |
114 |
#define TDC_MRANGE2_HIT2_1CH1 2 |
| 115 |
#define TDC_MRANGE2_HIT2_2CH1 3 |
115 |
#define TDC_MRANGE2_HIT2_2CH1 3 |
| 116 |
#define TDC_MRANGE2_HIT2_3CH1 4 |
116 |
#define TDC_MRANGE2_HIT2_3CH1 4 |
| 117 |
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117 |
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| 118 |
//register 2 |
118 |
//register 2 |
| - |
|
119 |
#define TDC_INT_TIMEOUT 4 |
| - |
|
120 |
#define TDC_INT_ENDHIT 2 |
| - |
|
121 |
#define TDC_INT_ALU 1 |
| 119 |
#define TDC_CH1EDGE_RIS 0 |
122 |
#define TDC_CH1EDGE_RIS 0 |
| 120 |
#define TDC_CH1EDGE_FAL 1 |
123 |
#define TDC_CH1EDGE_FAL 1 |
| - |
|
124 |
#define TDC_CH2EDGE_RIS 0 |
| - |
|
125 |
#define TDC_CH2EDGE_FAL 1 |
| 121 |
|
126 |
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| 122 |
//register 3 |
127 |
//register 3 |
| 123 |
#define TDC_TIM0MR2_256 0 |
128 |
#define TDC_TIM0MR2_256CLKHS 0 |
| 124 |
#define TDC_TIM0MR2_1024 1 |
129 |
#define TDC_TIM0MR2_1024CLKHS 1 |
| 125 |
#define TDC_TIM0MR2_4096 2 |
130 |
#define TDC_TIM0MR2_4096CLKHS 2 |
| 126 |
#define TDC_TIM0MR2_16384 3 |
131 |
#define TDC_TIM0MR2_16384CLKHS 3 |
| 127 |
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132 |
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| 128 |
#define TDC_ERRVAL_EN 1 |
133 |
#define TDC_ERRVAL_EN 1 |
| 129 |
#define TDC_ERRVAL_DIS 0 |
134 |
#define TDC_ERRVAL_DIS 0 |
| 130 |
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135 |
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| 131 |
//register 5 |
136 |
//register 5 |
| 132 |
#define TDC_FIRE_PHASE 0 |
- |
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| 133 |
#define TDC_FIRE_PHASE_INV 1 |
- |
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| 134 |
#define TDC_REPEAT_FIRE_0 0 |
137 |
#define TDC_REPEAT_FIRE_0 0 |
| 135 |
#define TDC_REPEAT_FIRE_1 1 |
138 |
#define TDC_REPEAT_FIRE_1 1 |
| 136 |
#define TDC_REPEAT_FIRE_2 2 |
139 |
#define TDC_REPEAT_FIRE_2 2 |
| 137 |
#define TDC_REPEAT_FIRE_3 3 |
140 |
#define TDC_REPEAT_FIRE_3 3 |
| 138 |
#define TDC_REPEAT_FIRE_4 4 |
141 |
#define TDC_REPEAT_FIRE_4 4 |